sky2.c 94 KB

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  1. /*
  2. * New driver for Marvell Yukon 2 chipset.
  3. * Based on earlier sk98lin, and skge driver.
  4. *
  5. * This driver intentionally does not support all the features
  6. * of the original driver such as link fail-over and link management because
  7. * those should be done at higher levels.
  8. *
  9. * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24. */
  25. #include <linux/crc32.h>
  26. #include <linux/kernel.h>
  27. #include <linux/version.h>
  28. #include <linux/module.h>
  29. #include <linux/netdevice.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/ethtool.h>
  33. #include <linux/pci.h>
  34. #include <linux/ip.h>
  35. #include <linux/tcp.h>
  36. #include <linux/in.h>
  37. #include <linux/delay.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/if_vlan.h>
  40. #include <linux/prefetch.h>
  41. #include <linux/mii.h>
  42. #include <asm/irq.h>
  43. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  44. #define SKY2_VLAN_TAG_USED 1
  45. #endif
  46. #include "sky2.h"
  47. #define DRV_NAME "sky2"
  48. #define DRV_VERSION "1.7"
  49. #define PFX DRV_NAME " "
  50. /*
  51. * The Yukon II chipset takes 64 bit command blocks (called list elements)
  52. * that are organized into three (receive, transmit, status) different rings
  53. * similar to Tigon3. A transmit can require several elements;
  54. * a receive requires one (or two if using 64 bit dma).
  55. */
  56. #define RX_LE_SIZE 512
  57. #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
  58. #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
  59. #define RX_DEF_PENDING RX_MAX_PENDING
  60. #define RX_SKB_ALIGN 8
  61. #define RX_BUF_WRITE 16
  62. #define TX_RING_SIZE 512
  63. #define TX_DEF_PENDING (TX_RING_SIZE - 1)
  64. #define TX_MIN_PENDING 64
  65. #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
  66. #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
  67. #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
  68. #define ETH_JUMBO_MTU 9000
  69. #define TX_WATCHDOG (5 * HZ)
  70. #define NAPI_WEIGHT 64
  71. #define PHY_RETRIES 1000
  72. #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
  73. static const u32 default_msg =
  74. NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  75. | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
  76. | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  77. static int debug = -1; /* defaults above */
  78. module_param(debug, int, 0);
  79. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  80. static int copybreak __read_mostly = 256;
  81. module_param(copybreak, int, 0);
  82. MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  83. static int disable_msi = 0;
  84. module_param(disable_msi, int, 0);
  85. MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  86. static int idle_timeout = 100;
  87. module_param(idle_timeout, int, 0);
  88. MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
  89. static const struct pci_device_id sky2_id_table[] = {
  90. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
  91. { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
  92. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
  93. { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
  94. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
  95. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
  96. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
  97. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
  98. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
  99. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
  100. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
  101. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
  102. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
  103. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
  104. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
  105. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
  106. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
  107. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
  108. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
  109. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
  110. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
  111. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
  112. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
  113. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
  114. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
  115. { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
  116. { 0 }
  117. };
  118. MODULE_DEVICE_TABLE(pci, sky2_id_table);
  119. /* Avoid conditionals by using array */
  120. static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
  121. static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
  122. static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
  123. /* This driver supports yukon2 chipset only */
  124. static const char *yukon2_name[] = {
  125. "XL", /* 0xb3 */
  126. "EC Ultra", /* 0xb4 */
  127. "UNKNOWN", /* 0xb5 */
  128. "EC", /* 0xb6 */
  129. "FE", /* 0xb7 */
  130. };
  131. /* Access to external PHY */
  132. static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
  133. {
  134. int i;
  135. gma_write16(hw, port, GM_SMI_DATA, val);
  136. gma_write16(hw, port, GM_SMI_CTRL,
  137. GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
  138. for (i = 0; i < PHY_RETRIES; i++) {
  139. if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
  140. return 0;
  141. udelay(1);
  142. }
  143. printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
  144. return -ETIMEDOUT;
  145. }
  146. static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
  147. {
  148. int i;
  149. gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
  150. | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
  151. for (i = 0; i < PHY_RETRIES; i++) {
  152. if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
  153. *val = gma_read16(hw, port, GM_SMI_DATA);
  154. return 0;
  155. }
  156. udelay(1);
  157. }
  158. return -ETIMEDOUT;
  159. }
  160. static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
  161. {
  162. u16 v;
  163. if (__gm_phy_read(hw, port, reg, &v) != 0)
  164. printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
  165. return v;
  166. }
  167. static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
  168. {
  169. u16 power_control;
  170. int vaux;
  171. pr_debug("sky2_set_power_state %d\n", state);
  172. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  173. power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
  174. vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
  175. (power_control & PCI_PM_CAP_PME_D3cold);
  176. power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
  177. power_control |= PCI_PM_CTRL_PME_STATUS;
  178. power_control &= ~(PCI_PM_CTRL_STATE_MASK);
  179. switch (state) {
  180. case PCI_D0:
  181. /* switch power to VCC (WA for VAUX problem) */
  182. sky2_write8(hw, B0_POWER_CTRL,
  183. PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
  184. /* disable Core Clock Division, */
  185. sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
  186. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  187. /* enable bits are inverted */
  188. sky2_write8(hw, B2_Y2_CLK_GATE,
  189. Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  190. Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
  191. Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
  192. else
  193. sky2_write8(hw, B2_Y2_CLK_GATE, 0);
  194. if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
  195. u32 reg1;
  196. sky2_pci_write32(hw, PCI_DEV_REG3, 0);
  197. reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
  198. reg1 &= P_ASPM_CONTROL_MSK;
  199. sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
  200. sky2_pci_write32(hw, PCI_DEV_REG5, 0);
  201. }
  202. break;
  203. case PCI_D3hot:
  204. case PCI_D3cold:
  205. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  206. sky2_write8(hw, B2_Y2_CLK_GATE, 0);
  207. else
  208. /* enable bits are inverted */
  209. sky2_write8(hw, B2_Y2_CLK_GATE,
  210. Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  211. Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
  212. Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
  213. /* switch power to VAUX */
  214. if (vaux && state != PCI_D3cold)
  215. sky2_write8(hw, B0_POWER_CTRL,
  216. (PC_VAUX_ENA | PC_VCC_ENA |
  217. PC_VAUX_ON | PC_VCC_OFF));
  218. break;
  219. default:
  220. printk(KERN_ERR PFX "Unknown power state %d\n", state);
  221. }
  222. sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
  223. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  224. }
  225. static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
  226. {
  227. u16 reg;
  228. /* disable all GMAC IRQ's */
  229. sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
  230. /* disable PHY IRQs */
  231. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
  232. gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
  233. gma_write16(hw, port, GM_MC_ADDR_H2, 0);
  234. gma_write16(hw, port, GM_MC_ADDR_H3, 0);
  235. gma_write16(hw, port, GM_MC_ADDR_H4, 0);
  236. reg = gma_read16(hw, port, GM_RX_CTRL);
  237. reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
  238. gma_write16(hw, port, GM_RX_CTRL, reg);
  239. }
  240. static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
  241. {
  242. struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
  243. u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
  244. if (sky2->autoneg == AUTONEG_ENABLE &&
  245. !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
  246. u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
  247. ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
  248. PHY_M_EC_MAC_S_MSK);
  249. ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
  250. if (hw->chip_id == CHIP_ID_YUKON_EC)
  251. ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
  252. else
  253. ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
  254. gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
  255. }
  256. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  257. if (sky2_is_copper(hw)) {
  258. if (hw->chip_id == CHIP_ID_YUKON_FE) {
  259. /* enable automatic crossover */
  260. ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
  261. } else {
  262. /* disable energy detect */
  263. ctrl &= ~PHY_M_PC_EN_DET_MSK;
  264. /* enable automatic crossover */
  265. ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
  266. if (sky2->autoneg == AUTONEG_ENABLE &&
  267. (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
  268. ctrl &= ~PHY_M_PC_DSC_MSK;
  269. ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
  270. }
  271. }
  272. } else {
  273. /* workaround for deviation #4.88 (CRC errors) */
  274. /* disable Automatic Crossover */
  275. ctrl &= ~PHY_M_PC_MDIX_MSK;
  276. }
  277. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  278. /* special setup for PHY 88E1112 Fiber */
  279. if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
  280. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  281. /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
  282. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
  283. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  284. ctrl &= ~PHY_M_MAC_MD_MSK;
  285. ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
  286. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  287. if (hw->pmd_type == 'P') {
  288. /* select page 1 to access Fiber registers */
  289. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
  290. /* for SFP-module set SIGDET polarity to low */
  291. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  292. ctrl |= PHY_M_FIB_SIGD_POL;
  293. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  294. }
  295. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  296. }
  297. ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
  298. if (sky2->autoneg == AUTONEG_DISABLE)
  299. ctrl &= ~PHY_CT_ANE;
  300. else
  301. ctrl |= PHY_CT_ANE;
  302. ctrl |= PHY_CT_RESET;
  303. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  304. ctrl = 0;
  305. ct1000 = 0;
  306. adv = PHY_AN_CSMA;
  307. reg = 0;
  308. if (sky2->autoneg == AUTONEG_ENABLE) {
  309. if (sky2_is_copper(hw)) {
  310. if (sky2->advertising & ADVERTISED_1000baseT_Full)
  311. ct1000 |= PHY_M_1000C_AFD;
  312. if (sky2->advertising & ADVERTISED_1000baseT_Half)
  313. ct1000 |= PHY_M_1000C_AHD;
  314. if (sky2->advertising & ADVERTISED_100baseT_Full)
  315. adv |= PHY_M_AN_100_FD;
  316. if (sky2->advertising & ADVERTISED_100baseT_Half)
  317. adv |= PHY_M_AN_100_HD;
  318. if (sky2->advertising & ADVERTISED_10baseT_Full)
  319. adv |= PHY_M_AN_10_FD;
  320. if (sky2->advertising & ADVERTISED_10baseT_Half)
  321. adv |= PHY_M_AN_10_HD;
  322. } else { /* special defines for FIBER (88E1040S only) */
  323. if (sky2->advertising & ADVERTISED_1000baseT_Full)
  324. adv |= PHY_M_AN_1000X_AFD;
  325. if (sky2->advertising & ADVERTISED_1000baseT_Half)
  326. adv |= PHY_M_AN_1000X_AHD;
  327. }
  328. /* Set Flow-control capabilities */
  329. if (sky2->tx_pause && sky2->rx_pause)
  330. adv |= PHY_AN_PAUSE_CAP; /* symmetric */
  331. else if (sky2->rx_pause && !sky2->tx_pause)
  332. adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
  333. else if (!sky2->rx_pause && sky2->tx_pause)
  334. adv |= PHY_AN_PAUSE_ASYM; /* local */
  335. /* Restart Auto-negotiation */
  336. ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  337. } else {
  338. /* forced speed/duplex settings */
  339. ct1000 = PHY_M_1000C_MSE;
  340. /* Disable auto update for duplex flow control and speed */
  341. reg |= GM_GPCR_AU_ALL_DIS;
  342. switch (sky2->speed) {
  343. case SPEED_1000:
  344. ctrl |= PHY_CT_SP1000;
  345. reg |= GM_GPCR_SPEED_1000;
  346. break;
  347. case SPEED_100:
  348. ctrl |= PHY_CT_SP100;
  349. reg |= GM_GPCR_SPEED_100;
  350. break;
  351. }
  352. if (sky2->duplex == DUPLEX_FULL) {
  353. reg |= GM_GPCR_DUP_FULL;
  354. ctrl |= PHY_CT_DUP_MD;
  355. } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) {
  356. /* Turn off flow control for 10/100mbps */
  357. sky2->rx_pause = 0;
  358. sky2->tx_pause = 0;
  359. }
  360. if (!sky2->rx_pause)
  361. reg |= GM_GPCR_FC_RX_DIS;
  362. if (!sky2->tx_pause)
  363. reg |= GM_GPCR_FC_TX_DIS;
  364. /* Forward pause packets to GMAC? */
  365. if (sky2->tx_pause || sky2->rx_pause)
  366. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  367. else
  368. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  369. ctrl |= PHY_CT_RESET;
  370. }
  371. gma_write16(hw, port, GM_GP_CTRL, reg);
  372. if (hw->chip_id != CHIP_ID_YUKON_FE)
  373. gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
  374. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
  375. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  376. /* Setup Phy LED's */
  377. ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
  378. ledover = 0;
  379. switch (hw->chip_id) {
  380. case CHIP_ID_YUKON_FE:
  381. /* on 88E3082 these bits are at 11..9 (shifted left) */
  382. ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
  383. ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
  384. /* delete ACT LED control bits */
  385. ctrl &= ~PHY_M_FELP_LED1_MSK;
  386. /* change ACT LED control to blink mode */
  387. ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
  388. gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
  389. break;
  390. case CHIP_ID_YUKON_XL:
  391. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  392. /* select page 3 to access LED control register */
  393. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  394. /* set LED Function Control register */
  395. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  396. (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
  397. PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
  398. PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
  399. PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
  400. /* set Polarity Control register */
  401. gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
  402. (PHY_M_POLC_LS1_P_MIX(4) |
  403. PHY_M_POLC_IS0_P_MIX(4) |
  404. PHY_M_POLC_LOS_CTRL(2) |
  405. PHY_M_POLC_INIT_CTRL(2) |
  406. PHY_M_POLC_STA1_CTRL(2) |
  407. PHY_M_POLC_STA0_CTRL(2)));
  408. /* restore page register */
  409. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  410. break;
  411. case CHIP_ID_YUKON_EC_U:
  412. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  413. /* select page 3 to access LED control register */
  414. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  415. /* set LED Function Control register */
  416. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  417. (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
  418. PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
  419. PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
  420. PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
  421. /* set Blink Rate in LED Timer Control Register */
  422. gm_phy_write(hw, port, PHY_MARV_INT_MASK,
  423. ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
  424. /* restore page register */
  425. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  426. break;
  427. default:
  428. /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
  429. ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
  430. /* turn off the Rx LED (LED_RX) */
  431. ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
  432. }
  433. if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
  434. /* apply fixes in PHY AFE */
  435. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  436. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
  437. /* increase differential signal amplitude in 10BASE-T */
  438. gm_phy_write(hw, port, 0x18, 0xaa99);
  439. gm_phy_write(hw, port, 0x17, 0x2011);
  440. /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
  441. gm_phy_write(hw, port, 0x18, 0xa204);
  442. gm_phy_write(hw, port, 0x17, 0x2002);
  443. /* set page register to 0 */
  444. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  445. } else {
  446. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
  447. if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
  448. /* turn on 100 Mbps LED (LED_LINK100) */
  449. ledover |= PHY_M_LED_MO_100(MO_LED_ON);
  450. }
  451. if (ledover)
  452. gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
  453. }
  454. /* Enable phy interrupt on auto-negotiation complete (or link up) */
  455. if (sky2->autoneg == AUTONEG_ENABLE)
  456. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
  457. else
  458. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
  459. }
  460. static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
  461. {
  462. u32 reg1;
  463. static const u32 phy_power[]
  464. = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
  465. /* looks like this XL is back asswards .. */
  466. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  467. onoff = !onoff;
  468. reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
  469. if (onoff)
  470. /* Turn off phy power saving */
  471. reg1 &= ~phy_power[port];
  472. else
  473. reg1 |= phy_power[port];
  474. sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
  475. sky2_pci_read32(hw, PCI_DEV_REG1);
  476. udelay(100);
  477. }
  478. /* Force a renegotiation */
  479. static void sky2_phy_reinit(struct sky2_port *sky2)
  480. {
  481. spin_lock_bh(&sky2->phy_lock);
  482. sky2_phy_init(sky2->hw, sky2->port);
  483. spin_unlock_bh(&sky2->phy_lock);
  484. }
  485. static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
  486. {
  487. struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
  488. u16 reg;
  489. int i;
  490. const u8 *addr = hw->dev[port]->dev_addr;
  491. sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  492. sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
  493. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
  494. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
  495. /* WA DEV_472 -- looks like crossed wires on port 2 */
  496. /* clear GMAC 1 Control reset */
  497. sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
  498. do {
  499. sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
  500. sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
  501. } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
  502. gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
  503. gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
  504. }
  505. sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
  506. /* Enable Transmit FIFO Underrun */
  507. sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
  508. spin_lock_bh(&sky2->phy_lock);
  509. sky2_phy_init(hw, port);
  510. spin_unlock_bh(&sky2->phy_lock);
  511. /* MIB clear */
  512. reg = gma_read16(hw, port, GM_PHY_ADDR);
  513. gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
  514. for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
  515. gma_read16(hw, port, i);
  516. gma_write16(hw, port, GM_PHY_ADDR, reg);
  517. /* transmit control */
  518. gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
  519. /* receive control reg: unicast + multicast + no FCS */
  520. gma_write16(hw, port, GM_RX_CTRL,
  521. GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
  522. /* transmit flow control */
  523. gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
  524. /* transmit parameter */
  525. gma_write16(hw, port, GM_TX_PARAM,
  526. TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
  527. TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
  528. TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
  529. TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
  530. /* serial mode register */
  531. reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
  532. GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
  533. if (hw->dev[port]->mtu > ETH_DATA_LEN)
  534. reg |= GM_SMOD_JUMBO_ENA;
  535. gma_write16(hw, port, GM_SERIAL_MODE, reg);
  536. /* virtual address for data */
  537. gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
  538. /* physical address: used for pause frames */
  539. gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
  540. /* ignore counter overflows */
  541. gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
  542. gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
  543. gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
  544. /* Configure Rx MAC FIFO */
  545. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
  546. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
  547. GMF_OPER_ON | GMF_RX_F_FL_ON);
  548. /* Flush Rx MAC FIFO on any flow control or error */
  549. sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
  550. /* Set threshold to 0xa (64 bytes)
  551. * ASF disabled so no need to do WA dev #4.30
  552. */
  553. sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
  554. /* Configure Tx MAC FIFO */
  555. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
  556. sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
  557. if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
  558. sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
  559. sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
  560. if (hw->dev[port]->mtu > ETH_DATA_LEN) {
  561. /* set Tx GMAC FIFO Almost Empty Threshold */
  562. sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
  563. /* Disable Store & Forward mode for TX */
  564. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
  565. }
  566. }
  567. }
  568. /* Assign Ram Buffer allocation.
  569. * start and end are in units of 4k bytes
  570. * ram registers are in units of 64bit words
  571. */
  572. static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
  573. {
  574. u32 start, end;
  575. start = startk * 4096/8;
  576. end = (endk * 4096/8) - 1;
  577. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
  578. sky2_write32(hw, RB_ADDR(q, RB_START), start);
  579. sky2_write32(hw, RB_ADDR(q, RB_END), end);
  580. sky2_write32(hw, RB_ADDR(q, RB_WP), start);
  581. sky2_write32(hw, RB_ADDR(q, RB_RP), start);
  582. if (q == Q_R1 || q == Q_R2) {
  583. u32 space = (endk - startk) * 4096/8;
  584. u32 tp = space - space/4;
  585. /* On receive queue's set the thresholds
  586. * give receiver priority when > 3/4 full
  587. * send pause when down to 2K
  588. */
  589. sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
  590. sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
  591. tp = space - 2048/8;
  592. sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
  593. sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
  594. } else {
  595. /* Enable store & forward on Tx queue's because
  596. * Tx FIFO is only 1K on Yukon
  597. */
  598. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
  599. }
  600. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
  601. sky2_read8(hw, RB_ADDR(q, RB_CTRL));
  602. }
  603. /* Setup Bus Memory Interface */
  604. static void sky2_qset(struct sky2_hw *hw, u16 q)
  605. {
  606. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
  607. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
  608. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
  609. sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
  610. }
  611. /* Setup prefetch unit registers. This is the interface between
  612. * hardware and driver list elements
  613. */
  614. static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
  615. u64 addr, u32 last)
  616. {
  617. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  618. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
  619. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
  620. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
  621. sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
  622. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
  623. sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
  624. }
  625. static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
  626. {
  627. struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
  628. sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
  629. return le;
  630. }
  631. /* Update chip's next pointer */
  632. static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
  633. {
  634. q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
  635. wmb();
  636. sky2_write16(hw, q, idx);
  637. sky2_read16(hw, q);
  638. }
  639. static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
  640. {
  641. struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
  642. sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
  643. return le;
  644. }
  645. /* Return high part of DMA address (could be 32 or 64 bit) */
  646. static inline u32 high32(dma_addr_t a)
  647. {
  648. return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
  649. }
  650. /* Build description to hardware about buffer */
  651. static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
  652. {
  653. struct sky2_rx_le *le;
  654. u32 hi = high32(map);
  655. u16 len = sky2->rx_bufsize;
  656. if (sky2->rx_addr64 != hi) {
  657. le = sky2_next_rx(sky2);
  658. le->addr = cpu_to_le32(hi);
  659. le->ctrl = 0;
  660. le->opcode = OP_ADDR64 | HW_OWNER;
  661. sky2->rx_addr64 = high32(map + len);
  662. }
  663. le = sky2_next_rx(sky2);
  664. le->addr = cpu_to_le32((u32) map);
  665. le->length = cpu_to_le16(len);
  666. le->ctrl = 0;
  667. le->opcode = OP_PACKET | HW_OWNER;
  668. }
  669. /* Tell chip where to start receive checksum.
  670. * Actually has two checksums, but set both same to avoid possible byte
  671. * order problems.
  672. */
  673. static void rx_set_checksum(struct sky2_port *sky2)
  674. {
  675. struct sky2_rx_le *le;
  676. le = sky2_next_rx(sky2);
  677. le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
  678. le->ctrl = 0;
  679. le->opcode = OP_TCPSTART | HW_OWNER;
  680. sky2_write32(sky2->hw,
  681. Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  682. sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
  683. }
  684. /*
  685. * The RX Stop command will not work for Yukon-2 if the BMU does not
  686. * reach the end of packet and since we can't make sure that we have
  687. * incoming data, we must reset the BMU while it is not doing a DMA
  688. * transfer. Since it is possible that the RX path is still active,
  689. * the RX RAM buffer will be stopped first, so any possible incoming
  690. * data will not trigger a DMA. After the RAM buffer is stopped, the
  691. * BMU is polled until any DMA in progress is ended and only then it
  692. * will be reset.
  693. */
  694. static void sky2_rx_stop(struct sky2_port *sky2)
  695. {
  696. struct sky2_hw *hw = sky2->hw;
  697. unsigned rxq = rxqaddr[sky2->port];
  698. int i;
  699. /* disable the RAM Buffer receive queue */
  700. sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
  701. for (i = 0; i < 0xffff; i++)
  702. if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
  703. == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
  704. goto stopped;
  705. printk(KERN_WARNING PFX "%s: receiver stop failed\n",
  706. sky2->netdev->name);
  707. stopped:
  708. sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
  709. /* reset the Rx prefetch unit */
  710. sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  711. }
  712. /* Clean out receive buffer area, assumes receiver hardware stopped */
  713. static void sky2_rx_clean(struct sky2_port *sky2)
  714. {
  715. unsigned i;
  716. memset(sky2->rx_le, 0, RX_LE_BYTES);
  717. for (i = 0; i < sky2->rx_pending; i++) {
  718. struct ring_info *re = sky2->rx_ring + i;
  719. if (re->skb) {
  720. pci_unmap_single(sky2->hw->pdev,
  721. re->mapaddr, sky2->rx_bufsize,
  722. PCI_DMA_FROMDEVICE);
  723. kfree_skb(re->skb);
  724. re->skb = NULL;
  725. }
  726. }
  727. }
  728. /* Basic MII support */
  729. static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  730. {
  731. struct mii_ioctl_data *data = if_mii(ifr);
  732. struct sky2_port *sky2 = netdev_priv(dev);
  733. struct sky2_hw *hw = sky2->hw;
  734. int err = -EOPNOTSUPP;
  735. if (!netif_running(dev))
  736. return -ENODEV; /* Phy still in reset */
  737. switch (cmd) {
  738. case SIOCGMIIPHY:
  739. data->phy_id = PHY_ADDR_MARV;
  740. /* fallthru */
  741. case SIOCGMIIREG: {
  742. u16 val = 0;
  743. spin_lock_bh(&sky2->phy_lock);
  744. err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
  745. spin_unlock_bh(&sky2->phy_lock);
  746. data->val_out = val;
  747. break;
  748. }
  749. case SIOCSMIIREG:
  750. if (!capable(CAP_NET_ADMIN))
  751. return -EPERM;
  752. spin_lock_bh(&sky2->phy_lock);
  753. err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
  754. data->val_in);
  755. spin_unlock_bh(&sky2->phy_lock);
  756. break;
  757. }
  758. return err;
  759. }
  760. #ifdef SKY2_VLAN_TAG_USED
  761. static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  762. {
  763. struct sky2_port *sky2 = netdev_priv(dev);
  764. struct sky2_hw *hw = sky2->hw;
  765. u16 port = sky2->port;
  766. spin_lock_bh(&sky2->tx_lock);
  767. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
  768. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
  769. sky2->vlgrp = grp;
  770. spin_unlock_bh(&sky2->tx_lock);
  771. }
  772. static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
  773. {
  774. struct sky2_port *sky2 = netdev_priv(dev);
  775. struct sky2_hw *hw = sky2->hw;
  776. u16 port = sky2->port;
  777. spin_lock_bh(&sky2->tx_lock);
  778. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
  779. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
  780. if (sky2->vlgrp)
  781. sky2->vlgrp->vlan_devices[vid] = NULL;
  782. spin_unlock_bh(&sky2->tx_lock);
  783. }
  784. #endif
  785. /*
  786. * It appears the hardware has a bug in the FIFO logic that
  787. * cause it to hang if the FIFO gets overrun and the receive buffer
  788. * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
  789. * aligned except if slab debugging is enabled.
  790. */
  791. static inline struct sk_buff *sky2_alloc_skb(struct net_device *dev,
  792. unsigned int length,
  793. gfp_t gfp_mask)
  794. {
  795. struct sk_buff *skb;
  796. skb = __netdev_alloc_skb(dev, length + RX_SKB_ALIGN, gfp_mask);
  797. if (likely(skb)) {
  798. unsigned long p = (unsigned long) skb->data;
  799. skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
  800. }
  801. return skb;
  802. }
  803. /*
  804. * Allocate and setup receiver buffer pool.
  805. * In case of 64 bit dma, there are 2X as many list elements
  806. * available as ring entries
  807. * and need to reserve one list element so we don't wrap around.
  808. */
  809. static int sky2_rx_start(struct sky2_port *sky2)
  810. {
  811. struct sky2_hw *hw = sky2->hw;
  812. unsigned rxq = rxqaddr[sky2->port];
  813. int i;
  814. unsigned thresh;
  815. sky2->rx_put = sky2->rx_next = 0;
  816. sky2_qset(hw, rxq);
  817. if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
  818. /* MAC Rx RAM Read is controlled by hardware */
  819. sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
  820. }
  821. sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
  822. rx_set_checksum(sky2);
  823. for (i = 0; i < sky2->rx_pending; i++) {
  824. struct ring_info *re = sky2->rx_ring + i;
  825. re->skb = sky2_alloc_skb(sky2->netdev, sky2->rx_bufsize,
  826. GFP_KERNEL);
  827. if (!re->skb)
  828. goto nomem;
  829. re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
  830. sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
  831. sky2_rx_add(sky2, re->mapaddr);
  832. }
  833. /*
  834. * The receiver hangs if it receives frames larger than the
  835. * packet buffer. As a workaround, truncate oversize frames, but
  836. * the register is limited to 9 bits, so if you do frames > 2052
  837. * you better get the MTU right!
  838. */
  839. thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
  840. if (thresh > 0x1ff)
  841. sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
  842. else {
  843. sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
  844. sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
  845. }
  846. /* Tell chip about available buffers */
  847. sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
  848. return 0;
  849. nomem:
  850. sky2_rx_clean(sky2);
  851. return -ENOMEM;
  852. }
  853. /* Bring up network interface. */
  854. static int sky2_up(struct net_device *dev)
  855. {
  856. struct sky2_port *sky2 = netdev_priv(dev);
  857. struct sky2_hw *hw = sky2->hw;
  858. unsigned port = sky2->port;
  859. u32 ramsize, rxspace, imask;
  860. int cap, err = -ENOMEM;
  861. struct net_device *otherdev = hw->dev[sky2->port^1];
  862. /*
  863. * On dual port PCI-X card, there is an problem where status
  864. * can be received out of order due to split transactions
  865. */
  866. if (otherdev && netif_running(otherdev) &&
  867. (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
  868. struct sky2_port *osky2 = netdev_priv(otherdev);
  869. u16 cmd;
  870. cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
  871. cmd &= ~PCI_X_CMD_MAX_SPLIT;
  872. sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
  873. sky2->rx_csum = 0;
  874. osky2->rx_csum = 0;
  875. }
  876. if (netif_msg_ifup(sky2))
  877. printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
  878. /* must be power of 2 */
  879. sky2->tx_le = pci_alloc_consistent(hw->pdev,
  880. TX_RING_SIZE *
  881. sizeof(struct sky2_tx_le),
  882. &sky2->tx_le_map);
  883. if (!sky2->tx_le)
  884. goto err_out;
  885. sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
  886. GFP_KERNEL);
  887. if (!sky2->tx_ring)
  888. goto err_out;
  889. sky2->tx_prod = sky2->tx_cons = 0;
  890. sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
  891. &sky2->rx_le_map);
  892. if (!sky2->rx_le)
  893. goto err_out;
  894. memset(sky2->rx_le, 0, RX_LE_BYTES);
  895. sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
  896. GFP_KERNEL);
  897. if (!sky2->rx_ring)
  898. goto err_out;
  899. sky2_phy_power(hw, port, 1);
  900. sky2_mac_init(hw, port);
  901. /* Determine available ram buffer space (in 4K blocks).
  902. * Note: not sure about the FE setting below yet
  903. */
  904. if (hw->chip_id == CHIP_ID_YUKON_FE)
  905. ramsize = 4;
  906. else
  907. ramsize = sky2_read8(hw, B2_E_0);
  908. /* Give transmitter one third (rounded up) */
  909. rxspace = ramsize - (ramsize + 2) / 3;
  910. sky2_ramset(hw, rxqaddr[port], 0, rxspace);
  911. sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
  912. /* Make sure SyncQ is disabled */
  913. sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
  914. RB_RST_SET);
  915. sky2_qset(hw, txqaddr[port]);
  916. /* Set almost empty threshold */
  917. if (hw->chip_id == CHIP_ID_YUKON_EC_U
  918. && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
  919. sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
  920. sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
  921. TX_RING_SIZE - 1);
  922. err = sky2_rx_start(sky2);
  923. if (err)
  924. goto err_out;
  925. /* Enable interrupts from phy/mac for port */
  926. imask = sky2_read32(hw, B0_IMSK);
  927. imask |= portirq_msk[port];
  928. sky2_write32(hw, B0_IMSK, imask);
  929. return 0;
  930. err_out:
  931. if (sky2->rx_le) {
  932. pci_free_consistent(hw->pdev, RX_LE_BYTES,
  933. sky2->rx_le, sky2->rx_le_map);
  934. sky2->rx_le = NULL;
  935. }
  936. if (sky2->tx_le) {
  937. pci_free_consistent(hw->pdev,
  938. TX_RING_SIZE * sizeof(struct sky2_tx_le),
  939. sky2->tx_le, sky2->tx_le_map);
  940. sky2->tx_le = NULL;
  941. }
  942. kfree(sky2->tx_ring);
  943. kfree(sky2->rx_ring);
  944. sky2->tx_ring = NULL;
  945. sky2->rx_ring = NULL;
  946. return err;
  947. }
  948. /* Modular subtraction in ring */
  949. static inline int tx_dist(unsigned tail, unsigned head)
  950. {
  951. return (head - tail) & (TX_RING_SIZE - 1);
  952. }
  953. /* Number of list elements available for next tx */
  954. static inline int tx_avail(const struct sky2_port *sky2)
  955. {
  956. return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
  957. }
  958. /* Estimate of number of transmit list elements required */
  959. static unsigned tx_le_req(const struct sk_buff *skb)
  960. {
  961. unsigned count;
  962. count = sizeof(dma_addr_t) / sizeof(u32);
  963. count += skb_shinfo(skb)->nr_frags * count;
  964. if (skb_is_gso(skb))
  965. ++count;
  966. if (skb->ip_summed == CHECKSUM_PARTIAL)
  967. ++count;
  968. return count;
  969. }
  970. /*
  971. * Put one packet in ring for transmit.
  972. * A single packet can generate multiple list elements, and
  973. * the number of ring elements will probably be less than the number
  974. * of list elements used.
  975. *
  976. * No BH disabling for tx_lock here (like tg3)
  977. */
  978. static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
  979. {
  980. struct sky2_port *sky2 = netdev_priv(dev);
  981. struct sky2_hw *hw = sky2->hw;
  982. struct sky2_tx_le *le = NULL;
  983. struct tx_ring_info *re;
  984. unsigned i, len;
  985. dma_addr_t mapping;
  986. u32 addr64;
  987. u16 mss;
  988. u8 ctrl;
  989. /* No BH disabling for tx_lock here. We are running in BH disabled
  990. * context and TX reclaim runs via poll inside of a software
  991. * interrupt, and no related locks in IRQ processing.
  992. */
  993. if (!spin_trylock(&sky2->tx_lock))
  994. return NETDEV_TX_LOCKED;
  995. if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
  996. /* There is a known but harmless race with lockless tx
  997. * and netif_stop_queue.
  998. */
  999. if (!netif_queue_stopped(dev)) {
  1000. netif_stop_queue(dev);
  1001. if (net_ratelimit())
  1002. printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
  1003. dev->name);
  1004. }
  1005. spin_unlock(&sky2->tx_lock);
  1006. return NETDEV_TX_BUSY;
  1007. }
  1008. if (unlikely(netif_msg_tx_queued(sky2)))
  1009. printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
  1010. dev->name, sky2->tx_prod, skb->len);
  1011. len = skb_headlen(skb);
  1012. mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
  1013. addr64 = high32(mapping);
  1014. re = sky2->tx_ring + sky2->tx_prod;
  1015. /* Send high bits if changed or crosses boundary */
  1016. if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
  1017. le = get_tx_le(sky2);
  1018. le->addr = cpu_to_le32(addr64);
  1019. le->ctrl = 0;
  1020. le->opcode = OP_ADDR64 | HW_OWNER;
  1021. sky2->tx_addr64 = high32(mapping + len);
  1022. }
  1023. /* Check for TCP Segmentation Offload */
  1024. mss = skb_shinfo(skb)->gso_size;
  1025. if (mss != 0) {
  1026. mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
  1027. mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
  1028. mss += ETH_HLEN;
  1029. if (mss != sky2->tx_last_mss) {
  1030. le = get_tx_le(sky2);
  1031. le->addr = cpu_to_le32(mss);
  1032. le->opcode = OP_LRGLEN | HW_OWNER;
  1033. le->ctrl = 0;
  1034. sky2->tx_last_mss = mss;
  1035. }
  1036. }
  1037. ctrl = 0;
  1038. #ifdef SKY2_VLAN_TAG_USED
  1039. /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
  1040. if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
  1041. if (!le) {
  1042. le = get_tx_le(sky2);
  1043. le->addr = 0;
  1044. le->opcode = OP_VLAN|HW_OWNER;
  1045. le->ctrl = 0;
  1046. } else
  1047. le->opcode |= OP_VLAN;
  1048. le->length = cpu_to_be16(vlan_tx_tag_get(skb));
  1049. ctrl |= INS_VLAN;
  1050. }
  1051. #endif
  1052. /* Handle TCP checksum offload */
  1053. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1054. unsigned offset = skb->h.raw - skb->data;
  1055. u32 tcpsum;
  1056. tcpsum = offset << 16; /* sum start */
  1057. tcpsum |= offset + skb->csum; /* sum write */
  1058. ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
  1059. if (skb->nh.iph->protocol == IPPROTO_UDP)
  1060. ctrl |= UDPTCP;
  1061. if (tcpsum != sky2->tx_tcpsum) {
  1062. sky2->tx_tcpsum = tcpsum;
  1063. le = get_tx_le(sky2);
  1064. le->addr = cpu_to_le32(tcpsum);
  1065. le->length = 0; /* initial checksum value */
  1066. le->ctrl = 1; /* one packet */
  1067. le->opcode = OP_TCPLISW | HW_OWNER;
  1068. }
  1069. }
  1070. le = get_tx_le(sky2);
  1071. le->addr = cpu_to_le32((u32) mapping);
  1072. le->length = cpu_to_le16(len);
  1073. le->ctrl = ctrl;
  1074. le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
  1075. /* Record the transmit mapping info */
  1076. re->skb = skb;
  1077. pci_unmap_addr_set(re, mapaddr, mapping);
  1078. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  1079. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1080. struct tx_ring_info *fre;
  1081. mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
  1082. frag->size, PCI_DMA_TODEVICE);
  1083. addr64 = high32(mapping);
  1084. if (addr64 != sky2->tx_addr64) {
  1085. le = get_tx_le(sky2);
  1086. le->addr = cpu_to_le32(addr64);
  1087. le->ctrl = 0;
  1088. le->opcode = OP_ADDR64 | HW_OWNER;
  1089. sky2->tx_addr64 = addr64;
  1090. }
  1091. le = get_tx_le(sky2);
  1092. le->addr = cpu_to_le32((u32) mapping);
  1093. le->length = cpu_to_le16(frag->size);
  1094. le->ctrl = ctrl;
  1095. le->opcode = OP_BUFFER | HW_OWNER;
  1096. fre = sky2->tx_ring
  1097. + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
  1098. pci_unmap_addr_set(fre, mapaddr, mapping);
  1099. }
  1100. re->idx = sky2->tx_prod;
  1101. le->ctrl |= EOP;
  1102. if (tx_avail(sky2) <= MAX_SKB_TX_LE)
  1103. netif_stop_queue(dev);
  1104. sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
  1105. spin_unlock(&sky2->tx_lock);
  1106. dev->trans_start = jiffies;
  1107. return NETDEV_TX_OK;
  1108. }
  1109. /*
  1110. * Free ring elements from starting at tx_cons until "done"
  1111. *
  1112. * NB: the hardware will tell us about partial completion of multi-part
  1113. * buffers; these are deferred until completion.
  1114. */
  1115. static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
  1116. {
  1117. struct net_device *dev = sky2->netdev;
  1118. struct pci_dev *pdev = sky2->hw->pdev;
  1119. u16 nxt, put;
  1120. unsigned i;
  1121. BUG_ON(done >= TX_RING_SIZE);
  1122. if (unlikely(netif_msg_tx_done(sky2)))
  1123. printk(KERN_DEBUG "%s: tx done, up to %u\n",
  1124. dev->name, done);
  1125. for (put = sky2->tx_cons; put != done; put = nxt) {
  1126. struct tx_ring_info *re = sky2->tx_ring + put;
  1127. struct sk_buff *skb = re->skb;
  1128. nxt = re->idx;
  1129. BUG_ON(nxt >= TX_RING_SIZE);
  1130. prefetch(sky2->tx_ring + nxt);
  1131. /* Check for partial status */
  1132. if (tx_dist(put, done) < tx_dist(put, nxt))
  1133. break;
  1134. skb = re->skb;
  1135. pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
  1136. skb_headlen(skb), PCI_DMA_TODEVICE);
  1137. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  1138. struct tx_ring_info *fre;
  1139. fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
  1140. pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
  1141. skb_shinfo(skb)->frags[i].size,
  1142. PCI_DMA_TODEVICE);
  1143. }
  1144. dev_kfree_skb(skb);
  1145. }
  1146. sky2->tx_cons = put;
  1147. if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
  1148. netif_wake_queue(dev);
  1149. }
  1150. /* Cleanup all untransmitted buffers, assume transmitter not running */
  1151. static void sky2_tx_clean(struct sky2_port *sky2)
  1152. {
  1153. spin_lock_bh(&sky2->tx_lock);
  1154. sky2_tx_complete(sky2, sky2->tx_prod);
  1155. spin_unlock_bh(&sky2->tx_lock);
  1156. }
  1157. /* Network shutdown */
  1158. static int sky2_down(struct net_device *dev)
  1159. {
  1160. struct sky2_port *sky2 = netdev_priv(dev);
  1161. struct sky2_hw *hw = sky2->hw;
  1162. unsigned port = sky2->port;
  1163. u16 ctrl;
  1164. u32 imask;
  1165. /* Never really got started! */
  1166. if (!sky2->tx_le)
  1167. return 0;
  1168. if (netif_msg_ifdown(sky2))
  1169. printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
  1170. /* Stop more packets from being queued */
  1171. netif_stop_queue(dev);
  1172. sky2_gmac_reset(hw, port);
  1173. /* Stop transmitter */
  1174. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
  1175. sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
  1176. sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
  1177. RB_RST_SET | RB_DIS_OP_MD);
  1178. /* WA for dev. #4.209 */
  1179. if (hw->chip_id == CHIP_ID_YUKON_EC_U
  1180. && hw->chip_rev == CHIP_REV_YU_EC_U_A1)
  1181. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
  1182. sky2->speed != SPEED_1000 ?
  1183. TX_STFW_ENA : TX_STFW_DIS);
  1184. ctrl = gma_read16(hw, port, GM_GP_CTRL);
  1185. ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
  1186. gma_write16(hw, port, GM_GP_CTRL, ctrl);
  1187. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1188. /* Workaround shared GMAC reset */
  1189. if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
  1190. && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
  1191. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1192. /* Disable Force Sync bit and Enable Alloc bit */
  1193. sky2_write8(hw, SK_REG(port, TXA_CTRL),
  1194. TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
  1195. /* Stop Interval Timer and Limit Counter of Tx Arbiter */
  1196. sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
  1197. sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
  1198. /* Reset the PCI FIFO of the async Tx queue */
  1199. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
  1200. BMU_RST_SET | BMU_FIFO_RST);
  1201. /* Reset the Tx prefetch units */
  1202. sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
  1203. PREF_UNIT_RST_SET);
  1204. sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
  1205. sky2_rx_stop(sky2);
  1206. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  1207. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  1208. /* Disable port IRQ */
  1209. imask = sky2_read32(hw, B0_IMSK);
  1210. imask &= ~portirq_msk[port];
  1211. sky2_write32(hw, B0_IMSK, imask);
  1212. sky2_phy_power(hw, port, 0);
  1213. /* turn off LED's */
  1214. sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
  1215. synchronize_irq(hw->pdev->irq);
  1216. sky2_tx_clean(sky2);
  1217. sky2_rx_clean(sky2);
  1218. pci_free_consistent(hw->pdev, RX_LE_BYTES,
  1219. sky2->rx_le, sky2->rx_le_map);
  1220. kfree(sky2->rx_ring);
  1221. pci_free_consistent(hw->pdev,
  1222. TX_RING_SIZE * sizeof(struct sky2_tx_le),
  1223. sky2->tx_le, sky2->tx_le_map);
  1224. kfree(sky2->tx_ring);
  1225. sky2->tx_le = NULL;
  1226. sky2->rx_le = NULL;
  1227. sky2->rx_ring = NULL;
  1228. sky2->tx_ring = NULL;
  1229. return 0;
  1230. }
  1231. static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
  1232. {
  1233. if (!sky2_is_copper(hw))
  1234. return SPEED_1000;
  1235. if (hw->chip_id == CHIP_ID_YUKON_FE)
  1236. return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
  1237. switch (aux & PHY_M_PS_SPEED_MSK) {
  1238. case PHY_M_PS_SPEED_1000:
  1239. return SPEED_1000;
  1240. case PHY_M_PS_SPEED_100:
  1241. return SPEED_100;
  1242. default:
  1243. return SPEED_10;
  1244. }
  1245. }
  1246. static void sky2_link_up(struct sky2_port *sky2)
  1247. {
  1248. struct sky2_hw *hw = sky2->hw;
  1249. unsigned port = sky2->port;
  1250. u16 reg;
  1251. /* enable Rx/Tx */
  1252. reg = gma_read16(hw, port, GM_GP_CTRL);
  1253. reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
  1254. gma_write16(hw, port, GM_GP_CTRL, reg);
  1255. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
  1256. netif_carrier_on(sky2->netdev);
  1257. netif_wake_queue(sky2->netdev);
  1258. /* Turn on link LED */
  1259. sky2_write8(hw, SK_REG(port, LNK_LED_REG),
  1260. LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
  1261. if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
  1262. u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  1263. u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
  1264. switch(sky2->speed) {
  1265. case SPEED_10:
  1266. led |= PHY_M_LEDC_INIT_CTRL(7);
  1267. break;
  1268. case SPEED_100:
  1269. led |= PHY_M_LEDC_STA1_CTRL(7);
  1270. break;
  1271. case SPEED_1000:
  1272. led |= PHY_M_LEDC_STA0_CTRL(7);
  1273. break;
  1274. }
  1275. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  1276. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
  1277. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  1278. }
  1279. if (netif_msg_link(sky2))
  1280. printk(KERN_INFO PFX
  1281. "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
  1282. sky2->netdev->name, sky2->speed,
  1283. sky2->duplex == DUPLEX_FULL ? "full" : "half",
  1284. (sky2->tx_pause && sky2->rx_pause) ? "both" :
  1285. sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
  1286. }
  1287. static void sky2_link_down(struct sky2_port *sky2)
  1288. {
  1289. struct sky2_hw *hw = sky2->hw;
  1290. unsigned port = sky2->port;
  1291. u16 reg;
  1292. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
  1293. reg = gma_read16(hw, port, GM_GP_CTRL);
  1294. reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  1295. gma_write16(hw, port, GM_GP_CTRL, reg);
  1296. if (sky2->rx_pause && !sky2->tx_pause) {
  1297. /* restore Asymmetric Pause bit */
  1298. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
  1299. gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
  1300. | PHY_M_AN_ASP);
  1301. }
  1302. netif_carrier_off(sky2->netdev);
  1303. netif_stop_queue(sky2->netdev);
  1304. /* Turn on link LED */
  1305. sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
  1306. if (netif_msg_link(sky2))
  1307. printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
  1308. sky2_phy_init(hw, port);
  1309. }
  1310. static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
  1311. {
  1312. struct sky2_hw *hw = sky2->hw;
  1313. unsigned port = sky2->port;
  1314. u16 lpa;
  1315. lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
  1316. if (lpa & PHY_M_AN_RF) {
  1317. printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
  1318. return -1;
  1319. }
  1320. if (!(aux & PHY_M_PS_SPDUP_RES)) {
  1321. printk(KERN_ERR PFX "%s: speed/duplex mismatch",
  1322. sky2->netdev->name);
  1323. return -1;
  1324. }
  1325. sky2->speed = sky2_phy_speed(hw, aux);
  1326. if (sky2->speed == SPEED_1000) {
  1327. u16 ctl2 = gm_phy_read(hw, port, PHY_MARV_1000T_CTRL);
  1328. u16 lpa2 = gm_phy_read(hw, port, PHY_MARV_1000T_STAT);
  1329. if (lpa2 & PHY_B_1000S_MSF) {
  1330. printk(KERN_ERR PFX "%s: master/slave fault",
  1331. sky2->netdev->name);
  1332. return -1;
  1333. }
  1334. if ((ctl2 & PHY_M_1000C_AFD) && (lpa2 & PHY_B_1000S_LP_FD))
  1335. sky2->duplex = DUPLEX_FULL;
  1336. else
  1337. sky2->duplex = DUPLEX_HALF;
  1338. } else {
  1339. u16 adv = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
  1340. if ((aux & adv) & PHY_AN_FULL)
  1341. sky2->duplex = DUPLEX_FULL;
  1342. else
  1343. sky2->duplex = DUPLEX_HALF;
  1344. }
  1345. /* Pause bits are offset (9..8) */
  1346. if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
  1347. aux >>= 6;
  1348. sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
  1349. sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
  1350. if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000
  1351. && hw->chip_id != CHIP_ID_YUKON_EC_U)
  1352. sky2->rx_pause = sky2->tx_pause = 0;
  1353. if (sky2->rx_pause || sky2->tx_pause)
  1354. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  1355. else
  1356. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1357. return 0;
  1358. }
  1359. /* Interrupt from PHY */
  1360. static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
  1361. {
  1362. struct net_device *dev = hw->dev[port];
  1363. struct sky2_port *sky2 = netdev_priv(dev);
  1364. u16 istatus, phystat;
  1365. spin_lock(&sky2->phy_lock);
  1366. istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
  1367. phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
  1368. if (!netif_running(dev))
  1369. goto out;
  1370. if (netif_msg_intr(sky2))
  1371. printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
  1372. sky2->netdev->name, istatus, phystat);
  1373. if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
  1374. if (sky2_autoneg_done(sky2, phystat) == 0)
  1375. sky2_link_up(sky2);
  1376. goto out;
  1377. }
  1378. if (istatus & PHY_M_IS_LSP_CHANGE)
  1379. sky2->speed = sky2_phy_speed(hw, phystat);
  1380. if (istatus & PHY_M_IS_DUP_CHANGE)
  1381. sky2->duplex =
  1382. (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1383. if (istatus & PHY_M_IS_LST_CHANGE) {
  1384. if (phystat & PHY_M_PS_LINK_UP)
  1385. sky2_link_up(sky2);
  1386. else
  1387. sky2_link_down(sky2);
  1388. }
  1389. out:
  1390. spin_unlock(&sky2->phy_lock);
  1391. }
  1392. /* Transmit timeout is only called if we are running, carries is up
  1393. * and tx queue is full (stopped).
  1394. */
  1395. static void sky2_tx_timeout(struct net_device *dev)
  1396. {
  1397. struct sky2_port *sky2 = netdev_priv(dev);
  1398. struct sky2_hw *hw = sky2->hw;
  1399. unsigned txq = txqaddr[sky2->port];
  1400. u16 report, done;
  1401. if (netif_msg_timer(sky2))
  1402. printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
  1403. report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
  1404. done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
  1405. printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
  1406. dev->name,
  1407. sky2->tx_cons, sky2->tx_prod, report, done);
  1408. if (report != done) {
  1409. printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
  1410. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
  1411. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  1412. } else if (report != sky2->tx_cons) {
  1413. printk(KERN_INFO PFX "status report lost?\n");
  1414. spin_lock_bh(&sky2->tx_lock);
  1415. sky2_tx_complete(sky2, report);
  1416. spin_unlock_bh(&sky2->tx_lock);
  1417. } else {
  1418. printk(KERN_INFO PFX "hardware hung? flushing\n");
  1419. sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
  1420. sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  1421. sky2_tx_clean(sky2);
  1422. sky2_qset(hw, txq);
  1423. sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
  1424. }
  1425. }
  1426. /* Want receive buffer size to be multiple of 64 bits
  1427. * and incl room for vlan and truncation
  1428. */
  1429. static inline unsigned sky2_buf_size(int mtu)
  1430. {
  1431. return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
  1432. }
  1433. static int sky2_change_mtu(struct net_device *dev, int new_mtu)
  1434. {
  1435. struct sky2_port *sky2 = netdev_priv(dev);
  1436. struct sky2_hw *hw = sky2->hw;
  1437. int err;
  1438. u16 ctl, mode;
  1439. u32 imask;
  1440. if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
  1441. return -EINVAL;
  1442. if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
  1443. return -EINVAL;
  1444. if (!netif_running(dev)) {
  1445. dev->mtu = new_mtu;
  1446. return 0;
  1447. }
  1448. imask = sky2_read32(hw, B0_IMSK);
  1449. sky2_write32(hw, B0_IMSK, 0);
  1450. dev->trans_start = jiffies; /* prevent tx timeout */
  1451. netif_stop_queue(dev);
  1452. netif_poll_disable(hw->dev[0]);
  1453. synchronize_irq(hw->pdev->irq);
  1454. ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
  1455. gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
  1456. sky2_rx_stop(sky2);
  1457. sky2_rx_clean(sky2);
  1458. dev->mtu = new_mtu;
  1459. sky2->rx_bufsize = sky2_buf_size(new_mtu);
  1460. mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
  1461. GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
  1462. if (dev->mtu > ETH_DATA_LEN)
  1463. mode |= GM_SMOD_JUMBO_ENA;
  1464. gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
  1465. sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
  1466. err = sky2_rx_start(sky2);
  1467. sky2_write32(hw, B0_IMSK, imask);
  1468. if (err)
  1469. dev_close(dev);
  1470. else {
  1471. gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
  1472. netif_poll_enable(hw->dev[0]);
  1473. netif_wake_queue(dev);
  1474. }
  1475. return err;
  1476. }
  1477. /*
  1478. * Receive one packet.
  1479. * For small packets or errors, just reuse existing skb.
  1480. * For larger packets, get new buffer.
  1481. */
  1482. static struct sk_buff *sky2_receive(struct net_device *dev,
  1483. u16 length, u32 status)
  1484. {
  1485. struct sky2_port *sky2 = netdev_priv(dev);
  1486. struct ring_info *re = sky2->rx_ring + sky2->rx_next;
  1487. struct sk_buff *skb = NULL;
  1488. if (unlikely(netif_msg_rx_status(sky2)))
  1489. printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
  1490. dev->name, sky2->rx_next, status, length);
  1491. sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
  1492. prefetch(sky2->rx_ring + sky2->rx_next);
  1493. if (status & GMR_FS_ANY_ERR)
  1494. goto error;
  1495. if (!(status & GMR_FS_RX_OK))
  1496. goto resubmit;
  1497. if (length > dev->mtu + ETH_HLEN)
  1498. goto oversize;
  1499. if (length < copybreak) {
  1500. skb = netdev_alloc_skb(dev, length + 2);
  1501. if (!skb)
  1502. goto resubmit;
  1503. skb_reserve(skb, 2);
  1504. pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
  1505. length, PCI_DMA_FROMDEVICE);
  1506. memcpy(skb->data, re->skb->data, length);
  1507. skb->ip_summed = re->skb->ip_summed;
  1508. skb->csum = re->skb->csum;
  1509. pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
  1510. length, PCI_DMA_FROMDEVICE);
  1511. } else {
  1512. struct sk_buff *nskb;
  1513. nskb = sky2_alloc_skb(dev, sky2->rx_bufsize, GFP_ATOMIC);
  1514. if (!nskb)
  1515. goto resubmit;
  1516. skb = re->skb;
  1517. re->skb = nskb;
  1518. pci_unmap_single(sky2->hw->pdev, re->mapaddr,
  1519. sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
  1520. prefetch(skb->data);
  1521. re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
  1522. sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
  1523. }
  1524. skb_put(skb, length);
  1525. resubmit:
  1526. re->skb->ip_summed = CHECKSUM_NONE;
  1527. sky2_rx_add(sky2, re->mapaddr);
  1528. return skb;
  1529. oversize:
  1530. ++sky2->net_stats.rx_over_errors;
  1531. goto resubmit;
  1532. error:
  1533. ++sky2->net_stats.rx_errors;
  1534. if (netif_msg_rx_err(sky2) && net_ratelimit())
  1535. printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
  1536. dev->name, status, length);
  1537. if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
  1538. sky2->net_stats.rx_length_errors++;
  1539. if (status & GMR_FS_FRAGMENT)
  1540. sky2->net_stats.rx_frame_errors++;
  1541. if (status & GMR_FS_CRC_ERR)
  1542. sky2->net_stats.rx_crc_errors++;
  1543. if (status & GMR_FS_RX_FF_OV)
  1544. sky2->net_stats.rx_fifo_errors++;
  1545. goto resubmit;
  1546. }
  1547. /* Transmit complete */
  1548. static inline void sky2_tx_done(struct net_device *dev, u16 last)
  1549. {
  1550. struct sky2_port *sky2 = netdev_priv(dev);
  1551. if (netif_running(dev)) {
  1552. spin_lock(&sky2->tx_lock);
  1553. sky2_tx_complete(sky2, last);
  1554. spin_unlock(&sky2->tx_lock);
  1555. }
  1556. }
  1557. /* Process status response ring */
  1558. static int sky2_status_intr(struct sky2_hw *hw, int to_do)
  1559. {
  1560. struct sky2_port *sky2;
  1561. int work_done = 0;
  1562. unsigned buf_write[2] = { 0, 0 };
  1563. u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
  1564. rmb();
  1565. while (hw->st_idx != hwidx) {
  1566. struct sky2_status_le *le = hw->st_le + hw->st_idx;
  1567. struct net_device *dev;
  1568. struct sk_buff *skb;
  1569. u32 status;
  1570. u16 length;
  1571. hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
  1572. BUG_ON(le->link >= 2);
  1573. dev = hw->dev[le->link];
  1574. sky2 = netdev_priv(dev);
  1575. length = le16_to_cpu(le->length);
  1576. status = le32_to_cpu(le->status);
  1577. switch (le->opcode & ~HW_OWNER) {
  1578. case OP_RXSTAT:
  1579. skb = sky2_receive(dev, length, status);
  1580. if (!skb)
  1581. break;
  1582. skb->protocol = eth_type_trans(skb, dev);
  1583. dev->last_rx = jiffies;
  1584. #ifdef SKY2_VLAN_TAG_USED
  1585. if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
  1586. vlan_hwaccel_receive_skb(skb,
  1587. sky2->vlgrp,
  1588. be16_to_cpu(sky2->rx_tag));
  1589. } else
  1590. #endif
  1591. netif_receive_skb(skb);
  1592. /* Update receiver after 16 frames */
  1593. if (++buf_write[le->link] == RX_BUF_WRITE) {
  1594. sky2_put_idx(hw, rxqaddr[le->link],
  1595. sky2->rx_put);
  1596. buf_write[le->link] = 0;
  1597. }
  1598. /* Stop after net poll weight */
  1599. if (++work_done >= to_do)
  1600. goto exit_loop;
  1601. break;
  1602. #ifdef SKY2_VLAN_TAG_USED
  1603. case OP_RXVLAN:
  1604. sky2->rx_tag = length;
  1605. break;
  1606. case OP_RXCHKSVLAN:
  1607. sky2->rx_tag = length;
  1608. /* fall through */
  1609. #endif
  1610. case OP_RXCHKS:
  1611. skb = sky2->rx_ring[sky2->rx_next].skb;
  1612. skb->ip_summed = CHECKSUM_COMPLETE;
  1613. skb->csum = status & 0xffff;
  1614. break;
  1615. case OP_TXINDEXLE:
  1616. /* TX index reports status for both ports */
  1617. BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
  1618. sky2_tx_done(hw->dev[0], status & 0xfff);
  1619. if (hw->dev[1])
  1620. sky2_tx_done(hw->dev[1],
  1621. ((status >> 24) & 0xff)
  1622. | (u16)(length & 0xf) << 8);
  1623. break;
  1624. default:
  1625. if (net_ratelimit())
  1626. printk(KERN_WARNING PFX
  1627. "unknown status opcode 0x%x\n", le->opcode);
  1628. goto exit_loop;
  1629. }
  1630. }
  1631. /* Fully processed status ring so clear irq */
  1632. sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
  1633. exit_loop:
  1634. if (buf_write[0]) {
  1635. sky2 = netdev_priv(hw->dev[0]);
  1636. sky2_put_idx(hw, Q_R1, sky2->rx_put);
  1637. }
  1638. if (buf_write[1]) {
  1639. sky2 = netdev_priv(hw->dev[1]);
  1640. sky2_put_idx(hw, Q_R2, sky2->rx_put);
  1641. }
  1642. return work_done;
  1643. }
  1644. static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
  1645. {
  1646. struct net_device *dev = hw->dev[port];
  1647. if (net_ratelimit())
  1648. printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
  1649. dev->name, status);
  1650. if (status & Y2_IS_PAR_RD1) {
  1651. if (net_ratelimit())
  1652. printk(KERN_ERR PFX "%s: ram data read parity error\n",
  1653. dev->name);
  1654. /* Clear IRQ */
  1655. sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
  1656. }
  1657. if (status & Y2_IS_PAR_WR1) {
  1658. if (net_ratelimit())
  1659. printk(KERN_ERR PFX "%s: ram data write parity error\n",
  1660. dev->name);
  1661. sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
  1662. }
  1663. if (status & Y2_IS_PAR_MAC1) {
  1664. if (net_ratelimit())
  1665. printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
  1666. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
  1667. }
  1668. if (status & Y2_IS_PAR_RX1) {
  1669. if (net_ratelimit())
  1670. printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
  1671. sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
  1672. }
  1673. if (status & Y2_IS_TCP_TXA1) {
  1674. if (net_ratelimit())
  1675. printk(KERN_ERR PFX "%s: TCP segmentation error\n",
  1676. dev->name);
  1677. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
  1678. }
  1679. }
  1680. static void sky2_hw_intr(struct sky2_hw *hw)
  1681. {
  1682. u32 status = sky2_read32(hw, B0_HWE_ISRC);
  1683. if (status & Y2_IS_TIST_OV)
  1684. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  1685. if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
  1686. u16 pci_err;
  1687. pci_err = sky2_pci_read16(hw, PCI_STATUS);
  1688. if (net_ratelimit())
  1689. printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
  1690. pci_name(hw->pdev), pci_err);
  1691. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1692. sky2_pci_write16(hw, PCI_STATUS,
  1693. pci_err | PCI_STATUS_ERROR_BITS);
  1694. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1695. }
  1696. if (status & Y2_IS_PCI_EXP) {
  1697. /* PCI-Express uncorrectable Error occurred */
  1698. u32 pex_err;
  1699. pex_err = sky2_pci_read32(hw,
  1700. hw->err_cap + PCI_ERR_UNCOR_STATUS);
  1701. if (net_ratelimit())
  1702. printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
  1703. pci_name(hw->pdev), pex_err);
  1704. /* clear the interrupt */
  1705. sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1706. sky2_pci_write32(hw,
  1707. hw->err_cap + PCI_ERR_UNCOR_STATUS,
  1708. 0xffffffffUL);
  1709. sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1710. /* In case of fatal error mask off to keep from getting stuck */
  1711. if (pex_err & (PCI_ERR_UNC_POISON_TLP | PCI_ERR_UNC_FCP
  1712. | PCI_ERR_UNC_DLP)) {
  1713. u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
  1714. hwmsk &= ~Y2_IS_PCI_EXP;
  1715. sky2_write32(hw, B0_HWE_IMSK, hwmsk);
  1716. }
  1717. }
  1718. if (status & Y2_HWE_L1_MASK)
  1719. sky2_hw_error(hw, 0, status);
  1720. status >>= 8;
  1721. if (status & Y2_HWE_L1_MASK)
  1722. sky2_hw_error(hw, 1, status);
  1723. }
  1724. static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
  1725. {
  1726. struct net_device *dev = hw->dev[port];
  1727. struct sky2_port *sky2 = netdev_priv(dev);
  1728. u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
  1729. if (netif_msg_intr(sky2))
  1730. printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
  1731. dev->name, status);
  1732. if (status & GM_IS_RX_FF_OR) {
  1733. ++sky2->net_stats.rx_fifo_errors;
  1734. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
  1735. }
  1736. if (status & GM_IS_TX_FF_UR) {
  1737. ++sky2->net_stats.tx_fifo_errors;
  1738. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
  1739. }
  1740. }
  1741. /* This should never happen it is a fatal situation */
  1742. static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
  1743. const char *rxtx, u32 mask)
  1744. {
  1745. struct net_device *dev = hw->dev[port];
  1746. struct sky2_port *sky2 = netdev_priv(dev);
  1747. u32 imask;
  1748. printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
  1749. dev ? dev->name : "<not registered>", rxtx);
  1750. imask = sky2_read32(hw, B0_IMSK);
  1751. imask &= ~mask;
  1752. sky2_write32(hw, B0_IMSK, imask);
  1753. if (dev) {
  1754. spin_lock(&sky2->phy_lock);
  1755. sky2_link_down(sky2);
  1756. spin_unlock(&sky2->phy_lock);
  1757. }
  1758. }
  1759. /* If idle then force a fake soft NAPI poll once a second
  1760. * to work around cases where sharing an edge triggered interrupt.
  1761. */
  1762. static inline void sky2_idle_start(struct sky2_hw *hw)
  1763. {
  1764. if (idle_timeout > 0)
  1765. mod_timer(&hw->idle_timer,
  1766. jiffies + msecs_to_jiffies(idle_timeout));
  1767. }
  1768. static void sky2_idle(unsigned long arg)
  1769. {
  1770. struct sky2_hw *hw = (struct sky2_hw *) arg;
  1771. struct net_device *dev = hw->dev[0];
  1772. if (__netif_rx_schedule_prep(dev))
  1773. __netif_rx_schedule(dev);
  1774. mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
  1775. }
  1776. static int sky2_poll(struct net_device *dev0, int *budget)
  1777. {
  1778. struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
  1779. int work_limit = min(dev0->quota, *budget);
  1780. int work_done = 0;
  1781. u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
  1782. if (status & Y2_IS_HW_ERR)
  1783. sky2_hw_intr(hw);
  1784. if (status & Y2_IS_IRQ_PHY1)
  1785. sky2_phy_intr(hw, 0);
  1786. if (status & Y2_IS_IRQ_PHY2)
  1787. sky2_phy_intr(hw, 1);
  1788. if (status & Y2_IS_IRQ_MAC1)
  1789. sky2_mac_intr(hw, 0);
  1790. if (status & Y2_IS_IRQ_MAC2)
  1791. sky2_mac_intr(hw, 1);
  1792. if (status & Y2_IS_CHK_RX1)
  1793. sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
  1794. if (status & Y2_IS_CHK_RX2)
  1795. sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
  1796. if (status & Y2_IS_CHK_TXA1)
  1797. sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
  1798. if (status & Y2_IS_CHK_TXA2)
  1799. sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
  1800. work_done = sky2_status_intr(hw, work_limit);
  1801. if (work_done < work_limit) {
  1802. netif_rx_complete(dev0);
  1803. sky2_read32(hw, B0_Y2_SP_LISR);
  1804. return 0;
  1805. } else {
  1806. *budget -= work_done;
  1807. dev0->quota -= work_done;
  1808. return 1;
  1809. }
  1810. }
  1811. static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
  1812. {
  1813. struct sky2_hw *hw = dev_id;
  1814. struct net_device *dev0 = hw->dev[0];
  1815. u32 status;
  1816. /* Reading this mask interrupts as side effect */
  1817. status = sky2_read32(hw, B0_Y2_SP_ISRC2);
  1818. if (status == 0 || status == ~0)
  1819. return IRQ_NONE;
  1820. prefetch(&hw->st_le[hw->st_idx]);
  1821. if (likely(__netif_rx_schedule_prep(dev0)))
  1822. __netif_rx_schedule(dev0);
  1823. return IRQ_HANDLED;
  1824. }
  1825. #ifdef CONFIG_NET_POLL_CONTROLLER
  1826. static void sky2_netpoll(struct net_device *dev)
  1827. {
  1828. struct sky2_port *sky2 = netdev_priv(dev);
  1829. struct net_device *dev0 = sky2->hw->dev[0];
  1830. if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
  1831. __netif_rx_schedule(dev0);
  1832. }
  1833. #endif
  1834. /* Chip internal frequency for clock calculations */
  1835. static inline u32 sky2_mhz(const struct sky2_hw *hw)
  1836. {
  1837. switch (hw->chip_id) {
  1838. case CHIP_ID_YUKON_EC:
  1839. case CHIP_ID_YUKON_EC_U:
  1840. return 125; /* 125 Mhz */
  1841. case CHIP_ID_YUKON_FE:
  1842. return 100; /* 100 Mhz */
  1843. default: /* YUKON_XL */
  1844. return 156; /* 156 Mhz */
  1845. }
  1846. }
  1847. static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
  1848. {
  1849. return sky2_mhz(hw) * us;
  1850. }
  1851. static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
  1852. {
  1853. return clk / sky2_mhz(hw);
  1854. }
  1855. static int sky2_reset(struct sky2_hw *hw)
  1856. {
  1857. u16 status;
  1858. u8 t8;
  1859. int i;
  1860. u32 msk;
  1861. sky2_write8(hw, B0_CTST, CS_RST_CLR);
  1862. hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
  1863. if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
  1864. printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
  1865. pci_name(hw->pdev), hw->chip_id);
  1866. return -EOPNOTSUPP;
  1867. }
  1868. hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
  1869. /* This rev is really old, and requires untested workarounds */
  1870. if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
  1871. printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
  1872. pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
  1873. hw->chip_id, hw->chip_rev);
  1874. return -EOPNOTSUPP;
  1875. }
  1876. /* disable ASF */
  1877. if (hw->chip_id <= CHIP_ID_YUKON_EC) {
  1878. sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
  1879. sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
  1880. }
  1881. /* do a SW reset */
  1882. sky2_write8(hw, B0_CTST, CS_RST_SET);
  1883. sky2_write8(hw, B0_CTST, CS_RST_CLR);
  1884. /* clear PCI errors, if any */
  1885. status = sky2_pci_read16(hw, PCI_STATUS);
  1886. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1887. sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
  1888. sky2_write8(hw, B0_CTST, CS_MRST_CLR);
  1889. /* clear any PEX errors */
  1890. if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
  1891. hw->err_cap = pci_find_ext_capability(hw->pdev, PCI_EXT_CAP_ID_ERR);
  1892. if (hw->err_cap)
  1893. sky2_pci_write32(hw,
  1894. hw->err_cap + PCI_ERR_UNCOR_STATUS,
  1895. 0xffffffffUL);
  1896. }
  1897. hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
  1898. hw->ports = 1;
  1899. t8 = sky2_read8(hw, B2_Y2_HW_RES);
  1900. if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
  1901. if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
  1902. ++hw->ports;
  1903. }
  1904. sky2_set_power_state(hw, PCI_D0);
  1905. for (i = 0; i < hw->ports; i++) {
  1906. sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
  1907. sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
  1908. }
  1909. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1910. /* Clear I2C IRQ noise */
  1911. sky2_write32(hw, B2_I2C_IRQ, 1);
  1912. /* turn off hardware timer (unused) */
  1913. sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
  1914. sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
  1915. sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
  1916. /* Turn off descriptor polling */
  1917. sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
  1918. /* Turn off receive timestamp */
  1919. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
  1920. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  1921. /* enable the Tx Arbiters */
  1922. for (i = 0; i < hw->ports; i++)
  1923. sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
  1924. /* Initialize ram interface */
  1925. for (i = 0; i < hw->ports; i++) {
  1926. sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
  1927. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
  1928. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
  1929. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
  1930. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
  1931. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
  1932. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
  1933. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
  1934. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
  1935. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
  1936. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
  1937. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
  1938. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
  1939. }
  1940. msk = Y2_HWE_ALL_MASK;
  1941. if (!hw->err_cap)
  1942. msk &= ~Y2_IS_PCI_EXP;
  1943. sky2_write32(hw, B0_HWE_IMSK, msk);
  1944. for (i = 0; i < hw->ports; i++)
  1945. sky2_gmac_reset(hw, i);
  1946. memset(hw->st_le, 0, STATUS_LE_BYTES);
  1947. hw->st_idx = 0;
  1948. sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
  1949. sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
  1950. sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
  1951. sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
  1952. /* Set the list last index */
  1953. sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
  1954. sky2_write16(hw, STAT_TX_IDX_TH, 10);
  1955. sky2_write8(hw, STAT_FIFO_WM, 16);
  1956. /* set Status-FIFO ISR watermark */
  1957. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
  1958. sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
  1959. else
  1960. sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
  1961. sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
  1962. sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
  1963. sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
  1964. /* enable status unit */
  1965. sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
  1966. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  1967. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
  1968. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
  1969. return 0;
  1970. }
  1971. static u32 sky2_supported_modes(const struct sky2_hw *hw)
  1972. {
  1973. if (sky2_is_copper(hw)) {
  1974. u32 modes = SUPPORTED_10baseT_Half
  1975. | SUPPORTED_10baseT_Full
  1976. | SUPPORTED_100baseT_Half
  1977. | SUPPORTED_100baseT_Full
  1978. | SUPPORTED_Autoneg | SUPPORTED_TP;
  1979. if (hw->chip_id != CHIP_ID_YUKON_FE)
  1980. modes |= SUPPORTED_1000baseT_Half
  1981. | SUPPORTED_1000baseT_Full;
  1982. return modes;
  1983. } else
  1984. return SUPPORTED_1000baseT_Half
  1985. | SUPPORTED_1000baseT_Full
  1986. | SUPPORTED_Autoneg
  1987. | SUPPORTED_FIBRE;
  1988. }
  1989. static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  1990. {
  1991. struct sky2_port *sky2 = netdev_priv(dev);
  1992. struct sky2_hw *hw = sky2->hw;
  1993. ecmd->transceiver = XCVR_INTERNAL;
  1994. ecmd->supported = sky2_supported_modes(hw);
  1995. ecmd->phy_address = PHY_ADDR_MARV;
  1996. if (sky2_is_copper(hw)) {
  1997. ecmd->supported = SUPPORTED_10baseT_Half
  1998. | SUPPORTED_10baseT_Full
  1999. | SUPPORTED_100baseT_Half
  2000. | SUPPORTED_100baseT_Full
  2001. | SUPPORTED_1000baseT_Half
  2002. | SUPPORTED_1000baseT_Full
  2003. | SUPPORTED_Autoneg | SUPPORTED_TP;
  2004. ecmd->port = PORT_TP;
  2005. ecmd->speed = sky2->speed;
  2006. } else {
  2007. ecmd->speed = SPEED_1000;
  2008. ecmd->port = PORT_FIBRE;
  2009. }
  2010. ecmd->advertising = sky2->advertising;
  2011. ecmd->autoneg = sky2->autoneg;
  2012. ecmd->duplex = sky2->duplex;
  2013. return 0;
  2014. }
  2015. static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  2016. {
  2017. struct sky2_port *sky2 = netdev_priv(dev);
  2018. const struct sky2_hw *hw = sky2->hw;
  2019. u32 supported = sky2_supported_modes(hw);
  2020. if (ecmd->autoneg == AUTONEG_ENABLE) {
  2021. ecmd->advertising = supported;
  2022. sky2->duplex = -1;
  2023. sky2->speed = -1;
  2024. } else {
  2025. u32 setting;
  2026. switch (ecmd->speed) {
  2027. case SPEED_1000:
  2028. if (ecmd->duplex == DUPLEX_FULL)
  2029. setting = SUPPORTED_1000baseT_Full;
  2030. else if (ecmd->duplex == DUPLEX_HALF)
  2031. setting = SUPPORTED_1000baseT_Half;
  2032. else
  2033. return -EINVAL;
  2034. break;
  2035. case SPEED_100:
  2036. if (ecmd->duplex == DUPLEX_FULL)
  2037. setting = SUPPORTED_100baseT_Full;
  2038. else if (ecmd->duplex == DUPLEX_HALF)
  2039. setting = SUPPORTED_100baseT_Half;
  2040. else
  2041. return -EINVAL;
  2042. break;
  2043. case SPEED_10:
  2044. if (ecmd->duplex == DUPLEX_FULL)
  2045. setting = SUPPORTED_10baseT_Full;
  2046. else if (ecmd->duplex == DUPLEX_HALF)
  2047. setting = SUPPORTED_10baseT_Half;
  2048. else
  2049. return -EINVAL;
  2050. break;
  2051. default:
  2052. return -EINVAL;
  2053. }
  2054. if ((setting & supported) == 0)
  2055. return -EINVAL;
  2056. sky2->speed = ecmd->speed;
  2057. sky2->duplex = ecmd->duplex;
  2058. }
  2059. sky2->autoneg = ecmd->autoneg;
  2060. sky2->advertising = ecmd->advertising;
  2061. if (netif_running(dev))
  2062. sky2_phy_reinit(sky2);
  2063. return 0;
  2064. }
  2065. static void sky2_get_drvinfo(struct net_device *dev,
  2066. struct ethtool_drvinfo *info)
  2067. {
  2068. struct sky2_port *sky2 = netdev_priv(dev);
  2069. strcpy(info->driver, DRV_NAME);
  2070. strcpy(info->version, DRV_VERSION);
  2071. strcpy(info->fw_version, "N/A");
  2072. strcpy(info->bus_info, pci_name(sky2->hw->pdev));
  2073. }
  2074. static const struct sky2_stat {
  2075. char name[ETH_GSTRING_LEN];
  2076. u16 offset;
  2077. } sky2_stats[] = {
  2078. { "tx_bytes", GM_TXO_OK_HI },
  2079. { "rx_bytes", GM_RXO_OK_HI },
  2080. { "tx_broadcast", GM_TXF_BC_OK },
  2081. { "rx_broadcast", GM_RXF_BC_OK },
  2082. { "tx_multicast", GM_TXF_MC_OK },
  2083. { "rx_multicast", GM_RXF_MC_OK },
  2084. { "tx_unicast", GM_TXF_UC_OK },
  2085. { "rx_unicast", GM_RXF_UC_OK },
  2086. { "tx_mac_pause", GM_TXF_MPAUSE },
  2087. { "rx_mac_pause", GM_RXF_MPAUSE },
  2088. { "collisions", GM_TXF_COL },
  2089. { "late_collision",GM_TXF_LAT_COL },
  2090. { "aborted", GM_TXF_ABO_COL },
  2091. { "single_collisions", GM_TXF_SNG_COL },
  2092. { "multi_collisions", GM_TXF_MUL_COL },
  2093. { "rx_short", GM_RXF_SHT },
  2094. { "rx_runt", GM_RXE_FRAG },
  2095. { "rx_64_byte_packets", GM_RXF_64B },
  2096. { "rx_65_to_127_byte_packets", GM_RXF_127B },
  2097. { "rx_128_to_255_byte_packets", GM_RXF_255B },
  2098. { "rx_256_to_511_byte_packets", GM_RXF_511B },
  2099. { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
  2100. { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
  2101. { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
  2102. { "rx_too_long", GM_RXF_LNG_ERR },
  2103. { "rx_fifo_overflow", GM_RXE_FIFO_OV },
  2104. { "rx_jabber", GM_RXF_JAB_PKT },
  2105. { "rx_fcs_error", GM_RXF_FCS_ERR },
  2106. { "tx_64_byte_packets", GM_TXF_64B },
  2107. { "tx_65_to_127_byte_packets", GM_TXF_127B },
  2108. { "tx_128_to_255_byte_packets", GM_TXF_255B },
  2109. { "tx_256_to_511_byte_packets", GM_TXF_511B },
  2110. { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
  2111. { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
  2112. { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
  2113. { "tx_fifo_underrun", GM_TXE_FIFO_UR },
  2114. };
  2115. static u32 sky2_get_rx_csum(struct net_device *dev)
  2116. {
  2117. struct sky2_port *sky2 = netdev_priv(dev);
  2118. return sky2->rx_csum;
  2119. }
  2120. static int sky2_set_rx_csum(struct net_device *dev, u32 data)
  2121. {
  2122. struct sky2_port *sky2 = netdev_priv(dev);
  2123. sky2->rx_csum = data;
  2124. sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  2125. data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
  2126. return 0;
  2127. }
  2128. static u32 sky2_get_msglevel(struct net_device *netdev)
  2129. {
  2130. struct sky2_port *sky2 = netdev_priv(netdev);
  2131. return sky2->msg_enable;
  2132. }
  2133. static int sky2_nway_reset(struct net_device *dev)
  2134. {
  2135. struct sky2_port *sky2 = netdev_priv(dev);
  2136. if (sky2->autoneg != AUTONEG_ENABLE)
  2137. return -EINVAL;
  2138. sky2_phy_reinit(sky2);
  2139. return 0;
  2140. }
  2141. static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
  2142. {
  2143. struct sky2_hw *hw = sky2->hw;
  2144. unsigned port = sky2->port;
  2145. int i;
  2146. data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
  2147. | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
  2148. data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
  2149. | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
  2150. for (i = 2; i < count; i++)
  2151. data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
  2152. }
  2153. static void sky2_set_msglevel(struct net_device *netdev, u32 value)
  2154. {
  2155. struct sky2_port *sky2 = netdev_priv(netdev);
  2156. sky2->msg_enable = value;
  2157. }
  2158. static int sky2_get_stats_count(struct net_device *dev)
  2159. {
  2160. return ARRAY_SIZE(sky2_stats);
  2161. }
  2162. static void sky2_get_ethtool_stats(struct net_device *dev,
  2163. struct ethtool_stats *stats, u64 * data)
  2164. {
  2165. struct sky2_port *sky2 = netdev_priv(dev);
  2166. sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
  2167. }
  2168. static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
  2169. {
  2170. int i;
  2171. switch (stringset) {
  2172. case ETH_SS_STATS:
  2173. for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
  2174. memcpy(data + i * ETH_GSTRING_LEN,
  2175. sky2_stats[i].name, ETH_GSTRING_LEN);
  2176. break;
  2177. }
  2178. }
  2179. /* Use hardware MIB variables for critical path statistics and
  2180. * transmit feedback not reported at interrupt.
  2181. * Other errors are accounted for in interrupt handler.
  2182. */
  2183. static struct net_device_stats *sky2_get_stats(struct net_device *dev)
  2184. {
  2185. struct sky2_port *sky2 = netdev_priv(dev);
  2186. u64 data[13];
  2187. sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
  2188. sky2->net_stats.tx_bytes = data[0];
  2189. sky2->net_stats.rx_bytes = data[1];
  2190. sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
  2191. sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
  2192. sky2->net_stats.multicast = data[3] + data[5];
  2193. sky2->net_stats.collisions = data[10];
  2194. sky2->net_stats.tx_aborted_errors = data[12];
  2195. return &sky2->net_stats;
  2196. }
  2197. static int sky2_set_mac_address(struct net_device *dev, void *p)
  2198. {
  2199. struct sky2_port *sky2 = netdev_priv(dev);
  2200. struct sky2_hw *hw = sky2->hw;
  2201. unsigned port = sky2->port;
  2202. const struct sockaddr *addr = p;
  2203. if (!is_valid_ether_addr(addr->sa_data))
  2204. return -EADDRNOTAVAIL;
  2205. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  2206. memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
  2207. dev->dev_addr, ETH_ALEN);
  2208. memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
  2209. dev->dev_addr, ETH_ALEN);
  2210. /* virtual address for data */
  2211. gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
  2212. /* physical address: used for pause frames */
  2213. gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
  2214. return 0;
  2215. }
  2216. static void sky2_set_multicast(struct net_device *dev)
  2217. {
  2218. struct sky2_port *sky2 = netdev_priv(dev);
  2219. struct sky2_hw *hw = sky2->hw;
  2220. unsigned port = sky2->port;
  2221. struct dev_mc_list *list = dev->mc_list;
  2222. u16 reg;
  2223. u8 filter[8];
  2224. memset(filter, 0, sizeof(filter));
  2225. reg = gma_read16(hw, port, GM_RX_CTRL);
  2226. reg |= GM_RXCR_UCF_ENA;
  2227. if (dev->flags & IFF_PROMISC) /* promiscuous */
  2228. reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  2229. else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
  2230. memset(filter, 0xff, sizeof(filter));
  2231. else if (dev->mc_count == 0) /* no multicast */
  2232. reg &= ~GM_RXCR_MCF_ENA;
  2233. else {
  2234. int i;
  2235. reg |= GM_RXCR_MCF_ENA;
  2236. for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
  2237. u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
  2238. filter[bit / 8] |= 1 << (bit % 8);
  2239. }
  2240. }
  2241. gma_write16(hw, port, GM_MC_ADDR_H1,
  2242. (u16) filter[0] | ((u16) filter[1] << 8));
  2243. gma_write16(hw, port, GM_MC_ADDR_H2,
  2244. (u16) filter[2] | ((u16) filter[3] << 8));
  2245. gma_write16(hw, port, GM_MC_ADDR_H3,
  2246. (u16) filter[4] | ((u16) filter[5] << 8));
  2247. gma_write16(hw, port, GM_MC_ADDR_H4,
  2248. (u16) filter[6] | ((u16) filter[7] << 8));
  2249. gma_write16(hw, port, GM_RX_CTRL, reg);
  2250. }
  2251. /* Can have one global because blinking is controlled by
  2252. * ethtool and that is always under RTNL mutex
  2253. */
  2254. static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
  2255. {
  2256. u16 pg;
  2257. switch (hw->chip_id) {
  2258. case CHIP_ID_YUKON_XL:
  2259. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  2260. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  2261. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  2262. on ? (PHY_M_LEDC_LOS_CTRL(1) |
  2263. PHY_M_LEDC_INIT_CTRL(7) |
  2264. PHY_M_LEDC_STA1_CTRL(7) |
  2265. PHY_M_LEDC_STA0_CTRL(7))
  2266. : 0);
  2267. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  2268. break;
  2269. default:
  2270. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
  2271. gm_phy_write(hw, port, PHY_MARV_LED_OVER,
  2272. on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
  2273. PHY_M_LED_MO_10(MO_LED_ON) |
  2274. PHY_M_LED_MO_100(MO_LED_ON) |
  2275. PHY_M_LED_MO_1000(MO_LED_ON) |
  2276. PHY_M_LED_MO_RX(MO_LED_ON)
  2277. : PHY_M_LED_MO_DUP(MO_LED_OFF) |
  2278. PHY_M_LED_MO_10(MO_LED_OFF) |
  2279. PHY_M_LED_MO_100(MO_LED_OFF) |
  2280. PHY_M_LED_MO_1000(MO_LED_OFF) |
  2281. PHY_M_LED_MO_RX(MO_LED_OFF));
  2282. }
  2283. }
  2284. /* blink LED's for finding board */
  2285. static int sky2_phys_id(struct net_device *dev, u32 data)
  2286. {
  2287. struct sky2_port *sky2 = netdev_priv(dev);
  2288. struct sky2_hw *hw = sky2->hw;
  2289. unsigned port = sky2->port;
  2290. u16 ledctrl, ledover = 0;
  2291. long ms;
  2292. int interrupted;
  2293. int onoff = 1;
  2294. if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
  2295. ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
  2296. else
  2297. ms = data * 1000;
  2298. /* save initial values */
  2299. spin_lock_bh(&sky2->phy_lock);
  2300. if (hw->chip_id == CHIP_ID_YUKON_XL) {
  2301. u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  2302. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  2303. ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  2304. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  2305. } else {
  2306. ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
  2307. ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
  2308. }
  2309. interrupted = 0;
  2310. while (!interrupted && ms > 0) {
  2311. sky2_led(hw, port, onoff);
  2312. onoff = !onoff;
  2313. spin_unlock_bh(&sky2->phy_lock);
  2314. interrupted = msleep_interruptible(250);
  2315. spin_lock_bh(&sky2->phy_lock);
  2316. ms -= 250;
  2317. }
  2318. /* resume regularly scheduled programming */
  2319. if (hw->chip_id == CHIP_ID_YUKON_XL) {
  2320. u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  2321. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  2322. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
  2323. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  2324. } else {
  2325. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
  2326. gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
  2327. }
  2328. spin_unlock_bh(&sky2->phy_lock);
  2329. return 0;
  2330. }
  2331. static void sky2_get_pauseparam(struct net_device *dev,
  2332. struct ethtool_pauseparam *ecmd)
  2333. {
  2334. struct sky2_port *sky2 = netdev_priv(dev);
  2335. ecmd->tx_pause = sky2->tx_pause;
  2336. ecmd->rx_pause = sky2->rx_pause;
  2337. ecmd->autoneg = sky2->autoneg;
  2338. }
  2339. static int sky2_set_pauseparam(struct net_device *dev,
  2340. struct ethtool_pauseparam *ecmd)
  2341. {
  2342. struct sky2_port *sky2 = netdev_priv(dev);
  2343. sky2->autoneg = ecmd->autoneg;
  2344. sky2->tx_pause = ecmd->tx_pause != 0;
  2345. sky2->rx_pause = ecmd->rx_pause != 0;
  2346. sky2_phy_reinit(sky2);
  2347. return 0;
  2348. }
  2349. static int sky2_get_coalesce(struct net_device *dev,
  2350. struct ethtool_coalesce *ecmd)
  2351. {
  2352. struct sky2_port *sky2 = netdev_priv(dev);
  2353. struct sky2_hw *hw = sky2->hw;
  2354. if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
  2355. ecmd->tx_coalesce_usecs = 0;
  2356. else {
  2357. u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
  2358. ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
  2359. }
  2360. ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
  2361. if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
  2362. ecmd->rx_coalesce_usecs = 0;
  2363. else {
  2364. u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
  2365. ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
  2366. }
  2367. ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
  2368. if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
  2369. ecmd->rx_coalesce_usecs_irq = 0;
  2370. else {
  2371. u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
  2372. ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
  2373. }
  2374. ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
  2375. return 0;
  2376. }
  2377. /* Note: this affect both ports */
  2378. static int sky2_set_coalesce(struct net_device *dev,
  2379. struct ethtool_coalesce *ecmd)
  2380. {
  2381. struct sky2_port *sky2 = netdev_priv(dev);
  2382. struct sky2_hw *hw = sky2->hw;
  2383. const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
  2384. if (ecmd->tx_coalesce_usecs > tmax ||
  2385. ecmd->rx_coalesce_usecs > tmax ||
  2386. ecmd->rx_coalesce_usecs_irq > tmax)
  2387. return -EINVAL;
  2388. if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
  2389. return -EINVAL;
  2390. if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
  2391. return -EINVAL;
  2392. if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
  2393. return -EINVAL;
  2394. if (ecmd->tx_coalesce_usecs == 0)
  2395. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
  2396. else {
  2397. sky2_write32(hw, STAT_TX_TIMER_INI,
  2398. sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
  2399. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  2400. }
  2401. sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
  2402. if (ecmd->rx_coalesce_usecs == 0)
  2403. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
  2404. else {
  2405. sky2_write32(hw, STAT_LEV_TIMER_INI,
  2406. sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
  2407. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
  2408. }
  2409. sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
  2410. if (ecmd->rx_coalesce_usecs_irq == 0)
  2411. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
  2412. else {
  2413. sky2_write32(hw, STAT_ISR_TIMER_INI,
  2414. sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
  2415. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
  2416. }
  2417. sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
  2418. return 0;
  2419. }
  2420. static void sky2_get_ringparam(struct net_device *dev,
  2421. struct ethtool_ringparam *ering)
  2422. {
  2423. struct sky2_port *sky2 = netdev_priv(dev);
  2424. ering->rx_max_pending = RX_MAX_PENDING;
  2425. ering->rx_mini_max_pending = 0;
  2426. ering->rx_jumbo_max_pending = 0;
  2427. ering->tx_max_pending = TX_RING_SIZE - 1;
  2428. ering->rx_pending = sky2->rx_pending;
  2429. ering->rx_mini_pending = 0;
  2430. ering->rx_jumbo_pending = 0;
  2431. ering->tx_pending = sky2->tx_pending;
  2432. }
  2433. static int sky2_set_ringparam(struct net_device *dev,
  2434. struct ethtool_ringparam *ering)
  2435. {
  2436. struct sky2_port *sky2 = netdev_priv(dev);
  2437. int err = 0;
  2438. if (ering->rx_pending > RX_MAX_PENDING ||
  2439. ering->rx_pending < 8 ||
  2440. ering->tx_pending < MAX_SKB_TX_LE ||
  2441. ering->tx_pending > TX_RING_SIZE - 1)
  2442. return -EINVAL;
  2443. if (netif_running(dev))
  2444. sky2_down(dev);
  2445. sky2->rx_pending = ering->rx_pending;
  2446. sky2->tx_pending = ering->tx_pending;
  2447. if (netif_running(dev)) {
  2448. err = sky2_up(dev);
  2449. if (err)
  2450. dev_close(dev);
  2451. else
  2452. sky2_set_multicast(dev);
  2453. }
  2454. return err;
  2455. }
  2456. static int sky2_get_regs_len(struct net_device *dev)
  2457. {
  2458. return 0x4000;
  2459. }
  2460. /*
  2461. * Returns copy of control register region
  2462. * Note: access to the RAM address register set will cause timeouts.
  2463. */
  2464. static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
  2465. void *p)
  2466. {
  2467. const struct sky2_port *sky2 = netdev_priv(dev);
  2468. const void __iomem *io = sky2->hw->regs;
  2469. BUG_ON(regs->len < B3_RI_WTO_R1);
  2470. regs->version = 1;
  2471. memset(p, 0, regs->len);
  2472. memcpy_fromio(p, io, B3_RAM_ADDR);
  2473. memcpy_fromio(p + B3_RI_WTO_R1,
  2474. io + B3_RI_WTO_R1,
  2475. regs->len - B3_RI_WTO_R1);
  2476. }
  2477. static const struct ethtool_ops sky2_ethtool_ops = {
  2478. .get_settings = sky2_get_settings,
  2479. .set_settings = sky2_set_settings,
  2480. .get_drvinfo = sky2_get_drvinfo,
  2481. .get_msglevel = sky2_get_msglevel,
  2482. .set_msglevel = sky2_set_msglevel,
  2483. .nway_reset = sky2_nway_reset,
  2484. .get_regs_len = sky2_get_regs_len,
  2485. .get_regs = sky2_get_regs,
  2486. .get_link = ethtool_op_get_link,
  2487. .get_sg = ethtool_op_get_sg,
  2488. .set_sg = ethtool_op_set_sg,
  2489. .get_tx_csum = ethtool_op_get_tx_csum,
  2490. .set_tx_csum = ethtool_op_set_tx_csum,
  2491. .get_tso = ethtool_op_get_tso,
  2492. .set_tso = ethtool_op_set_tso,
  2493. .get_rx_csum = sky2_get_rx_csum,
  2494. .set_rx_csum = sky2_set_rx_csum,
  2495. .get_strings = sky2_get_strings,
  2496. .get_coalesce = sky2_get_coalesce,
  2497. .set_coalesce = sky2_set_coalesce,
  2498. .get_ringparam = sky2_get_ringparam,
  2499. .set_ringparam = sky2_set_ringparam,
  2500. .get_pauseparam = sky2_get_pauseparam,
  2501. .set_pauseparam = sky2_set_pauseparam,
  2502. .phys_id = sky2_phys_id,
  2503. .get_stats_count = sky2_get_stats_count,
  2504. .get_ethtool_stats = sky2_get_ethtool_stats,
  2505. .get_perm_addr = ethtool_op_get_perm_addr,
  2506. };
  2507. /* Initialize network device */
  2508. static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
  2509. unsigned port, int highmem)
  2510. {
  2511. struct sky2_port *sky2;
  2512. struct net_device *dev = alloc_etherdev(sizeof(*sky2));
  2513. if (!dev) {
  2514. printk(KERN_ERR "sky2 etherdev alloc failed");
  2515. return NULL;
  2516. }
  2517. SET_MODULE_OWNER(dev);
  2518. SET_NETDEV_DEV(dev, &hw->pdev->dev);
  2519. dev->irq = hw->pdev->irq;
  2520. dev->open = sky2_up;
  2521. dev->stop = sky2_down;
  2522. dev->do_ioctl = sky2_ioctl;
  2523. dev->hard_start_xmit = sky2_xmit_frame;
  2524. dev->get_stats = sky2_get_stats;
  2525. dev->set_multicast_list = sky2_set_multicast;
  2526. dev->set_mac_address = sky2_set_mac_address;
  2527. dev->change_mtu = sky2_change_mtu;
  2528. SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
  2529. dev->tx_timeout = sky2_tx_timeout;
  2530. dev->watchdog_timeo = TX_WATCHDOG;
  2531. if (port == 0)
  2532. dev->poll = sky2_poll;
  2533. dev->weight = NAPI_WEIGHT;
  2534. #ifdef CONFIG_NET_POLL_CONTROLLER
  2535. dev->poll_controller = sky2_netpoll;
  2536. #endif
  2537. sky2 = netdev_priv(dev);
  2538. sky2->netdev = dev;
  2539. sky2->hw = hw;
  2540. sky2->msg_enable = netif_msg_init(debug, default_msg);
  2541. spin_lock_init(&sky2->tx_lock);
  2542. /* Auto speed and flow control */
  2543. sky2->autoneg = AUTONEG_ENABLE;
  2544. sky2->tx_pause = 1;
  2545. sky2->rx_pause = 1;
  2546. sky2->duplex = -1;
  2547. sky2->speed = -1;
  2548. sky2->advertising = sky2_supported_modes(hw);
  2549. sky2->rx_csum = 1;
  2550. spin_lock_init(&sky2->phy_lock);
  2551. sky2->tx_pending = TX_DEF_PENDING;
  2552. sky2->rx_pending = RX_DEF_PENDING;
  2553. sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
  2554. hw->dev[port] = dev;
  2555. sky2->port = port;
  2556. dev->features |= NETIF_F_LLTX;
  2557. if (hw->chip_id != CHIP_ID_YUKON_EC_U)
  2558. dev->features |= NETIF_F_TSO;
  2559. if (highmem)
  2560. dev->features |= NETIF_F_HIGHDMA;
  2561. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  2562. #ifdef SKY2_VLAN_TAG_USED
  2563. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  2564. dev->vlan_rx_register = sky2_vlan_rx_register;
  2565. dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
  2566. #endif
  2567. /* read the mac address */
  2568. memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
  2569. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  2570. /* device is off until link detection */
  2571. netif_carrier_off(dev);
  2572. netif_stop_queue(dev);
  2573. return dev;
  2574. }
  2575. static void __devinit sky2_show_addr(struct net_device *dev)
  2576. {
  2577. const struct sky2_port *sky2 = netdev_priv(dev);
  2578. if (netif_msg_probe(sky2))
  2579. printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
  2580. dev->name,
  2581. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  2582. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
  2583. }
  2584. /* Handle software interrupt used during MSI test */
  2585. static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
  2586. struct pt_regs *regs)
  2587. {
  2588. struct sky2_hw *hw = dev_id;
  2589. u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
  2590. if (status == 0)
  2591. return IRQ_NONE;
  2592. if (status & Y2_IS_IRQ_SW) {
  2593. hw->msi_detected = 1;
  2594. wake_up(&hw->msi_wait);
  2595. sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
  2596. }
  2597. sky2_write32(hw, B0_Y2_SP_ICR, 2);
  2598. return IRQ_HANDLED;
  2599. }
  2600. /* Test interrupt path by forcing a a software IRQ */
  2601. static int __devinit sky2_test_msi(struct sky2_hw *hw)
  2602. {
  2603. struct pci_dev *pdev = hw->pdev;
  2604. int err;
  2605. init_waitqueue_head (&hw->msi_wait);
  2606. sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
  2607. err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
  2608. if (err) {
  2609. printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
  2610. pci_name(pdev), pdev->irq);
  2611. return err;
  2612. }
  2613. sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
  2614. sky2_read8(hw, B0_CTST);
  2615. wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
  2616. if (!hw->msi_detected) {
  2617. /* MSI test failed, go back to INTx mode */
  2618. printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
  2619. "switching to INTx mode. Please report this failure to "
  2620. "the PCI maintainer and include system chipset information.\n",
  2621. pci_name(pdev));
  2622. err = -EOPNOTSUPP;
  2623. sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
  2624. }
  2625. sky2_write32(hw, B0_IMSK, 0);
  2626. free_irq(pdev->irq, hw);
  2627. return err;
  2628. }
  2629. static int __devinit sky2_probe(struct pci_dev *pdev,
  2630. const struct pci_device_id *ent)
  2631. {
  2632. struct net_device *dev, *dev1 = NULL;
  2633. struct sky2_hw *hw;
  2634. int err, pm_cap, using_dac = 0;
  2635. err = pci_enable_device(pdev);
  2636. if (err) {
  2637. printk(KERN_ERR PFX "%s cannot enable PCI device\n",
  2638. pci_name(pdev));
  2639. goto err_out;
  2640. }
  2641. err = pci_request_regions(pdev, DRV_NAME);
  2642. if (err) {
  2643. printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
  2644. pci_name(pdev));
  2645. goto err_out;
  2646. }
  2647. pci_set_master(pdev);
  2648. /* Find power-management capability. */
  2649. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  2650. if (pm_cap == 0) {
  2651. printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
  2652. "aborting.\n");
  2653. err = -EIO;
  2654. goto err_out_free_regions;
  2655. }
  2656. if (sizeof(dma_addr_t) > sizeof(u32) &&
  2657. !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
  2658. using_dac = 1;
  2659. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  2660. if (err < 0) {
  2661. printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
  2662. "for consistent allocations\n", pci_name(pdev));
  2663. goto err_out_free_regions;
  2664. }
  2665. } else {
  2666. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  2667. if (err) {
  2668. printk(KERN_ERR PFX "%s no usable DMA configuration\n",
  2669. pci_name(pdev));
  2670. goto err_out_free_regions;
  2671. }
  2672. }
  2673. err = -ENOMEM;
  2674. hw = kzalloc(sizeof(*hw), GFP_KERNEL);
  2675. if (!hw) {
  2676. printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
  2677. pci_name(pdev));
  2678. goto err_out_free_regions;
  2679. }
  2680. hw->pdev = pdev;
  2681. hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
  2682. if (!hw->regs) {
  2683. printk(KERN_ERR PFX "%s: cannot map device registers\n",
  2684. pci_name(pdev));
  2685. goto err_out_free_hw;
  2686. }
  2687. hw->pm_cap = pm_cap;
  2688. #ifdef __BIG_ENDIAN
  2689. /* The sk98lin vendor driver uses hardware byte swapping but
  2690. * this driver uses software swapping.
  2691. */
  2692. {
  2693. u32 reg;
  2694. reg = sky2_pci_read32(hw, PCI_DEV_REG2);
  2695. reg &= ~PCI_REV_DESC;
  2696. sky2_pci_write32(hw, PCI_DEV_REG2, reg);
  2697. }
  2698. #endif
  2699. /* ring for status responses */
  2700. hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
  2701. &hw->st_dma);
  2702. if (!hw->st_le)
  2703. goto err_out_iounmap;
  2704. err = sky2_reset(hw);
  2705. if (err)
  2706. goto err_out_iounmap;
  2707. printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
  2708. DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
  2709. pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
  2710. hw->chip_id, hw->chip_rev);
  2711. dev = sky2_init_netdev(hw, 0, using_dac);
  2712. if (!dev)
  2713. goto err_out_free_pci;
  2714. if (!disable_msi && pci_enable_msi(pdev) == 0) {
  2715. err = sky2_test_msi(hw);
  2716. if (err == -EOPNOTSUPP)
  2717. pci_disable_msi(pdev);
  2718. else if (err)
  2719. goto err_out_free_netdev;
  2720. }
  2721. err = register_netdev(dev);
  2722. if (err) {
  2723. printk(KERN_ERR PFX "%s: cannot register net device\n",
  2724. pci_name(pdev));
  2725. goto err_out_free_netdev;
  2726. }
  2727. err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, dev->name, hw);
  2728. if (err) {
  2729. printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
  2730. pci_name(pdev), pdev->irq);
  2731. goto err_out_unregister;
  2732. }
  2733. sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
  2734. sky2_show_addr(dev);
  2735. if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
  2736. if (register_netdev(dev1) == 0)
  2737. sky2_show_addr(dev1);
  2738. else {
  2739. /* Failure to register second port need not be fatal */
  2740. printk(KERN_WARNING PFX
  2741. "register of second port failed\n");
  2742. hw->dev[1] = NULL;
  2743. free_netdev(dev1);
  2744. }
  2745. }
  2746. setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
  2747. sky2_idle_start(hw);
  2748. pci_set_drvdata(pdev, hw);
  2749. return 0;
  2750. err_out_unregister:
  2751. pci_disable_msi(pdev);
  2752. unregister_netdev(dev);
  2753. err_out_free_netdev:
  2754. free_netdev(dev);
  2755. err_out_free_pci:
  2756. sky2_write8(hw, B0_CTST, CS_RST_SET);
  2757. pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
  2758. err_out_iounmap:
  2759. iounmap(hw->regs);
  2760. err_out_free_hw:
  2761. kfree(hw);
  2762. err_out_free_regions:
  2763. pci_release_regions(pdev);
  2764. pci_disable_device(pdev);
  2765. err_out:
  2766. return err;
  2767. }
  2768. static void __devexit sky2_remove(struct pci_dev *pdev)
  2769. {
  2770. struct sky2_hw *hw = pci_get_drvdata(pdev);
  2771. struct net_device *dev0, *dev1;
  2772. if (!hw)
  2773. return;
  2774. del_timer_sync(&hw->idle_timer);
  2775. sky2_write32(hw, B0_IMSK, 0);
  2776. synchronize_irq(hw->pdev->irq);
  2777. dev0 = hw->dev[0];
  2778. dev1 = hw->dev[1];
  2779. if (dev1)
  2780. unregister_netdev(dev1);
  2781. unregister_netdev(dev0);
  2782. sky2_set_power_state(hw, PCI_D3hot);
  2783. sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
  2784. sky2_write8(hw, B0_CTST, CS_RST_SET);
  2785. sky2_read8(hw, B0_CTST);
  2786. free_irq(pdev->irq, hw);
  2787. pci_disable_msi(pdev);
  2788. pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
  2789. pci_release_regions(pdev);
  2790. pci_disable_device(pdev);
  2791. if (dev1)
  2792. free_netdev(dev1);
  2793. free_netdev(dev0);
  2794. iounmap(hw->regs);
  2795. kfree(hw);
  2796. pci_set_drvdata(pdev, NULL);
  2797. }
  2798. #ifdef CONFIG_PM
  2799. static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
  2800. {
  2801. struct sky2_hw *hw = pci_get_drvdata(pdev);
  2802. int i;
  2803. pci_power_t pstate = pci_choose_state(pdev, state);
  2804. if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
  2805. return -EINVAL;
  2806. del_timer_sync(&hw->idle_timer);
  2807. netif_poll_disable(hw->dev[0]);
  2808. for (i = 0; i < hw->ports; i++) {
  2809. struct net_device *dev = hw->dev[i];
  2810. if (netif_running(dev)) {
  2811. sky2_down(dev);
  2812. netif_device_detach(dev);
  2813. }
  2814. }
  2815. sky2_write32(hw, B0_IMSK, 0);
  2816. pci_save_state(pdev);
  2817. sky2_set_power_state(hw, pstate);
  2818. return 0;
  2819. }
  2820. static int sky2_resume(struct pci_dev *pdev)
  2821. {
  2822. struct sky2_hw *hw = pci_get_drvdata(pdev);
  2823. int i, err;
  2824. pci_restore_state(pdev);
  2825. pci_enable_wake(pdev, PCI_D0, 0);
  2826. sky2_set_power_state(hw, PCI_D0);
  2827. err = sky2_reset(hw);
  2828. if (err)
  2829. goto out;
  2830. sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
  2831. for (i = 0; i < hw->ports; i++) {
  2832. struct net_device *dev = hw->dev[i];
  2833. if (netif_running(dev)) {
  2834. netif_device_attach(dev);
  2835. err = sky2_up(dev);
  2836. if (err) {
  2837. printk(KERN_ERR PFX "%s: could not up: %d\n",
  2838. dev->name, err);
  2839. dev_close(dev);
  2840. goto out;
  2841. }
  2842. }
  2843. }
  2844. netif_poll_enable(hw->dev[0]);
  2845. sky2_idle_start(hw);
  2846. out:
  2847. return err;
  2848. }
  2849. #endif
  2850. static struct pci_driver sky2_driver = {
  2851. .name = DRV_NAME,
  2852. .id_table = sky2_id_table,
  2853. .probe = sky2_probe,
  2854. .remove = __devexit_p(sky2_remove),
  2855. #ifdef CONFIG_PM
  2856. .suspend = sky2_suspend,
  2857. .resume = sky2_resume,
  2858. #endif
  2859. };
  2860. static int __init sky2_init_module(void)
  2861. {
  2862. return pci_register_driver(&sky2_driver);
  2863. }
  2864. static void __exit sky2_cleanup_module(void)
  2865. {
  2866. pci_unregister_driver(&sky2_driver);
  2867. }
  2868. module_init(sky2_init_module);
  2869. module_exit(sky2_cleanup_module);
  2870. MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
  2871. MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
  2872. MODULE_LICENSE("GPL");
  2873. MODULE_VERSION(DRV_VERSION);