qeth_core_main.c 125 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/ipv6.h>
  19. #include <linux/tcp.h>
  20. #include <linux/mii.h>
  21. #include <linux/kthread.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include "qeth_core.h"
  25. #include "qeth_core_offl.h"
  26. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  27. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  28. /* N P A M L V H */
  29. [QETH_DBF_SETUP] = {"qeth_setup",
  30. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_QERR] = {"qeth_qerr",
  32. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  33. [QETH_DBF_TRACE] = {"qeth_trace",
  34. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  35. [QETH_DBF_MSG] = {"qeth_msg",
  36. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  37. [QETH_DBF_SENSE] = {"qeth_sense",
  38. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  39. [QETH_DBF_MISC] = {"qeth_misc",
  40. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  41. [QETH_DBF_CTRL] = {"qeth_control",
  42. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  43. };
  44. EXPORT_SYMBOL_GPL(qeth_dbf);
  45. struct qeth_card_list_struct qeth_core_card_list;
  46. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  47. struct kmem_cache *qeth_core_header_cache;
  48. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  49. static struct device *qeth_core_root_dev;
  50. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  51. static struct lock_class_key qdio_out_skb_queue_key;
  52. static void qeth_send_control_data_cb(struct qeth_channel *,
  53. struct qeth_cmd_buffer *);
  54. static int qeth_issue_next_read(struct qeth_card *);
  55. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  56. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  57. static void qeth_free_buffer_pool(struct qeth_card *);
  58. static int qeth_qdio_establish(struct qeth_card *);
  59. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  60. struct qdio_buffer *buffer, int is_tso,
  61. int *next_element_to_fill)
  62. {
  63. struct skb_frag_struct *frag;
  64. int fragno;
  65. unsigned long addr;
  66. int element, cnt, dlen;
  67. fragno = skb_shinfo(skb)->nr_frags;
  68. element = *next_element_to_fill;
  69. dlen = 0;
  70. if (is_tso)
  71. buffer->element[element].flags =
  72. SBAL_FLAGS_MIDDLE_FRAG;
  73. else
  74. buffer->element[element].flags =
  75. SBAL_FLAGS_FIRST_FRAG;
  76. dlen = skb->len - skb->data_len;
  77. if (dlen) {
  78. buffer->element[element].addr = skb->data;
  79. buffer->element[element].length = dlen;
  80. element++;
  81. }
  82. for (cnt = 0; cnt < fragno; cnt++) {
  83. frag = &skb_shinfo(skb)->frags[cnt];
  84. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  85. frag->page_offset;
  86. buffer->element[element].addr = (char *)addr;
  87. buffer->element[element].length = frag->size;
  88. if (cnt < (fragno - 1))
  89. buffer->element[element].flags =
  90. SBAL_FLAGS_MIDDLE_FRAG;
  91. else
  92. buffer->element[element].flags =
  93. SBAL_FLAGS_LAST_FRAG;
  94. element++;
  95. }
  96. *next_element_to_fill = element;
  97. }
  98. static inline const char *qeth_get_cardname(struct qeth_card *card)
  99. {
  100. if (card->info.guestlan) {
  101. switch (card->info.type) {
  102. case QETH_CARD_TYPE_OSAE:
  103. return " Guest LAN QDIO";
  104. case QETH_CARD_TYPE_IQD:
  105. return " Guest LAN Hiper";
  106. default:
  107. return " unknown";
  108. }
  109. } else {
  110. switch (card->info.type) {
  111. case QETH_CARD_TYPE_OSAE:
  112. return " OSD Express";
  113. case QETH_CARD_TYPE_IQD:
  114. return " HiperSockets";
  115. case QETH_CARD_TYPE_OSN:
  116. return " OSN QDIO";
  117. default:
  118. return " unknown";
  119. }
  120. }
  121. return " n/a";
  122. }
  123. /* max length to be returned: 14 */
  124. const char *qeth_get_cardname_short(struct qeth_card *card)
  125. {
  126. if (card->info.guestlan) {
  127. switch (card->info.type) {
  128. case QETH_CARD_TYPE_OSAE:
  129. return "GuestLAN QDIO";
  130. case QETH_CARD_TYPE_IQD:
  131. return "GuestLAN Hiper";
  132. default:
  133. return "unknown";
  134. }
  135. } else {
  136. switch (card->info.type) {
  137. case QETH_CARD_TYPE_OSAE:
  138. switch (card->info.link_type) {
  139. case QETH_LINK_TYPE_FAST_ETH:
  140. return "OSD_100";
  141. case QETH_LINK_TYPE_HSTR:
  142. return "HSTR";
  143. case QETH_LINK_TYPE_GBIT_ETH:
  144. return "OSD_1000";
  145. case QETH_LINK_TYPE_10GBIT_ETH:
  146. return "OSD_10GIG";
  147. case QETH_LINK_TYPE_LANE_ETH100:
  148. return "OSD_FE_LANE";
  149. case QETH_LINK_TYPE_LANE_TR:
  150. return "OSD_TR_LANE";
  151. case QETH_LINK_TYPE_LANE_ETH1000:
  152. return "OSD_GbE_LANE";
  153. case QETH_LINK_TYPE_LANE:
  154. return "OSD_ATM_LANE";
  155. default:
  156. return "OSD_Express";
  157. }
  158. case QETH_CARD_TYPE_IQD:
  159. return "HiperSockets";
  160. case QETH_CARD_TYPE_OSN:
  161. return "OSN";
  162. default:
  163. return "unknown";
  164. }
  165. }
  166. return "n/a";
  167. }
  168. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  169. int clear_start_mask)
  170. {
  171. unsigned long flags;
  172. spin_lock_irqsave(&card->thread_mask_lock, flags);
  173. card->thread_allowed_mask = threads;
  174. if (clear_start_mask)
  175. card->thread_start_mask &= threads;
  176. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  177. wake_up(&card->wait_q);
  178. }
  179. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  180. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  181. {
  182. unsigned long flags;
  183. int rc = 0;
  184. spin_lock_irqsave(&card->thread_mask_lock, flags);
  185. rc = (card->thread_running_mask & threads);
  186. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  187. return rc;
  188. }
  189. EXPORT_SYMBOL_GPL(qeth_threads_running);
  190. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  191. {
  192. return wait_event_interruptible(card->wait_q,
  193. qeth_threads_running(card, threads) == 0);
  194. }
  195. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  196. void qeth_clear_working_pool_list(struct qeth_card *card)
  197. {
  198. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  199. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  200. list_for_each_entry_safe(pool_entry, tmp,
  201. &card->qdio.in_buf_pool.entry_list, list){
  202. list_del(&pool_entry->list);
  203. }
  204. }
  205. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  206. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  207. {
  208. struct qeth_buffer_pool_entry *pool_entry;
  209. void *ptr;
  210. int i, j;
  211. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  212. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  213. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  214. if (!pool_entry) {
  215. qeth_free_buffer_pool(card);
  216. return -ENOMEM;
  217. }
  218. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  219. ptr = (void *) __get_free_page(GFP_KERNEL);
  220. if (!ptr) {
  221. while (j > 0)
  222. free_page((unsigned long)
  223. pool_entry->elements[--j]);
  224. kfree(pool_entry);
  225. qeth_free_buffer_pool(card);
  226. return -ENOMEM;
  227. }
  228. pool_entry->elements[j] = ptr;
  229. }
  230. list_add(&pool_entry->init_list,
  231. &card->qdio.init_pool.entry_list);
  232. }
  233. return 0;
  234. }
  235. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  236. {
  237. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  238. if ((card->state != CARD_STATE_DOWN) &&
  239. (card->state != CARD_STATE_RECOVER))
  240. return -EPERM;
  241. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  242. qeth_clear_working_pool_list(card);
  243. qeth_free_buffer_pool(card);
  244. card->qdio.in_buf_pool.buf_count = bufcnt;
  245. card->qdio.init_pool.buf_count = bufcnt;
  246. return qeth_alloc_buffer_pool(card);
  247. }
  248. int qeth_set_large_send(struct qeth_card *card,
  249. enum qeth_large_send_types type)
  250. {
  251. int rc = 0;
  252. if (card->dev == NULL) {
  253. card->options.large_send = type;
  254. return 0;
  255. }
  256. if (card->state == CARD_STATE_UP)
  257. netif_tx_disable(card->dev);
  258. card->options.large_send = type;
  259. switch (card->options.large_send) {
  260. case QETH_LARGE_SEND_EDDP:
  261. if (card->info.type != QETH_CARD_TYPE_IQD) {
  262. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  263. NETIF_F_HW_CSUM;
  264. } else {
  265. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  266. NETIF_F_HW_CSUM);
  267. card->options.large_send = QETH_LARGE_SEND_NO;
  268. rc = -EOPNOTSUPP;
  269. }
  270. break;
  271. case QETH_LARGE_SEND_TSO:
  272. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  273. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  274. NETIF_F_HW_CSUM;
  275. } else {
  276. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  277. NETIF_F_HW_CSUM);
  278. card->options.large_send = QETH_LARGE_SEND_NO;
  279. rc = -EOPNOTSUPP;
  280. }
  281. break;
  282. default: /* includes QETH_LARGE_SEND_NO */
  283. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  284. NETIF_F_HW_CSUM);
  285. break;
  286. }
  287. if (card->state == CARD_STATE_UP)
  288. netif_wake_queue(card->dev);
  289. return rc;
  290. }
  291. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  292. static int qeth_issue_next_read(struct qeth_card *card)
  293. {
  294. int rc;
  295. struct qeth_cmd_buffer *iob;
  296. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  297. if (card->read.state != CH_STATE_UP)
  298. return -EIO;
  299. iob = qeth_get_buffer(&card->read);
  300. if (!iob) {
  301. dev_warn(&card->gdev->dev, "The qeth device driver "
  302. "failed to recover an error on the device\n");
  303. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  304. "available\n", dev_name(&card->gdev->dev));
  305. return -ENOMEM;
  306. }
  307. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  308. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  309. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  310. (addr_t) iob, 0, 0);
  311. if (rc) {
  312. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  313. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  314. atomic_set(&card->read.irq_pending, 0);
  315. qeth_schedule_recovery(card);
  316. wake_up(&card->wait_q);
  317. }
  318. return rc;
  319. }
  320. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  321. {
  322. struct qeth_reply *reply;
  323. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  324. if (reply) {
  325. atomic_set(&reply->refcnt, 1);
  326. atomic_set(&reply->received, 0);
  327. reply->card = card;
  328. };
  329. return reply;
  330. }
  331. static void qeth_get_reply(struct qeth_reply *reply)
  332. {
  333. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  334. atomic_inc(&reply->refcnt);
  335. }
  336. static void qeth_put_reply(struct qeth_reply *reply)
  337. {
  338. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  339. if (atomic_dec_and_test(&reply->refcnt))
  340. kfree(reply);
  341. }
  342. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  343. struct qeth_card *card)
  344. {
  345. char *ipa_name;
  346. int com = cmd->hdr.command;
  347. ipa_name = qeth_get_ipa_cmd_name(com);
  348. if (rc)
  349. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  350. ipa_name, com, QETH_CARD_IFNAME(card),
  351. rc, qeth_get_ipa_msg(rc));
  352. else
  353. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  354. ipa_name, com, QETH_CARD_IFNAME(card));
  355. }
  356. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  357. struct qeth_cmd_buffer *iob)
  358. {
  359. struct qeth_ipa_cmd *cmd = NULL;
  360. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  361. if (IS_IPA(iob->data)) {
  362. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  363. if (IS_IPA_REPLY(cmd)) {
  364. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  365. cmd->hdr.command > IPA_CMD_MODCCID)
  366. qeth_issue_ipa_msg(cmd,
  367. cmd->hdr.return_code, card);
  368. return cmd;
  369. } else {
  370. switch (cmd->hdr.command) {
  371. case IPA_CMD_STOPLAN:
  372. dev_warn(&card->gdev->dev,
  373. "The link for interface %s on CHPID"
  374. " 0x%X failed\n",
  375. QETH_CARD_IFNAME(card),
  376. card->info.chpid);
  377. card->lan_online = 0;
  378. if (card->dev && netif_carrier_ok(card->dev))
  379. netif_carrier_off(card->dev);
  380. return NULL;
  381. case IPA_CMD_STARTLAN:
  382. dev_info(&card->gdev->dev,
  383. "The link for %s on CHPID 0x%X has"
  384. " been restored\n",
  385. QETH_CARD_IFNAME(card),
  386. card->info.chpid);
  387. netif_carrier_on(card->dev);
  388. card->lan_online = 1;
  389. qeth_schedule_recovery(card);
  390. return NULL;
  391. case IPA_CMD_MODCCID:
  392. return cmd;
  393. case IPA_CMD_REGISTER_LOCAL_ADDR:
  394. QETH_DBF_TEXT(TRACE, 3, "irla");
  395. break;
  396. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  397. QETH_DBF_TEXT(TRACE, 3, "urla");
  398. break;
  399. default:
  400. QETH_DBF_MESSAGE(2, "Received data is IPA "
  401. "but not a reply!\n");
  402. break;
  403. }
  404. }
  405. }
  406. return cmd;
  407. }
  408. void qeth_clear_ipacmd_list(struct qeth_card *card)
  409. {
  410. struct qeth_reply *reply, *r;
  411. unsigned long flags;
  412. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  413. spin_lock_irqsave(&card->lock, flags);
  414. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  415. qeth_get_reply(reply);
  416. reply->rc = -EIO;
  417. atomic_inc(&reply->received);
  418. list_del_init(&reply->list);
  419. wake_up(&reply->wait_q);
  420. qeth_put_reply(reply);
  421. }
  422. spin_unlock_irqrestore(&card->lock, flags);
  423. }
  424. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  425. static int qeth_check_idx_response(unsigned char *buffer)
  426. {
  427. if (!buffer)
  428. return 0;
  429. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  430. if ((buffer[2] & 0xc0) == 0xc0) {
  431. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  432. "with cause code 0x%02x%s\n",
  433. buffer[4],
  434. ((buffer[4] == 0x22) ?
  435. " -- try another portname" : ""));
  436. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  437. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  438. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  439. return -EIO;
  440. }
  441. return 0;
  442. }
  443. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  444. __u32 len)
  445. {
  446. struct qeth_card *card;
  447. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  448. card = CARD_FROM_CDEV(channel->ccwdev);
  449. if (channel == &card->read)
  450. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  451. else
  452. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  453. channel->ccw.count = len;
  454. channel->ccw.cda = (__u32) __pa(iob);
  455. }
  456. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  457. {
  458. __u8 index;
  459. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  460. index = channel->io_buf_no;
  461. do {
  462. if (channel->iob[index].state == BUF_STATE_FREE) {
  463. channel->iob[index].state = BUF_STATE_LOCKED;
  464. channel->io_buf_no = (channel->io_buf_no + 1) %
  465. QETH_CMD_BUFFER_NO;
  466. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  467. return channel->iob + index;
  468. }
  469. index = (index + 1) % QETH_CMD_BUFFER_NO;
  470. } while (index != channel->io_buf_no);
  471. return NULL;
  472. }
  473. void qeth_release_buffer(struct qeth_channel *channel,
  474. struct qeth_cmd_buffer *iob)
  475. {
  476. unsigned long flags;
  477. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  478. spin_lock_irqsave(&channel->iob_lock, flags);
  479. memset(iob->data, 0, QETH_BUFSIZE);
  480. iob->state = BUF_STATE_FREE;
  481. iob->callback = qeth_send_control_data_cb;
  482. iob->rc = 0;
  483. spin_unlock_irqrestore(&channel->iob_lock, flags);
  484. }
  485. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  486. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  487. {
  488. struct qeth_cmd_buffer *buffer = NULL;
  489. unsigned long flags;
  490. spin_lock_irqsave(&channel->iob_lock, flags);
  491. buffer = __qeth_get_buffer(channel);
  492. spin_unlock_irqrestore(&channel->iob_lock, flags);
  493. return buffer;
  494. }
  495. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  496. {
  497. struct qeth_cmd_buffer *buffer;
  498. wait_event(channel->wait_q,
  499. ((buffer = qeth_get_buffer(channel)) != NULL));
  500. return buffer;
  501. }
  502. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  503. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  504. {
  505. int cnt;
  506. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  507. qeth_release_buffer(channel, &channel->iob[cnt]);
  508. channel->buf_no = 0;
  509. channel->io_buf_no = 0;
  510. }
  511. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  512. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  513. struct qeth_cmd_buffer *iob)
  514. {
  515. struct qeth_card *card;
  516. struct qeth_reply *reply, *r;
  517. struct qeth_ipa_cmd *cmd;
  518. unsigned long flags;
  519. int keep_reply;
  520. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  521. card = CARD_FROM_CDEV(channel->ccwdev);
  522. if (qeth_check_idx_response(iob->data)) {
  523. qeth_clear_ipacmd_list(card);
  524. if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
  525. dev_err(&card->gdev->dev,
  526. "The qeth device is not configured "
  527. "for the OSI layer required by z/VM\n");
  528. qeth_schedule_recovery(card);
  529. goto out;
  530. }
  531. cmd = qeth_check_ipa_data(card, iob);
  532. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  533. goto out;
  534. /*in case of OSN : check if cmd is set */
  535. if (card->info.type == QETH_CARD_TYPE_OSN &&
  536. cmd &&
  537. cmd->hdr.command != IPA_CMD_STARTLAN &&
  538. card->osn_info.assist_cb != NULL) {
  539. card->osn_info.assist_cb(card->dev, cmd);
  540. goto out;
  541. }
  542. spin_lock_irqsave(&card->lock, flags);
  543. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  544. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  545. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  546. qeth_get_reply(reply);
  547. list_del_init(&reply->list);
  548. spin_unlock_irqrestore(&card->lock, flags);
  549. keep_reply = 0;
  550. if (reply->callback != NULL) {
  551. if (cmd) {
  552. reply->offset = (__u16)((char *)cmd -
  553. (char *)iob->data);
  554. keep_reply = reply->callback(card,
  555. reply,
  556. (unsigned long)cmd);
  557. } else
  558. keep_reply = reply->callback(card,
  559. reply,
  560. (unsigned long)iob);
  561. }
  562. if (cmd)
  563. reply->rc = (u16) cmd->hdr.return_code;
  564. else if (iob->rc)
  565. reply->rc = iob->rc;
  566. if (keep_reply) {
  567. spin_lock_irqsave(&card->lock, flags);
  568. list_add_tail(&reply->list,
  569. &card->cmd_waiter_list);
  570. spin_unlock_irqrestore(&card->lock, flags);
  571. } else {
  572. atomic_inc(&reply->received);
  573. wake_up(&reply->wait_q);
  574. }
  575. qeth_put_reply(reply);
  576. goto out;
  577. }
  578. }
  579. spin_unlock_irqrestore(&card->lock, flags);
  580. out:
  581. memcpy(&card->seqno.pdu_hdr_ack,
  582. QETH_PDU_HEADER_SEQ_NO(iob->data),
  583. QETH_SEQ_NO_LENGTH);
  584. qeth_release_buffer(channel, iob);
  585. }
  586. static int qeth_setup_channel(struct qeth_channel *channel)
  587. {
  588. int cnt;
  589. QETH_DBF_TEXT(SETUP, 2, "setupch");
  590. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  591. channel->iob[cnt].data = (char *)
  592. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  593. if (channel->iob[cnt].data == NULL)
  594. break;
  595. channel->iob[cnt].state = BUF_STATE_FREE;
  596. channel->iob[cnt].channel = channel;
  597. channel->iob[cnt].callback = qeth_send_control_data_cb;
  598. channel->iob[cnt].rc = 0;
  599. }
  600. if (cnt < QETH_CMD_BUFFER_NO) {
  601. while (cnt-- > 0)
  602. kfree(channel->iob[cnt].data);
  603. return -ENOMEM;
  604. }
  605. channel->buf_no = 0;
  606. channel->io_buf_no = 0;
  607. atomic_set(&channel->irq_pending, 0);
  608. spin_lock_init(&channel->iob_lock);
  609. init_waitqueue_head(&channel->wait_q);
  610. return 0;
  611. }
  612. static int qeth_set_thread_start_bit(struct qeth_card *card,
  613. unsigned long thread)
  614. {
  615. unsigned long flags;
  616. spin_lock_irqsave(&card->thread_mask_lock, flags);
  617. if (!(card->thread_allowed_mask & thread) ||
  618. (card->thread_start_mask & thread)) {
  619. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  620. return -EPERM;
  621. }
  622. card->thread_start_mask |= thread;
  623. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  624. return 0;
  625. }
  626. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  627. {
  628. unsigned long flags;
  629. spin_lock_irqsave(&card->thread_mask_lock, flags);
  630. card->thread_start_mask &= ~thread;
  631. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  632. wake_up(&card->wait_q);
  633. }
  634. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  635. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  636. {
  637. unsigned long flags;
  638. spin_lock_irqsave(&card->thread_mask_lock, flags);
  639. card->thread_running_mask &= ~thread;
  640. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  641. wake_up(&card->wait_q);
  642. }
  643. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  644. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  645. {
  646. unsigned long flags;
  647. int rc = 0;
  648. spin_lock_irqsave(&card->thread_mask_lock, flags);
  649. if (card->thread_start_mask & thread) {
  650. if ((card->thread_allowed_mask & thread) &&
  651. !(card->thread_running_mask & thread)) {
  652. rc = 1;
  653. card->thread_start_mask &= ~thread;
  654. card->thread_running_mask |= thread;
  655. } else
  656. rc = -EPERM;
  657. }
  658. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  659. return rc;
  660. }
  661. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  662. {
  663. int rc = 0;
  664. wait_event(card->wait_q,
  665. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  666. return rc;
  667. }
  668. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  669. void qeth_schedule_recovery(struct qeth_card *card)
  670. {
  671. QETH_DBF_TEXT(TRACE, 2, "startrec");
  672. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  673. schedule_work(&card->kernel_thread_starter);
  674. }
  675. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  676. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  677. {
  678. int dstat, cstat;
  679. char *sense;
  680. sense = (char *) irb->ecw;
  681. cstat = irb->scsw.cmd.cstat;
  682. dstat = irb->scsw.cmd.dstat;
  683. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  684. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  685. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  686. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  687. dev_warn(&cdev->dev, "The qeth device driver "
  688. "failed to recover an error on the device\n");
  689. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
  690. dev_name(&cdev->dev), dstat, cstat);
  691. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  692. 16, 1, irb, 64, 1);
  693. return 1;
  694. }
  695. if (dstat & DEV_STAT_UNIT_CHECK) {
  696. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  697. SENSE_RESETTING_EVENT_FLAG) {
  698. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  699. return 1;
  700. }
  701. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  702. SENSE_COMMAND_REJECT_FLAG) {
  703. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  704. return 1;
  705. }
  706. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  707. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  708. return 1;
  709. }
  710. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  711. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  712. return 0;
  713. }
  714. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  715. return 1;
  716. }
  717. return 0;
  718. }
  719. static long __qeth_check_irb_error(struct ccw_device *cdev,
  720. unsigned long intparm, struct irb *irb)
  721. {
  722. if (!IS_ERR(irb))
  723. return 0;
  724. switch (PTR_ERR(irb)) {
  725. case -EIO:
  726. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  727. dev_name(&cdev->dev));
  728. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  729. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  730. break;
  731. case -ETIMEDOUT:
  732. dev_warn(&cdev->dev, "A hardware operation timed out"
  733. " on the device\n");
  734. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  735. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  736. if (intparm == QETH_RCD_PARM) {
  737. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  738. if (card && (card->data.ccwdev == cdev)) {
  739. card->data.state = CH_STATE_DOWN;
  740. wake_up(&card->wait_q);
  741. }
  742. }
  743. break;
  744. default:
  745. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  746. dev_name(&cdev->dev), PTR_ERR(irb));
  747. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  748. QETH_DBF_TEXT(TRACE, 2, " rc???");
  749. }
  750. return PTR_ERR(irb);
  751. }
  752. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  753. struct irb *irb)
  754. {
  755. int rc;
  756. int cstat, dstat;
  757. struct qeth_cmd_buffer *buffer;
  758. struct qeth_channel *channel;
  759. struct qeth_card *card;
  760. struct qeth_cmd_buffer *iob;
  761. __u8 index;
  762. QETH_DBF_TEXT(TRACE, 5, "irq");
  763. if (__qeth_check_irb_error(cdev, intparm, irb))
  764. return;
  765. cstat = irb->scsw.cmd.cstat;
  766. dstat = irb->scsw.cmd.dstat;
  767. card = CARD_FROM_CDEV(cdev);
  768. if (!card)
  769. return;
  770. if (card->read.ccwdev == cdev) {
  771. channel = &card->read;
  772. QETH_DBF_TEXT(TRACE, 5, "read");
  773. } else if (card->write.ccwdev == cdev) {
  774. channel = &card->write;
  775. QETH_DBF_TEXT(TRACE, 5, "write");
  776. } else {
  777. channel = &card->data;
  778. QETH_DBF_TEXT(TRACE, 5, "data");
  779. }
  780. atomic_set(&channel->irq_pending, 0);
  781. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  782. channel->state = CH_STATE_STOPPED;
  783. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  784. channel->state = CH_STATE_HALTED;
  785. /*let's wake up immediately on data channel*/
  786. if ((channel == &card->data) && (intparm != 0) &&
  787. (intparm != QETH_RCD_PARM))
  788. goto out;
  789. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  790. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  791. /* we don't have to handle this further */
  792. intparm = 0;
  793. }
  794. if (intparm == QETH_HALT_CHANNEL_PARM) {
  795. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  796. /* we don't have to handle this further */
  797. intparm = 0;
  798. }
  799. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  800. (dstat & DEV_STAT_UNIT_CHECK) ||
  801. (cstat)) {
  802. if (irb->esw.esw0.erw.cons) {
  803. dev_warn(&channel->ccwdev->dev,
  804. "The qeth device driver failed to recover "
  805. "an error on the device\n");
  806. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  807. "0x%X dstat 0x%X\n",
  808. dev_name(&channel->ccwdev->dev), cstat, dstat);
  809. print_hex_dump(KERN_WARNING, "qeth: irb ",
  810. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  811. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  812. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  813. }
  814. if (intparm == QETH_RCD_PARM) {
  815. channel->state = CH_STATE_DOWN;
  816. goto out;
  817. }
  818. rc = qeth_get_problem(cdev, irb);
  819. if (rc) {
  820. qeth_clear_ipacmd_list(card);
  821. qeth_schedule_recovery(card);
  822. goto out;
  823. }
  824. }
  825. if (intparm == QETH_RCD_PARM) {
  826. channel->state = CH_STATE_RCD_DONE;
  827. goto out;
  828. }
  829. if (intparm) {
  830. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  831. buffer->state = BUF_STATE_PROCESSED;
  832. }
  833. if (channel == &card->data)
  834. return;
  835. if (channel == &card->read &&
  836. channel->state == CH_STATE_UP)
  837. qeth_issue_next_read(card);
  838. iob = channel->iob;
  839. index = channel->buf_no;
  840. while (iob[index].state == BUF_STATE_PROCESSED) {
  841. if (iob[index].callback != NULL)
  842. iob[index].callback(channel, iob + index);
  843. index = (index + 1) % QETH_CMD_BUFFER_NO;
  844. }
  845. channel->buf_no = index;
  846. out:
  847. wake_up(&card->wait_q);
  848. return;
  849. }
  850. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  851. struct qeth_qdio_out_buffer *buf)
  852. {
  853. int i;
  854. struct sk_buff *skb;
  855. /* is PCI flag set on buffer? */
  856. if (buf->buffer->element[0].flags & 0x40)
  857. atomic_dec(&queue->set_pci_flags_count);
  858. skb = skb_dequeue(&buf->skb_list);
  859. while (skb) {
  860. atomic_dec(&skb->users);
  861. dev_kfree_skb_any(skb);
  862. skb = skb_dequeue(&buf->skb_list);
  863. }
  864. qeth_eddp_buf_release_contexts(buf);
  865. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  866. if (buf->buffer->element[i].addr && buf->is_header[i])
  867. kmem_cache_free(qeth_core_header_cache,
  868. buf->buffer->element[i].addr);
  869. buf->is_header[i] = 0;
  870. buf->buffer->element[i].length = 0;
  871. buf->buffer->element[i].addr = NULL;
  872. buf->buffer->element[i].flags = 0;
  873. }
  874. buf->next_element_to_fill = 0;
  875. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  876. }
  877. void qeth_clear_qdio_buffers(struct qeth_card *card)
  878. {
  879. int i, j;
  880. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  881. /* clear outbound buffers to free skbs */
  882. for (i = 0; i < card->qdio.no_out_queues; ++i)
  883. if (card->qdio.out_qs[i]) {
  884. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  885. qeth_clear_output_buffer(card->qdio.out_qs[i],
  886. &card->qdio.out_qs[i]->bufs[j]);
  887. }
  888. }
  889. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  890. static void qeth_free_buffer_pool(struct qeth_card *card)
  891. {
  892. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  893. int i = 0;
  894. QETH_DBF_TEXT(TRACE, 5, "freepool");
  895. list_for_each_entry_safe(pool_entry, tmp,
  896. &card->qdio.init_pool.entry_list, init_list){
  897. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  898. free_page((unsigned long)pool_entry->elements[i]);
  899. list_del(&pool_entry->init_list);
  900. kfree(pool_entry);
  901. }
  902. }
  903. static void qeth_free_qdio_buffers(struct qeth_card *card)
  904. {
  905. int i, j;
  906. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  907. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  908. QETH_QDIO_UNINITIALIZED)
  909. return;
  910. kfree(card->qdio.in_q);
  911. card->qdio.in_q = NULL;
  912. /* inbound buffer pool */
  913. qeth_free_buffer_pool(card);
  914. /* free outbound qdio_qs */
  915. if (card->qdio.out_qs) {
  916. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  917. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  918. qeth_clear_output_buffer(card->qdio.out_qs[i],
  919. &card->qdio.out_qs[i]->bufs[j]);
  920. kfree(card->qdio.out_qs[i]);
  921. }
  922. kfree(card->qdio.out_qs);
  923. card->qdio.out_qs = NULL;
  924. }
  925. }
  926. static void qeth_clean_channel(struct qeth_channel *channel)
  927. {
  928. int cnt;
  929. QETH_DBF_TEXT(SETUP, 2, "freech");
  930. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  931. kfree(channel->iob[cnt].data);
  932. }
  933. static int qeth_is_1920_device(struct qeth_card *card)
  934. {
  935. int single_queue = 0;
  936. struct ccw_device *ccwdev;
  937. struct channelPath_dsc {
  938. u8 flags;
  939. u8 lsn;
  940. u8 desc;
  941. u8 chpid;
  942. u8 swla;
  943. u8 zeroes;
  944. u8 chla;
  945. u8 chpp;
  946. } *chp_dsc;
  947. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  948. ccwdev = card->data.ccwdev;
  949. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  950. if (chp_dsc != NULL) {
  951. /* CHPP field bit 6 == 1 -> single queue */
  952. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  953. kfree(chp_dsc);
  954. }
  955. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  956. return single_queue;
  957. }
  958. static void qeth_init_qdio_info(struct qeth_card *card)
  959. {
  960. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  961. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  962. /* inbound */
  963. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  964. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  965. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  966. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  967. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  968. }
  969. static void qeth_set_intial_options(struct qeth_card *card)
  970. {
  971. card->options.route4.type = NO_ROUTER;
  972. card->options.route6.type = NO_ROUTER;
  973. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  974. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  975. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  976. card->options.fake_broadcast = 0;
  977. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  978. card->options.performance_stats = 0;
  979. card->options.rx_sg_cb = QETH_RX_SG_CB;
  980. }
  981. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  982. {
  983. unsigned long flags;
  984. int rc = 0;
  985. spin_lock_irqsave(&card->thread_mask_lock, flags);
  986. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  987. (u8) card->thread_start_mask,
  988. (u8) card->thread_allowed_mask,
  989. (u8) card->thread_running_mask);
  990. rc = (card->thread_start_mask & thread);
  991. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  992. return rc;
  993. }
  994. static void qeth_start_kernel_thread(struct work_struct *work)
  995. {
  996. struct qeth_card *card = container_of(work, struct qeth_card,
  997. kernel_thread_starter);
  998. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  999. if (card->read.state != CH_STATE_UP &&
  1000. card->write.state != CH_STATE_UP)
  1001. return;
  1002. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  1003. kthread_run(card->discipline.recover, (void *) card,
  1004. "qeth_recover");
  1005. }
  1006. static int qeth_setup_card(struct qeth_card *card)
  1007. {
  1008. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1009. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1010. card->read.state = CH_STATE_DOWN;
  1011. card->write.state = CH_STATE_DOWN;
  1012. card->data.state = CH_STATE_DOWN;
  1013. card->state = CARD_STATE_DOWN;
  1014. card->lan_online = 0;
  1015. card->use_hard_stop = 0;
  1016. card->dev = NULL;
  1017. spin_lock_init(&card->vlanlock);
  1018. spin_lock_init(&card->mclock);
  1019. card->vlangrp = NULL;
  1020. spin_lock_init(&card->lock);
  1021. spin_lock_init(&card->ip_lock);
  1022. spin_lock_init(&card->thread_mask_lock);
  1023. card->thread_start_mask = 0;
  1024. card->thread_allowed_mask = 0;
  1025. card->thread_running_mask = 0;
  1026. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1027. INIT_LIST_HEAD(&card->ip_list);
  1028. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1029. if (!card->ip_tbd_list) {
  1030. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1031. return -ENOMEM;
  1032. }
  1033. INIT_LIST_HEAD(card->ip_tbd_list);
  1034. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1035. init_waitqueue_head(&card->wait_q);
  1036. /* intial options */
  1037. qeth_set_intial_options(card);
  1038. /* IP address takeover */
  1039. INIT_LIST_HEAD(&card->ipato.entries);
  1040. card->ipato.enabled = 0;
  1041. card->ipato.invert4 = 0;
  1042. card->ipato.invert6 = 0;
  1043. /* init QDIO stuff */
  1044. qeth_init_qdio_info(card);
  1045. return 0;
  1046. }
  1047. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1048. {
  1049. struct qeth_card *card = container_of(slr, struct qeth_card,
  1050. qeth_service_level);
  1051. seq_printf(m, "qeth: %s firmware level %s\n", CARD_BUS_ID(card),
  1052. card->info.mcl_level);
  1053. }
  1054. static struct qeth_card *qeth_alloc_card(void)
  1055. {
  1056. struct qeth_card *card;
  1057. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1058. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1059. if (!card)
  1060. return NULL;
  1061. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1062. if (qeth_setup_channel(&card->read)) {
  1063. kfree(card);
  1064. return NULL;
  1065. }
  1066. if (qeth_setup_channel(&card->write)) {
  1067. qeth_clean_channel(&card->read);
  1068. kfree(card);
  1069. return NULL;
  1070. }
  1071. card->options.layer2 = -1;
  1072. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1073. register_service_level(&card->qeth_service_level);
  1074. return card;
  1075. }
  1076. static int qeth_determine_card_type(struct qeth_card *card)
  1077. {
  1078. int i = 0;
  1079. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1080. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1081. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1082. while (known_devices[i][4]) {
  1083. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1084. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1085. card->info.type = known_devices[i][4];
  1086. card->qdio.no_out_queues = known_devices[i][8];
  1087. card->info.is_multicast_different = known_devices[i][9];
  1088. if (qeth_is_1920_device(card)) {
  1089. dev_info(&card->gdev->dev,
  1090. "Priority Queueing not supported\n");
  1091. card->qdio.no_out_queues = 1;
  1092. card->qdio.default_out_queue = 0;
  1093. }
  1094. return 0;
  1095. }
  1096. i++;
  1097. }
  1098. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1099. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1100. "unknown type\n");
  1101. return -ENOENT;
  1102. }
  1103. static int qeth_clear_channel(struct qeth_channel *channel)
  1104. {
  1105. unsigned long flags;
  1106. struct qeth_card *card;
  1107. int rc;
  1108. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1109. card = CARD_FROM_CDEV(channel->ccwdev);
  1110. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1111. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1112. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1113. if (rc)
  1114. return rc;
  1115. rc = wait_event_interruptible_timeout(card->wait_q,
  1116. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1117. if (rc == -ERESTARTSYS)
  1118. return rc;
  1119. if (channel->state != CH_STATE_STOPPED)
  1120. return -ETIME;
  1121. channel->state = CH_STATE_DOWN;
  1122. return 0;
  1123. }
  1124. static int qeth_halt_channel(struct qeth_channel *channel)
  1125. {
  1126. unsigned long flags;
  1127. struct qeth_card *card;
  1128. int rc;
  1129. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1130. card = CARD_FROM_CDEV(channel->ccwdev);
  1131. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1132. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1133. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1134. if (rc)
  1135. return rc;
  1136. rc = wait_event_interruptible_timeout(card->wait_q,
  1137. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1138. if (rc == -ERESTARTSYS)
  1139. return rc;
  1140. if (channel->state != CH_STATE_HALTED)
  1141. return -ETIME;
  1142. return 0;
  1143. }
  1144. static int qeth_halt_channels(struct qeth_card *card)
  1145. {
  1146. int rc1 = 0, rc2 = 0, rc3 = 0;
  1147. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1148. rc1 = qeth_halt_channel(&card->read);
  1149. rc2 = qeth_halt_channel(&card->write);
  1150. rc3 = qeth_halt_channel(&card->data);
  1151. if (rc1)
  1152. return rc1;
  1153. if (rc2)
  1154. return rc2;
  1155. return rc3;
  1156. }
  1157. static int qeth_clear_channels(struct qeth_card *card)
  1158. {
  1159. int rc1 = 0, rc2 = 0, rc3 = 0;
  1160. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1161. rc1 = qeth_clear_channel(&card->read);
  1162. rc2 = qeth_clear_channel(&card->write);
  1163. rc3 = qeth_clear_channel(&card->data);
  1164. if (rc1)
  1165. return rc1;
  1166. if (rc2)
  1167. return rc2;
  1168. return rc3;
  1169. }
  1170. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1171. {
  1172. int rc = 0;
  1173. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1174. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1175. if (halt)
  1176. rc = qeth_halt_channels(card);
  1177. if (rc)
  1178. return rc;
  1179. return qeth_clear_channels(card);
  1180. }
  1181. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1182. {
  1183. int rc = 0;
  1184. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1185. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1186. QETH_QDIO_CLEANING)) {
  1187. case QETH_QDIO_ESTABLISHED:
  1188. if (card->info.type == QETH_CARD_TYPE_IQD)
  1189. rc = qdio_cleanup(CARD_DDEV(card),
  1190. QDIO_FLAG_CLEANUP_USING_HALT);
  1191. else
  1192. rc = qdio_cleanup(CARD_DDEV(card),
  1193. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1194. if (rc)
  1195. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1196. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1197. break;
  1198. case QETH_QDIO_CLEANING:
  1199. return rc;
  1200. default:
  1201. break;
  1202. }
  1203. rc = qeth_clear_halt_card(card, use_halt);
  1204. if (rc)
  1205. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1206. card->state = CARD_STATE_DOWN;
  1207. return rc;
  1208. }
  1209. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1210. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1211. int *length)
  1212. {
  1213. struct ciw *ciw;
  1214. char *rcd_buf;
  1215. int ret;
  1216. struct qeth_channel *channel = &card->data;
  1217. unsigned long flags;
  1218. /*
  1219. * scan for RCD command in extended SenseID data
  1220. */
  1221. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1222. if (!ciw || ciw->cmd == 0)
  1223. return -EOPNOTSUPP;
  1224. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1225. if (!rcd_buf)
  1226. return -ENOMEM;
  1227. channel->ccw.cmd_code = ciw->cmd;
  1228. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1229. channel->ccw.count = ciw->count;
  1230. channel->ccw.flags = CCW_FLAG_SLI;
  1231. channel->state = CH_STATE_RCD;
  1232. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1233. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1234. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1235. QETH_RCD_TIMEOUT);
  1236. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1237. if (!ret)
  1238. wait_event(card->wait_q,
  1239. (channel->state == CH_STATE_RCD_DONE ||
  1240. channel->state == CH_STATE_DOWN));
  1241. if (channel->state == CH_STATE_DOWN)
  1242. ret = -EIO;
  1243. else
  1244. channel->state = CH_STATE_DOWN;
  1245. if (ret) {
  1246. kfree(rcd_buf);
  1247. *buffer = NULL;
  1248. *length = 0;
  1249. } else {
  1250. *length = ciw->count;
  1251. *buffer = rcd_buf;
  1252. }
  1253. return ret;
  1254. }
  1255. static int qeth_get_unitaddr(struct qeth_card *card)
  1256. {
  1257. int length;
  1258. char *prcd;
  1259. int rc;
  1260. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1261. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1262. if (rc) {
  1263. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  1264. dev_name(&card->gdev->dev), rc);
  1265. return rc;
  1266. }
  1267. card->info.chpid = prcd[30];
  1268. card->info.unit_addr2 = prcd[31];
  1269. card->info.cula = prcd[63];
  1270. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1271. (prcd[0x11] == _ascebc['M']));
  1272. kfree(prcd);
  1273. return 0;
  1274. }
  1275. static void qeth_init_tokens(struct qeth_card *card)
  1276. {
  1277. card->token.issuer_rm_w = 0x00010103UL;
  1278. card->token.cm_filter_w = 0x00010108UL;
  1279. card->token.cm_connection_w = 0x0001010aUL;
  1280. card->token.ulp_filter_w = 0x0001010bUL;
  1281. card->token.ulp_connection_w = 0x0001010dUL;
  1282. }
  1283. static void qeth_init_func_level(struct qeth_card *card)
  1284. {
  1285. if (card->ipato.enabled) {
  1286. if (card->info.type == QETH_CARD_TYPE_IQD)
  1287. card->info.func_level =
  1288. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1289. else
  1290. card->info.func_level =
  1291. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1292. } else {
  1293. if (card->info.type == QETH_CARD_TYPE_IQD)
  1294. /*FIXME:why do we have same values for dis and ena for
  1295. osae??? */
  1296. card->info.func_level =
  1297. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1298. else
  1299. card->info.func_level =
  1300. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1301. }
  1302. }
  1303. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1304. void (*idx_reply_cb)(struct qeth_channel *,
  1305. struct qeth_cmd_buffer *))
  1306. {
  1307. struct qeth_cmd_buffer *iob;
  1308. unsigned long flags;
  1309. int rc;
  1310. struct qeth_card *card;
  1311. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1312. card = CARD_FROM_CDEV(channel->ccwdev);
  1313. iob = qeth_get_buffer(channel);
  1314. iob->callback = idx_reply_cb;
  1315. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1316. channel->ccw.count = QETH_BUFSIZE;
  1317. channel->ccw.cda = (__u32) __pa(iob->data);
  1318. wait_event(card->wait_q,
  1319. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1320. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1321. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1322. rc = ccw_device_start(channel->ccwdev,
  1323. &channel->ccw, (addr_t) iob, 0, 0);
  1324. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1325. if (rc) {
  1326. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1327. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1328. atomic_set(&channel->irq_pending, 0);
  1329. wake_up(&card->wait_q);
  1330. return rc;
  1331. }
  1332. rc = wait_event_interruptible_timeout(card->wait_q,
  1333. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1334. if (rc == -ERESTARTSYS)
  1335. return rc;
  1336. if (channel->state != CH_STATE_UP) {
  1337. rc = -ETIME;
  1338. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1339. qeth_clear_cmd_buffers(channel);
  1340. } else
  1341. rc = 0;
  1342. return rc;
  1343. }
  1344. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1345. void (*idx_reply_cb)(struct qeth_channel *,
  1346. struct qeth_cmd_buffer *))
  1347. {
  1348. struct qeth_card *card;
  1349. struct qeth_cmd_buffer *iob;
  1350. unsigned long flags;
  1351. __u16 temp;
  1352. __u8 tmp;
  1353. int rc;
  1354. struct ccw_dev_id temp_devid;
  1355. card = CARD_FROM_CDEV(channel->ccwdev);
  1356. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1357. iob = qeth_get_buffer(channel);
  1358. iob->callback = idx_reply_cb;
  1359. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1360. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1361. channel->ccw.cda = (__u32) __pa(iob->data);
  1362. if (channel == &card->write) {
  1363. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1364. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1365. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1366. card->seqno.trans_hdr++;
  1367. } else {
  1368. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1369. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1370. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1371. }
  1372. tmp = ((__u8)card->info.portno) | 0x80;
  1373. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1374. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1375. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1376. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1377. &card->info.func_level, sizeof(__u16));
  1378. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1379. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1380. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1381. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1382. wait_event(card->wait_q,
  1383. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1384. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1385. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1386. rc = ccw_device_start(channel->ccwdev,
  1387. &channel->ccw, (addr_t) iob, 0, 0);
  1388. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1389. if (rc) {
  1390. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1391. rc);
  1392. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1393. atomic_set(&channel->irq_pending, 0);
  1394. wake_up(&card->wait_q);
  1395. return rc;
  1396. }
  1397. rc = wait_event_interruptible_timeout(card->wait_q,
  1398. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1399. if (rc == -ERESTARTSYS)
  1400. return rc;
  1401. if (channel->state != CH_STATE_ACTIVATING) {
  1402. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1403. " failed to recover an error on the device\n");
  1404. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1405. dev_name(&channel->ccwdev->dev));
  1406. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1407. qeth_clear_cmd_buffers(channel);
  1408. return -ETIME;
  1409. }
  1410. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1411. }
  1412. static int qeth_peer_func_level(int level)
  1413. {
  1414. if ((level & 0xff) == 8)
  1415. return (level & 0xff) + 0x400;
  1416. if (((level >> 8) & 3) == 1)
  1417. return (level & 0xff) + 0x200;
  1418. return level;
  1419. }
  1420. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1421. struct qeth_cmd_buffer *iob)
  1422. {
  1423. struct qeth_card *card;
  1424. __u16 temp;
  1425. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1426. if (channel->state == CH_STATE_DOWN) {
  1427. channel->state = CH_STATE_ACTIVATING;
  1428. goto out;
  1429. }
  1430. card = CARD_FROM_CDEV(channel->ccwdev);
  1431. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1432. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1433. dev_err(&card->write.ccwdev->dev,
  1434. "The adapter is used exclusively by another "
  1435. "host\n");
  1436. else
  1437. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1438. " negative reply\n",
  1439. dev_name(&card->write.ccwdev->dev));
  1440. goto out;
  1441. }
  1442. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1443. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1444. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1445. "function level mismatch (sent: 0x%x, received: "
  1446. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1447. card->info.func_level, temp);
  1448. goto out;
  1449. }
  1450. channel->state = CH_STATE_UP;
  1451. out:
  1452. qeth_release_buffer(channel, iob);
  1453. }
  1454. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1455. struct qeth_cmd_buffer *iob)
  1456. {
  1457. struct qeth_card *card;
  1458. __u16 temp;
  1459. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1460. if (channel->state == CH_STATE_DOWN) {
  1461. channel->state = CH_STATE_ACTIVATING;
  1462. goto out;
  1463. }
  1464. card = CARD_FROM_CDEV(channel->ccwdev);
  1465. if (qeth_check_idx_response(iob->data))
  1466. goto out;
  1467. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1468. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1469. dev_err(&card->write.ccwdev->dev,
  1470. "The adapter is used exclusively by another "
  1471. "host\n");
  1472. else
  1473. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1474. " negative reply\n",
  1475. dev_name(&card->read.ccwdev->dev));
  1476. goto out;
  1477. }
  1478. /**
  1479. * temporary fix for microcode bug
  1480. * to revert it,replace OR by AND
  1481. */
  1482. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1483. (card->info.type == QETH_CARD_TYPE_OSAE))
  1484. card->info.portname_required = 1;
  1485. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1486. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1487. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1488. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1489. dev_name(&card->read.ccwdev->dev),
  1490. card->info.func_level, temp);
  1491. goto out;
  1492. }
  1493. memcpy(&card->token.issuer_rm_r,
  1494. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1495. QETH_MPC_TOKEN_LENGTH);
  1496. memcpy(&card->info.mcl_level[0],
  1497. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1498. channel->state = CH_STATE_UP;
  1499. out:
  1500. qeth_release_buffer(channel, iob);
  1501. }
  1502. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1503. struct qeth_cmd_buffer *iob)
  1504. {
  1505. qeth_setup_ccw(&card->write, iob->data, len);
  1506. iob->callback = qeth_release_buffer;
  1507. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1508. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1509. card->seqno.trans_hdr++;
  1510. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1511. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1512. card->seqno.pdu_hdr++;
  1513. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1514. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1515. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1516. }
  1517. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1518. int qeth_send_control_data(struct qeth_card *card, int len,
  1519. struct qeth_cmd_buffer *iob,
  1520. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1521. unsigned long),
  1522. void *reply_param)
  1523. {
  1524. int rc;
  1525. unsigned long flags;
  1526. struct qeth_reply *reply = NULL;
  1527. unsigned long timeout;
  1528. struct qeth_ipa_cmd *cmd;
  1529. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1530. reply = qeth_alloc_reply(card);
  1531. if (!reply) {
  1532. return -ENOMEM;
  1533. }
  1534. reply->callback = reply_cb;
  1535. reply->param = reply_param;
  1536. if (card->state == CARD_STATE_DOWN)
  1537. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1538. else
  1539. reply->seqno = card->seqno.ipa++;
  1540. init_waitqueue_head(&reply->wait_q);
  1541. spin_lock_irqsave(&card->lock, flags);
  1542. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1543. spin_unlock_irqrestore(&card->lock, flags);
  1544. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1545. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1546. qeth_prepare_control_data(card, len, iob);
  1547. if (IS_IPA(iob->data))
  1548. timeout = jiffies + QETH_IPA_TIMEOUT;
  1549. else
  1550. timeout = jiffies + QETH_TIMEOUT;
  1551. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1552. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1553. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1554. (addr_t) iob, 0, 0);
  1555. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1556. if (rc) {
  1557. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1558. "ccw_device_start rc = %i\n",
  1559. dev_name(&card->write.ccwdev->dev), rc);
  1560. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1561. spin_lock_irqsave(&card->lock, flags);
  1562. list_del_init(&reply->list);
  1563. qeth_put_reply(reply);
  1564. spin_unlock_irqrestore(&card->lock, flags);
  1565. qeth_release_buffer(iob->channel, iob);
  1566. atomic_set(&card->write.irq_pending, 0);
  1567. wake_up(&card->wait_q);
  1568. return rc;
  1569. }
  1570. /* we have only one long running ipassist, since we can ensure
  1571. process context of this command we can sleep */
  1572. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1573. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1574. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1575. if (!wait_event_timeout(reply->wait_q,
  1576. atomic_read(&reply->received), timeout))
  1577. goto time_err;
  1578. } else {
  1579. while (!atomic_read(&reply->received)) {
  1580. if (time_after(jiffies, timeout))
  1581. goto time_err;
  1582. cpu_relax();
  1583. };
  1584. }
  1585. rc = reply->rc;
  1586. qeth_put_reply(reply);
  1587. return rc;
  1588. time_err:
  1589. spin_lock_irqsave(&reply->card->lock, flags);
  1590. list_del_init(&reply->list);
  1591. spin_unlock_irqrestore(&reply->card->lock, flags);
  1592. reply->rc = -ETIME;
  1593. atomic_inc(&reply->received);
  1594. wake_up(&reply->wait_q);
  1595. rc = reply->rc;
  1596. qeth_put_reply(reply);
  1597. return rc;
  1598. }
  1599. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1600. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1601. unsigned long data)
  1602. {
  1603. struct qeth_cmd_buffer *iob;
  1604. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1605. iob = (struct qeth_cmd_buffer *) data;
  1606. memcpy(&card->token.cm_filter_r,
  1607. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1608. QETH_MPC_TOKEN_LENGTH);
  1609. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1610. return 0;
  1611. }
  1612. static int qeth_cm_enable(struct qeth_card *card)
  1613. {
  1614. int rc;
  1615. struct qeth_cmd_buffer *iob;
  1616. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1617. iob = qeth_wait_for_buffer(&card->write);
  1618. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1619. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1620. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1621. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1622. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1623. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1624. qeth_cm_enable_cb, NULL);
  1625. return rc;
  1626. }
  1627. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1628. unsigned long data)
  1629. {
  1630. struct qeth_cmd_buffer *iob;
  1631. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1632. iob = (struct qeth_cmd_buffer *) data;
  1633. memcpy(&card->token.cm_connection_r,
  1634. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1635. QETH_MPC_TOKEN_LENGTH);
  1636. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1637. return 0;
  1638. }
  1639. static int qeth_cm_setup(struct qeth_card *card)
  1640. {
  1641. int rc;
  1642. struct qeth_cmd_buffer *iob;
  1643. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1644. iob = qeth_wait_for_buffer(&card->write);
  1645. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1646. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1647. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1648. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1649. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1650. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1651. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1652. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1653. qeth_cm_setup_cb, NULL);
  1654. return rc;
  1655. }
  1656. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1657. {
  1658. switch (card->info.type) {
  1659. case QETH_CARD_TYPE_UNKNOWN:
  1660. return 1500;
  1661. case QETH_CARD_TYPE_IQD:
  1662. return card->info.max_mtu;
  1663. case QETH_CARD_TYPE_OSAE:
  1664. switch (card->info.link_type) {
  1665. case QETH_LINK_TYPE_HSTR:
  1666. case QETH_LINK_TYPE_LANE_TR:
  1667. return 2000;
  1668. default:
  1669. return 1492;
  1670. }
  1671. default:
  1672. return 1500;
  1673. }
  1674. }
  1675. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1676. {
  1677. switch (cardtype) {
  1678. case QETH_CARD_TYPE_UNKNOWN:
  1679. case QETH_CARD_TYPE_OSAE:
  1680. case QETH_CARD_TYPE_OSN:
  1681. return 61440;
  1682. case QETH_CARD_TYPE_IQD:
  1683. return 57344;
  1684. default:
  1685. return 1500;
  1686. }
  1687. }
  1688. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1689. {
  1690. switch (cardtype) {
  1691. case QETH_CARD_TYPE_IQD:
  1692. return 1;
  1693. default:
  1694. return 0;
  1695. }
  1696. }
  1697. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1698. {
  1699. switch (framesize) {
  1700. case 0x4000:
  1701. return 8192;
  1702. case 0x6000:
  1703. return 16384;
  1704. case 0xa000:
  1705. return 32768;
  1706. case 0xffff:
  1707. return 57344;
  1708. default:
  1709. return 0;
  1710. }
  1711. }
  1712. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1713. {
  1714. switch (card->info.type) {
  1715. case QETH_CARD_TYPE_OSAE:
  1716. return ((mtu >= 576) && (mtu <= 61440));
  1717. case QETH_CARD_TYPE_IQD:
  1718. return ((mtu >= 576) &&
  1719. (mtu <= card->info.max_mtu + 4096 - 32));
  1720. case QETH_CARD_TYPE_OSN:
  1721. case QETH_CARD_TYPE_UNKNOWN:
  1722. default:
  1723. return 1;
  1724. }
  1725. }
  1726. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1727. unsigned long data)
  1728. {
  1729. __u16 mtu, framesize;
  1730. __u16 len;
  1731. __u8 link_type;
  1732. struct qeth_cmd_buffer *iob;
  1733. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1734. iob = (struct qeth_cmd_buffer *) data;
  1735. memcpy(&card->token.ulp_filter_r,
  1736. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1737. QETH_MPC_TOKEN_LENGTH);
  1738. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1739. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1740. mtu = qeth_get_mtu_outof_framesize(framesize);
  1741. if (!mtu) {
  1742. iob->rc = -EINVAL;
  1743. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1744. return 0;
  1745. }
  1746. card->info.max_mtu = mtu;
  1747. card->info.initial_mtu = mtu;
  1748. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1749. } else {
  1750. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1751. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1752. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1753. }
  1754. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1755. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1756. memcpy(&link_type,
  1757. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1758. card->info.link_type = link_type;
  1759. } else
  1760. card->info.link_type = 0;
  1761. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1762. return 0;
  1763. }
  1764. static int qeth_ulp_enable(struct qeth_card *card)
  1765. {
  1766. int rc;
  1767. char prot_type;
  1768. struct qeth_cmd_buffer *iob;
  1769. /*FIXME: trace view callbacks*/
  1770. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1771. iob = qeth_wait_for_buffer(&card->write);
  1772. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1773. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1774. (__u8) card->info.portno;
  1775. if (card->options.layer2)
  1776. if (card->info.type == QETH_CARD_TYPE_OSN)
  1777. prot_type = QETH_PROT_OSN2;
  1778. else
  1779. prot_type = QETH_PROT_LAYER2;
  1780. else
  1781. prot_type = QETH_PROT_TCPIP;
  1782. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1783. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1784. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1785. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1786. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1787. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1788. card->info.portname, 9);
  1789. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1790. qeth_ulp_enable_cb, NULL);
  1791. return rc;
  1792. }
  1793. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1794. unsigned long data)
  1795. {
  1796. struct qeth_cmd_buffer *iob;
  1797. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1798. iob = (struct qeth_cmd_buffer *) data;
  1799. memcpy(&card->token.ulp_connection_r,
  1800. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1801. QETH_MPC_TOKEN_LENGTH);
  1802. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1803. return 0;
  1804. }
  1805. static int qeth_ulp_setup(struct qeth_card *card)
  1806. {
  1807. int rc;
  1808. __u16 temp;
  1809. struct qeth_cmd_buffer *iob;
  1810. struct ccw_dev_id dev_id;
  1811. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1812. iob = qeth_wait_for_buffer(&card->write);
  1813. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1814. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1815. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1816. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1817. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1818. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1819. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1820. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1821. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1822. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1823. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1824. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1825. qeth_ulp_setup_cb, NULL);
  1826. return rc;
  1827. }
  1828. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1829. {
  1830. int i, j;
  1831. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1832. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1833. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1834. return 0;
  1835. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1836. GFP_KERNEL);
  1837. if (!card->qdio.in_q)
  1838. goto out_nomem;
  1839. QETH_DBF_TEXT(SETUP, 2, "inq");
  1840. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1841. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1842. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1843. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1844. card->qdio.in_q->bufs[i].buffer =
  1845. &card->qdio.in_q->qdio_bufs[i];
  1846. /* inbound buffer pool */
  1847. if (qeth_alloc_buffer_pool(card))
  1848. goto out_freeinq;
  1849. /* outbound */
  1850. card->qdio.out_qs =
  1851. kmalloc(card->qdio.no_out_queues *
  1852. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1853. if (!card->qdio.out_qs)
  1854. goto out_freepool;
  1855. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1856. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1857. GFP_KERNEL);
  1858. if (!card->qdio.out_qs[i])
  1859. goto out_freeoutq;
  1860. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1861. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1862. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1863. card->qdio.out_qs[i]->queue_no = i;
  1864. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1865. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1866. card->qdio.out_qs[i]->bufs[j].buffer =
  1867. &card->qdio.out_qs[i]->qdio_bufs[j];
  1868. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1869. skb_list);
  1870. lockdep_set_class(
  1871. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1872. &qdio_out_skb_queue_key);
  1873. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1874. }
  1875. }
  1876. return 0;
  1877. out_freeoutq:
  1878. while (i > 0)
  1879. kfree(card->qdio.out_qs[--i]);
  1880. kfree(card->qdio.out_qs);
  1881. card->qdio.out_qs = NULL;
  1882. out_freepool:
  1883. qeth_free_buffer_pool(card);
  1884. out_freeinq:
  1885. kfree(card->qdio.in_q);
  1886. card->qdio.in_q = NULL;
  1887. out_nomem:
  1888. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1889. return -ENOMEM;
  1890. }
  1891. static void qeth_create_qib_param_field(struct qeth_card *card,
  1892. char *param_field)
  1893. {
  1894. param_field[0] = _ascebc['P'];
  1895. param_field[1] = _ascebc['C'];
  1896. param_field[2] = _ascebc['I'];
  1897. param_field[3] = _ascebc['T'];
  1898. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1899. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1900. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1901. }
  1902. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1903. char *param_field)
  1904. {
  1905. param_field[16] = _ascebc['B'];
  1906. param_field[17] = _ascebc['L'];
  1907. param_field[18] = _ascebc['K'];
  1908. param_field[19] = _ascebc['T'];
  1909. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1910. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1911. *((unsigned int *) (&param_field[28])) =
  1912. card->info.blkt.inter_packet_jumbo;
  1913. }
  1914. static int qeth_qdio_activate(struct qeth_card *card)
  1915. {
  1916. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1917. return qdio_activate(CARD_DDEV(card));
  1918. }
  1919. static int qeth_dm_act(struct qeth_card *card)
  1920. {
  1921. int rc;
  1922. struct qeth_cmd_buffer *iob;
  1923. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1924. iob = qeth_wait_for_buffer(&card->write);
  1925. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1926. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1927. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1928. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1929. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1930. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1931. return rc;
  1932. }
  1933. static int qeth_mpc_initialize(struct qeth_card *card)
  1934. {
  1935. int rc;
  1936. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1937. rc = qeth_issue_next_read(card);
  1938. if (rc) {
  1939. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1940. return rc;
  1941. }
  1942. rc = qeth_cm_enable(card);
  1943. if (rc) {
  1944. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1945. goto out_qdio;
  1946. }
  1947. rc = qeth_cm_setup(card);
  1948. if (rc) {
  1949. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1950. goto out_qdio;
  1951. }
  1952. rc = qeth_ulp_enable(card);
  1953. if (rc) {
  1954. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1955. goto out_qdio;
  1956. }
  1957. rc = qeth_ulp_setup(card);
  1958. if (rc) {
  1959. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1960. goto out_qdio;
  1961. }
  1962. rc = qeth_alloc_qdio_buffers(card);
  1963. if (rc) {
  1964. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1965. goto out_qdio;
  1966. }
  1967. rc = qeth_qdio_establish(card);
  1968. if (rc) {
  1969. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1970. qeth_free_qdio_buffers(card);
  1971. goto out_qdio;
  1972. }
  1973. rc = qeth_qdio_activate(card);
  1974. if (rc) {
  1975. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1976. goto out_qdio;
  1977. }
  1978. rc = qeth_dm_act(card);
  1979. if (rc) {
  1980. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1981. goto out_qdio;
  1982. }
  1983. return 0;
  1984. out_qdio:
  1985. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1986. return rc;
  1987. }
  1988. static void qeth_print_status_with_portname(struct qeth_card *card)
  1989. {
  1990. char dbf_text[15];
  1991. int i;
  1992. sprintf(dbf_text, "%s", card->info.portname + 1);
  1993. for (i = 0; i < 8; i++)
  1994. dbf_text[i] =
  1995. (char) _ebcasc[(__u8) dbf_text[i]];
  1996. dbf_text[8] = 0;
  1997. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1998. "with link type %s (portname: %s)\n",
  1999. qeth_get_cardname(card),
  2000. (card->info.mcl_level[0]) ? " (level: " : "",
  2001. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2002. (card->info.mcl_level[0]) ? ")" : "",
  2003. qeth_get_cardname_short(card),
  2004. dbf_text);
  2005. }
  2006. static void qeth_print_status_no_portname(struct qeth_card *card)
  2007. {
  2008. if (card->info.portname[0])
  2009. dev_info(&card->gdev->dev, "Device is a%s "
  2010. "card%s%s%s\nwith link type %s "
  2011. "(no portname needed by interface).\n",
  2012. qeth_get_cardname(card),
  2013. (card->info.mcl_level[0]) ? " (level: " : "",
  2014. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2015. (card->info.mcl_level[0]) ? ")" : "",
  2016. qeth_get_cardname_short(card));
  2017. else
  2018. dev_info(&card->gdev->dev, "Device is a%s "
  2019. "card%s%s%s\nwith link type %s.\n",
  2020. qeth_get_cardname(card),
  2021. (card->info.mcl_level[0]) ? " (level: " : "",
  2022. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2023. (card->info.mcl_level[0]) ? ")" : "",
  2024. qeth_get_cardname_short(card));
  2025. }
  2026. void qeth_print_status_message(struct qeth_card *card)
  2027. {
  2028. switch (card->info.type) {
  2029. case QETH_CARD_TYPE_OSAE:
  2030. /* VM will use a non-zero first character
  2031. * to indicate a HiperSockets like reporting
  2032. * of the level OSA sets the first character to zero
  2033. * */
  2034. if (!card->info.mcl_level[0]) {
  2035. sprintf(card->info.mcl_level, "%02x%02x",
  2036. card->info.mcl_level[2],
  2037. card->info.mcl_level[3]);
  2038. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2039. break;
  2040. }
  2041. /* fallthrough */
  2042. case QETH_CARD_TYPE_IQD:
  2043. if ((card->info.guestlan) ||
  2044. (card->info.mcl_level[0] & 0x80)) {
  2045. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2046. card->info.mcl_level[0]];
  2047. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2048. card->info.mcl_level[1]];
  2049. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2050. card->info.mcl_level[2]];
  2051. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2052. card->info.mcl_level[3]];
  2053. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2054. }
  2055. break;
  2056. default:
  2057. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2058. }
  2059. if (card->info.portname_required)
  2060. qeth_print_status_with_portname(card);
  2061. else
  2062. qeth_print_status_no_portname(card);
  2063. }
  2064. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2065. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2066. {
  2067. struct qeth_buffer_pool_entry *entry;
  2068. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2069. list_for_each_entry(entry,
  2070. &card->qdio.init_pool.entry_list, init_list) {
  2071. qeth_put_buffer_pool_entry(card, entry);
  2072. }
  2073. }
  2074. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2075. struct qeth_card *card)
  2076. {
  2077. struct list_head *plh;
  2078. struct qeth_buffer_pool_entry *entry;
  2079. int i, free;
  2080. struct page *page;
  2081. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2082. return NULL;
  2083. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2084. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2085. free = 1;
  2086. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2087. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2088. free = 0;
  2089. break;
  2090. }
  2091. }
  2092. if (free) {
  2093. list_del_init(&entry->list);
  2094. return entry;
  2095. }
  2096. }
  2097. /* no free buffer in pool so take first one and swap pages */
  2098. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2099. struct qeth_buffer_pool_entry, list);
  2100. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2101. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2102. page = alloc_page(GFP_ATOMIC);
  2103. if (!page) {
  2104. return NULL;
  2105. } else {
  2106. free_page((unsigned long)entry->elements[i]);
  2107. entry->elements[i] = page_address(page);
  2108. if (card->options.performance_stats)
  2109. card->perf_stats.sg_alloc_page_rx++;
  2110. }
  2111. }
  2112. }
  2113. list_del_init(&entry->list);
  2114. return entry;
  2115. }
  2116. static int qeth_init_input_buffer(struct qeth_card *card,
  2117. struct qeth_qdio_buffer *buf)
  2118. {
  2119. struct qeth_buffer_pool_entry *pool_entry;
  2120. int i;
  2121. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2122. if (!pool_entry)
  2123. return 1;
  2124. /*
  2125. * since the buffer is accessed only from the input_tasklet
  2126. * there shouldn't be a need to synchronize; also, since we use
  2127. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2128. * buffers
  2129. */
  2130. buf->pool_entry = pool_entry;
  2131. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2132. buf->buffer->element[i].length = PAGE_SIZE;
  2133. buf->buffer->element[i].addr = pool_entry->elements[i];
  2134. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2135. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2136. else
  2137. buf->buffer->element[i].flags = 0;
  2138. }
  2139. return 0;
  2140. }
  2141. int qeth_init_qdio_queues(struct qeth_card *card)
  2142. {
  2143. int i, j;
  2144. int rc;
  2145. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2146. /* inbound queue */
  2147. memset(card->qdio.in_q->qdio_bufs, 0,
  2148. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2149. qeth_initialize_working_pool_list(card);
  2150. /*give only as many buffers to hardware as we have buffer pool entries*/
  2151. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2152. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2153. card->qdio.in_q->next_buf_to_init =
  2154. card->qdio.in_buf_pool.buf_count - 1;
  2155. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2156. card->qdio.in_buf_pool.buf_count - 1);
  2157. if (rc) {
  2158. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2159. return rc;
  2160. }
  2161. /* outbound queue */
  2162. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2163. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2164. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2165. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2166. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2167. &card->qdio.out_qs[i]->bufs[j]);
  2168. }
  2169. card->qdio.out_qs[i]->card = card;
  2170. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2171. card->qdio.out_qs[i]->do_pack = 0;
  2172. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2173. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2174. atomic_set(&card->qdio.out_qs[i]->state,
  2175. QETH_OUT_Q_UNLOCKED);
  2176. }
  2177. return 0;
  2178. }
  2179. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2180. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2181. {
  2182. switch (link_type) {
  2183. case QETH_LINK_TYPE_HSTR:
  2184. return 2;
  2185. default:
  2186. return 1;
  2187. }
  2188. }
  2189. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2190. struct qeth_ipa_cmd *cmd, __u8 command,
  2191. enum qeth_prot_versions prot)
  2192. {
  2193. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2194. cmd->hdr.command = command;
  2195. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2196. cmd->hdr.seqno = card->seqno.ipa;
  2197. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2198. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2199. if (card->options.layer2)
  2200. cmd->hdr.prim_version_no = 2;
  2201. else
  2202. cmd->hdr.prim_version_no = 1;
  2203. cmd->hdr.param_count = 1;
  2204. cmd->hdr.prot_version = prot;
  2205. cmd->hdr.ipa_supported = 0;
  2206. cmd->hdr.ipa_enabled = 0;
  2207. }
  2208. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2209. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2210. {
  2211. struct qeth_cmd_buffer *iob;
  2212. struct qeth_ipa_cmd *cmd;
  2213. iob = qeth_wait_for_buffer(&card->write);
  2214. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2215. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2216. return iob;
  2217. }
  2218. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2219. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2220. char prot_type)
  2221. {
  2222. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2223. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2224. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2225. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2226. }
  2227. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2228. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2229. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2230. unsigned long),
  2231. void *reply_param)
  2232. {
  2233. int rc;
  2234. char prot_type;
  2235. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2236. if (card->options.layer2)
  2237. if (card->info.type == QETH_CARD_TYPE_OSN)
  2238. prot_type = QETH_PROT_OSN2;
  2239. else
  2240. prot_type = QETH_PROT_LAYER2;
  2241. else
  2242. prot_type = QETH_PROT_TCPIP;
  2243. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2244. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2245. iob, reply_cb, reply_param);
  2246. return rc;
  2247. }
  2248. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2249. static int qeth_send_startstoplan(struct qeth_card *card,
  2250. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2251. {
  2252. int rc;
  2253. struct qeth_cmd_buffer *iob;
  2254. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2255. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2256. return rc;
  2257. }
  2258. int qeth_send_startlan(struct qeth_card *card)
  2259. {
  2260. int rc;
  2261. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2262. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2263. return rc;
  2264. }
  2265. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2266. int qeth_send_stoplan(struct qeth_card *card)
  2267. {
  2268. int rc = 0;
  2269. /*
  2270. * TODO: according to the IPA format document page 14,
  2271. * TCP/IP (we!) never issue a STOPLAN
  2272. * is this right ?!?
  2273. */
  2274. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2275. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2276. return rc;
  2277. }
  2278. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2279. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2280. struct qeth_reply *reply, unsigned long data)
  2281. {
  2282. struct qeth_ipa_cmd *cmd;
  2283. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2284. cmd = (struct qeth_ipa_cmd *) data;
  2285. if (cmd->hdr.return_code == 0)
  2286. cmd->hdr.return_code =
  2287. cmd->data.setadapterparms.hdr.return_code;
  2288. return 0;
  2289. }
  2290. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2291. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2292. struct qeth_reply *reply, unsigned long data)
  2293. {
  2294. struct qeth_ipa_cmd *cmd;
  2295. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2296. cmd = (struct qeth_ipa_cmd *) data;
  2297. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2298. card->info.link_type =
  2299. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2300. card->options.adp.supported_funcs =
  2301. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2302. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2303. }
  2304. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2305. __u32 command, __u32 cmdlen)
  2306. {
  2307. struct qeth_cmd_buffer *iob;
  2308. struct qeth_ipa_cmd *cmd;
  2309. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2310. QETH_PROT_IPV4);
  2311. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2312. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2313. cmd->data.setadapterparms.hdr.command_code = command;
  2314. cmd->data.setadapterparms.hdr.used_total = 1;
  2315. cmd->data.setadapterparms.hdr.seq_no = 1;
  2316. return iob;
  2317. }
  2318. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2319. int qeth_query_setadapterparms(struct qeth_card *card)
  2320. {
  2321. int rc;
  2322. struct qeth_cmd_buffer *iob;
  2323. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2324. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2325. sizeof(struct qeth_ipacmd_setadpparms));
  2326. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2327. return rc;
  2328. }
  2329. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2330. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2331. const char *dbftext)
  2332. {
  2333. if (qdio_error) {
  2334. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2335. QETH_DBF_TEXT(QERR, 2, dbftext);
  2336. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2337. buf->element[15].flags & 0xff);
  2338. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2339. buf->element[14].flags & 0xff);
  2340. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2341. return 1;
  2342. }
  2343. return 0;
  2344. }
  2345. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2346. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2347. {
  2348. struct qeth_qdio_q *queue = card->qdio.in_q;
  2349. int count;
  2350. int i;
  2351. int rc;
  2352. int newcount = 0;
  2353. count = (index < queue->next_buf_to_init)?
  2354. card->qdio.in_buf_pool.buf_count -
  2355. (queue->next_buf_to_init - index) :
  2356. card->qdio.in_buf_pool.buf_count -
  2357. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2358. /* only requeue at a certain threshold to avoid SIGAs */
  2359. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2360. for (i = queue->next_buf_to_init;
  2361. i < queue->next_buf_to_init + count; ++i) {
  2362. if (qeth_init_input_buffer(card,
  2363. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2364. break;
  2365. } else {
  2366. newcount++;
  2367. }
  2368. }
  2369. if (newcount < count) {
  2370. /* we are in memory shortage so we switch back to
  2371. traditional skb allocation and drop packages */
  2372. atomic_set(&card->force_alloc_skb, 3);
  2373. count = newcount;
  2374. } else {
  2375. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2376. }
  2377. /*
  2378. * according to old code it should be avoided to requeue all
  2379. * 128 buffers in order to benefit from PCI avoidance.
  2380. * this function keeps at least one buffer (the buffer at
  2381. * 'index') un-requeued -> this buffer is the first buffer that
  2382. * will be requeued the next time
  2383. */
  2384. if (card->options.performance_stats) {
  2385. card->perf_stats.inbound_do_qdio_cnt++;
  2386. card->perf_stats.inbound_do_qdio_start_time =
  2387. qeth_get_micros();
  2388. }
  2389. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2390. queue->next_buf_to_init, count);
  2391. if (card->options.performance_stats)
  2392. card->perf_stats.inbound_do_qdio_time +=
  2393. qeth_get_micros() -
  2394. card->perf_stats.inbound_do_qdio_start_time;
  2395. if (rc) {
  2396. dev_warn(&card->gdev->dev,
  2397. "QDIO reported an error, rc=%i\n", rc);
  2398. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2399. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2400. }
  2401. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2402. QDIO_MAX_BUFFERS_PER_Q;
  2403. }
  2404. }
  2405. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2406. static int qeth_handle_send_error(struct qeth_card *card,
  2407. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2408. {
  2409. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2410. int cc = qdio_err & 3;
  2411. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2412. qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
  2413. switch (cc) {
  2414. case 0:
  2415. if (qdio_err) {
  2416. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2417. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2418. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2419. (u16)qdio_err, (u8)sbalf15);
  2420. return QETH_SEND_ERROR_LINK_FAILURE;
  2421. }
  2422. return QETH_SEND_ERROR_NONE;
  2423. case 2:
  2424. if (qdio_err & QDIO_ERROR_SIGA_BUSY) {
  2425. QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
  2426. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2427. return QETH_SEND_ERROR_KICK_IT;
  2428. }
  2429. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2430. return QETH_SEND_ERROR_RETRY;
  2431. return QETH_SEND_ERROR_LINK_FAILURE;
  2432. /* look at qdio_error and sbalf 15 */
  2433. case 1:
  2434. QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
  2435. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2436. return QETH_SEND_ERROR_LINK_FAILURE;
  2437. case 3:
  2438. default:
  2439. QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
  2440. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2441. return QETH_SEND_ERROR_KICK_IT;
  2442. }
  2443. }
  2444. /*
  2445. * Switched to packing state if the number of used buffers on a queue
  2446. * reaches a certain limit.
  2447. */
  2448. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2449. {
  2450. if (!queue->do_pack) {
  2451. if (atomic_read(&queue->used_buffers)
  2452. >= QETH_HIGH_WATERMARK_PACK){
  2453. /* switch non-PACKING -> PACKING */
  2454. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2455. if (queue->card->options.performance_stats)
  2456. queue->card->perf_stats.sc_dp_p++;
  2457. queue->do_pack = 1;
  2458. }
  2459. }
  2460. }
  2461. /*
  2462. * Switches from packing to non-packing mode. If there is a packing
  2463. * buffer on the queue this buffer will be prepared to be flushed.
  2464. * In that case 1 is returned to inform the caller. If no buffer
  2465. * has to be flushed, zero is returned.
  2466. */
  2467. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2468. {
  2469. struct qeth_qdio_out_buffer *buffer;
  2470. int flush_count = 0;
  2471. if (queue->do_pack) {
  2472. if (atomic_read(&queue->used_buffers)
  2473. <= QETH_LOW_WATERMARK_PACK) {
  2474. /* switch PACKING -> non-PACKING */
  2475. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2476. if (queue->card->options.performance_stats)
  2477. queue->card->perf_stats.sc_p_dp++;
  2478. queue->do_pack = 0;
  2479. /* flush packing buffers */
  2480. buffer = &queue->bufs[queue->next_buf_to_fill];
  2481. if ((atomic_read(&buffer->state) ==
  2482. QETH_QDIO_BUF_EMPTY) &&
  2483. (buffer->next_element_to_fill > 0)) {
  2484. atomic_set(&buffer->state,
  2485. QETH_QDIO_BUF_PRIMED);
  2486. flush_count++;
  2487. queue->next_buf_to_fill =
  2488. (queue->next_buf_to_fill + 1) %
  2489. QDIO_MAX_BUFFERS_PER_Q;
  2490. }
  2491. }
  2492. }
  2493. return flush_count;
  2494. }
  2495. /*
  2496. * Called to flush a packing buffer if no more pci flags are on the queue.
  2497. * Checks if there is a packing buffer and prepares it to be flushed.
  2498. * In that case returns 1, otherwise zero.
  2499. */
  2500. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2501. {
  2502. struct qeth_qdio_out_buffer *buffer;
  2503. buffer = &queue->bufs[queue->next_buf_to_fill];
  2504. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2505. (buffer->next_element_to_fill > 0)) {
  2506. /* it's a packing buffer */
  2507. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2508. queue->next_buf_to_fill =
  2509. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2510. return 1;
  2511. }
  2512. return 0;
  2513. }
  2514. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2515. int count)
  2516. {
  2517. struct qeth_qdio_out_buffer *buf;
  2518. int rc;
  2519. int i;
  2520. unsigned int qdio_flags;
  2521. for (i = index; i < index + count; ++i) {
  2522. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2523. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2524. SBAL_FLAGS_LAST_ENTRY;
  2525. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2526. continue;
  2527. if (!queue->do_pack) {
  2528. if ((atomic_read(&queue->used_buffers) >=
  2529. (QETH_HIGH_WATERMARK_PACK -
  2530. QETH_WATERMARK_PACK_FUZZ)) &&
  2531. !atomic_read(&queue->set_pci_flags_count)) {
  2532. /* it's likely that we'll go to packing
  2533. * mode soon */
  2534. atomic_inc(&queue->set_pci_flags_count);
  2535. buf->buffer->element[0].flags |= 0x40;
  2536. }
  2537. } else {
  2538. if (!atomic_read(&queue->set_pci_flags_count)) {
  2539. /*
  2540. * there's no outstanding PCI any more, so we
  2541. * have to request a PCI to be sure the the PCI
  2542. * will wake at some time in the future then we
  2543. * can flush packed buffers that might still be
  2544. * hanging around, which can happen if no
  2545. * further send was requested by the stack
  2546. */
  2547. atomic_inc(&queue->set_pci_flags_count);
  2548. buf->buffer->element[0].flags |= 0x40;
  2549. }
  2550. }
  2551. }
  2552. queue->card->dev->trans_start = jiffies;
  2553. if (queue->card->options.performance_stats) {
  2554. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2555. queue->card->perf_stats.outbound_do_qdio_start_time =
  2556. qeth_get_micros();
  2557. }
  2558. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2559. if (atomic_read(&queue->set_pci_flags_count))
  2560. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2561. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2562. queue->queue_no, index, count);
  2563. if (queue->card->options.performance_stats)
  2564. queue->card->perf_stats.outbound_do_qdio_time +=
  2565. qeth_get_micros() -
  2566. queue->card->perf_stats.outbound_do_qdio_start_time;
  2567. if (rc) {
  2568. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2569. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2570. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2571. queue->card->stats.tx_errors += count;
  2572. /* this must not happen under normal circumstances. if it
  2573. * happens something is really wrong -> recover */
  2574. qeth_schedule_recovery(queue->card);
  2575. return;
  2576. }
  2577. atomic_add(count, &queue->used_buffers);
  2578. if (queue->card->options.performance_stats)
  2579. queue->card->perf_stats.bufs_sent += count;
  2580. }
  2581. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2582. {
  2583. int index;
  2584. int flush_cnt = 0;
  2585. int q_was_packing = 0;
  2586. /*
  2587. * check if weed have to switch to non-packing mode or if
  2588. * we have to get a pci flag out on the queue
  2589. */
  2590. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2591. !atomic_read(&queue->set_pci_flags_count)) {
  2592. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2593. QETH_OUT_Q_UNLOCKED) {
  2594. /*
  2595. * If we get in here, there was no action in
  2596. * do_send_packet. So, we check if there is a
  2597. * packing buffer to be flushed here.
  2598. */
  2599. netif_stop_queue(queue->card->dev);
  2600. index = queue->next_buf_to_fill;
  2601. q_was_packing = queue->do_pack;
  2602. /* queue->do_pack may change */
  2603. barrier();
  2604. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2605. if (!flush_cnt &&
  2606. !atomic_read(&queue->set_pci_flags_count))
  2607. flush_cnt +=
  2608. qeth_flush_buffers_on_no_pci(queue);
  2609. if (queue->card->options.performance_stats &&
  2610. q_was_packing)
  2611. queue->card->perf_stats.bufs_sent_pack +=
  2612. flush_cnt;
  2613. if (flush_cnt)
  2614. qeth_flush_buffers(queue, index, flush_cnt);
  2615. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2616. }
  2617. }
  2618. }
  2619. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2620. unsigned int qdio_error, int __queue, int first_element,
  2621. int count, unsigned long card_ptr)
  2622. {
  2623. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2624. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2625. struct qeth_qdio_out_buffer *buffer;
  2626. int i;
  2627. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2628. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2629. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2630. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2631. netif_stop_queue(card->dev);
  2632. qeth_schedule_recovery(card);
  2633. return;
  2634. }
  2635. if (card->options.performance_stats) {
  2636. card->perf_stats.outbound_handler_cnt++;
  2637. card->perf_stats.outbound_handler_start_time =
  2638. qeth_get_micros();
  2639. }
  2640. for (i = first_element; i < (first_element + count); ++i) {
  2641. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2642. /*we only handle the KICK_IT error by doing a recovery */
  2643. if (qeth_handle_send_error(card, buffer, qdio_error)
  2644. == QETH_SEND_ERROR_KICK_IT){
  2645. netif_stop_queue(card->dev);
  2646. qeth_schedule_recovery(card);
  2647. return;
  2648. }
  2649. qeth_clear_output_buffer(queue, buffer);
  2650. }
  2651. atomic_sub(count, &queue->used_buffers);
  2652. /* check if we need to do something on this outbound queue */
  2653. if (card->info.type != QETH_CARD_TYPE_IQD)
  2654. qeth_check_outbound_queue(queue);
  2655. netif_wake_queue(queue->card->dev);
  2656. if (card->options.performance_stats)
  2657. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2658. card->perf_stats.outbound_handler_start_time;
  2659. }
  2660. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2661. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2662. {
  2663. int cast_type = RTN_UNSPEC;
  2664. if (card->info.type == QETH_CARD_TYPE_OSN)
  2665. return cast_type;
  2666. if (skb->dst && skb->dst->neighbour) {
  2667. cast_type = skb->dst->neighbour->type;
  2668. if ((cast_type == RTN_BROADCAST) ||
  2669. (cast_type == RTN_MULTICAST) ||
  2670. (cast_type == RTN_ANYCAST))
  2671. return cast_type;
  2672. else
  2673. return RTN_UNSPEC;
  2674. }
  2675. /* try something else */
  2676. if (skb->protocol == ETH_P_IPV6)
  2677. return (skb_network_header(skb)[24] == 0xff) ?
  2678. RTN_MULTICAST : 0;
  2679. else if (skb->protocol == ETH_P_IP)
  2680. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2681. RTN_MULTICAST : 0;
  2682. /* ... */
  2683. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2684. return RTN_BROADCAST;
  2685. else {
  2686. u16 hdr_mac;
  2687. hdr_mac = *((u16 *)skb->data);
  2688. /* tr multicast? */
  2689. switch (card->info.link_type) {
  2690. case QETH_LINK_TYPE_HSTR:
  2691. case QETH_LINK_TYPE_LANE_TR:
  2692. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2693. (hdr_mac == QETH_TR_MAC_C))
  2694. return RTN_MULTICAST;
  2695. break;
  2696. /* eth or so multicast? */
  2697. default:
  2698. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2699. (hdr_mac == QETH_ETH_MAC_V6))
  2700. return RTN_MULTICAST;
  2701. }
  2702. }
  2703. return cast_type;
  2704. }
  2705. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2706. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2707. int ipv, int cast_type)
  2708. {
  2709. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2710. return card->qdio.default_out_queue;
  2711. switch (card->qdio.no_out_queues) {
  2712. case 4:
  2713. if (cast_type && card->info.is_multicast_different)
  2714. return card->info.is_multicast_different &
  2715. (card->qdio.no_out_queues - 1);
  2716. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2717. const u8 tos = ip_hdr(skb)->tos;
  2718. if (card->qdio.do_prio_queueing ==
  2719. QETH_PRIO_Q_ING_TOS) {
  2720. if (tos & IP_TOS_NOTIMPORTANT)
  2721. return 3;
  2722. if (tos & IP_TOS_HIGHRELIABILITY)
  2723. return 2;
  2724. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2725. return 1;
  2726. if (tos & IP_TOS_LOWDELAY)
  2727. return 0;
  2728. }
  2729. if (card->qdio.do_prio_queueing ==
  2730. QETH_PRIO_Q_ING_PREC)
  2731. return 3 - (tos >> 6);
  2732. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2733. /* TODO: IPv6!!! */
  2734. }
  2735. return card->qdio.default_out_queue;
  2736. case 1: /* fallthrough for single-out-queue 1920-device */
  2737. default:
  2738. return card->qdio.default_out_queue;
  2739. }
  2740. }
  2741. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2742. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2743. struct sk_buff *skb, int elems)
  2744. {
  2745. int elements_needed = 0;
  2746. if (skb_shinfo(skb)->nr_frags > 0)
  2747. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2748. if (elements_needed == 0)
  2749. elements_needed = 1 + (((((unsigned long) skb->data) %
  2750. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2751. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2752. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2753. "(Number=%d / Length=%d). Discarded.\n",
  2754. (elements_needed+elems), skb->len);
  2755. return 0;
  2756. }
  2757. return elements_needed;
  2758. }
  2759. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2760. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2761. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2762. int offset)
  2763. {
  2764. int length = skb->len;
  2765. int length_here;
  2766. int element;
  2767. char *data;
  2768. int first_lap ;
  2769. element = *next_element_to_fill;
  2770. data = skb->data;
  2771. first_lap = (is_tso == 0 ? 1 : 0);
  2772. if (offset >= 0) {
  2773. data = skb->data + offset;
  2774. length -= offset;
  2775. first_lap = 0;
  2776. }
  2777. while (length > 0) {
  2778. /* length_here is the remaining amount of data in this page */
  2779. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2780. if (length < length_here)
  2781. length_here = length;
  2782. buffer->element[element].addr = data;
  2783. buffer->element[element].length = length_here;
  2784. length -= length_here;
  2785. if (!length) {
  2786. if (first_lap)
  2787. buffer->element[element].flags = 0;
  2788. else
  2789. buffer->element[element].flags =
  2790. SBAL_FLAGS_LAST_FRAG;
  2791. } else {
  2792. if (first_lap)
  2793. buffer->element[element].flags =
  2794. SBAL_FLAGS_FIRST_FRAG;
  2795. else
  2796. buffer->element[element].flags =
  2797. SBAL_FLAGS_MIDDLE_FRAG;
  2798. }
  2799. data += length_here;
  2800. element++;
  2801. first_lap = 0;
  2802. }
  2803. *next_element_to_fill = element;
  2804. }
  2805. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2806. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2807. struct qeth_hdr *hdr, int offset, int hd_len)
  2808. {
  2809. struct qdio_buffer *buffer;
  2810. int flush_cnt = 0, hdr_len, large_send = 0;
  2811. buffer = buf->buffer;
  2812. atomic_inc(&skb->users);
  2813. skb_queue_tail(&buf->skb_list, skb);
  2814. /*check first on TSO ....*/
  2815. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2816. int element = buf->next_element_to_fill;
  2817. hdr_len = sizeof(struct qeth_hdr_tso) +
  2818. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2819. /*fill first buffer entry only with header information */
  2820. buffer->element[element].addr = skb->data;
  2821. buffer->element[element].length = hdr_len;
  2822. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2823. buf->next_element_to_fill++;
  2824. skb->data += hdr_len;
  2825. skb->len -= hdr_len;
  2826. large_send = 1;
  2827. }
  2828. if (offset >= 0) {
  2829. int element = buf->next_element_to_fill;
  2830. buffer->element[element].addr = hdr;
  2831. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2832. hd_len;
  2833. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2834. buf->is_header[element] = 1;
  2835. buf->next_element_to_fill++;
  2836. }
  2837. if (skb_shinfo(skb)->nr_frags == 0)
  2838. __qeth_fill_buffer(skb, buffer, large_send,
  2839. (int *)&buf->next_element_to_fill, offset);
  2840. else
  2841. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2842. (int *)&buf->next_element_to_fill);
  2843. if (!queue->do_pack) {
  2844. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2845. /* set state to PRIMED -> will be flushed */
  2846. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2847. flush_cnt = 1;
  2848. } else {
  2849. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2850. if (queue->card->options.performance_stats)
  2851. queue->card->perf_stats.skbs_sent_pack++;
  2852. if (buf->next_element_to_fill >=
  2853. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2854. /*
  2855. * packed buffer if full -> set state PRIMED
  2856. * -> will be flushed
  2857. */
  2858. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2859. flush_cnt = 1;
  2860. }
  2861. }
  2862. return flush_cnt;
  2863. }
  2864. int qeth_do_send_packet_fast(struct qeth_card *card,
  2865. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2866. struct qeth_hdr *hdr, int elements_needed,
  2867. struct qeth_eddp_context *ctx, int offset, int hd_len)
  2868. {
  2869. struct qeth_qdio_out_buffer *buffer;
  2870. int buffers_needed = 0;
  2871. int flush_cnt = 0;
  2872. int index;
  2873. /* spin until we get the queue ... */
  2874. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2875. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2876. /* ... now we've got the queue */
  2877. index = queue->next_buf_to_fill;
  2878. buffer = &queue->bufs[queue->next_buf_to_fill];
  2879. /*
  2880. * check if buffer is empty to make sure that we do not 'overtake'
  2881. * ourselves and try to fill a buffer that is already primed
  2882. */
  2883. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2884. goto out;
  2885. if (ctx == NULL)
  2886. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2887. QDIO_MAX_BUFFERS_PER_Q;
  2888. else {
  2889. buffers_needed = qeth_eddp_check_buffers_for_context(queue,
  2890. ctx);
  2891. if (buffers_needed < 0)
  2892. goto out;
  2893. queue->next_buf_to_fill =
  2894. (queue->next_buf_to_fill + buffers_needed) %
  2895. QDIO_MAX_BUFFERS_PER_Q;
  2896. }
  2897. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2898. if (ctx == NULL) {
  2899. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2900. qeth_flush_buffers(queue, index, 1);
  2901. } else {
  2902. flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
  2903. WARN_ON(buffers_needed != flush_cnt);
  2904. qeth_flush_buffers(queue, index, flush_cnt);
  2905. }
  2906. return 0;
  2907. out:
  2908. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2909. return -EBUSY;
  2910. }
  2911. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2912. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2913. struct sk_buff *skb, struct qeth_hdr *hdr,
  2914. int elements_needed, struct qeth_eddp_context *ctx)
  2915. {
  2916. struct qeth_qdio_out_buffer *buffer;
  2917. int start_index;
  2918. int flush_count = 0;
  2919. int do_pack = 0;
  2920. int tmp;
  2921. int rc = 0;
  2922. /* spin until we get the queue ... */
  2923. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2924. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2925. start_index = queue->next_buf_to_fill;
  2926. buffer = &queue->bufs[queue->next_buf_to_fill];
  2927. /*
  2928. * check if buffer is empty to make sure that we do not 'overtake'
  2929. * ourselves and try to fill a buffer that is already primed
  2930. */
  2931. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2932. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2933. return -EBUSY;
  2934. }
  2935. /* check if we need to switch packing state of this queue */
  2936. qeth_switch_to_packing_if_needed(queue);
  2937. if (queue->do_pack) {
  2938. do_pack = 1;
  2939. if (ctx == NULL) {
  2940. /* does packet fit in current buffer? */
  2941. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2942. buffer->next_element_to_fill) < elements_needed) {
  2943. /* ... no -> set state PRIMED */
  2944. atomic_set(&buffer->state,
  2945. QETH_QDIO_BUF_PRIMED);
  2946. flush_count++;
  2947. queue->next_buf_to_fill =
  2948. (queue->next_buf_to_fill + 1) %
  2949. QDIO_MAX_BUFFERS_PER_Q;
  2950. buffer = &queue->bufs[queue->next_buf_to_fill];
  2951. /* we did a step forward, so check buffer state
  2952. * again */
  2953. if (atomic_read(&buffer->state) !=
  2954. QETH_QDIO_BUF_EMPTY){
  2955. qeth_flush_buffers(queue, start_index,
  2956. flush_count);
  2957. atomic_set(&queue->state,
  2958. QETH_OUT_Q_UNLOCKED);
  2959. return -EBUSY;
  2960. }
  2961. }
  2962. } else {
  2963. /* check if we have enough elements (including following
  2964. * free buffers) to handle eddp context */
  2965. if (qeth_eddp_check_buffers_for_context(queue, ctx)
  2966. < 0) {
  2967. rc = -EBUSY;
  2968. goto out;
  2969. }
  2970. }
  2971. }
  2972. if (ctx == NULL)
  2973. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2974. else {
  2975. tmp = qeth_eddp_fill_buffer(queue, ctx,
  2976. queue->next_buf_to_fill);
  2977. if (tmp < 0) {
  2978. rc = -EBUSY;
  2979. goto out;
  2980. }
  2981. }
  2982. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2983. QDIO_MAX_BUFFERS_PER_Q;
  2984. flush_count += tmp;
  2985. out:
  2986. if (flush_count)
  2987. qeth_flush_buffers(queue, start_index, flush_count);
  2988. else if (!atomic_read(&queue->set_pci_flags_count))
  2989. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2990. /*
  2991. * queue->state will go from LOCKED -> UNLOCKED or from
  2992. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2993. * (switch packing state or flush buffer to get another pci flag out).
  2994. * In that case we will enter this loop
  2995. */
  2996. while (atomic_dec_return(&queue->state)) {
  2997. flush_count = 0;
  2998. start_index = queue->next_buf_to_fill;
  2999. /* check if we can go back to non-packing state */
  3000. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3001. /*
  3002. * check if we need to flush a packing buffer to get a pci
  3003. * flag out on the queue
  3004. */
  3005. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3006. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3007. if (flush_count)
  3008. qeth_flush_buffers(queue, start_index, flush_count);
  3009. }
  3010. /* at this point the queue is UNLOCKED again */
  3011. if (queue->card->options.performance_stats && do_pack)
  3012. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3013. return rc;
  3014. }
  3015. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3016. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3017. struct qeth_reply *reply, unsigned long data)
  3018. {
  3019. struct qeth_ipa_cmd *cmd;
  3020. struct qeth_ipacmd_setadpparms *setparms;
  3021. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  3022. cmd = (struct qeth_ipa_cmd *) data;
  3023. setparms = &(cmd->data.setadapterparms);
  3024. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3025. if (cmd->hdr.return_code) {
  3026. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3027. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3028. }
  3029. card->info.promisc_mode = setparms->data.mode;
  3030. return 0;
  3031. }
  3032. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3033. {
  3034. enum qeth_ipa_promisc_modes mode;
  3035. struct net_device *dev = card->dev;
  3036. struct qeth_cmd_buffer *iob;
  3037. struct qeth_ipa_cmd *cmd;
  3038. QETH_DBF_TEXT(TRACE, 4, "setprom");
  3039. if (((dev->flags & IFF_PROMISC) &&
  3040. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3041. (!(dev->flags & IFF_PROMISC) &&
  3042. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3043. return;
  3044. mode = SET_PROMISC_MODE_OFF;
  3045. if (dev->flags & IFF_PROMISC)
  3046. mode = SET_PROMISC_MODE_ON;
  3047. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  3048. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3049. sizeof(struct qeth_ipacmd_setadpparms));
  3050. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3051. cmd->data.setadapterparms.data.mode = mode;
  3052. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3053. }
  3054. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3055. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3056. {
  3057. struct qeth_card *card;
  3058. char dbf_text[15];
  3059. card = dev->ml_priv;
  3060. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  3061. sprintf(dbf_text, "%8x", new_mtu);
  3062. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  3063. if (new_mtu < 64)
  3064. return -EINVAL;
  3065. if (new_mtu > 65535)
  3066. return -EINVAL;
  3067. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3068. (!qeth_mtu_is_valid(card, new_mtu)))
  3069. return -EINVAL;
  3070. dev->mtu = new_mtu;
  3071. return 0;
  3072. }
  3073. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3074. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3075. {
  3076. struct qeth_card *card;
  3077. card = dev->ml_priv;
  3078. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3079. return &card->stats;
  3080. }
  3081. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3082. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3083. struct qeth_reply *reply, unsigned long data)
  3084. {
  3085. struct qeth_ipa_cmd *cmd;
  3086. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3087. cmd = (struct qeth_ipa_cmd *) data;
  3088. if (!card->options.layer2 ||
  3089. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3090. memcpy(card->dev->dev_addr,
  3091. &cmd->data.setadapterparms.data.change_addr.addr,
  3092. OSA_ADDR_LEN);
  3093. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3094. }
  3095. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3096. return 0;
  3097. }
  3098. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3099. {
  3100. int rc;
  3101. struct qeth_cmd_buffer *iob;
  3102. struct qeth_ipa_cmd *cmd;
  3103. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3104. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3105. sizeof(struct qeth_ipacmd_setadpparms));
  3106. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3107. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3108. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3109. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3110. card->dev->dev_addr, OSA_ADDR_LEN);
  3111. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3112. NULL);
  3113. return rc;
  3114. }
  3115. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3116. void qeth_tx_timeout(struct net_device *dev)
  3117. {
  3118. struct qeth_card *card;
  3119. card = dev->ml_priv;
  3120. card->stats.tx_errors++;
  3121. qeth_schedule_recovery(card);
  3122. }
  3123. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3124. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3125. {
  3126. struct qeth_card *card = dev->ml_priv;
  3127. int rc = 0;
  3128. switch (regnum) {
  3129. case MII_BMCR: /* Basic mode control register */
  3130. rc = BMCR_FULLDPLX;
  3131. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3132. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3133. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3134. rc |= BMCR_SPEED100;
  3135. break;
  3136. case MII_BMSR: /* Basic mode status register */
  3137. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3138. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3139. BMSR_100BASE4;
  3140. break;
  3141. case MII_PHYSID1: /* PHYS ID 1 */
  3142. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3143. dev->dev_addr[2];
  3144. rc = (rc >> 5) & 0xFFFF;
  3145. break;
  3146. case MII_PHYSID2: /* PHYS ID 2 */
  3147. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3148. break;
  3149. case MII_ADVERTISE: /* Advertisement control reg */
  3150. rc = ADVERTISE_ALL;
  3151. break;
  3152. case MII_LPA: /* Link partner ability reg */
  3153. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3154. LPA_100BASE4 | LPA_LPACK;
  3155. break;
  3156. case MII_EXPANSION: /* Expansion register */
  3157. break;
  3158. case MII_DCOUNTER: /* disconnect counter */
  3159. break;
  3160. case MII_FCSCOUNTER: /* false carrier counter */
  3161. break;
  3162. case MII_NWAYTEST: /* N-way auto-neg test register */
  3163. break;
  3164. case MII_RERRCOUNTER: /* rx error counter */
  3165. rc = card->stats.rx_errors;
  3166. break;
  3167. case MII_SREVISION: /* silicon revision */
  3168. break;
  3169. case MII_RESV1: /* reserved 1 */
  3170. break;
  3171. case MII_LBRERROR: /* loopback, rx, bypass error */
  3172. break;
  3173. case MII_PHYADDR: /* physical address */
  3174. break;
  3175. case MII_RESV2: /* reserved 2 */
  3176. break;
  3177. case MII_TPISTATUS: /* TPI status for 10mbps */
  3178. break;
  3179. case MII_NCONFIG: /* network interface config */
  3180. break;
  3181. default:
  3182. break;
  3183. }
  3184. return rc;
  3185. }
  3186. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3187. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3188. struct qeth_cmd_buffer *iob, int len,
  3189. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3190. unsigned long),
  3191. void *reply_param)
  3192. {
  3193. u16 s1, s2;
  3194. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3195. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3196. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3197. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3198. /* adjust PDU length fields in IPA_PDU_HEADER */
  3199. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3200. s2 = (u32) len;
  3201. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3202. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3203. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3204. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3205. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3206. reply_cb, reply_param);
  3207. }
  3208. static int qeth_snmp_command_cb(struct qeth_card *card,
  3209. struct qeth_reply *reply, unsigned long sdata)
  3210. {
  3211. struct qeth_ipa_cmd *cmd;
  3212. struct qeth_arp_query_info *qinfo;
  3213. struct qeth_snmp_cmd *snmp;
  3214. unsigned char *data;
  3215. __u16 data_len;
  3216. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3217. cmd = (struct qeth_ipa_cmd *) sdata;
  3218. data = (unsigned char *)((char *)cmd - reply->offset);
  3219. qinfo = (struct qeth_arp_query_info *) reply->param;
  3220. snmp = &cmd->data.setadapterparms.data.snmp;
  3221. if (cmd->hdr.return_code) {
  3222. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3223. return 0;
  3224. }
  3225. if (cmd->data.setadapterparms.hdr.return_code) {
  3226. cmd->hdr.return_code =
  3227. cmd->data.setadapterparms.hdr.return_code;
  3228. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3229. return 0;
  3230. }
  3231. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3232. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3233. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3234. else
  3235. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3236. /* check if there is enough room in userspace */
  3237. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3238. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3239. cmd->hdr.return_code = -ENOMEM;
  3240. return 0;
  3241. }
  3242. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3243. cmd->data.setadapterparms.hdr.used_total);
  3244. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3245. cmd->data.setadapterparms.hdr.seq_no);
  3246. /*copy entries to user buffer*/
  3247. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3248. memcpy(qinfo->udata + qinfo->udata_offset,
  3249. (char *)snmp,
  3250. data_len + offsetof(struct qeth_snmp_cmd, data));
  3251. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3252. } else {
  3253. memcpy(qinfo->udata + qinfo->udata_offset,
  3254. (char *)&snmp->request, data_len);
  3255. }
  3256. qinfo->udata_offset += data_len;
  3257. /* check if all replies received ... */
  3258. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3259. cmd->data.setadapterparms.hdr.used_total);
  3260. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3261. cmd->data.setadapterparms.hdr.seq_no);
  3262. if (cmd->data.setadapterparms.hdr.seq_no <
  3263. cmd->data.setadapterparms.hdr.used_total)
  3264. return 1;
  3265. return 0;
  3266. }
  3267. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3268. {
  3269. struct qeth_cmd_buffer *iob;
  3270. struct qeth_ipa_cmd *cmd;
  3271. struct qeth_snmp_ureq *ureq;
  3272. int req_len;
  3273. struct qeth_arp_query_info qinfo = {0, };
  3274. int rc = 0;
  3275. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3276. if (card->info.guestlan)
  3277. return -EOPNOTSUPP;
  3278. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3279. (!card->options.layer2)) {
  3280. return -EOPNOTSUPP;
  3281. }
  3282. /* skip 4 bytes (data_len struct member) to get req_len */
  3283. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3284. return -EFAULT;
  3285. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3286. if (!ureq) {
  3287. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3288. return -ENOMEM;
  3289. }
  3290. if (copy_from_user(ureq, udata,
  3291. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3292. kfree(ureq);
  3293. return -EFAULT;
  3294. }
  3295. qinfo.udata_len = ureq->hdr.data_len;
  3296. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3297. if (!qinfo.udata) {
  3298. kfree(ureq);
  3299. return -ENOMEM;
  3300. }
  3301. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3302. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3303. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3304. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3305. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3306. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3307. qeth_snmp_command_cb, (void *)&qinfo);
  3308. if (rc)
  3309. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3310. QETH_CARD_IFNAME(card), rc);
  3311. else {
  3312. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3313. rc = -EFAULT;
  3314. }
  3315. kfree(ureq);
  3316. kfree(qinfo.udata);
  3317. return rc;
  3318. }
  3319. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3320. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3321. {
  3322. switch (card->info.type) {
  3323. case QETH_CARD_TYPE_IQD:
  3324. return 2;
  3325. default:
  3326. return 0;
  3327. }
  3328. }
  3329. static int qeth_qdio_establish(struct qeth_card *card)
  3330. {
  3331. struct qdio_initialize init_data;
  3332. char *qib_param_field;
  3333. struct qdio_buffer **in_sbal_ptrs;
  3334. struct qdio_buffer **out_sbal_ptrs;
  3335. int i, j, k;
  3336. int rc = 0;
  3337. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3338. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3339. GFP_KERNEL);
  3340. if (!qib_param_field)
  3341. return -ENOMEM;
  3342. qeth_create_qib_param_field(card, qib_param_field);
  3343. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3344. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3345. GFP_KERNEL);
  3346. if (!in_sbal_ptrs) {
  3347. kfree(qib_param_field);
  3348. return -ENOMEM;
  3349. }
  3350. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3351. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3352. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3353. out_sbal_ptrs =
  3354. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3355. sizeof(void *), GFP_KERNEL);
  3356. if (!out_sbal_ptrs) {
  3357. kfree(in_sbal_ptrs);
  3358. kfree(qib_param_field);
  3359. return -ENOMEM;
  3360. }
  3361. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3362. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3363. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3364. card->qdio.out_qs[i]->bufs[j].buffer);
  3365. }
  3366. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3367. init_data.cdev = CARD_DDEV(card);
  3368. init_data.q_format = qeth_get_qdio_q_format(card);
  3369. init_data.qib_param_field_format = 0;
  3370. init_data.qib_param_field = qib_param_field;
  3371. init_data.no_input_qs = 1;
  3372. init_data.no_output_qs = card->qdio.no_out_queues;
  3373. init_data.input_handler = card->discipline.input_handler;
  3374. init_data.output_handler = card->discipline.output_handler;
  3375. init_data.int_parm = (unsigned long) card;
  3376. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3377. QDIO_OUTBOUND_0COPY_SBALS |
  3378. QDIO_USE_OUTBOUND_PCIS;
  3379. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3380. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3381. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3382. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3383. rc = qdio_initialize(&init_data);
  3384. if (rc)
  3385. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3386. }
  3387. kfree(out_sbal_ptrs);
  3388. kfree(in_sbal_ptrs);
  3389. kfree(qib_param_field);
  3390. return rc;
  3391. }
  3392. static void qeth_core_free_card(struct qeth_card *card)
  3393. {
  3394. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3395. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3396. qeth_clean_channel(&card->read);
  3397. qeth_clean_channel(&card->write);
  3398. if (card->dev)
  3399. free_netdev(card->dev);
  3400. kfree(card->ip_tbd_list);
  3401. qeth_free_qdio_buffers(card);
  3402. unregister_service_level(&card->qeth_service_level);
  3403. kfree(card);
  3404. }
  3405. static struct ccw_device_id qeth_ids[] = {
  3406. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3407. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3408. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3409. {},
  3410. };
  3411. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3412. static struct ccw_driver qeth_ccw_driver = {
  3413. .name = "qeth",
  3414. .ids = qeth_ids,
  3415. .probe = ccwgroup_probe_ccwdev,
  3416. .remove = ccwgroup_remove_ccwdev,
  3417. };
  3418. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3419. unsigned long driver_id)
  3420. {
  3421. return ccwgroup_create_from_string(root_dev, driver_id,
  3422. &qeth_ccw_driver, 3, buf);
  3423. }
  3424. int qeth_core_hardsetup_card(struct qeth_card *card)
  3425. {
  3426. struct qdio_ssqd_desc *ssqd;
  3427. int retries = 3;
  3428. int mpno = 0;
  3429. int rc;
  3430. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3431. atomic_set(&card->force_alloc_skb, 0);
  3432. retry:
  3433. if (retries < 3) {
  3434. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3435. dev_name(&card->gdev->dev));
  3436. ccw_device_set_offline(CARD_DDEV(card));
  3437. ccw_device_set_offline(CARD_WDEV(card));
  3438. ccw_device_set_offline(CARD_RDEV(card));
  3439. ccw_device_set_online(CARD_RDEV(card));
  3440. ccw_device_set_online(CARD_WDEV(card));
  3441. ccw_device_set_online(CARD_DDEV(card));
  3442. }
  3443. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3444. if (rc == -ERESTARTSYS) {
  3445. QETH_DBF_TEXT(SETUP, 2, "break1");
  3446. return rc;
  3447. } else if (rc) {
  3448. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3449. if (--retries < 0)
  3450. goto out;
  3451. else
  3452. goto retry;
  3453. }
  3454. rc = qeth_get_unitaddr(card);
  3455. if (rc) {
  3456. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3457. return rc;
  3458. }
  3459. ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL);
  3460. if (!ssqd) {
  3461. rc = -ENOMEM;
  3462. goto out;
  3463. }
  3464. rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd);
  3465. if (rc == 0)
  3466. mpno = ssqd->pcnt;
  3467. kfree(ssqd);
  3468. if (mpno)
  3469. mpno = min(mpno - 1, QETH_MAX_PORTNO);
  3470. if (card->info.portno > mpno) {
  3471. QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
  3472. "\n.", CARD_BUS_ID(card), card->info.portno);
  3473. rc = -ENODEV;
  3474. goto out;
  3475. }
  3476. qeth_init_tokens(card);
  3477. qeth_init_func_level(card);
  3478. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3479. if (rc == -ERESTARTSYS) {
  3480. QETH_DBF_TEXT(SETUP, 2, "break2");
  3481. return rc;
  3482. } else if (rc) {
  3483. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3484. if (--retries < 0)
  3485. goto out;
  3486. else
  3487. goto retry;
  3488. }
  3489. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3490. if (rc == -ERESTARTSYS) {
  3491. QETH_DBF_TEXT(SETUP, 2, "break3");
  3492. return rc;
  3493. } else if (rc) {
  3494. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3495. if (--retries < 0)
  3496. goto out;
  3497. else
  3498. goto retry;
  3499. }
  3500. rc = qeth_mpc_initialize(card);
  3501. if (rc) {
  3502. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3503. goto out;
  3504. }
  3505. return 0;
  3506. out:
  3507. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3508. "an error on the device\n");
  3509. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3510. dev_name(&card->gdev->dev), rc);
  3511. return rc;
  3512. }
  3513. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3514. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3515. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3516. {
  3517. struct page *page = virt_to_page(element->addr);
  3518. if (*pskb == NULL) {
  3519. /* the upper protocol layers assume that there is data in the
  3520. * skb itself. Copy a small amount (64 bytes) to make them
  3521. * happy. */
  3522. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3523. if (!(*pskb))
  3524. return -ENOMEM;
  3525. skb_reserve(*pskb, ETH_HLEN);
  3526. if (data_len <= 64) {
  3527. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3528. data_len);
  3529. } else {
  3530. get_page(page);
  3531. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3532. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3533. data_len - 64);
  3534. (*pskb)->data_len += data_len - 64;
  3535. (*pskb)->len += data_len - 64;
  3536. (*pskb)->truesize += data_len - 64;
  3537. (*pfrag)++;
  3538. }
  3539. } else {
  3540. get_page(page);
  3541. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3542. (*pskb)->data_len += data_len;
  3543. (*pskb)->len += data_len;
  3544. (*pskb)->truesize += data_len;
  3545. (*pfrag)++;
  3546. }
  3547. return 0;
  3548. }
  3549. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3550. struct qdio_buffer *buffer,
  3551. struct qdio_buffer_element **__element, int *__offset,
  3552. struct qeth_hdr **hdr)
  3553. {
  3554. struct qdio_buffer_element *element = *__element;
  3555. int offset = *__offset;
  3556. struct sk_buff *skb = NULL;
  3557. int skb_len;
  3558. void *data_ptr;
  3559. int data_len;
  3560. int headroom = 0;
  3561. int use_rx_sg = 0;
  3562. int frag = 0;
  3563. /* qeth_hdr must not cross element boundaries */
  3564. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3565. if (qeth_is_last_sbale(element))
  3566. return NULL;
  3567. element++;
  3568. offset = 0;
  3569. if (element->length < sizeof(struct qeth_hdr))
  3570. return NULL;
  3571. }
  3572. *hdr = element->addr + offset;
  3573. offset += sizeof(struct qeth_hdr);
  3574. if (card->options.layer2) {
  3575. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3576. skb_len = (*hdr)->hdr.osn.pdu_length;
  3577. headroom = sizeof(struct qeth_hdr);
  3578. } else {
  3579. skb_len = (*hdr)->hdr.l2.pkt_length;
  3580. }
  3581. } else {
  3582. skb_len = (*hdr)->hdr.l3.length;
  3583. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3584. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3585. headroom = TR_HLEN;
  3586. else
  3587. headroom = ETH_HLEN;
  3588. }
  3589. if (!skb_len)
  3590. return NULL;
  3591. if ((skb_len >= card->options.rx_sg_cb) &&
  3592. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3593. (!atomic_read(&card->force_alloc_skb))) {
  3594. use_rx_sg = 1;
  3595. } else {
  3596. skb = dev_alloc_skb(skb_len + headroom);
  3597. if (!skb)
  3598. goto no_mem;
  3599. if (headroom)
  3600. skb_reserve(skb, headroom);
  3601. }
  3602. data_ptr = element->addr + offset;
  3603. while (skb_len) {
  3604. data_len = min(skb_len, (int)(element->length - offset));
  3605. if (data_len) {
  3606. if (use_rx_sg) {
  3607. if (qeth_create_skb_frag(element, &skb, offset,
  3608. &frag, data_len))
  3609. goto no_mem;
  3610. } else {
  3611. memcpy(skb_put(skb, data_len), data_ptr,
  3612. data_len);
  3613. }
  3614. }
  3615. skb_len -= data_len;
  3616. if (skb_len) {
  3617. if (qeth_is_last_sbale(element)) {
  3618. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3619. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3620. CARD_BUS_ID(card));
  3621. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3622. QETH_DBF_TEXT_(QERR, 2, "%s",
  3623. CARD_BUS_ID(card));
  3624. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3625. dev_kfree_skb_any(skb);
  3626. card->stats.rx_errors++;
  3627. return NULL;
  3628. }
  3629. element++;
  3630. offset = 0;
  3631. data_ptr = element->addr;
  3632. } else {
  3633. offset += data_len;
  3634. }
  3635. }
  3636. *__element = element;
  3637. *__offset = offset;
  3638. if (use_rx_sg && card->options.performance_stats) {
  3639. card->perf_stats.sg_skbs_rx++;
  3640. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3641. }
  3642. return skb;
  3643. no_mem:
  3644. if (net_ratelimit()) {
  3645. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3646. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3647. }
  3648. card->stats.rx_dropped++;
  3649. return NULL;
  3650. }
  3651. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3652. static void qeth_unregister_dbf_views(void)
  3653. {
  3654. int x;
  3655. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3656. debug_unregister(qeth_dbf[x].id);
  3657. qeth_dbf[x].id = NULL;
  3658. }
  3659. }
  3660. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3661. {
  3662. char dbf_txt_buf[32];
  3663. va_list args;
  3664. if (level > (qeth_dbf[dbf_nix].id)->level)
  3665. return;
  3666. va_start(args, fmt);
  3667. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3668. va_end(args);
  3669. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3670. }
  3671. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3672. static int qeth_register_dbf_views(void)
  3673. {
  3674. int ret;
  3675. int x;
  3676. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3677. /* register the areas */
  3678. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3679. qeth_dbf[x].pages,
  3680. qeth_dbf[x].areas,
  3681. qeth_dbf[x].len);
  3682. if (qeth_dbf[x].id == NULL) {
  3683. qeth_unregister_dbf_views();
  3684. return -ENOMEM;
  3685. }
  3686. /* register a view */
  3687. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3688. if (ret) {
  3689. qeth_unregister_dbf_views();
  3690. return ret;
  3691. }
  3692. /* set a passing level */
  3693. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3694. }
  3695. return 0;
  3696. }
  3697. int qeth_core_load_discipline(struct qeth_card *card,
  3698. enum qeth_discipline_id discipline)
  3699. {
  3700. int rc = 0;
  3701. switch (discipline) {
  3702. case QETH_DISCIPLINE_LAYER3:
  3703. card->discipline.ccwgdriver = try_then_request_module(
  3704. symbol_get(qeth_l3_ccwgroup_driver),
  3705. "qeth_l3");
  3706. break;
  3707. case QETH_DISCIPLINE_LAYER2:
  3708. card->discipline.ccwgdriver = try_then_request_module(
  3709. symbol_get(qeth_l2_ccwgroup_driver),
  3710. "qeth_l2");
  3711. break;
  3712. }
  3713. if (!card->discipline.ccwgdriver) {
  3714. dev_err(&card->gdev->dev, "There is no kernel module to "
  3715. "support discipline %d\n", discipline);
  3716. rc = -EINVAL;
  3717. }
  3718. return rc;
  3719. }
  3720. void qeth_core_free_discipline(struct qeth_card *card)
  3721. {
  3722. if (card->options.layer2)
  3723. symbol_put(qeth_l2_ccwgroup_driver);
  3724. else
  3725. symbol_put(qeth_l3_ccwgroup_driver);
  3726. card->discipline.ccwgdriver = NULL;
  3727. }
  3728. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3729. {
  3730. struct qeth_card *card;
  3731. struct device *dev;
  3732. int rc;
  3733. unsigned long flags;
  3734. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3735. dev = &gdev->dev;
  3736. if (!get_device(dev))
  3737. return -ENODEV;
  3738. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3739. card = qeth_alloc_card();
  3740. if (!card) {
  3741. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3742. rc = -ENOMEM;
  3743. goto err_dev;
  3744. }
  3745. card->read.ccwdev = gdev->cdev[0];
  3746. card->write.ccwdev = gdev->cdev[1];
  3747. card->data.ccwdev = gdev->cdev[2];
  3748. dev_set_drvdata(&gdev->dev, card);
  3749. card->gdev = gdev;
  3750. gdev->cdev[0]->handler = qeth_irq;
  3751. gdev->cdev[1]->handler = qeth_irq;
  3752. gdev->cdev[2]->handler = qeth_irq;
  3753. rc = qeth_determine_card_type(card);
  3754. if (rc) {
  3755. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3756. goto err_card;
  3757. }
  3758. rc = qeth_setup_card(card);
  3759. if (rc) {
  3760. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3761. goto err_card;
  3762. }
  3763. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3764. rc = qeth_core_create_osn_attributes(dev);
  3765. if (rc)
  3766. goto err_card;
  3767. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3768. if (rc) {
  3769. qeth_core_remove_osn_attributes(dev);
  3770. goto err_card;
  3771. }
  3772. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3773. if (rc) {
  3774. qeth_core_free_discipline(card);
  3775. qeth_core_remove_osn_attributes(dev);
  3776. goto err_card;
  3777. }
  3778. } else {
  3779. rc = qeth_core_create_device_attributes(dev);
  3780. if (rc)
  3781. goto err_card;
  3782. }
  3783. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3784. list_add_tail(&card->list, &qeth_core_card_list.list);
  3785. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3786. return 0;
  3787. err_card:
  3788. qeth_core_free_card(card);
  3789. err_dev:
  3790. put_device(dev);
  3791. return rc;
  3792. }
  3793. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3794. {
  3795. unsigned long flags;
  3796. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3797. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3798. if (card->discipline.ccwgdriver) {
  3799. card->discipline.ccwgdriver->remove(gdev);
  3800. qeth_core_free_discipline(card);
  3801. }
  3802. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3803. qeth_core_remove_osn_attributes(&gdev->dev);
  3804. } else {
  3805. qeth_core_remove_device_attributes(&gdev->dev);
  3806. }
  3807. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3808. list_del(&card->list);
  3809. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3810. qeth_core_free_card(card);
  3811. dev_set_drvdata(&gdev->dev, NULL);
  3812. put_device(&gdev->dev);
  3813. return;
  3814. }
  3815. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3816. {
  3817. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3818. int rc = 0;
  3819. int def_discipline;
  3820. if (!card->discipline.ccwgdriver) {
  3821. if (card->info.type == QETH_CARD_TYPE_IQD)
  3822. def_discipline = QETH_DISCIPLINE_LAYER3;
  3823. else
  3824. def_discipline = QETH_DISCIPLINE_LAYER2;
  3825. rc = qeth_core_load_discipline(card, def_discipline);
  3826. if (rc)
  3827. goto err;
  3828. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3829. if (rc)
  3830. goto err;
  3831. }
  3832. rc = card->discipline.ccwgdriver->set_online(gdev);
  3833. err:
  3834. return rc;
  3835. }
  3836. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3837. {
  3838. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3839. return card->discipline.ccwgdriver->set_offline(gdev);
  3840. }
  3841. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3842. {
  3843. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3844. if (card->discipline.ccwgdriver &&
  3845. card->discipline.ccwgdriver->shutdown)
  3846. card->discipline.ccwgdriver->shutdown(gdev);
  3847. }
  3848. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3849. .owner = THIS_MODULE,
  3850. .name = "qeth",
  3851. .driver_id = 0xD8C5E3C8,
  3852. .probe = qeth_core_probe_device,
  3853. .remove = qeth_core_remove_device,
  3854. .set_online = qeth_core_set_online,
  3855. .set_offline = qeth_core_set_offline,
  3856. .shutdown = qeth_core_shutdown,
  3857. };
  3858. static ssize_t
  3859. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3860. size_t count)
  3861. {
  3862. int err;
  3863. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3864. qeth_core_ccwgroup_driver.driver_id);
  3865. if (err)
  3866. return err;
  3867. else
  3868. return count;
  3869. }
  3870. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3871. static struct {
  3872. const char str[ETH_GSTRING_LEN];
  3873. } qeth_ethtool_stats_keys[] = {
  3874. /* 0 */{"rx skbs"},
  3875. {"rx buffers"},
  3876. {"tx skbs"},
  3877. {"tx buffers"},
  3878. {"tx skbs no packing"},
  3879. {"tx buffers no packing"},
  3880. {"tx skbs packing"},
  3881. {"tx buffers packing"},
  3882. {"tx sg skbs"},
  3883. {"tx sg frags"},
  3884. /* 10 */{"rx sg skbs"},
  3885. {"rx sg frags"},
  3886. {"rx sg page allocs"},
  3887. {"tx large kbytes"},
  3888. {"tx large count"},
  3889. {"tx pk state ch n->p"},
  3890. {"tx pk state ch p->n"},
  3891. {"tx pk watermark low"},
  3892. {"tx pk watermark high"},
  3893. {"queue 0 buffer usage"},
  3894. /* 20 */{"queue 1 buffer usage"},
  3895. {"queue 2 buffer usage"},
  3896. {"queue 3 buffer usage"},
  3897. {"rx handler time"},
  3898. {"rx handler count"},
  3899. {"rx do_QDIO time"},
  3900. {"rx do_QDIO count"},
  3901. {"tx handler time"},
  3902. {"tx handler count"},
  3903. {"tx time"},
  3904. /* 30 */{"tx count"},
  3905. {"tx do_QDIO time"},
  3906. {"tx do_QDIO count"},
  3907. };
  3908. int qeth_core_get_stats_count(struct net_device *dev)
  3909. {
  3910. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3911. }
  3912. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3913. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3914. struct ethtool_stats *stats, u64 *data)
  3915. {
  3916. struct qeth_card *card = dev->ml_priv;
  3917. data[0] = card->stats.rx_packets -
  3918. card->perf_stats.initial_rx_packets;
  3919. data[1] = card->perf_stats.bufs_rec;
  3920. data[2] = card->stats.tx_packets -
  3921. card->perf_stats.initial_tx_packets;
  3922. data[3] = card->perf_stats.bufs_sent;
  3923. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3924. - card->perf_stats.skbs_sent_pack;
  3925. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3926. data[6] = card->perf_stats.skbs_sent_pack;
  3927. data[7] = card->perf_stats.bufs_sent_pack;
  3928. data[8] = card->perf_stats.sg_skbs_sent;
  3929. data[9] = card->perf_stats.sg_frags_sent;
  3930. data[10] = card->perf_stats.sg_skbs_rx;
  3931. data[11] = card->perf_stats.sg_frags_rx;
  3932. data[12] = card->perf_stats.sg_alloc_page_rx;
  3933. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3934. data[14] = card->perf_stats.large_send_cnt;
  3935. data[15] = card->perf_stats.sc_dp_p;
  3936. data[16] = card->perf_stats.sc_p_dp;
  3937. data[17] = QETH_LOW_WATERMARK_PACK;
  3938. data[18] = QETH_HIGH_WATERMARK_PACK;
  3939. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3940. data[20] = (card->qdio.no_out_queues > 1) ?
  3941. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3942. data[21] = (card->qdio.no_out_queues > 2) ?
  3943. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  3944. data[22] = (card->qdio.no_out_queues > 3) ?
  3945. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  3946. data[23] = card->perf_stats.inbound_time;
  3947. data[24] = card->perf_stats.inbound_cnt;
  3948. data[25] = card->perf_stats.inbound_do_qdio_time;
  3949. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  3950. data[27] = card->perf_stats.outbound_handler_time;
  3951. data[28] = card->perf_stats.outbound_handler_cnt;
  3952. data[29] = card->perf_stats.outbound_time;
  3953. data[30] = card->perf_stats.outbound_cnt;
  3954. data[31] = card->perf_stats.outbound_do_qdio_time;
  3955. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  3956. }
  3957. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  3958. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3959. {
  3960. switch (stringset) {
  3961. case ETH_SS_STATS:
  3962. memcpy(data, &qeth_ethtool_stats_keys,
  3963. sizeof(qeth_ethtool_stats_keys));
  3964. break;
  3965. default:
  3966. WARN_ON(1);
  3967. break;
  3968. }
  3969. }
  3970. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  3971. void qeth_core_get_drvinfo(struct net_device *dev,
  3972. struct ethtool_drvinfo *info)
  3973. {
  3974. struct qeth_card *card = dev->ml_priv;
  3975. if (card->options.layer2)
  3976. strcpy(info->driver, "qeth_l2");
  3977. else
  3978. strcpy(info->driver, "qeth_l3");
  3979. strcpy(info->version, "1.0");
  3980. strcpy(info->fw_version, card->info.mcl_level);
  3981. sprintf(info->bus_info, "%s/%s/%s",
  3982. CARD_RDEV_ID(card),
  3983. CARD_WDEV_ID(card),
  3984. CARD_DDEV_ID(card));
  3985. }
  3986. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  3987. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  3988. struct ethtool_cmd *ecmd)
  3989. {
  3990. struct qeth_card *card = netdev->ml_priv;
  3991. enum qeth_link_types link_type;
  3992. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  3993. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  3994. else
  3995. link_type = card->info.link_type;
  3996. ecmd->transceiver = XCVR_INTERNAL;
  3997. ecmd->supported = SUPPORTED_Autoneg;
  3998. ecmd->advertising = ADVERTISED_Autoneg;
  3999. ecmd->duplex = DUPLEX_FULL;
  4000. ecmd->autoneg = AUTONEG_ENABLE;
  4001. switch (link_type) {
  4002. case QETH_LINK_TYPE_FAST_ETH:
  4003. case QETH_LINK_TYPE_LANE_ETH100:
  4004. ecmd->supported |= SUPPORTED_10baseT_Half |
  4005. SUPPORTED_10baseT_Full |
  4006. SUPPORTED_100baseT_Half |
  4007. SUPPORTED_100baseT_Full |
  4008. SUPPORTED_TP;
  4009. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4010. ADVERTISED_10baseT_Full |
  4011. ADVERTISED_100baseT_Half |
  4012. ADVERTISED_100baseT_Full |
  4013. ADVERTISED_TP;
  4014. ecmd->speed = SPEED_100;
  4015. ecmd->port = PORT_TP;
  4016. break;
  4017. case QETH_LINK_TYPE_GBIT_ETH:
  4018. case QETH_LINK_TYPE_LANE_ETH1000:
  4019. ecmd->supported |= SUPPORTED_10baseT_Half |
  4020. SUPPORTED_10baseT_Full |
  4021. SUPPORTED_100baseT_Half |
  4022. SUPPORTED_100baseT_Full |
  4023. SUPPORTED_1000baseT_Half |
  4024. SUPPORTED_1000baseT_Full |
  4025. SUPPORTED_FIBRE;
  4026. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4027. ADVERTISED_10baseT_Full |
  4028. ADVERTISED_100baseT_Half |
  4029. ADVERTISED_100baseT_Full |
  4030. ADVERTISED_1000baseT_Half |
  4031. ADVERTISED_1000baseT_Full |
  4032. ADVERTISED_FIBRE;
  4033. ecmd->speed = SPEED_1000;
  4034. ecmd->port = PORT_FIBRE;
  4035. break;
  4036. case QETH_LINK_TYPE_10GBIT_ETH:
  4037. ecmd->supported |= SUPPORTED_10baseT_Half |
  4038. SUPPORTED_10baseT_Full |
  4039. SUPPORTED_100baseT_Half |
  4040. SUPPORTED_100baseT_Full |
  4041. SUPPORTED_1000baseT_Half |
  4042. SUPPORTED_1000baseT_Full |
  4043. SUPPORTED_10000baseT_Full |
  4044. SUPPORTED_FIBRE;
  4045. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4046. ADVERTISED_10baseT_Full |
  4047. ADVERTISED_100baseT_Half |
  4048. ADVERTISED_100baseT_Full |
  4049. ADVERTISED_1000baseT_Half |
  4050. ADVERTISED_1000baseT_Full |
  4051. ADVERTISED_10000baseT_Full |
  4052. ADVERTISED_FIBRE;
  4053. ecmd->speed = SPEED_10000;
  4054. ecmd->port = PORT_FIBRE;
  4055. break;
  4056. default:
  4057. ecmd->supported |= SUPPORTED_10baseT_Half |
  4058. SUPPORTED_10baseT_Full |
  4059. SUPPORTED_TP;
  4060. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4061. ADVERTISED_10baseT_Full |
  4062. ADVERTISED_TP;
  4063. ecmd->speed = SPEED_10;
  4064. ecmd->port = PORT_TP;
  4065. }
  4066. return 0;
  4067. }
  4068. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4069. static int __init qeth_core_init(void)
  4070. {
  4071. int rc;
  4072. pr_info("loading core functions\n");
  4073. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4074. rwlock_init(&qeth_core_card_list.rwlock);
  4075. rc = qeth_register_dbf_views();
  4076. if (rc)
  4077. goto out_err;
  4078. rc = ccw_driver_register(&qeth_ccw_driver);
  4079. if (rc)
  4080. goto ccw_err;
  4081. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4082. if (rc)
  4083. goto ccwgroup_err;
  4084. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4085. &driver_attr_group);
  4086. if (rc)
  4087. goto driver_err;
  4088. qeth_core_root_dev = root_device_register("qeth");
  4089. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4090. if (rc)
  4091. goto register_err;
  4092. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4093. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4094. if (!qeth_core_header_cache) {
  4095. rc = -ENOMEM;
  4096. goto slab_err;
  4097. }
  4098. return 0;
  4099. slab_err:
  4100. root_device_unregister(qeth_core_root_dev);
  4101. register_err:
  4102. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4103. &driver_attr_group);
  4104. driver_err:
  4105. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4106. ccwgroup_err:
  4107. ccw_driver_unregister(&qeth_ccw_driver);
  4108. ccw_err:
  4109. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4110. qeth_unregister_dbf_views();
  4111. out_err:
  4112. pr_err("Initializing the qeth device driver failed\n");
  4113. return rc;
  4114. }
  4115. static void __exit qeth_core_exit(void)
  4116. {
  4117. root_device_unregister(qeth_core_root_dev);
  4118. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4119. &driver_attr_group);
  4120. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4121. ccw_driver_unregister(&qeth_ccw_driver);
  4122. kmem_cache_destroy(qeth_core_header_cache);
  4123. qeth_unregister_dbf_views();
  4124. pr_info("core functions removed\n");
  4125. }
  4126. module_init(qeth_core_init);
  4127. module_exit(qeth_core_exit);
  4128. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4129. MODULE_DESCRIPTION("qeth core functions");
  4130. MODULE_LICENSE("GPL");