ps3vram.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768
  1. /**
  2. * ps3vram - Use extra PS3 video ram as MTD block device.
  3. *
  4. * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
  5. * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
  6. */
  7. #include <linux/io.h>
  8. #include <linux/mm.h>
  9. #include <linux/init.h>
  10. #include <linux/kernel.h>
  11. #include <linux/list.h>
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/slab.h>
  15. #include <linux/version.h>
  16. #include <linux/gfp.h>
  17. #include <linux/delay.h>
  18. #include <linux/mtd/mtd.h>
  19. #include <asm/lv1call.h>
  20. #include <asm/ps3.h>
  21. #define DEVICE_NAME "ps3vram"
  22. #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
  23. #define XDR_IOIF 0x0c000000
  24. #define FIFO_BASE XDR_IOIF
  25. #define FIFO_SIZE (64 * 1024)
  26. #define DMA_PAGE_SIZE (4 * 1024)
  27. #define CACHE_PAGE_SIZE (256 * 1024)
  28. #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
  29. #define CACHE_OFFSET CACHE_PAGE_SIZE
  30. #define FIFO_OFFSET 0
  31. #define CTRL_PUT 0x10
  32. #define CTRL_GET 0x11
  33. #define CTRL_TOP 0x15
  34. #define UPLOAD_SUBCH 1
  35. #define DOWNLOAD_SUBCH 2
  36. #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
  37. #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
  38. #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
  39. struct mtd_info ps3vram_mtd;
  40. #define CACHE_PAGE_PRESENT 1
  41. #define CACHE_PAGE_DIRTY 2
  42. struct ps3vram_tag {
  43. unsigned int address;
  44. unsigned int flags;
  45. };
  46. struct ps3vram_cache {
  47. unsigned int page_count;
  48. unsigned int page_size;
  49. struct ps3vram_tag *tags;
  50. };
  51. struct ps3vram_priv {
  52. u64 memory_handle;
  53. u64 context_handle;
  54. u32 *ctrl;
  55. u32 *reports;
  56. u8 __iomem *ddr_base;
  57. u8 *xdr_buf;
  58. u32 *fifo_base;
  59. u32 *fifo_ptr;
  60. struct device *dev;
  61. struct ps3vram_cache cache;
  62. /* Used to serialize cache/DMA operations */
  63. struct mutex lock;
  64. };
  65. #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
  66. #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */
  67. #define DMA_NOTIFIER_SIZE 0x40
  68. #define NOTIFIER 7 /* notifier used for completion report */
  69. /* A trailing '-' means to subtract off ps3fb_videomemory.size */
  70. char *size = "256M-";
  71. module_param(size, charp, 0);
  72. MODULE_PARM_DESC(size, "memory size");
  73. static u32 *ps3vram_get_notifier(u32 *reports, int notifier)
  74. {
  75. return (void *) reports +
  76. DMA_NOTIFIER_OFFSET_BASE +
  77. DMA_NOTIFIER_SIZE * notifier;
  78. }
  79. static void ps3vram_notifier_reset(struct mtd_info *mtd)
  80. {
  81. int i;
  82. struct ps3vram_priv *priv = mtd->priv;
  83. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  84. for (i = 0; i < 4; i++)
  85. notify[i] = 0xffffffff;
  86. }
  87. static int ps3vram_notifier_wait(struct mtd_info *mtd, unsigned int timeout_ms)
  88. {
  89. struct ps3vram_priv *priv = mtd->priv;
  90. u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
  91. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  92. do {
  93. if (!notify[3])
  94. return 0;
  95. msleep(1);
  96. } while (time_before(jiffies, timeout));
  97. return -ETIMEDOUT;
  98. }
  99. static void ps3vram_init_ring(struct mtd_info *mtd)
  100. {
  101. struct ps3vram_priv *priv = mtd->priv;
  102. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  103. priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
  104. }
  105. static int ps3vram_wait_ring(struct mtd_info *mtd, unsigned int timeout_ms)
  106. {
  107. struct ps3vram_priv *priv = mtd->priv;
  108. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  109. do {
  110. if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
  111. return 0;
  112. msleep(1);
  113. } while (time_before(jiffies, timeout));
  114. dev_dbg(priv->dev, "%s:%d: FIFO timeout (%08x/%08x/%08x)\n", __func__,
  115. __LINE__, priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET],
  116. priv->ctrl[CTRL_TOP]);
  117. return -ETIMEDOUT;
  118. }
  119. static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data)
  120. {
  121. *(priv->fifo_ptr)++ = data;
  122. }
  123. static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan,
  124. u32 tag, u32 size)
  125. {
  126. ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
  127. }
  128. static void ps3vram_rewind_ring(struct mtd_info *mtd)
  129. {
  130. struct ps3vram_priv *priv = mtd->priv;
  131. u64 status;
  132. ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
  133. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
  134. /* asking the HV for a blit will kick the fifo */
  135. status = lv1_gpu_context_attribute(priv->context_handle,
  136. L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
  137. 0, 0, 0, 0);
  138. if (status)
  139. dev_err(priv->dev, "%s:%d: lv1_gpu_context_attribute failed\n",
  140. __func__, __LINE__);
  141. priv->fifo_ptr = priv->fifo_base;
  142. }
  143. static void ps3vram_fire_ring(struct mtd_info *mtd)
  144. {
  145. struct ps3vram_priv *priv = mtd->priv;
  146. u64 status;
  147. mutex_lock(&ps3_gpu_mutex);
  148. priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
  149. (priv->fifo_ptr - priv->fifo_base) * sizeof(u32);
  150. /* asking the HV for a blit will kick the fifo */
  151. status = lv1_gpu_context_attribute(priv->context_handle,
  152. L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
  153. 0, 0, 0, 0);
  154. if (status)
  155. dev_err(priv->dev, "%s:%d: lv1_gpu_context_attribute failed\n",
  156. __func__, __LINE__);
  157. if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) >
  158. FIFO_SIZE - 1024) {
  159. dev_dbg(priv->dev, "%s:%d: fifo full, rewinding\n", __func__,
  160. __LINE__);
  161. ps3vram_wait_ring(mtd, 200);
  162. ps3vram_rewind_ring(mtd);
  163. }
  164. mutex_unlock(&ps3_gpu_mutex);
  165. }
  166. static void ps3vram_bind(struct mtd_info *mtd)
  167. {
  168. struct ps3vram_priv *priv = mtd->priv;
  169. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
  170. ps3vram_out_ring(priv, 0x31337303);
  171. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
  172. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  173. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  174. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  175. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
  176. ps3vram_out_ring(priv, 0x3137c0de);
  177. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
  178. ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
  179. ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */
  180. ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */
  181. ps3vram_fire_ring(mtd);
  182. }
  183. static int ps3vram_upload(struct mtd_info *mtd, unsigned int src_offset,
  184. unsigned int dst_offset, int len, int count)
  185. {
  186. struct ps3vram_priv *priv = mtd->priv;
  187. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  188. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  189. ps3vram_out_ring(priv, XDR_IOIF + src_offset);
  190. ps3vram_out_ring(priv, dst_offset);
  191. ps3vram_out_ring(priv, len);
  192. ps3vram_out_ring(priv, len);
  193. ps3vram_out_ring(priv, len);
  194. ps3vram_out_ring(priv, count);
  195. ps3vram_out_ring(priv, (1 << 8) | 1);
  196. ps3vram_out_ring(priv, 0);
  197. ps3vram_notifier_reset(mtd);
  198. ps3vram_begin_ring(priv, UPLOAD_SUBCH,
  199. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  200. ps3vram_out_ring(priv, 0);
  201. ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
  202. ps3vram_out_ring(priv, 0);
  203. ps3vram_fire_ring(mtd);
  204. if (ps3vram_notifier_wait(mtd, 200) < 0) {
  205. dev_dbg(priv->dev, "%s:%d: notifier timeout\n", __func__,
  206. __LINE__);
  207. return -1;
  208. }
  209. return 0;
  210. }
  211. static int ps3vram_download(struct mtd_info *mtd, unsigned int src_offset,
  212. unsigned int dst_offset, int len, int count)
  213. {
  214. struct ps3vram_priv *priv = mtd->priv;
  215. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  216. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  217. ps3vram_out_ring(priv, src_offset);
  218. ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
  219. ps3vram_out_ring(priv, len);
  220. ps3vram_out_ring(priv, len);
  221. ps3vram_out_ring(priv, len);
  222. ps3vram_out_ring(priv, count);
  223. ps3vram_out_ring(priv, (1 << 8) | 1);
  224. ps3vram_out_ring(priv, 0);
  225. ps3vram_notifier_reset(mtd);
  226. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
  227. NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
  228. ps3vram_out_ring(priv, 0);
  229. ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
  230. ps3vram_out_ring(priv, 0);
  231. ps3vram_fire_ring(mtd);
  232. if (ps3vram_notifier_wait(mtd, 200) < 0) {
  233. dev_dbg(priv->dev, "%s:%d: notifier timeout\n", __func__,
  234. __LINE__);
  235. return -1;
  236. }
  237. return 0;
  238. }
  239. static void ps3vram_cache_evict(struct mtd_info *mtd, int entry)
  240. {
  241. struct ps3vram_priv *priv = mtd->priv;
  242. struct ps3vram_cache *cache = &priv->cache;
  243. if (cache->tags[entry].flags & CACHE_PAGE_DIRTY) {
  244. dev_dbg(priv->dev, "%s:%d: flushing %d : 0x%08x\n", __func__,
  245. __LINE__, entry, cache->tags[entry].address);
  246. if (ps3vram_upload(mtd,
  247. CACHE_OFFSET + entry * cache->page_size,
  248. cache->tags[entry].address,
  249. DMA_PAGE_SIZE,
  250. cache->page_size / DMA_PAGE_SIZE) < 0) {
  251. dev_dbg(priv->dev, "%s:%d: failed to upload from "
  252. "0x%x to 0x%x size 0x%x\n", __func__, __LINE__,
  253. entry * cache->page_size,
  254. cache->tags[entry].address, cache->page_size);
  255. }
  256. cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
  257. }
  258. }
  259. static void ps3vram_cache_load(struct mtd_info *mtd, int entry,
  260. unsigned int address)
  261. {
  262. struct ps3vram_priv *priv = mtd->priv;
  263. struct ps3vram_cache *cache = &priv->cache;
  264. dev_dbg(priv->dev, "%s:%d: fetching %d : 0x%08x\n", __func__, __LINE__,
  265. entry, address);
  266. if (ps3vram_download(mtd,
  267. address,
  268. CACHE_OFFSET + entry * cache->page_size,
  269. DMA_PAGE_SIZE,
  270. cache->page_size / DMA_PAGE_SIZE) < 0) {
  271. dev_err(priv->dev, "%s:%d: failed to download from "
  272. "0x%x to 0x%x size 0x%x\n", __func__, __LINE__, address,
  273. entry * cache->page_size, cache->page_size);
  274. }
  275. cache->tags[entry].address = address;
  276. cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
  277. }
  278. static void ps3vram_cache_flush(struct mtd_info *mtd)
  279. {
  280. struct ps3vram_priv *priv = mtd->priv;
  281. struct ps3vram_cache *cache = &priv->cache;
  282. int i;
  283. dev_dbg(priv->dev, "%s:%d: FLUSH\n", __func__, __LINE__);
  284. for (i = 0; i < cache->page_count; i++) {
  285. ps3vram_cache_evict(mtd, i);
  286. cache->tags[i].flags = 0;
  287. }
  288. }
  289. static unsigned int ps3vram_cache_match(struct mtd_info *mtd, loff_t address)
  290. {
  291. struct ps3vram_priv *priv = mtd->priv;
  292. struct ps3vram_cache *cache = &priv->cache;
  293. unsigned int base;
  294. unsigned int offset;
  295. int i;
  296. static int counter;
  297. offset = (unsigned int) (address & (cache->page_size - 1));
  298. base = (unsigned int) (address - offset);
  299. /* fully associative check */
  300. for (i = 0; i < cache->page_count; i++) {
  301. if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
  302. cache->tags[i].address == base) {
  303. dev_dbg(priv->dev, "%s:%d: found entry %d : 0x%08x\n",
  304. __func__, __LINE__, i, cache->tags[i].address);
  305. return i;
  306. }
  307. }
  308. /* choose a random entry */
  309. i = (jiffies + (counter++)) % cache->page_count;
  310. dev_dbg(priv->dev, "%s:%d: using entry %d\n", __func__, __LINE__, i);
  311. ps3vram_cache_evict(mtd, i);
  312. ps3vram_cache_load(mtd, i, base);
  313. return i;
  314. }
  315. static int ps3vram_cache_init(struct mtd_info *mtd)
  316. {
  317. struct ps3vram_priv *priv = mtd->priv;
  318. priv->cache.page_count = CACHE_PAGE_COUNT;
  319. priv->cache.page_size = CACHE_PAGE_SIZE;
  320. priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
  321. CACHE_PAGE_COUNT, GFP_KERNEL);
  322. if (priv->cache.tags == NULL) {
  323. dev_err(priv->dev, "%s:%d: could not allocate cache tags\n",
  324. __func__, __LINE__);
  325. return -ENOMEM;
  326. }
  327. dev_info(priv->dev, "created ram cache: %d entries, %d KiB each\n",
  328. CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
  329. return 0;
  330. }
  331. static void ps3vram_cache_cleanup(struct mtd_info *mtd)
  332. {
  333. struct ps3vram_priv *priv = mtd->priv;
  334. ps3vram_cache_flush(mtd);
  335. kfree(priv->cache.tags);
  336. }
  337. static int ps3vram_erase(struct mtd_info *mtd, struct erase_info *instr)
  338. {
  339. struct ps3vram_priv *priv = mtd->priv;
  340. if (instr->addr + instr->len > mtd->size)
  341. return -EINVAL;
  342. mutex_lock(&priv->lock);
  343. ps3vram_cache_flush(mtd);
  344. /* Set bytes to 0xFF */
  345. memset_io(priv->ddr_base + instr->addr, 0xFF, instr->len);
  346. mutex_unlock(&priv->lock);
  347. instr->state = MTD_ERASE_DONE;
  348. mtd_erase_callback(instr);
  349. return 0;
  350. }
  351. static int ps3vram_read(struct mtd_info *mtd, loff_t from, size_t len,
  352. size_t *retlen, u_char *buf)
  353. {
  354. struct ps3vram_priv *priv = mtd->priv;
  355. unsigned int cached, count;
  356. dev_dbg(priv->dev, "%s:%d: from=0x%08x len=0x%zx\n", __func__, __LINE__,
  357. (unsigned int)from, len);
  358. if (from >= mtd->size)
  359. return -EINVAL;
  360. if (len > mtd->size - from)
  361. len = mtd->size - from;
  362. /* Copy from vram to buf */
  363. count = len;
  364. while (count) {
  365. unsigned int offset, avail;
  366. unsigned int entry;
  367. offset = (unsigned int) (from & (priv->cache.page_size - 1));
  368. avail = priv->cache.page_size - offset;
  369. mutex_lock(&priv->lock);
  370. entry = ps3vram_cache_match(mtd, from);
  371. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  372. dev_dbg(priv->dev, "%s:%d: from=%08x cached=%08x offset=%08x "
  373. "avail=%08x count=%08x\n", __func__, __LINE__,
  374. (unsigned int)from, cached, offset, avail, count);
  375. if (avail > count)
  376. avail = count;
  377. memcpy(buf, priv->xdr_buf + cached, avail);
  378. mutex_unlock(&priv->lock);
  379. buf += avail;
  380. count -= avail;
  381. from += avail;
  382. }
  383. *retlen = len;
  384. return 0;
  385. }
  386. static int ps3vram_write(struct mtd_info *mtd, loff_t to, size_t len,
  387. size_t *retlen, const u_char *buf)
  388. {
  389. struct ps3vram_priv *priv = mtd->priv;
  390. unsigned int cached, count;
  391. if (to >= mtd->size)
  392. return -EINVAL;
  393. if (len > mtd->size - to)
  394. len = mtd->size - to;
  395. /* Copy from buf to vram */
  396. count = len;
  397. while (count) {
  398. unsigned int offset, avail;
  399. unsigned int entry;
  400. offset = (unsigned int) (to & (priv->cache.page_size - 1));
  401. avail = priv->cache.page_size - offset;
  402. mutex_lock(&priv->lock);
  403. entry = ps3vram_cache_match(mtd, to);
  404. cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
  405. dev_dbg(priv->dev, "%s:%d: to=%08x cached=%08x offset=%08x "
  406. "avail=%08x count=%08x\n", __func__, __LINE__,
  407. (unsigned int)to, cached, offset, avail, count);
  408. if (avail > count)
  409. avail = count;
  410. memcpy(priv->xdr_buf + cached, buf, avail);
  411. priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
  412. mutex_unlock(&priv->lock);
  413. buf += avail;
  414. count -= avail;
  415. to += avail;
  416. }
  417. *retlen = len;
  418. return 0;
  419. }
  420. static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
  421. {
  422. struct ps3vram_priv *priv;
  423. int status;
  424. u64 ddr_lpar;
  425. u64 ctrl_lpar;
  426. u64 info_lpar;
  427. u64 reports_lpar;
  428. u64 ddr_size;
  429. u64 reports_size;
  430. int ret = -ENOMEM;
  431. char *rest;
  432. ret = -EIO;
  433. ps3vram_mtd.priv = kzalloc(sizeof(struct ps3vram_priv), GFP_KERNEL);
  434. if (!ps3vram_mtd.priv)
  435. goto out;
  436. priv = ps3vram_mtd.priv;
  437. mutex_init(&priv->lock);
  438. priv->dev = &dev->core;
  439. /* Allocate XDR buffer (1MiB aligned) */
  440. priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL,
  441. get_order(XDR_BUF_SIZE));
  442. if (priv->xdr_buf == NULL) {
  443. dev_dbg(&dev->core, "%s:%d: could not allocate XDR buffer\n",
  444. __func__, __LINE__);
  445. ret = -ENOMEM;
  446. goto out_free_priv;
  447. }
  448. /* Put FIFO at begginning of XDR buffer */
  449. priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET);
  450. priv->fifo_ptr = priv->fifo_base;
  451. /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
  452. if (ps3_open_hv_device(dev)) {
  453. dev_err(&dev->core, "%s:%d: ps3_open_hv_device failed\n",
  454. __func__, __LINE__);
  455. ret = -EAGAIN;
  456. goto out_close_gpu;
  457. }
  458. /* Request memory */
  459. status = -1;
  460. ddr_size = memparse(size, &rest);
  461. if (*rest == '-')
  462. ddr_size -= ps3fb_videomemory.size;
  463. ddr_size = ALIGN(ddr_size, 1024*1024);
  464. if (ddr_size <= 0) {
  465. dev_err(&dev->core, "%s:%d: specified size is too small\n",
  466. __func__, __LINE__);
  467. ret = -EINVAL;
  468. goto out_close_gpu;
  469. }
  470. while (ddr_size > 0) {
  471. status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
  472. &priv->memory_handle,
  473. &ddr_lpar);
  474. if (!status)
  475. break;
  476. ddr_size -= 1024*1024;
  477. }
  478. if (status || ddr_size <= 0) {
  479. dev_err(&dev->core, "%s:%d: lv1_gpu_memory_allocate failed\n",
  480. __func__, __LINE__);
  481. ret = -ENOMEM;
  482. goto out_free_xdr_buf;
  483. }
  484. /* Request context */
  485. status = lv1_gpu_context_allocate(priv->memory_handle,
  486. 0,
  487. &priv->context_handle,
  488. &ctrl_lpar,
  489. &info_lpar,
  490. &reports_lpar,
  491. &reports_size);
  492. if (status) {
  493. dev_err(&dev->core, "%s:%d: lv1_gpu_context_allocate failed\n",
  494. __func__, __LINE__);
  495. ret = -ENOMEM;
  496. goto out_free_memory;
  497. }
  498. /* Map XDR buffer to RSX */
  499. status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
  500. ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
  501. XDR_BUF_SIZE, 0);
  502. if (status) {
  503. dev_err(&dev->core, "%s:%d: lv1_gpu_context_iomap failed\n",
  504. __func__, __LINE__);
  505. ret = -ENOMEM;
  506. goto out_free_context;
  507. }
  508. priv->ddr_base = ioremap_flags(ddr_lpar, ddr_size, _PAGE_NO_CACHE);
  509. if (!priv->ddr_base) {
  510. dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__,
  511. __LINE__);
  512. ret = -ENOMEM;
  513. goto out_free_context;
  514. }
  515. priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
  516. if (!priv->ctrl) {
  517. dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__,
  518. __LINE__);
  519. ret = -ENOMEM;
  520. goto out_unmap_vram;
  521. }
  522. priv->reports = ioremap(reports_lpar, reports_size);
  523. if (!priv->reports) {
  524. dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__,
  525. __LINE__);
  526. ret = -ENOMEM;
  527. goto out_unmap_ctrl;
  528. }
  529. mutex_lock(&ps3_gpu_mutex);
  530. ps3vram_init_ring(&ps3vram_mtd);
  531. mutex_unlock(&ps3_gpu_mutex);
  532. ps3vram_mtd.name = "ps3vram";
  533. ps3vram_mtd.size = ddr_size;
  534. ps3vram_mtd.flags = MTD_CAP_RAM;
  535. ps3vram_mtd.erase = ps3vram_erase;
  536. ps3vram_mtd.point = NULL;
  537. ps3vram_mtd.unpoint = NULL;
  538. ps3vram_mtd.read = ps3vram_read;
  539. ps3vram_mtd.write = ps3vram_write;
  540. ps3vram_mtd.owner = THIS_MODULE;
  541. ps3vram_mtd.type = MTD_RAM;
  542. ps3vram_mtd.erasesize = CACHE_PAGE_SIZE;
  543. ps3vram_mtd.writesize = 1;
  544. ps3vram_bind(&ps3vram_mtd);
  545. mutex_lock(&ps3_gpu_mutex);
  546. ret = ps3vram_wait_ring(&ps3vram_mtd, 100);
  547. mutex_unlock(&ps3_gpu_mutex);
  548. if (ret < 0) {
  549. dev_err(&dev->core, "%s:%d: failed to initialize channels\n",
  550. __func__, __LINE__);
  551. ret = -ETIMEDOUT;
  552. goto out_unmap_reports;
  553. }
  554. ps3vram_cache_init(&ps3vram_mtd);
  555. if (add_mtd_device(&ps3vram_mtd)) {
  556. dev_err(&dev->core, "%s:%d: add_mtd_device failed\n",
  557. __func__, __LINE__);
  558. ret = -EAGAIN;
  559. goto out_cache_cleanup;
  560. }
  561. dev_info(&dev->core, "reserved %u MiB of gpu memory\n",
  562. (unsigned int)(ddr_size / 1024 / 1024));
  563. return 0;
  564. out_cache_cleanup:
  565. ps3vram_cache_cleanup(&ps3vram_mtd);
  566. out_unmap_reports:
  567. iounmap(priv->reports);
  568. out_unmap_ctrl:
  569. iounmap(priv->ctrl);
  570. out_unmap_vram:
  571. iounmap(priv->ddr_base);
  572. out_free_context:
  573. lv1_gpu_context_free(priv->context_handle);
  574. out_free_memory:
  575. lv1_gpu_memory_free(priv->memory_handle);
  576. out_close_gpu:
  577. ps3_close_hv_device(dev);
  578. out_free_xdr_buf:
  579. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  580. out_free_priv:
  581. kfree(ps3vram_mtd.priv);
  582. ps3vram_mtd.priv = NULL;
  583. out:
  584. return ret;
  585. }
  586. static int ps3vram_shutdown(struct ps3_system_bus_device *dev)
  587. {
  588. struct ps3vram_priv *priv;
  589. priv = ps3vram_mtd.priv;
  590. del_mtd_device(&ps3vram_mtd);
  591. ps3vram_cache_cleanup(&ps3vram_mtd);
  592. iounmap(priv->reports);
  593. iounmap(priv->ctrl);
  594. iounmap(priv->ddr_base);
  595. lv1_gpu_context_free(priv->context_handle);
  596. lv1_gpu_memory_free(priv->memory_handle);
  597. ps3_close_hv_device(dev);
  598. free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
  599. kfree(priv);
  600. return 0;
  601. }
  602. static struct ps3_system_bus_driver ps3vram_driver = {
  603. .match_id = PS3_MATCH_ID_GPU,
  604. .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK,
  605. .core.name = DEVICE_NAME,
  606. .core.owner = THIS_MODULE,
  607. .probe = ps3vram_probe,
  608. .remove = ps3vram_shutdown,
  609. .shutdown = ps3vram_shutdown,
  610. };
  611. static int __init ps3vram_init(void)
  612. {
  613. return ps3_system_bus_driver_register(&ps3vram_driver);
  614. }
  615. static void __exit ps3vram_exit(void)
  616. {
  617. ps3_system_bus_driver_unregister(&ps3vram_driver);
  618. }
  619. module_init(ps3vram_init);
  620. module_exit(ps3vram_exit);
  621. MODULE_LICENSE("GPL");
  622. MODULE_AUTHOR("Jim Paris <jim@jtan.com>");
  623. MODULE_DESCRIPTION("MTD driver for PS3 video RAM");
  624. MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);