dmaengine.c 26 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #include <linux/init.h>
  47. #include <linux/module.h>
  48. #include <linux/mm.h>
  49. #include <linux/device.h>
  50. #include <linux/dmaengine.h>
  51. #include <linux/hardirq.h>
  52. #include <linux/spinlock.h>
  53. #include <linux/percpu.h>
  54. #include <linux/rcupdate.h>
  55. #include <linux/mutex.h>
  56. #include <linux/jiffies.h>
  57. #include <linux/rculist.h>
  58. #include <linux/idr.h>
  59. static DEFINE_MUTEX(dma_list_mutex);
  60. static LIST_HEAD(dma_device_list);
  61. static long dmaengine_ref_count;
  62. static struct idr dma_idr;
  63. /* --- sysfs implementation --- */
  64. /**
  65. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  66. * @dev - device node
  67. *
  68. * Must be called under dma_list_mutex
  69. */
  70. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  71. {
  72. struct dma_chan_dev *chan_dev;
  73. chan_dev = container_of(dev, typeof(*chan_dev), device);
  74. return chan_dev->chan;
  75. }
  76. static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
  77. {
  78. struct dma_chan *chan;
  79. unsigned long count = 0;
  80. int i;
  81. int err;
  82. mutex_lock(&dma_list_mutex);
  83. chan = dev_to_dma_chan(dev);
  84. if (chan) {
  85. for_each_possible_cpu(i)
  86. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  87. err = sprintf(buf, "%lu\n", count);
  88. } else
  89. err = -ENODEV;
  90. mutex_unlock(&dma_list_mutex);
  91. return err;
  92. }
  93. static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
  94. char *buf)
  95. {
  96. struct dma_chan *chan;
  97. unsigned long count = 0;
  98. int i;
  99. int err;
  100. mutex_lock(&dma_list_mutex);
  101. chan = dev_to_dma_chan(dev);
  102. if (chan) {
  103. for_each_possible_cpu(i)
  104. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  105. err = sprintf(buf, "%lu\n", count);
  106. } else
  107. err = -ENODEV;
  108. mutex_unlock(&dma_list_mutex);
  109. return err;
  110. }
  111. static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
  112. {
  113. struct dma_chan *chan;
  114. int err;
  115. mutex_lock(&dma_list_mutex);
  116. chan = dev_to_dma_chan(dev);
  117. if (chan)
  118. err = sprintf(buf, "%d\n", chan->client_count);
  119. else
  120. err = -ENODEV;
  121. mutex_unlock(&dma_list_mutex);
  122. return err;
  123. }
  124. static struct device_attribute dma_attrs[] = {
  125. __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
  126. __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
  127. __ATTR(in_use, S_IRUGO, show_in_use, NULL),
  128. __ATTR_NULL
  129. };
  130. static void chan_dev_release(struct device *dev)
  131. {
  132. struct dma_chan_dev *chan_dev;
  133. chan_dev = container_of(dev, typeof(*chan_dev), device);
  134. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  135. mutex_lock(&dma_list_mutex);
  136. idr_remove(&dma_idr, chan_dev->dev_id);
  137. mutex_unlock(&dma_list_mutex);
  138. kfree(chan_dev->idr_ref);
  139. }
  140. kfree(chan_dev);
  141. }
  142. static struct class dma_devclass = {
  143. .name = "dma",
  144. .dev_attrs = dma_attrs,
  145. .dev_release = chan_dev_release,
  146. };
  147. /* --- client and device registration --- */
  148. #define dma_device_satisfies_mask(device, mask) \
  149. __dma_device_satisfies_mask((device), &(mask))
  150. static int
  151. __dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
  152. {
  153. dma_cap_mask_t has;
  154. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  155. DMA_TX_TYPE_END);
  156. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  157. }
  158. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  159. {
  160. return chan->device->dev->driver->owner;
  161. }
  162. /**
  163. * balance_ref_count - catch up the channel reference count
  164. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  165. *
  166. * balance_ref_count must be called under dma_list_mutex
  167. */
  168. static void balance_ref_count(struct dma_chan *chan)
  169. {
  170. struct module *owner = dma_chan_to_owner(chan);
  171. while (chan->client_count < dmaengine_ref_count) {
  172. __module_get(owner);
  173. chan->client_count++;
  174. }
  175. }
  176. /**
  177. * dma_chan_get - try to grab a dma channel's parent driver module
  178. * @chan - channel to grab
  179. *
  180. * Must be called under dma_list_mutex
  181. */
  182. static int dma_chan_get(struct dma_chan *chan)
  183. {
  184. int err = -ENODEV;
  185. struct module *owner = dma_chan_to_owner(chan);
  186. if (chan->client_count) {
  187. __module_get(owner);
  188. err = 0;
  189. } else if (try_module_get(owner))
  190. err = 0;
  191. if (err == 0)
  192. chan->client_count++;
  193. /* allocate upon first client reference */
  194. if (chan->client_count == 1 && err == 0) {
  195. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  196. if (desc_cnt < 0) {
  197. err = desc_cnt;
  198. chan->client_count = 0;
  199. module_put(owner);
  200. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  201. balance_ref_count(chan);
  202. }
  203. return err;
  204. }
  205. /**
  206. * dma_chan_put - drop a reference to a dma channel's parent driver module
  207. * @chan - channel to release
  208. *
  209. * Must be called under dma_list_mutex
  210. */
  211. static void dma_chan_put(struct dma_chan *chan)
  212. {
  213. if (!chan->client_count)
  214. return; /* this channel failed alloc_chan_resources */
  215. chan->client_count--;
  216. module_put(dma_chan_to_owner(chan));
  217. if (chan->client_count == 0)
  218. chan->device->device_free_chan_resources(chan);
  219. }
  220. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  221. {
  222. enum dma_status status;
  223. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  224. dma_async_issue_pending(chan);
  225. do {
  226. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  227. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  228. printk(KERN_ERR "dma_sync_wait_timeout!\n");
  229. return DMA_ERROR;
  230. }
  231. } while (status == DMA_IN_PROGRESS);
  232. return status;
  233. }
  234. EXPORT_SYMBOL(dma_sync_wait);
  235. /**
  236. * dma_cap_mask_all - enable iteration over all operation types
  237. */
  238. static dma_cap_mask_t dma_cap_mask_all;
  239. /**
  240. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  241. * @chan - associated channel for this entry
  242. */
  243. struct dma_chan_tbl_ent {
  244. struct dma_chan *chan;
  245. };
  246. /**
  247. * channel_table - percpu lookup table for memory-to-memory offload providers
  248. */
  249. static struct dma_chan_tbl_ent *channel_table[DMA_TX_TYPE_END];
  250. static int __init dma_channel_table_init(void)
  251. {
  252. enum dma_transaction_type cap;
  253. int err = 0;
  254. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  255. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  256. * but are not associated with an operation so they do not need
  257. * an entry in the channel_table
  258. */
  259. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  260. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  261. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  262. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  263. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  264. if (!channel_table[cap]) {
  265. err = -ENOMEM;
  266. break;
  267. }
  268. }
  269. if (err) {
  270. pr_err("dmaengine: initialization failure\n");
  271. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  272. if (channel_table[cap])
  273. free_percpu(channel_table[cap]);
  274. }
  275. return err;
  276. }
  277. arch_initcall(dma_channel_table_init);
  278. /**
  279. * dma_find_channel - find a channel to carry out the operation
  280. * @tx_type: transaction type
  281. */
  282. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  283. {
  284. struct dma_chan *chan;
  285. int cpu;
  286. cpu = get_cpu();
  287. chan = per_cpu_ptr(channel_table[tx_type], cpu)->chan;
  288. put_cpu();
  289. return chan;
  290. }
  291. EXPORT_SYMBOL(dma_find_channel);
  292. /**
  293. * dma_issue_pending_all - flush all pending operations across all channels
  294. */
  295. void dma_issue_pending_all(void)
  296. {
  297. struct dma_device *device;
  298. struct dma_chan *chan;
  299. rcu_read_lock();
  300. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  301. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  302. continue;
  303. list_for_each_entry(chan, &device->channels, device_node)
  304. if (chan->client_count)
  305. device->device_issue_pending(chan);
  306. }
  307. rcu_read_unlock();
  308. }
  309. EXPORT_SYMBOL(dma_issue_pending_all);
  310. /**
  311. * nth_chan - returns the nth channel of the given capability
  312. * @cap: capability to match
  313. * @n: nth channel desired
  314. *
  315. * Defaults to returning the channel with the desired capability and the
  316. * lowest reference count when 'n' cannot be satisfied. Must be called
  317. * under dma_list_mutex.
  318. */
  319. static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
  320. {
  321. struct dma_device *device;
  322. struct dma_chan *chan;
  323. struct dma_chan *ret = NULL;
  324. struct dma_chan *min = NULL;
  325. list_for_each_entry(device, &dma_device_list, global_node) {
  326. if (!dma_has_cap(cap, device->cap_mask) ||
  327. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  328. continue;
  329. list_for_each_entry(chan, &device->channels, device_node) {
  330. if (!chan->client_count)
  331. continue;
  332. if (!min)
  333. min = chan;
  334. else if (chan->table_count < min->table_count)
  335. min = chan;
  336. if (n-- == 0) {
  337. ret = chan;
  338. break; /* done */
  339. }
  340. }
  341. if (ret)
  342. break; /* done */
  343. }
  344. if (!ret)
  345. ret = min;
  346. if (ret)
  347. ret->table_count++;
  348. return ret;
  349. }
  350. /**
  351. * dma_channel_rebalance - redistribute the available channels
  352. *
  353. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  354. * operation type) in the SMP case, and operation isolation (avoid
  355. * multi-tasking channels) in the non-SMP case. Must be called under
  356. * dma_list_mutex.
  357. */
  358. static void dma_channel_rebalance(void)
  359. {
  360. struct dma_chan *chan;
  361. struct dma_device *device;
  362. int cpu;
  363. int cap;
  364. int n;
  365. /* undo the last distribution */
  366. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  367. for_each_possible_cpu(cpu)
  368. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  369. list_for_each_entry(device, &dma_device_list, global_node) {
  370. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  371. continue;
  372. list_for_each_entry(chan, &device->channels, device_node)
  373. chan->table_count = 0;
  374. }
  375. /* don't populate the channel_table if no clients are available */
  376. if (!dmaengine_ref_count)
  377. return;
  378. /* redistribute available channels */
  379. n = 0;
  380. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  381. for_each_online_cpu(cpu) {
  382. if (num_possible_cpus() > 1)
  383. chan = nth_chan(cap, n++);
  384. else
  385. chan = nth_chan(cap, -1);
  386. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  387. }
  388. }
  389. static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
  390. dma_filter_fn fn, void *fn_param)
  391. {
  392. struct dma_chan *chan;
  393. if (!__dma_device_satisfies_mask(dev, mask)) {
  394. pr_debug("%s: wrong capabilities\n", __func__);
  395. return NULL;
  396. }
  397. /* devices with multiple channels need special handling as we need to
  398. * ensure that all channels are either private or public.
  399. */
  400. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  401. list_for_each_entry(chan, &dev->channels, device_node) {
  402. /* some channels are already publicly allocated */
  403. if (chan->client_count)
  404. return NULL;
  405. }
  406. list_for_each_entry(chan, &dev->channels, device_node) {
  407. if (chan->client_count) {
  408. pr_debug("%s: %s busy\n",
  409. __func__, dma_chan_name(chan));
  410. continue;
  411. }
  412. if (fn && !fn(chan, fn_param)) {
  413. pr_debug("%s: %s filter said false\n",
  414. __func__, dma_chan_name(chan));
  415. continue;
  416. }
  417. return chan;
  418. }
  419. return NULL;
  420. }
  421. /**
  422. * dma_request_channel - try to allocate an exclusive channel
  423. * @mask: capabilities that the channel must satisfy
  424. * @fn: optional callback to disposition available channels
  425. * @fn_param: opaque parameter to pass to dma_filter_fn
  426. */
  427. struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
  428. {
  429. struct dma_device *device, *_d;
  430. struct dma_chan *chan = NULL;
  431. int err;
  432. /* Find a channel */
  433. mutex_lock(&dma_list_mutex);
  434. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  435. chan = private_candidate(mask, device, fn, fn_param);
  436. if (chan) {
  437. /* Found a suitable channel, try to grab, prep, and
  438. * return it. We first set DMA_PRIVATE to disable
  439. * balance_ref_count as this channel will not be
  440. * published in the general-purpose allocator
  441. */
  442. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  443. err = dma_chan_get(chan);
  444. if (err == -ENODEV) {
  445. pr_debug("%s: %s module removed\n", __func__,
  446. dma_chan_name(chan));
  447. list_del_rcu(&device->global_node);
  448. } else if (err)
  449. pr_err("dmaengine: failed to get %s: (%d)\n",
  450. dma_chan_name(chan), err);
  451. else
  452. break;
  453. chan = NULL;
  454. }
  455. }
  456. mutex_unlock(&dma_list_mutex);
  457. pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
  458. chan ? dma_chan_name(chan) : NULL);
  459. return chan;
  460. }
  461. EXPORT_SYMBOL_GPL(__dma_request_channel);
  462. void dma_release_channel(struct dma_chan *chan)
  463. {
  464. mutex_lock(&dma_list_mutex);
  465. WARN_ONCE(chan->client_count != 1,
  466. "chan reference count %d != 1\n", chan->client_count);
  467. dma_chan_put(chan);
  468. mutex_unlock(&dma_list_mutex);
  469. }
  470. EXPORT_SYMBOL_GPL(dma_release_channel);
  471. /**
  472. * dmaengine_get - register interest in dma_channels
  473. */
  474. void dmaengine_get(void)
  475. {
  476. struct dma_device *device, *_d;
  477. struct dma_chan *chan;
  478. int err;
  479. mutex_lock(&dma_list_mutex);
  480. dmaengine_ref_count++;
  481. /* try to grab channels */
  482. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  483. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  484. continue;
  485. list_for_each_entry(chan, &device->channels, device_node) {
  486. err = dma_chan_get(chan);
  487. if (err == -ENODEV) {
  488. /* module removed before we could use it */
  489. list_del_rcu(&device->global_node);
  490. break;
  491. } else if (err)
  492. pr_err("dmaengine: failed to get %s: (%d)\n",
  493. dma_chan_name(chan), err);
  494. }
  495. }
  496. /* if this is the first reference and there were channels
  497. * waiting we need to rebalance to get those channels
  498. * incorporated into the channel table
  499. */
  500. if (dmaengine_ref_count == 1)
  501. dma_channel_rebalance();
  502. mutex_unlock(&dma_list_mutex);
  503. }
  504. EXPORT_SYMBOL(dmaengine_get);
  505. /**
  506. * dmaengine_put - let dma drivers be removed when ref_count == 0
  507. */
  508. void dmaengine_put(void)
  509. {
  510. struct dma_device *device;
  511. struct dma_chan *chan;
  512. mutex_lock(&dma_list_mutex);
  513. dmaengine_ref_count--;
  514. BUG_ON(dmaengine_ref_count < 0);
  515. /* drop channel references */
  516. list_for_each_entry(device, &dma_device_list, global_node) {
  517. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  518. continue;
  519. list_for_each_entry(chan, &device->channels, device_node)
  520. dma_chan_put(chan);
  521. }
  522. mutex_unlock(&dma_list_mutex);
  523. }
  524. EXPORT_SYMBOL(dmaengine_put);
  525. /**
  526. * dma_async_device_register - registers DMA devices found
  527. * @device: &dma_device
  528. */
  529. int dma_async_device_register(struct dma_device *device)
  530. {
  531. int chancnt = 0, rc;
  532. struct dma_chan* chan;
  533. atomic_t *idr_ref;
  534. if (!device)
  535. return -ENODEV;
  536. /* validate device routines */
  537. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  538. !device->device_prep_dma_memcpy);
  539. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  540. !device->device_prep_dma_xor);
  541. BUG_ON(dma_has_cap(DMA_ZERO_SUM, device->cap_mask) &&
  542. !device->device_prep_dma_zero_sum);
  543. BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
  544. !device->device_prep_dma_memset);
  545. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  546. !device->device_prep_dma_interrupt);
  547. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  548. !device->device_prep_slave_sg);
  549. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  550. !device->device_terminate_all);
  551. BUG_ON(!device->device_alloc_chan_resources);
  552. BUG_ON(!device->device_free_chan_resources);
  553. BUG_ON(!device->device_is_tx_complete);
  554. BUG_ON(!device->device_issue_pending);
  555. BUG_ON(!device->dev);
  556. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  557. if (!idr_ref)
  558. return -ENOMEM;
  559. atomic_set(idr_ref, 0);
  560. idr_retry:
  561. if (!idr_pre_get(&dma_idr, GFP_KERNEL))
  562. return -ENOMEM;
  563. mutex_lock(&dma_list_mutex);
  564. rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
  565. mutex_unlock(&dma_list_mutex);
  566. if (rc == -EAGAIN)
  567. goto idr_retry;
  568. else if (rc != 0)
  569. return rc;
  570. /* represent channels in sysfs. Probably want devs too */
  571. list_for_each_entry(chan, &device->channels, device_node) {
  572. chan->local = alloc_percpu(typeof(*chan->local));
  573. if (chan->local == NULL)
  574. continue;
  575. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  576. if (chan->dev == NULL) {
  577. free_percpu(chan->local);
  578. continue;
  579. }
  580. chan->chan_id = chancnt++;
  581. chan->dev->device.class = &dma_devclass;
  582. chan->dev->device.parent = device->dev;
  583. chan->dev->chan = chan;
  584. chan->dev->idr_ref = idr_ref;
  585. chan->dev->dev_id = device->dev_id;
  586. atomic_inc(idr_ref);
  587. dev_set_name(&chan->dev->device, "dma%dchan%d",
  588. device->dev_id, chan->chan_id);
  589. rc = device_register(&chan->dev->device);
  590. if (rc) {
  591. free_percpu(chan->local);
  592. chan->local = NULL;
  593. goto err_out;
  594. }
  595. chan->client_count = 0;
  596. }
  597. device->chancnt = chancnt;
  598. mutex_lock(&dma_list_mutex);
  599. /* take references on public channels */
  600. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  601. list_for_each_entry(chan, &device->channels, device_node) {
  602. /* if clients are already waiting for channels we need
  603. * to take references on their behalf
  604. */
  605. if (dma_chan_get(chan) == -ENODEV) {
  606. /* note we can only get here for the first
  607. * channel as the remaining channels are
  608. * guaranteed to get a reference
  609. */
  610. rc = -ENODEV;
  611. mutex_unlock(&dma_list_mutex);
  612. goto err_out;
  613. }
  614. }
  615. list_add_tail_rcu(&device->global_node, &dma_device_list);
  616. dma_channel_rebalance();
  617. mutex_unlock(&dma_list_mutex);
  618. return 0;
  619. err_out:
  620. list_for_each_entry(chan, &device->channels, device_node) {
  621. if (chan->local == NULL)
  622. continue;
  623. mutex_lock(&dma_list_mutex);
  624. chan->dev->chan = NULL;
  625. mutex_unlock(&dma_list_mutex);
  626. device_unregister(&chan->dev->device);
  627. free_percpu(chan->local);
  628. }
  629. return rc;
  630. }
  631. EXPORT_SYMBOL(dma_async_device_register);
  632. /**
  633. * dma_async_device_unregister - unregister a DMA device
  634. * @device: &dma_device
  635. *
  636. * This routine is called by dma driver exit routines, dmaengine holds module
  637. * references to prevent it being called while channels are in use.
  638. */
  639. void dma_async_device_unregister(struct dma_device *device)
  640. {
  641. struct dma_chan *chan;
  642. mutex_lock(&dma_list_mutex);
  643. list_del_rcu(&device->global_node);
  644. dma_channel_rebalance();
  645. mutex_unlock(&dma_list_mutex);
  646. list_for_each_entry(chan, &device->channels, device_node) {
  647. WARN_ONCE(chan->client_count,
  648. "%s called while %d clients hold a reference\n",
  649. __func__, chan->client_count);
  650. mutex_lock(&dma_list_mutex);
  651. chan->dev->chan = NULL;
  652. mutex_unlock(&dma_list_mutex);
  653. device_unregister(&chan->dev->device);
  654. }
  655. }
  656. EXPORT_SYMBOL(dma_async_device_unregister);
  657. /**
  658. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  659. * @chan: DMA channel to offload copy to
  660. * @dest: destination address (virtual)
  661. * @src: source address (virtual)
  662. * @len: length
  663. *
  664. * Both @dest and @src must be mappable to a bus address according to the
  665. * DMA mapping API rules for streaming mappings.
  666. * Both @dest and @src must stay memory resident (kernel memory or locked
  667. * user space pages).
  668. */
  669. dma_cookie_t
  670. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  671. void *src, size_t len)
  672. {
  673. struct dma_device *dev = chan->device;
  674. struct dma_async_tx_descriptor *tx;
  675. dma_addr_t dma_dest, dma_src;
  676. dma_cookie_t cookie;
  677. int cpu;
  678. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  679. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  680. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
  681. DMA_CTRL_ACK);
  682. if (!tx) {
  683. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  684. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  685. return -ENOMEM;
  686. }
  687. tx->callback = NULL;
  688. cookie = tx->tx_submit(tx);
  689. cpu = get_cpu();
  690. per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
  691. per_cpu_ptr(chan->local, cpu)->memcpy_count++;
  692. put_cpu();
  693. return cookie;
  694. }
  695. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  696. /**
  697. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  698. * @chan: DMA channel to offload copy to
  699. * @page: destination page
  700. * @offset: offset in page to copy to
  701. * @kdata: source address (virtual)
  702. * @len: length
  703. *
  704. * Both @page/@offset and @kdata must be mappable to a bus address according
  705. * to the DMA mapping API rules for streaming mappings.
  706. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  707. * locked user space pages)
  708. */
  709. dma_cookie_t
  710. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  711. unsigned int offset, void *kdata, size_t len)
  712. {
  713. struct dma_device *dev = chan->device;
  714. struct dma_async_tx_descriptor *tx;
  715. dma_addr_t dma_dest, dma_src;
  716. dma_cookie_t cookie;
  717. int cpu;
  718. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  719. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  720. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
  721. DMA_CTRL_ACK);
  722. if (!tx) {
  723. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  724. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  725. return -ENOMEM;
  726. }
  727. tx->callback = NULL;
  728. cookie = tx->tx_submit(tx);
  729. cpu = get_cpu();
  730. per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
  731. per_cpu_ptr(chan->local, cpu)->memcpy_count++;
  732. put_cpu();
  733. return cookie;
  734. }
  735. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  736. /**
  737. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  738. * @chan: DMA channel to offload copy to
  739. * @dest_pg: destination page
  740. * @dest_off: offset in page to copy to
  741. * @src_pg: source page
  742. * @src_off: offset in page to copy from
  743. * @len: length
  744. *
  745. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  746. * address according to the DMA mapping API rules for streaming mappings.
  747. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  748. * (kernel memory or locked user space pages).
  749. */
  750. dma_cookie_t
  751. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  752. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  753. size_t len)
  754. {
  755. struct dma_device *dev = chan->device;
  756. struct dma_async_tx_descriptor *tx;
  757. dma_addr_t dma_dest, dma_src;
  758. dma_cookie_t cookie;
  759. int cpu;
  760. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  761. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  762. DMA_FROM_DEVICE);
  763. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
  764. DMA_CTRL_ACK);
  765. if (!tx) {
  766. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  767. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  768. return -ENOMEM;
  769. }
  770. tx->callback = NULL;
  771. cookie = tx->tx_submit(tx);
  772. cpu = get_cpu();
  773. per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
  774. per_cpu_ptr(chan->local, cpu)->memcpy_count++;
  775. put_cpu();
  776. return cookie;
  777. }
  778. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  779. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  780. struct dma_chan *chan)
  781. {
  782. tx->chan = chan;
  783. spin_lock_init(&tx->lock);
  784. }
  785. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  786. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  787. * @tx: in-flight transaction to wait on
  788. *
  789. * This routine assumes that tx was obtained from a call to async_memcpy,
  790. * async_xor, async_memset, etc which ensures that tx is "in-flight" (prepped
  791. * and submitted). Walking the parent chain is only meant to cover for DMA
  792. * drivers that do not implement the DMA_INTERRUPT capability and may race with
  793. * the driver's descriptor cleanup routine.
  794. */
  795. enum dma_status
  796. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  797. {
  798. enum dma_status status;
  799. struct dma_async_tx_descriptor *iter;
  800. struct dma_async_tx_descriptor *parent;
  801. if (!tx)
  802. return DMA_SUCCESS;
  803. WARN_ONCE(tx->parent, "%s: speculatively walking dependency chain for"
  804. " %s\n", __func__, dma_chan_name(tx->chan));
  805. /* poll through the dependency chain, return when tx is complete */
  806. do {
  807. iter = tx;
  808. /* find the root of the unsubmitted dependency chain */
  809. do {
  810. parent = iter->parent;
  811. if (!parent)
  812. break;
  813. else
  814. iter = parent;
  815. } while (parent);
  816. /* there is a small window for ->parent == NULL and
  817. * ->cookie == -EBUSY
  818. */
  819. while (iter->cookie == -EBUSY)
  820. cpu_relax();
  821. status = dma_sync_wait(iter->chan, iter->cookie);
  822. } while (status == DMA_IN_PROGRESS || (iter != tx));
  823. return status;
  824. }
  825. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  826. /* dma_run_dependencies - helper routine for dma drivers to process
  827. * (start) dependent operations on their target channel
  828. * @tx: transaction with dependencies
  829. */
  830. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  831. {
  832. struct dma_async_tx_descriptor *dep = tx->next;
  833. struct dma_async_tx_descriptor *dep_next;
  834. struct dma_chan *chan;
  835. if (!dep)
  836. return;
  837. /* we'll submit tx->next now, so clear the link */
  838. tx->next = NULL;
  839. chan = dep->chan;
  840. /* keep submitting up until a channel switch is detected
  841. * in that case we will be called again as a result of
  842. * processing the interrupt from async_tx_channel_switch
  843. */
  844. for (; dep; dep = dep_next) {
  845. spin_lock_bh(&dep->lock);
  846. dep->parent = NULL;
  847. dep_next = dep->next;
  848. if (dep_next && dep_next->chan == chan)
  849. dep->next = NULL; /* ->next will be submitted */
  850. else
  851. dep_next = NULL; /* submit current dep and terminate */
  852. spin_unlock_bh(&dep->lock);
  853. dep->tx_submit(dep);
  854. }
  855. chan->device->device_issue_pending(chan);
  856. }
  857. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  858. static int __init dma_bus_init(void)
  859. {
  860. idr_init(&dma_idr);
  861. mutex_init(&dma_list_mutex);
  862. return class_register(&dma_devclass);
  863. }
  864. arch_initcall(dma_bus_init);