voyager_smp.c 50 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807
  1. /* -*- mode: c; c-basic-offset: 8 -*- */
  2. /* Copyright (C) 1999,2001
  3. *
  4. * Author: J.E.J.Bottomley@HansenPartnership.com
  5. *
  6. * This file provides all the same external entries as smp.c but uses
  7. * the voyager hal to provide the functionality
  8. */
  9. #include <linux/cpu.h>
  10. #include <linux/module.h>
  11. #include <linux/mm.h>
  12. #include <linux/kernel_stat.h>
  13. #include <linux/delay.h>
  14. #include <linux/mc146818rtc.h>
  15. #include <linux/cache.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/bootmem.h>
  20. #include <linux/completion.h>
  21. #include <asm/desc.h>
  22. #include <asm/voyager.h>
  23. #include <asm/vic.h>
  24. #include <asm/mtrr.h>
  25. #include <asm/pgalloc.h>
  26. #include <asm/tlbflush.h>
  27. #include <asm/arch_hooks.h>
  28. #include <asm/trampoline.h>
  29. /* TLB state -- visible externally, indexed physically */
  30. DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = { &init_mm, 0 };
  31. /* CPU IRQ affinity -- set to all ones initially */
  32. static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned =
  33. {[0 ... NR_CPUS-1] = ~0UL };
  34. /* per CPU data structure (for /proc/cpuinfo et al), visible externally
  35. * indexed physically */
  36. DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
  37. EXPORT_PER_CPU_SYMBOL(cpu_info);
  38. /* physical ID of the CPU used to boot the system */
  39. unsigned char boot_cpu_id;
  40. /* The memory line addresses for the Quad CPIs */
  41. struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
  42. /* The masks for the Extended VIC processors, filled in by cat_init */
  43. __u32 voyager_extended_vic_processors = 0;
  44. /* Masks for the extended Quad processors which cannot be VIC booted */
  45. __u32 voyager_allowed_boot_processors = 0;
  46. /* The mask for the Quad Processors (both extended and non-extended) */
  47. __u32 voyager_quad_processors = 0;
  48. /* Total count of live CPUs, used in process.c to display
  49. * the CPU information and in irq.c for the per CPU irq
  50. * activity count. Finally exported by i386_ksyms.c */
  51. static int voyager_extended_cpus = 1;
  52. /* Used for the invalidate map that's also checked in the spinlock */
  53. static volatile unsigned long smp_invalidate_needed;
  54. /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
  55. * by scheduler but indexed physically */
  56. cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
  57. /* The internal functions */
  58. static void send_CPI(__u32 cpuset, __u8 cpi);
  59. static void ack_CPI(__u8 cpi);
  60. static int ack_QIC_CPI(__u8 cpi);
  61. static void ack_special_QIC_CPI(__u8 cpi);
  62. static void ack_VIC_CPI(__u8 cpi);
  63. static void send_CPI_allbutself(__u8 cpi);
  64. static void mask_vic_irq(unsigned int irq);
  65. static void unmask_vic_irq(unsigned int irq);
  66. static unsigned int startup_vic_irq(unsigned int irq);
  67. static void enable_local_vic_irq(unsigned int irq);
  68. static void disable_local_vic_irq(unsigned int irq);
  69. static void before_handle_vic_irq(unsigned int irq);
  70. static void after_handle_vic_irq(unsigned int irq);
  71. static void set_vic_irq_affinity(unsigned int irq, const struct cpumask *mask);
  72. static void ack_vic_irq(unsigned int irq);
  73. static void vic_enable_cpi(void);
  74. static void do_boot_cpu(__u8 cpuid);
  75. static void do_quad_bootstrap(void);
  76. static void initialize_secondary(void);
  77. int hard_smp_processor_id(void);
  78. int safe_smp_processor_id(void);
  79. /* Inline functions */
  80. static inline void send_one_QIC_CPI(__u8 cpu, __u8 cpi)
  81. {
  82. voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
  83. (smp_processor_id() << 16) + cpi;
  84. }
  85. static inline void send_QIC_CPI(__u32 cpuset, __u8 cpi)
  86. {
  87. int cpu;
  88. for_each_online_cpu(cpu) {
  89. if (cpuset & (1 << cpu)) {
  90. #ifdef VOYAGER_DEBUG
  91. if (!cpu_online(cpu))
  92. VDEBUG(("CPU%d sending cpi %d to CPU%d not in "
  93. "cpu_online_map\n",
  94. hard_smp_processor_id(), cpi, cpu));
  95. #endif
  96. send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
  97. }
  98. }
  99. }
  100. static inline void wrapper_smp_local_timer_interrupt(void)
  101. {
  102. irq_enter();
  103. smp_local_timer_interrupt();
  104. irq_exit();
  105. }
  106. static inline void send_one_CPI(__u8 cpu, __u8 cpi)
  107. {
  108. if (voyager_quad_processors & (1 << cpu))
  109. send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
  110. else
  111. send_CPI(1 << cpu, cpi);
  112. }
  113. static inline void send_CPI_allbutself(__u8 cpi)
  114. {
  115. __u8 cpu = smp_processor_id();
  116. __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
  117. send_CPI(mask, cpi);
  118. }
  119. static inline int is_cpu_quad(void)
  120. {
  121. __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
  122. return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
  123. }
  124. static inline int is_cpu_extended(void)
  125. {
  126. __u8 cpu = hard_smp_processor_id();
  127. return (voyager_extended_vic_processors & (1 << cpu));
  128. }
  129. static inline int is_cpu_vic_boot(void)
  130. {
  131. __u8 cpu = hard_smp_processor_id();
  132. return (voyager_extended_vic_processors
  133. & voyager_allowed_boot_processors & (1 << cpu));
  134. }
  135. static inline void ack_CPI(__u8 cpi)
  136. {
  137. switch (cpi) {
  138. case VIC_CPU_BOOT_CPI:
  139. if (is_cpu_quad() && !is_cpu_vic_boot())
  140. ack_QIC_CPI(cpi);
  141. else
  142. ack_VIC_CPI(cpi);
  143. break;
  144. case VIC_SYS_INT:
  145. case VIC_CMN_INT:
  146. /* These are slightly strange. Even on the Quad card,
  147. * They are vectored as VIC CPIs */
  148. if (is_cpu_quad())
  149. ack_special_QIC_CPI(cpi);
  150. else
  151. ack_VIC_CPI(cpi);
  152. break;
  153. default:
  154. printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
  155. break;
  156. }
  157. }
  158. /* local variables */
  159. /* The VIC IRQ descriptors -- these look almost identical to the
  160. * 8259 IRQs except that masks and things must be kept per processor
  161. */
  162. static struct irq_chip vic_chip = {
  163. .name = "VIC",
  164. .startup = startup_vic_irq,
  165. .mask = mask_vic_irq,
  166. .unmask = unmask_vic_irq,
  167. .set_affinity = set_vic_irq_affinity,
  168. };
  169. /* used to count up as CPUs are brought on line (starts at 0) */
  170. static int cpucount = 0;
  171. /* The per cpu profile stuff - used in smp_local_timer_interrupt */
  172. static DEFINE_PER_CPU(int, prof_multiplier) = 1;
  173. static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
  174. static DEFINE_PER_CPU(int, prof_counter) = 1;
  175. /* the map used to check if a CPU has booted */
  176. static __u32 cpu_booted_map;
  177. /* the synchronize flag used to hold all secondary CPUs spinning in
  178. * a tight loop until the boot sequence is ready for them */
  179. static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
  180. /* This is for the new dynamic CPU boot code */
  181. /* The per processor IRQ masks (these are usually kept in sync) */
  182. static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
  183. /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
  184. static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
  185. /* Lock for enable/disable of VIC interrupts */
  186. static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
  187. /* The boot processor is correctly set up in PC mode when it
  188. * comes up, but the secondaries need their master/slave 8259
  189. * pairs initializing correctly */
  190. /* Interrupt counters (per cpu) and total - used to try to
  191. * even up the interrupt handling routines */
  192. static long vic_intr_total = 0;
  193. static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
  194. static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
  195. /* Since we can only use CPI0, we fake all the other CPIs */
  196. static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
  197. /* debugging routine to read the isr of the cpu's pic */
  198. static inline __u16 vic_read_isr(void)
  199. {
  200. __u16 isr;
  201. outb(0x0b, 0xa0);
  202. isr = inb(0xa0) << 8;
  203. outb(0x0b, 0x20);
  204. isr |= inb(0x20);
  205. return isr;
  206. }
  207. static __init void qic_setup(void)
  208. {
  209. if (!is_cpu_quad()) {
  210. /* not a quad, no setup */
  211. return;
  212. }
  213. outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
  214. outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
  215. if (is_cpu_extended()) {
  216. /* the QIC duplicate of the VIC base register */
  217. outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
  218. outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
  219. /* FIXME: should set up the QIC timer and memory parity
  220. * error vectors here */
  221. }
  222. }
  223. static __init void vic_setup_pic(void)
  224. {
  225. outb(1, VIC_REDIRECT_REGISTER_1);
  226. /* clear the claim registers for dynamic routing */
  227. outb(0, VIC_CLAIM_REGISTER_0);
  228. outb(0, VIC_CLAIM_REGISTER_1);
  229. outb(0, VIC_PRIORITY_REGISTER);
  230. /* Set the Primary and Secondary Microchannel vector
  231. * bases to be the same as the ordinary interrupts
  232. *
  233. * FIXME: This would be more efficient using separate
  234. * vectors. */
  235. outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
  236. outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
  237. /* Now initiallise the master PIC belonging to this CPU by
  238. * sending the four ICWs */
  239. /* ICW1: level triggered, ICW4 needed */
  240. outb(0x19, 0x20);
  241. /* ICW2: vector base */
  242. outb(FIRST_EXTERNAL_VECTOR, 0x21);
  243. /* ICW3: slave at line 2 */
  244. outb(0x04, 0x21);
  245. /* ICW4: 8086 mode */
  246. outb(0x01, 0x21);
  247. /* now the same for the slave PIC */
  248. /* ICW1: level trigger, ICW4 needed */
  249. outb(0x19, 0xA0);
  250. /* ICW2: slave vector base */
  251. outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
  252. /* ICW3: slave ID */
  253. outb(0x02, 0xA1);
  254. /* ICW4: 8086 mode */
  255. outb(0x01, 0xA1);
  256. }
  257. static void do_quad_bootstrap(void)
  258. {
  259. if (is_cpu_quad() && is_cpu_vic_boot()) {
  260. int i;
  261. unsigned long flags;
  262. __u8 cpuid = hard_smp_processor_id();
  263. local_irq_save(flags);
  264. for (i = 0; i < 4; i++) {
  265. /* FIXME: this would be >>3 &0x7 on the 32 way */
  266. if (((cpuid >> 2) & 0x03) == i)
  267. /* don't lower our own mask! */
  268. continue;
  269. /* masquerade as local Quad CPU */
  270. outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
  271. /* enable the startup CPI */
  272. outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
  273. /* restore cpu id */
  274. outb(0, QIC_PROCESSOR_ID);
  275. }
  276. local_irq_restore(flags);
  277. }
  278. }
  279. void prefill_possible_map(void)
  280. {
  281. /* This is empty on voyager because we need a much
  282. * earlier detection which is done in find_smp_config */
  283. }
  284. /* Set up all the basic stuff: read the SMP config and make all the
  285. * SMP information reflect only the boot cpu. All others will be
  286. * brought on-line later. */
  287. void __init find_smp_config(void)
  288. {
  289. int i;
  290. boot_cpu_id = hard_smp_processor_id();
  291. printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
  292. /* initialize the CPU structures (moved from smp_boot_cpus) */
  293. for (i = 0; i < nr_cpu_ids; i++)
  294. cpu_irq_affinity[i] = ~0;
  295. cpu_online_map = cpumask_of_cpu(boot_cpu_id);
  296. /* The boot CPU must be extended */
  297. voyager_extended_vic_processors = 1 << boot_cpu_id;
  298. /* initially, all of the first 8 CPUs can boot */
  299. voyager_allowed_boot_processors = 0xff;
  300. /* set up everything for just this CPU, we can alter
  301. * this as we start the other CPUs later */
  302. /* now get the CPU disposition from the extended CMOS */
  303. cpus_addr(phys_cpu_present_map)[0] =
  304. voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
  305. cpus_addr(phys_cpu_present_map)[0] |=
  306. voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
  307. cpus_addr(phys_cpu_present_map)[0] |=
  308. voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK +
  309. 2) << 16;
  310. cpus_addr(phys_cpu_present_map)[0] |=
  311. voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK +
  312. 3) << 24;
  313. init_cpu_possible(&phys_cpu_present_map);
  314. printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n",
  315. cpus_addr(phys_cpu_present_map)[0]);
  316. /* Here we set up the VIC to enable SMP */
  317. /* enable the CPIs by writing the base vector to their register */
  318. outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
  319. outb(1, VIC_REDIRECT_REGISTER_1);
  320. /* set the claim registers for static routing --- Boot CPU gets
  321. * all interrupts untill all other CPUs started */
  322. outb(0xff, VIC_CLAIM_REGISTER_0);
  323. outb(0xff, VIC_CLAIM_REGISTER_1);
  324. /* Set the Primary and Secondary Microchannel vector
  325. * bases to be the same as the ordinary interrupts
  326. *
  327. * FIXME: This would be more efficient using separate
  328. * vectors. */
  329. outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
  330. outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
  331. /* Finally tell the firmware that we're driving */
  332. outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
  333. VOYAGER_SUS_IN_CONTROL_PORT);
  334. current_thread_info()->cpu = boot_cpu_id;
  335. x86_write_percpu(cpu_number, boot_cpu_id);
  336. }
  337. /*
  338. * The bootstrap kernel entry code has set these up. Save them
  339. * for a given CPU, id is physical */
  340. void __init smp_store_cpu_info(int id)
  341. {
  342. struct cpuinfo_x86 *c = &cpu_data(id);
  343. *c = boot_cpu_data;
  344. c->cpu_index = id;
  345. identify_secondary_cpu(c);
  346. }
  347. /* Routine initially called when a non-boot CPU is brought online */
  348. static void __init start_secondary(void *unused)
  349. {
  350. __u8 cpuid = hard_smp_processor_id();
  351. cpu_init();
  352. /* OK, we're in the routine */
  353. ack_CPI(VIC_CPU_BOOT_CPI);
  354. /* setup the 8259 master slave pair belonging to this CPU ---
  355. * we won't actually receive any until the boot CPU
  356. * relinquishes it's static routing mask */
  357. vic_setup_pic();
  358. qic_setup();
  359. if (is_cpu_quad() && !is_cpu_vic_boot()) {
  360. /* clear the boot CPI */
  361. __u8 dummy;
  362. dummy =
  363. voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
  364. printk("read dummy %d\n", dummy);
  365. }
  366. /* lower the mask to receive CPIs */
  367. vic_enable_cpi();
  368. VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
  369. notify_cpu_starting(cpuid);
  370. /* enable interrupts */
  371. local_irq_enable();
  372. /* get our bogomips */
  373. calibrate_delay();
  374. /* save our processor parameters */
  375. smp_store_cpu_info(cpuid);
  376. /* if we're a quad, we may need to bootstrap other CPUs */
  377. do_quad_bootstrap();
  378. /* FIXME: this is rather a poor hack to prevent the CPU
  379. * activating softirqs while it's supposed to be waiting for
  380. * permission to proceed. Without this, the new per CPU stuff
  381. * in the softirqs will fail */
  382. local_irq_disable();
  383. cpu_set(cpuid, cpu_callin_map);
  384. /* signal that we're done */
  385. cpu_booted_map = 1;
  386. while (!cpu_isset(cpuid, smp_commenced_mask))
  387. rep_nop();
  388. local_irq_enable();
  389. local_flush_tlb();
  390. cpu_set(cpuid, cpu_online_map);
  391. wmb();
  392. cpu_idle();
  393. }
  394. /* Routine to kick start the given CPU and wait for it to report ready
  395. * (or timeout in startup). When this routine returns, the requested
  396. * CPU is either fully running and configured or known to be dead.
  397. *
  398. * We call this routine sequentially 1 CPU at a time, so no need for
  399. * locking */
  400. static void __init do_boot_cpu(__u8 cpu)
  401. {
  402. struct task_struct *idle;
  403. int timeout;
  404. unsigned long flags;
  405. int quad_boot = (1 << cpu) & voyager_quad_processors
  406. & ~(voyager_extended_vic_processors
  407. & voyager_allowed_boot_processors);
  408. /* This is the format of the CPI IDT gate (in real mode) which
  409. * we're hijacking to boot the CPU */
  410. union IDTFormat {
  411. struct seg {
  412. __u16 Offset;
  413. __u16 Segment;
  414. } idt;
  415. __u32 val;
  416. } hijack_source;
  417. __u32 *hijack_vector;
  418. __u32 start_phys_address = setup_trampoline();
  419. /* There's a clever trick to this: The linux trampoline is
  420. * compiled to begin at absolute location zero, so make the
  421. * address zero but have the data segment selector compensate
  422. * for the actual address */
  423. hijack_source.idt.Offset = start_phys_address & 0x000F;
  424. hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
  425. cpucount++;
  426. alternatives_smp_switch(1);
  427. idle = fork_idle(cpu);
  428. if (IS_ERR(idle))
  429. panic("failed fork for CPU%d", cpu);
  430. idle->thread.ip = (unsigned long)start_secondary;
  431. /* init_tasks (in sched.c) is indexed logically */
  432. stack_start.sp = (void *)idle->thread.sp;
  433. init_gdt(cpu);
  434. per_cpu(current_task, cpu) = idle;
  435. early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
  436. irq_ctx_init(cpu);
  437. /* Note: Don't modify initial ss override */
  438. VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
  439. (unsigned long)hijack_source.val, hijack_source.idt.Segment,
  440. hijack_source.idt.Offset, stack_start.sp));
  441. /* init lowmem identity mapping */
  442. clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY,
  443. min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY));
  444. flush_tlb_all();
  445. if (quad_boot) {
  446. printk("CPU %d: non extended Quad boot\n", cpu);
  447. hijack_vector =
  448. (__u32 *)
  449. phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE) * 4);
  450. *hijack_vector = hijack_source.val;
  451. } else {
  452. printk("CPU%d: extended VIC boot\n", cpu);
  453. hijack_vector =
  454. (__u32 *)
  455. phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE) * 4);
  456. *hijack_vector = hijack_source.val;
  457. /* VIC errata, may also receive interrupt at this address */
  458. hijack_vector =
  459. (__u32 *)
  460. phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI +
  461. VIC_DEFAULT_CPI_BASE) * 4);
  462. *hijack_vector = hijack_source.val;
  463. }
  464. /* All non-boot CPUs start with interrupts fully masked. Need
  465. * to lower the mask of the CPI we're about to send. We do
  466. * this in the VIC by masquerading as the processor we're
  467. * about to boot and lowering its interrupt mask */
  468. local_irq_save(flags);
  469. if (quad_boot) {
  470. send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
  471. } else {
  472. outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
  473. /* here we're altering registers belonging to `cpu' */
  474. outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
  475. /* now go back to our original identity */
  476. outb(boot_cpu_id, VIC_PROCESSOR_ID);
  477. /* and boot the CPU */
  478. send_CPI((1 << cpu), VIC_CPU_BOOT_CPI);
  479. }
  480. cpu_booted_map = 0;
  481. local_irq_restore(flags);
  482. /* now wait for it to become ready (or timeout) */
  483. for (timeout = 0; timeout < 50000; timeout++) {
  484. if (cpu_booted_map)
  485. break;
  486. udelay(100);
  487. }
  488. /* reset the page table */
  489. zap_low_mappings();
  490. if (cpu_booted_map) {
  491. VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
  492. cpu, smp_processor_id()));
  493. printk("CPU%d: ", cpu);
  494. print_cpu_info(&cpu_data(cpu));
  495. wmb();
  496. cpu_set(cpu, cpu_callout_map);
  497. cpu_set(cpu, cpu_present_map);
  498. } else {
  499. printk("CPU%d FAILED TO BOOT: ", cpu);
  500. if (*
  501. ((volatile unsigned char *)phys_to_virt(start_phys_address))
  502. == 0xA5)
  503. printk("Stuck.\n");
  504. else
  505. printk("Not responding.\n");
  506. cpucount--;
  507. }
  508. }
  509. void __init smp_boot_cpus(void)
  510. {
  511. int i;
  512. /* CAT BUS initialisation must be done after the memory */
  513. /* FIXME: The L4 has a catbus too, it just needs to be
  514. * accessed in a totally different way */
  515. if (voyager_level == 5) {
  516. voyager_cat_init();
  517. /* now that the cat has probed the Voyager System Bus, sanity
  518. * check the cpu map */
  519. if (((voyager_quad_processors | voyager_extended_vic_processors)
  520. & cpus_addr(phys_cpu_present_map)[0]) !=
  521. cpus_addr(phys_cpu_present_map)[0]) {
  522. /* should panic */
  523. printk("\n\n***WARNING*** "
  524. "Sanity check of CPU present map FAILED\n");
  525. }
  526. } else if (voyager_level == 4)
  527. voyager_extended_vic_processors =
  528. cpus_addr(phys_cpu_present_map)[0];
  529. /* this sets up the idle task to run on the current cpu */
  530. voyager_extended_cpus = 1;
  531. /* Remove the global_irq_holder setting, it triggers a BUG() on
  532. * schedule at the moment */
  533. //global_irq_holder = boot_cpu_id;
  534. /* FIXME: Need to do something about this but currently only works
  535. * on CPUs with a tsc which none of mine have.
  536. smp_tune_scheduling();
  537. */
  538. smp_store_cpu_info(boot_cpu_id);
  539. /* setup the jump vector */
  540. initial_code = (unsigned long)initialize_secondary;
  541. printk("CPU%d: ", boot_cpu_id);
  542. print_cpu_info(&cpu_data(boot_cpu_id));
  543. if (is_cpu_quad()) {
  544. /* booting on a Quad CPU */
  545. printk("VOYAGER SMP: Boot CPU is Quad\n");
  546. qic_setup();
  547. do_quad_bootstrap();
  548. }
  549. /* enable our own CPIs */
  550. vic_enable_cpi();
  551. cpu_set(boot_cpu_id, cpu_online_map);
  552. cpu_set(boot_cpu_id, cpu_callout_map);
  553. /* loop over all the extended VIC CPUs and boot them. The
  554. * Quad CPUs must be bootstrapped by their extended VIC cpu */
  555. for (i = 0; i < nr_cpu_ids; i++) {
  556. if (i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map))
  557. continue;
  558. do_boot_cpu(i);
  559. /* This udelay seems to be needed for the Quad boots
  560. * don't remove unless you know what you're doing */
  561. udelay(1000);
  562. }
  563. /* we could compute the total bogomips here, but why bother?,
  564. * Code added from smpboot.c */
  565. {
  566. unsigned long bogosum = 0;
  567. for_each_online_cpu(i)
  568. bogosum += cpu_data(i).loops_per_jiffy;
  569. printk(KERN_INFO "Total of %d processors activated "
  570. "(%lu.%02lu BogoMIPS).\n",
  571. cpucount + 1, bogosum / (500000 / HZ),
  572. (bogosum / (5000 / HZ)) % 100);
  573. }
  574. voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
  575. printk("VOYAGER: Extended (interrupt handling CPUs): "
  576. "%d, non-extended: %d\n", voyager_extended_cpus,
  577. num_booting_cpus() - voyager_extended_cpus);
  578. /* that's it, switch to symmetric mode */
  579. outb(0, VIC_PRIORITY_REGISTER);
  580. outb(0, VIC_CLAIM_REGISTER_0);
  581. outb(0, VIC_CLAIM_REGISTER_1);
  582. VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
  583. }
  584. /* Reload the secondary CPUs task structure (this function does not
  585. * return ) */
  586. static void __init initialize_secondary(void)
  587. {
  588. #if 0
  589. // AC kernels only
  590. set_current(hard_get_current());
  591. #endif
  592. /*
  593. * We don't actually need to load the full TSS,
  594. * basically just the stack pointer and the eip.
  595. */
  596. asm volatile ("movl %0,%%esp\n\t"
  597. "jmp *%1"::"r" (current->thread.sp),
  598. "r"(current->thread.ip));
  599. }
  600. /* handle a Voyager SYS_INT -- If we don't, the base board will
  601. * panic the system.
  602. *
  603. * System interrupts occur because some problem was detected on the
  604. * various busses. To find out what you have to probe all the
  605. * hardware via the CAT bus. FIXME: At the moment we do nothing. */
  606. void smp_vic_sys_interrupt(struct pt_regs *regs)
  607. {
  608. ack_CPI(VIC_SYS_INT);
  609. printk("Voyager SYSTEM INTERRUPT\n");
  610. }
  611. /* Handle a voyager CMN_INT; These interrupts occur either because of
  612. * a system status change or because a single bit memory error
  613. * occurred. FIXME: At the moment, ignore all this. */
  614. void smp_vic_cmn_interrupt(struct pt_regs *regs)
  615. {
  616. static __u8 in_cmn_int = 0;
  617. static DEFINE_SPINLOCK(cmn_int_lock);
  618. /* common ints are broadcast, so make sure we only do this once */
  619. _raw_spin_lock(&cmn_int_lock);
  620. if (in_cmn_int)
  621. goto unlock_end;
  622. in_cmn_int++;
  623. _raw_spin_unlock(&cmn_int_lock);
  624. VDEBUG(("Voyager COMMON INTERRUPT\n"));
  625. if (voyager_level == 5)
  626. voyager_cat_do_common_interrupt();
  627. _raw_spin_lock(&cmn_int_lock);
  628. in_cmn_int = 0;
  629. unlock_end:
  630. _raw_spin_unlock(&cmn_int_lock);
  631. ack_CPI(VIC_CMN_INT);
  632. }
  633. /*
  634. * Reschedule call back. Nothing to do, all the work is done
  635. * automatically when we return from the interrupt. */
  636. static void smp_reschedule_interrupt(void)
  637. {
  638. /* do nothing */
  639. }
  640. static struct mm_struct *flush_mm;
  641. static unsigned long flush_va;
  642. static DEFINE_SPINLOCK(tlbstate_lock);
  643. /*
  644. * We cannot call mmdrop() because we are in interrupt context,
  645. * instead update mm->cpu_vm_mask.
  646. *
  647. * We need to reload %cr3 since the page tables may be going
  648. * away from under us..
  649. */
  650. static inline void voyager_leave_mm(unsigned long cpu)
  651. {
  652. if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
  653. BUG();
  654. cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
  655. load_cr3(swapper_pg_dir);
  656. }
  657. /*
  658. * Invalidate call-back
  659. */
  660. static void smp_invalidate_interrupt(void)
  661. {
  662. __u8 cpu = smp_processor_id();
  663. if (!test_bit(cpu, &smp_invalidate_needed))
  664. return;
  665. /* This will flood messages. Don't uncomment unless you see
  666. * Problems with cross cpu invalidation
  667. VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
  668. smp_processor_id()));
  669. */
  670. if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
  671. if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
  672. if (flush_va == TLB_FLUSH_ALL)
  673. local_flush_tlb();
  674. else
  675. __flush_tlb_one(flush_va);
  676. } else
  677. voyager_leave_mm(cpu);
  678. }
  679. smp_mb__before_clear_bit();
  680. clear_bit(cpu, &smp_invalidate_needed);
  681. smp_mb__after_clear_bit();
  682. }
  683. /* All the new flush operations for 2.4 */
  684. /* This routine is called with a physical cpu mask */
  685. static void
  686. voyager_flush_tlb_others(unsigned long cpumask, struct mm_struct *mm,
  687. unsigned long va)
  688. {
  689. int stuck = 50000;
  690. if (!cpumask)
  691. BUG();
  692. if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
  693. BUG();
  694. if (cpumask & (1 << smp_processor_id()))
  695. BUG();
  696. if (!mm)
  697. BUG();
  698. spin_lock(&tlbstate_lock);
  699. flush_mm = mm;
  700. flush_va = va;
  701. atomic_set_mask(cpumask, &smp_invalidate_needed);
  702. /*
  703. * We have to send the CPI only to
  704. * CPUs affected.
  705. */
  706. send_CPI(cpumask, VIC_INVALIDATE_CPI);
  707. while (smp_invalidate_needed) {
  708. mb();
  709. if (--stuck == 0) {
  710. printk("***WARNING*** Stuck doing invalidate CPI "
  711. "(CPU%d)\n", smp_processor_id());
  712. break;
  713. }
  714. }
  715. /* Uncomment only to debug invalidation problems
  716. VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
  717. */
  718. flush_mm = NULL;
  719. flush_va = 0;
  720. spin_unlock(&tlbstate_lock);
  721. }
  722. void flush_tlb_current_task(void)
  723. {
  724. struct mm_struct *mm = current->mm;
  725. unsigned long cpu_mask;
  726. preempt_disable();
  727. cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
  728. local_flush_tlb();
  729. if (cpu_mask)
  730. voyager_flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
  731. preempt_enable();
  732. }
  733. void flush_tlb_mm(struct mm_struct *mm)
  734. {
  735. unsigned long cpu_mask;
  736. preempt_disable();
  737. cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
  738. if (current->active_mm == mm) {
  739. if (current->mm)
  740. local_flush_tlb();
  741. else
  742. voyager_leave_mm(smp_processor_id());
  743. }
  744. if (cpu_mask)
  745. voyager_flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
  746. preempt_enable();
  747. }
  748. void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
  749. {
  750. struct mm_struct *mm = vma->vm_mm;
  751. unsigned long cpu_mask;
  752. preempt_disable();
  753. cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
  754. if (current->active_mm == mm) {
  755. if (current->mm)
  756. __flush_tlb_one(va);
  757. else
  758. voyager_leave_mm(smp_processor_id());
  759. }
  760. if (cpu_mask)
  761. voyager_flush_tlb_others(cpu_mask, mm, va);
  762. preempt_enable();
  763. }
  764. EXPORT_SYMBOL(flush_tlb_page);
  765. /* enable the requested IRQs */
  766. static void smp_enable_irq_interrupt(void)
  767. {
  768. __u8 irq;
  769. __u8 cpu = get_cpu();
  770. VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
  771. vic_irq_enable_mask[cpu]));
  772. spin_lock(&vic_irq_lock);
  773. for (irq = 0; irq < 16; irq++) {
  774. if (vic_irq_enable_mask[cpu] & (1 << irq))
  775. enable_local_vic_irq(irq);
  776. }
  777. vic_irq_enable_mask[cpu] = 0;
  778. spin_unlock(&vic_irq_lock);
  779. put_cpu_no_resched();
  780. }
  781. /*
  782. * CPU halt call-back
  783. */
  784. static void smp_stop_cpu_function(void *dummy)
  785. {
  786. VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
  787. cpu_clear(smp_processor_id(), cpu_online_map);
  788. local_irq_disable();
  789. for (;;)
  790. halt();
  791. }
  792. /* execute a thread on a new CPU. The function to be called must be
  793. * previously set up. This is used to schedule a function for
  794. * execution on all CPUs - set up the function then broadcast a
  795. * function_interrupt CPI to come here on each CPU */
  796. static void smp_call_function_interrupt(void)
  797. {
  798. irq_enter();
  799. generic_smp_call_function_interrupt();
  800. __get_cpu_var(irq_stat).irq_call_count++;
  801. irq_exit();
  802. }
  803. static void smp_call_function_single_interrupt(void)
  804. {
  805. irq_enter();
  806. generic_smp_call_function_single_interrupt();
  807. __get_cpu_var(irq_stat).irq_call_count++;
  808. irq_exit();
  809. }
  810. /* Sorry about the name. In an APIC based system, the APICs
  811. * themselves are programmed to send a timer interrupt. This is used
  812. * by linux to reschedule the processor. Voyager doesn't have this,
  813. * so we use the system clock to interrupt one processor, which in
  814. * turn, broadcasts a timer CPI to all the others --- we receive that
  815. * CPI here. We don't use this actually for counting so losing
  816. * ticks doesn't matter
  817. *
  818. * FIXME: For those CPUs which actually have a local APIC, we could
  819. * try to use it to trigger this interrupt instead of having to
  820. * broadcast the timer tick. Unfortunately, all my pentium DYADs have
  821. * no local APIC, so I can't do this
  822. *
  823. * This function is currently a placeholder and is unused in the code */
  824. void smp_apic_timer_interrupt(struct pt_regs *regs)
  825. {
  826. struct pt_regs *old_regs = set_irq_regs(regs);
  827. wrapper_smp_local_timer_interrupt();
  828. set_irq_regs(old_regs);
  829. }
  830. /* All of the QUAD interrupt GATES */
  831. void smp_qic_timer_interrupt(struct pt_regs *regs)
  832. {
  833. struct pt_regs *old_regs = set_irq_regs(regs);
  834. ack_QIC_CPI(QIC_TIMER_CPI);
  835. wrapper_smp_local_timer_interrupt();
  836. set_irq_regs(old_regs);
  837. }
  838. void smp_qic_invalidate_interrupt(struct pt_regs *regs)
  839. {
  840. ack_QIC_CPI(QIC_INVALIDATE_CPI);
  841. smp_invalidate_interrupt();
  842. }
  843. void smp_qic_reschedule_interrupt(struct pt_regs *regs)
  844. {
  845. ack_QIC_CPI(QIC_RESCHEDULE_CPI);
  846. smp_reschedule_interrupt();
  847. }
  848. void smp_qic_enable_irq_interrupt(struct pt_regs *regs)
  849. {
  850. ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
  851. smp_enable_irq_interrupt();
  852. }
  853. void smp_qic_call_function_interrupt(struct pt_regs *regs)
  854. {
  855. ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
  856. smp_call_function_interrupt();
  857. }
  858. void smp_qic_call_function_single_interrupt(struct pt_regs *regs)
  859. {
  860. ack_QIC_CPI(QIC_CALL_FUNCTION_SINGLE_CPI);
  861. smp_call_function_single_interrupt();
  862. }
  863. void smp_vic_cpi_interrupt(struct pt_regs *regs)
  864. {
  865. struct pt_regs *old_regs = set_irq_regs(regs);
  866. __u8 cpu = smp_processor_id();
  867. if (is_cpu_quad())
  868. ack_QIC_CPI(VIC_CPI_LEVEL0);
  869. else
  870. ack_VIC_CPI(VIC_CPI_LEVEL0);
  871. if (test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
  872. wrapper_smp_local_timer_interrupt();
  873. if (test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
  874. smp_invalidate_interrupt();
  875. if (test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
  876. smp_reschedule_interrupt();
  877. if (test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
  878. smp_enable_irq_interrupt();
  879. if (test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
  880. smp_call_function_interrupt();
  881. if (test_and_clear_bit(VIC_CALL_FUNCTION_SINGLE_CPI, &vic_cpi_mailbox[cpu]))
  882. smp_call_function_single_interrupt();
  883. set_irq_regs(old_regs);
  884. }
  885. static void do_flush_tlb_all(void *info)
  886. {
  887. unsigned long cpu = smp_processor_id();
  888. __flush_tlb_all();
  889. if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
  890. voyager_leave_mm(cpu);
  891. }
  892. /* flush the TLB of every active CPU in the system */
  893. void flush_tlb_all(void)
  894. {
  895. on_each_cpu(do_flush_tlb_all, 0, 1);
  896. }
  897. /* send a reschedule CPI to one CPU by physical CPU number*/
  898. static void voyager_smp_send_reschedule(int cpu)
  899. {
  900. send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
  901. }
  902. int hard_smp_processor_id(void)
  903. {
  904. __u8 i;
  905. __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
  906. if ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
  907. return cpumask & 0x1F;
  908. for (i = 0; i < 8; i++) {
  909. if (cpumask & (1 << i))
  910. return i;
  911. }
  912. printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
  913. return 0;
  914. }
  915. int safe_smp_processor_id(void)
  916. {
  917. return hard_smp_processor_id();
  918. }
  919. /* broadcast a halt to all other CPUs */
  920. static void voyager_smp_send_stop(void)
  921. {
  922. smp_call_function(smp_stop_cpu_function, NULL, 1);
  923. }
  924. /* this function is triggered in time.c when a clock tick fires
  925. * we need to re-broadcast the tick to all CPUs */
  926. void smp_vic_timer_interrupt(void)
  927. {
  928. send_CPI_allbutself(VIC_TIMER_CPI);
  929. smp_local_timer_interrupt();
  930. }
  931. /* local (per CPU) timer interrupt. It does both profiling and
  932. * process statistics/rescheduling.
  933. *
  934. * We do profiling in every local tick, statistics/rescheduling
  935. * happen only every 'profiling multiplier' ticks. The default
  936. * multiplier is 1 and it can be changed by writing the new multiplier
  937. * value into /proc/profile.
  938. */
  939. void smp_local_timer_interrupt(void)
  940. {
  941. int cpu = smp_processor_id();
  942. long weight;
  943. profile_tick(CPU_PROFILING);
  944. if (--per_cpu(prof_counter, cpu) <= 0) {
  945. /*
  946. * The multiplier may have changed since the last time we got
  947. * to this point as a result of the user writing to
  948. * /proc/profile. In this case we need to adjust the APIC
  949. * timer accordingly.
  950. *
  951. * Interrupts are already masked off at this point.
  952. */
  953. per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
  954. if (per_cpu(prof_counter, cpu) !=
  955. per_cpu(prof_old_multiplier, cpu)) {
  956. /* FIXME: need to update the vic timer tick here */
  957. per_cpu(prof_old_multiplier, cpu) =
  958. per_cpu(prof_counter, cpu);
  959. }
  960. update_process_times(user_mode_vm(get_irq_regs()));
  961. }
  962. if (((1 << cpu) & voyager_extended_vic_processors) == 0)
  963. /* only extended VIC processors participate in
  964. * interrupt distribution */
  965. return;
  966. /*
  967. * We take the 'long' return path, and there every subsystem
  968. * grabs the appropriate locks (kernel lock/ irq lock).
  969. *
  970. * we might want to decouple profiling from the 'long path',
  971. * and do the profiling totally in assembly.
  972. *
  973. * Currently this isn't too much of an issue (performance wise),
  974. * we can take more than 100K local irqs per second on a 100 MHz P5.
  975. */
  976. if ((++vic_tick[cpu] & 0x7) != 0)
  977. return;
  978. /* get here every 16 ticks (about every 1/6 of a second) */
  979. /* Change our priority to give someone else a chance at getting
  980. * the IRQ. The algorithm goes like this:
  981. *
  982. * In the VIC, the dynamically routed interrupt is always
  983. * handled by the lowest priority eligible (i.e. receiving
  984. * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
  985. * lowest processor number gets it.
  986. *
  987. * The priority of a CPU is controlled by a special per-CPU
  988. * VIC priority register which is 3 bits wide 0 being lowest
  989. * and 7 highest priority..
  990. *
  991. * Therefore we subtract the average number of interrupts from
  992. * the number we've fielded. If this number is negative, we
  993. * lower the activity count and if it is positive, we raise
  994. * it.
  995. *
  996. * I'm afraid this still leads to odd looking interrupt counts:
  997. * the totals are all roughly equal, but the individual ones
  998. * look rather skewed.
  999. *
  1000. * FIXME: This algorithm is total crap when mixed with SMP
  1001. * affinity code since we now try to even up the interrupt
  1002. * counts when an affinity binding is keeping them on a
  1003. * particular CPU*/
  1004. weight = (vic_intr_count[cpu] * voyager_extended_cpus
  1005. - vic_intr_total) >> 4;
  1006. weight += 4;
  1007. if (weight > 7)
  1008. weight = 7;
  1009. if (weight < 0)
  1010. weight = 0;
  1011. outb((__u8) weight, VIC_PRIORITY_REGISTER);
  1012. #ifdef VOYAGER_DEBUG
  1013. if ((vic_tick[cpu] & 0xFFF) == 0) {
  1014. /* print this message roughly every 25 secs */
  1015. printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
  1016. cpu, vic_tick[cpu], weight);
  1017. }
  1018. #endif
  1019. }
  1020. /* setup the profiling timer */
  1021. int setup_profiling_timer(unsigned int multiplier)
  1022. {
  1023. int i;
  1024. if ((!multiplier))
  1025. return -EINVAL;
  1026. /*
  1027. * Set the new multiplier for each CPU. CPUs don't start using the
  1028. * new values until the next timer interrupt in which they do process
  1029. * accounting.
  1030. */
  1031. for (i = 0; i < nr_cpu_ids; ++i)
  1032. per_cpu(prof_multiplier, i) = multiplier;
  1033. return 0;
  1034. }
  1035. /* This is a bit of a mess, but forced on us by the genirq changes
  1036. * there's no genirq handler that really does what voyager wants
  1037. * so hack it up with the simple IRQ handler */
  1038. static void handle_vic_irq(unsigned int irq, struct irq_desc *desc)
  1039. {
  1040. before_handle_vic_irq(irq);
  1041. handle_simple_irq(irq, desc);
  1042. after_handle_vic_irq(irq);
  1043. }
  1044. /* The CPIs are handled in the per cpu 8259s, so they must be
  1045. * enabled to be received: FIX: enabling the CPIs in the early
  1046. * boot sequence interferes with bug checking; enable them later
  1047. * on in smp_init */
  1048. #define VIC_SET_GATE(cpi, vector) \
  1049. set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
  1050. #define QIC_SET_GATE(cpi, vector) \
  1051. set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
  1052. void __init voyager_smp_intr_init(void)
  1053. {
  1054. int i;
  1055. /* initialize the per cpu irq mask to all disabled */
  1056. for (i = 0; i < nr_cpu_ids; i++)
  1057. vic_irq_mask[i] = 0xFFFF;
  1058. VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
  1059. VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
  1060. VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
  1061. QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
  1062. QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
  1063. QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
  1064. QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
  1065. QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
  1066. /* now put the VIC descriptor into the first 48 IRQs
  1067. *
  1068. * This is for later: first 16 correspond to PC IRQs; next 16
  1069. * are Primary MC IRQs and final 16 are Secondary MC IRQs */
  1070. for (i = 0; i < 48; i++)
  1071. set_irq_chip_and_handler(i, &vic_chip, handle_vic_irq);
  1072. }
  1073. /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
  1074. * processor to receive CPI */
  1075. static void send_CPI(__u32 cpuset, __u8 cpi)
  1076. {
  1077. int cpu;
  1078. __u32 quad_cpuset = (cpuset & voyager_quad_processors);
  1079. if (cpi < VIC_START_FAKE_CPI) {
  1080. /* fake CPI are only used for booting, so send to the
  1081. * extended quads as well---Quads must be VIC booted */
  1082. outb((__u8) (cpuset), VIC_CPI_Registers[cpi]);
  1083. return;
  1084. }
  1085. if (quad_cpuset)
  1086. send_QIC_CPI(quad_cpuset, cpi);
  1087. cpuset &= ~quad_cpuset;
  1088. cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
  1089. if (cpuset == 0)
  1090. return;
  1091. for_each_online_cpu(cpu) {
  1092. if (cpuset & (1 << cpu))
  1093. set_bit(cpi, &vic_cpi_mailbox[cpu]);
  1094. }
  1095. if (cpuset)
  1096. outb((__u8) cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
  1097. }
  1098. /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
  1099. * set the cache line to shared by reading it.
  1100. *
  1101. * DON'T make this inline otherwise the cache line read will be
  1102. * optimised away
  1103. * */
  1104. static int ack_QIC_CPI(__u8 cpi)
  1105. {
  1106. __u8 cpu = hard_smp_processor_id();
  1107. cpi &= 7;
  1108. outb(1 << cpi, QIC_INTERRUPT_CLEAR1);
  1109. return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
  1110. }
  1111. static void ack_special_QIC_CPI(__u8 cpi)
  1112. {
  1113. switch (cpi) {
  1114. case VIC_CMN_INT:
  1115. outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
  1116. break;
  1117. case VIC_SYS_INT:
  1118. outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
  1119. break;
  1120. }
  1121. /* also clear at the VIC, just in case (nop for non-extended proc) */
  1122. ack_VIC_CPI(cpi);
  1123. }
  1124. /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
  1125. static void ack_VIC_CPI(__u8 cpi)
  1126. {
  1127. #ifdef VOYAGER_DEBUG
  1128. unsigned long flags;
  1129. __u16 isr;
  1130. __u8 cpu = smp_processor_id();
  1131. local_irq_save(flags);
  1132. isr = vic_read_isr();
  1133. if ((isr & (1 << (cpi & 7))) == 0) {
  1134. printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
  1135. }
  1136. #endif
  1137. /* send specific EOI; the two system interrupts have
  1138. * bit 4 set for a separate vector but behave as the
  1139. * corresponding 3 bit intr */
  1140. outb_p(0x60 | (cpi & 7), 0x20);
  1141. #ifdef VOYAGER_DEBUG
  1142. if ((vic_read_isr() & (1 << (cpi & 7))) != 0) {
  1143. printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
  1144. }
  1145. local_irq_restore(flags);
  1146. #endif
  1147. }
  1148. /* cribbed with thanks from irq.c */
  1149. #define __byte(x,y) (((unsigned char *)&(y))[x])
  1150. #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
  1151. #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
  1152. static unsigned int startup_vic_irq(unsigned int irq)
  1153. {
  1154. unmask_vic_irq(irq);
  1155. return 0;
  1156. }
  1157. /* The enable and disable routines. This is where we run into
  1158. * conflicting architectural philosophy. Fundamentally, the voyager
  1159. * architecture does not expect to have to disable interrupts globally
  1160. * (the IRQ controllers belong to each CPU). The processor masquerade
  1161. * which is used to start the system shouldn't be used in a running OS
  1162. * since it will cause great confusion if two separate CPUs drive to
  1163. * the same IRQ controller (I know, I've tried it).
  1164. *
  1165. * The solution is a variant on the NCR lazy SPL design:
  1166. *
  1167. * 1) To disable an interrupt, do nothing (other than set the
  1168. * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
  1169. *
  1170. * 2) If the interrupt dares to come in, raise the local mask against
  1171. * it (this will result in all the CPU masks being raised
  1172. * eventually).
  1173. *
  1174. * 3) To enable the interrupt, lower the mask on the local CPU and
  1175. * broadcast an Interrupt enable CPI which causes all other CPUs to
  1176. * adjust their masks accordingly. */
  1177. static void unmask_vic_irq(unsigned int irq)
  1178. {
  1179. /* linux doesn't to processor-irq affinity, so enable on
  1180. * all CPUs we know about */
  1181. int cpu = smp_processor_id(), real_cpu;
  1182. __u16 mask = (1 << irq);
  1183. __u32 processorList = 0;
  1184. unsigned long flags;
  1185. VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
  1186. irq, cpu, cpu_irq_affinity[cpu]));
  1187. spin_lock_irqsave(&vic_irq_lock, flags);
  1188. for_each_online_cpu(real_cpu) {
  1189. if (!(voyager_extended_vic_processors & (1 << real_cpu)))
  1190. continue;
  1191. if (!(cpu_irq_affinity[real_cpu] & mask)) {
  1192. /* irq has no affinity for this CPU, ignore */
  1193. continue;
  1194. }
  1195. if (real_cpu == cpu) {
  1196. enable_local_vic_irq(irq);
  1197. } else if (vic_irq_mask[real_cpu] & mask) {
  1198. vic_irq_enable_mask[real_cpu] |= mask;
  1199. processorList |= (1 << real_cpu);
  1200. }
  1201. }
  1202. spin_unlock_irqrestore(&vic_irq_lock, flags);
  1203. if (processorList)
  1204. send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
  1205. }
  1206. static void mask_vic_irq(unsigned int irq)
  1207. {
  1208. /* lazy disable, do nothing */
  1209. }
  1210. static void enable_local_vic_irq(unsigned int irq)
  1211. {
  1212. __u8 cpu = smp_processor_id();
  1213. __u16 mask = ~(1 << irq);
  1214. __u16 old_mask = vic_irq_mask[cpu];
  1215. vic_irq_mask[cpu] &= mask;
  1216. if (vic_irq_mask[cpu] == old_mask)
  1217. return;
  1218. VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
  1219. irq, cpu));
  1220. if (irq & 8) {
  1221. outb_p(cached_A1(cpu), 0xA1);
  1222. (void)inb_p(0xA1);
  1223. } else {
  1224. outb_p(cached_21(cpu), 0x21);
  1225. (void)inb_p(0x21);
  1226. }
  1227. }
  1228. static void disable_local_vic_irq(unsigned int irq)
  1229. {
  1230. __u8 cpu = smp_processor_id();
  1231. __u16 mask = (1 << irq);
  1232. __u16 old_mask = vic_irq_mask[cpu];
  1233. if (irq == 7)
  1234. return;
  1235. vic_irq_mask[cpu] |= mask;
  1236. if (old_mask == vic_irq_mask[cpu])
  1237. return;
  1238. VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
  1239. irq, cpu));
  1240. if (irq & 8) {
  1241. outb_p(cached_A1(cpu), 0xA1);
  1242. (void)inb_p(0xA1);
  1243. } else {
  1244. outb_p(cached_21(cpu), 0x21);
  1245. (void)inb_p(0x21);
  1246. }
  1247. }
  1248. /* The VIC is level triggered, so the ack can only be issued after the
  1249. * interrupt completes. However, we do Voyager lazy interrupt
  1250. * handling here: It is an extremely expensive operation to mask an
  1251. * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
  1252. * this interrupt actually comes in, then we mask and ack here to push
  1253. * the interrupt off to another CPU */
  1254. static void before_handle_vic_irq(unsigned int irq)
  1255. {
  1256. irq_desc_t *desc = irq_to_desc(irq);
  1257. __u8 cpu = smp_processor_id();
  1258. _raw_spin_lock(&vic_irq_lock);
  1259. vic_intr_total++;
  1260. vic_intr_count[cpu]++;
  1261. if (!(cpu_irq_affinity[cpu] & (1 << irq))) {
  1262. /* The irq is not in our affinity mask, push it off
  1263. * onto another CPU */
  1264. VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d "
  1265. "on cpu %d\n", irq, cpu));
  1266. disable_local_vic_irq(irq);
  1267. /* set IRQ_INPROGRESS to prevent the handler in irq.c from
  1268. * actually calling the interrupt routine */
  1269. desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
  1270. } else if (desc->status & IRQ_DISABLED) {
  1271. /* Damn, the interrupt actually arrived, do the lazy
  1272. * disable thing. The interrupt routine in irq.c will
  1273. * not handle a IRQ_DISABLED interrupt, so nothing more
  1274. * need be done here */
  1275. VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
  1276. irq, cpu));
  1277. disable_local_vic_irq(irq);
  1278. desc->status |= IRQ_REPLAY;
  1279. } else {
  1280. desc->status &= ~IRQ_REPLAY;
  1281. }
  1282. _raw_spin_unlock(&vic_irq_lock);
  1283. }
  1284. /* Finish the VIC interrupt: basically mask */
  1285. static void after_handle_vic_irq(unsigned int irq)
  1286. {
  1287. irq_desc_t *desc = irq_to_desc(irq);
  1288. _raw_spin_lock(&vic_irq_lock);
  1289. {
  1290. unsigned int status = desc->status & ~IRQ_INPROGRESS;
  1291. #ifdef VOYAGER_DEBUG
  1292. __u16 isr;
  1293. #endif
  1294. desc->status = status;
  1295. if ((status & IRQ_DISABLED))
  1296. disable_local_vic_irq(irq);
  1297. #ifdef VOYAGER_DEBUG
  1298. /* DEBUG: before we ack, check what's in progress */
  1299. isr = vic_read_isr();
  1300. if ((isr & (1 << irq) && !(status & IRQ_REPLAY)) == 0) {
  1301. int i;
  1302. __u8 cpu = smp_processor_id();
  1303. __u8 real_cpu;
  1304. int mask; /* Um... initialize me??? --RR */
  1305. printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
  1306. cpu, irq);
  1307. for_each_possible_cpu(real_cpu, mask) {
  1308. outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
  1309. VIC_PROCESSOR_ID);
  1310. isr = vic_read_isr();
  1311. if (isr & (1 << irq)) {
  1312. printk
  1313. ("VOYAGER SMP: CPU%d ack irq %d\n",
  1314. real_cpu, irq);
  1315. ack_vic_irq(irq);
  1316. }
  1317. outb(cpu, VIC_PROCESSOR_ID);
  1318. }
  1319. }
  1320. #endif /* VOYAGER_DEBUG */
  1321. /* as soon as we ack, the interrupt is eligible for
  1322. * receipt by another CPU so everything must be in
  1323. * order here */
  1324. ack_vic_irq(irq);
  1325. if (status & IRQ_REPLAY) {
  1326. /* replay is set if we disable the interrupt
  1327. * in the before_handle_vic_irq() routine, so
  1328. * clear the in progress bit here to allow the
  1329. * next CPU to handle this correctly */
  1330. desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
  1331. }
  1332. #ifdef VOYAGER_DEBUG
  1333. isr = vic_read_isr();
  1334. if ((isr & (1 << irq)) != 0)
  1335. printk("VOYAGER SMP: after_handle_vic_irq() after "
  1336. "ack irq=%d, isr=0x%x\n", irq, isr);
  1337. #endif /* VOYAGER_DEBUG */
  1338. }
  1339. _raw_spin_unlock(&vic_irq_lock);
  1340. /* All code after this point is out of the main path - the IRQ
  1341. * may be intercepted by another CPU if reasserted */
  1342. }
  1343. /* Linux processor - interrupt affinity manipulations.
  1344. *
  1345. * For each processor, we maintain a 32 bit irq affinity mask.
  1346. * Initially it is set to all 1's so every processor accepts every
  1347. * interrupt. In this call, we change the processor's affinity mask:
  1348. *
  1349. * Change from enable to disable:
  1350. *
  1351. * If the interrupt ever comes in to the processor, we will disable it
  1352. * and ack it to push it off to another CPU, so just accept the mask here.
  1353. *
  1354. * Change from disable to enable:
  1355. *
  1356. * change the mask and then do an interrupt enable CPI to re-enable on
  1357. * the selected processors */
  1358. void set_vic_irq_affinity(unsigned int irq, const struct cpumask *mask)
  1359. {
  1360. /* Only extended processors handle interrupts */
  1361. unsigned long real_mask;
  1362. unsigned long irq_mask = 1 << irq;
  1363. int cpu;
  1364. real_mask = cpus_addr(*mask)[0] & voyager_extended_vic_processors;
  1365. if (cpus_addr(*mask)[0] == 0)
  1366. /* can't have no CPUs to accept the interrupt -- extremely
  1367. * bad things will happen */
  1368. return;
  1369. if (irq == 0)
  1370. /* can't change the affinity of the timer IRQ. This
  1371. * is due to the constraint in the voyager
  1372. * architecture that the CPI also comes in on and IRQ
  1373. * line and we have chosen IRQ0 for this. If you
  1374. * raise the mask on this interrupt, the processor
  1375. * will no-longer be able to accept VIC CPIs */
  1376. return;
  1377. if (irq >= 32)
  1378. /* You can only have 32 interrupts in a voyager system
  1379. * (and 32 only if you have a secondary microchannel
  1380. * bus) */
  1381. return;
  1382. for_each_online_cpu(cpu) {
  1383. unsigned long cpu_mask = 1 << cpu;
  1384. if (cpu_mask & real_mask) {
  1385. /* enable the interrupt for this cpu */
  1386. cpu_irq_affinity[cpu] |= irq_mask;
  1387. } else {
  1388. /* disable the interrupt for this cpu */
  1389. cpu_irq_affinity[cpu] &= ~irq_mask;
  1390. }
  1391. }
  1392. /* this is magic, we now have the correct affinity maps, so
  1393. * enable the interrupt. This will send an enable CPI to
  1394. * those CPUs who need to enable it in their local masks,
  1395. * causing them to correct for the new affinity . If the
  1396. * interrupt is currently globally disabled, it will simply be
  1397. * disabled again as it comes in (voyager lazy disable). If
  1398. * the affinity map is tightened to disable the interrupt on a
  1399. * cpu, it will be pushed off when it comes in */
  1400. unmask_vic_irq(irq);
  1401. }
  1402. static void ack_vic_irq(unsigned int irq)
  1403. {
  1404. if (irq & 8) {
  1405. outb(0x62, 0x20); /* Specific EOI to cascade */
  1406. outb(0x60 | (irq & 7), 0xA0);
  1407. } else {
  1408. outb(0x60 | (irq & 7), 0x20);
  1409. }
  1410. }
  1411. /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
  1412. * but are not vectored by it. This means that the 8259 mask must be
  1413. * lowered to receive them */
  1414. static __init void vic_enable_cpi(void)
  1415. {
  1416. __u8 cpu = smp_processor_id();
  1417. /* just take a copy of the current mask (nop for boot cpu) */
  1418. vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
  1419. enable_local_vic_irq(VIC_CPI_LEVEL0);
  1420. enable_local_vic_irq(VIC_CPI_LEVEL1);
  1421. /* for sys int and cmn int */
  1422. enable_local_vic_irq(7);
  1423. if (is_cpu_quad()) {
  1424. outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
  1425. outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
  1426. VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
  1427. cpu, QIC_CPI_ENABLE));
  1428. }
  1429. VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
  1430. cpu, vic_irq_mask[cpu]));
  1431. }
  1432. void voyager_smp_dump()
  1433. {
  1434. int old_cpu = smp_processor_id(), cpu;
  1435. /* dump the interrupt masks of each processor */
  1436. for_each_online_cpu(cpu) {
  1437. __u16 imr, isr, irr;
  1438. unsigned long flags;
  1439. local_irq_save(flags);
  1440. outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
  1441. imr = (inb(0xa1) << 8) | inb(0x21);
  1442. outb(0x0a, 0xa0);
  1443. irr = inb(0xa0) << 8;
  1444. outb(0x0a, 0x20);
  1445. irr |= inb(0x20);
  1446. outb(0x0b, 0xa0);
  1447. isr = inb(0xa0) << 8;
  1448. outb(0x0b, 0x20);
  1449. isr |= inb(0x20);
  1450. outb(old_cpu, VIC_PROCESSOR_ID);
  1451. local_irq_restore(flags);
  1452. printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
  1453. cpu, vic_irq_mask[cpu], imr, irr, isr);
  1454. #if 0
  1455. /* These lines are put in to try to unstick an un ack'd irq */
  1456. if (isr != 0) {
  1457. int irq;
  1458. for (irq = 0; irq < 16; irq++) {
  1459. if (isr & (1 << irq)) {
  1460. printk("\tCPU%d: ack irq %d\n",
  1461. cpu, irq);
  1462. local_irq_save(flags);
  1463. outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
  1464. VIC_PROCESSOR_ID);
  1465. ack_vic_irq(irq);
  1466. outb(old_cpu, VIC_PROCESSOR_ID);
  1467. local_irq_restore(flags);
  1468. }
  1469. }
  1470. }
  1471. #endif
  1472. }
  1473. }
  1474. void smp_voyager_power_off(void *dummy)
  1475. {
  1476. if (smp_processor_id() == boot_cpu_id)
  1477. voyager_power_off();
  1478. else
  1479. smp_stop_cpu_function(NULL);
  1480. }
  1481. static void __init voyager_smp_prepare_cpus(unsigned int max_cpus)
  1482. {
  1483. /* FIXME: ignore max_cpus for now */
  1484. smp_boot_cpus();
  1485. }
  1486. static void __cpuinit voyager_smp_prepare_boot_cpu(void)
  1487. {
  1488. init_gdt(smp_processor_id());
  1489. switch_to_new_gdt();
  1490. cpu_online_map = cpumask_of_cpu(smp_processor_id());
  1491. cpu_callout_map = cpumask_of_cpu(smp_processor_id());
  1492. cpu_callin_map = CPU_MASK_NONE;
  1493. cpu_present_map = cpumask_of_cpu(smp_processor_id());
  1494. }
  1495. static int __cpuinit voyager_cpu_up(unsigned int cpu)
  1496. {
  1497. /* This only works at boot for x86. See "rewrite" above. */
  1498. if (cpu_isset(cpu, smp_commenced_mask))
  1499. return -ENOSYS;
  1500. /* In case one didn't come up */
  1501. if (!cpu_isset(cpu, cpu_callin_map))
  1502. return -EIO;
  1503. /* Unleash the CPU! */
  1504. cpu_set(cpu, smp_commenced_mask);
  1505. while (!cpu_online(cpu))
  1506. mb();
  1507. return 0;
  1508. }
  1509. static void __init voyager_smp_cpus_done(unsigned int max_cpus)
  1510. {
  1511. zap_low_mappings();
  1512. }
  1513. void __init smp_setup_processor_id(void)
  1514. {
  1515. current_thread_info()->cpu = hard_smp_processor_id();
  1516. x86_write_percpu(cpu_number, hard_smp_processor_id());
  1517. }
  1518. static void voyager_send_call_func(const struct cpumask *callmask)
  1519. {
  1520. __u32 mask = cpus_addr(*callmask)[0] & ~(1 << smp_processor_id());
  1521. send_CPI(mask, VIC_CALL_FUNCTION_CPI);
  1522. }
  1523. static void voyager_send_call_func_single(int cpu)
  1524. {
  1525. send_CPI(1 << cpu, VIC_CALL_FUNCTION_SINGLE_CPI);
  1526. }
  1527. struct smp_ops smp_ops = {
  1528. .smp_prepare_boot_cpu = voyager_smp_prepare_boot_cpu,
  1529. .smp_prepare_cpus = voyager_smp_prepare_cpus,
  1530. .cpu_up = voyager_cpu_up,
  1531. .smp_cpus_done = voyager_smp_cpus_done,
  1532. .smp_send_stop = voyager_smp_send_stop,
  1533. .smp_send_reschedule = voyager_smp_send_reschedule,
  1534. .send_call_func_ipi = voyager_send_call_func,
  1535. .send_call_func_single_ipi = voyager_send_call_func_single,
  1536. };