i2c.c 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165
  1. /*
  2. * linux/arch/arm/plat-omap/i2c.c
  3. *
  4. * Helper module for board specific I2C bus registration
  5. *
  6. * Copyright (C) 2007 Nokia Corporation.
  7. *
  8. * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License
  12. * version 2 as published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but
  15. * WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  22. * 02110-1301 USA
  23. *
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/i2c.h>
  28. #include <mach/irqs.h>
  29. #include <mach/mux.h>
  30. #define OMAP_I2C_SIZE 0x3f
  31. #define OMAP1_I2C_BASE 0xfffb3800
  32. #define OMAP2_I2C_BASE1 0x48070000
  33. #define OMAP2_I2C_BASE2 0x48072000
  34. #define OMAP2_I2C_BASE3 0x48060000
  35. static const char name[] = "i2c_omap";
  36. #define I2C_RESOURCE_BUILDER(base, irq) \
  37. { \
  38. .start = (base), \
  39. .end = (base) + OMAP_I2C_SIZE, \
  40. .flags = IORESOURCE_MEM, \
  41. }, \
  42. { \
  43. .start = (irq), \
  44. .flags = IORESOURCE_IRQ, \
  45. },
  46. static struct resource i2c_resources[][2] = {
  47. { I2C_RESOURCE_BUILDER(0, 0) },
  48. #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  49. { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) },
  50. #endif
  51. #if defined(CONFIG_ARCH_OMAP34XX)
  52. { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) },
  53. #endif
  54. };
  55. #define I2C_DEV_BUILDER(bus_id, res, data) \
  56. { \
  57. .id = (bus_id), \
  58. .name = name, \
  59. .num_resources = ARRAY_SIZE(res), \
  60. .resource = (res), \
  61. .dev = { \
  62. .platform_data = (data), \
  63. }, \
  64. }
  65. static u32 i2c_rate[ARRAY_SIZE(i2c_resources)];
  66. static struct platform_device omap_i2c_devices[] = {
  67. I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]),
  68. #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  69. I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]),
  70. #endif
  71. #if defined(CONFIG_ARCH_OMAP34XX)
  72. I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]),
  73. #endif
  74. };
  75. #if defined(CONFIG_ARCH_OMAP24XX)
  76. static const int omap24xx_pins[][2] = {
  77. { M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
  78. { J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
  79. };
  80. #else
  81. static const int omap24xx_pins[][2] = {};
  82. #endif
  83. #if defined(CONFIG_ARCH_OMAP34XX)
  84. static const int omap34xx_pins[][2] = {
  85. { K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA},
  86. { AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA},
  87. { AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA},
  88. };
  89. #else
  90. static const int omap34xx_pins[][2] = {};
  91. #endif
  92. static void __init omap_i2c_mux_pins(int bus)
  93. {
  94. int scl, sda;
  95. if (cpu_class_is_omap1()) {
  96. scl = I2C_SCL;
  97. sda = I2C_SDA;
  98. } else if (cpu_is_omap24xx()) {
  99. scl = omap24xx_pins[bus][0];
  100. sda = omap24xx_pins[bus][1];
  101. } else if (cpu_is_omap34xx()) {
  102. scl = omap34xx_pins[bus][0];
  103. sda = omap34xx_pins[bus][1];
  104. } else {
  105. return;
  106. }
  107. omap_cfg_reg(sda);
  108. omap_cfg_reg(scl);
  109. }
  110. int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
  111. struct i2c_board_info const *info,
  112. unsigned len)
  113. {
  114. int ports, err;
  115. struct platform_device *pdev;
  116. struct resource *res;
  117. resource_size_t base, irq;
  118. if (cpu_class_is_omap1())
  119. ports = 1;
  120. else if (cpu_is_omap24xx())
  121. ports = 2;
  122. else if (cpu_is_omap34xx())
  123. ports = 3;
  124. BUG_ON(bus_id < 1 || bus_id > ports);
  125. if (info) {
  126. err = i2c_register_board_info(bus_id, info, len);
  127. if (err)
  128. return err;
  129. }
  130. pdev = &omap_i2c_devices[bus_id - 1];
  131. *(u32 *)pdev->dev.platform_data = clkrate;
  132. if (bus_id == 1) {
  133. res = pdev->resource;
  134. if (cpu_class_is_omap1()) {
  135. base = OMAP1_I2C_BASE;
  136. irq = INT_I2C;
  137. } else {
  138. base = OMAP2_I2C_BASE1;
  139. irq = INT_24XX_I2C1_IRQ;
  140. }
  141. res[0].start = base;
  142. res[0].end = base + OMAP_I2C_SIZE;
  143. res[1].start = irq;
  144. }
  145. omap_i2c_mux_pins(bus_id - 1);
  146. return platform_device_register(pdev);
  147. }