devices.c 6.1 KB

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  1. /*
  2. * Author: MontaVista Software, Inc.
  3. * <source@mvista.com>
  4. *
  5. * Based on the OMAP devices.c
  6. *
  7. * 2005 (c) MontaVista Software, Inc. This file is licensed under the
  8. * terms of the GNU General Public License version 2. This program is
  9. * licensed "as is" without any warranty of any kind, whether express
  10. * or implied.
  11. *
  12. * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  13. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License
  17. * as published by the Free Software Foundation; either version 2
  18. * of the License, or (at your option) any later version.
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  27. * MA 02110-1301, USA.
  28. */
  29. #include <linux/module.h>
  30. #include <linux/kernel.h>
  31. #include <linux/init.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/gpio.h>
  34. #include <mach/irqs.h>
  35. #include <mach/hardware.h>
  36. /*
  37. * Resource definition for the MXC IrDA
  38. */
  39. static struct resource mxc_irda_resources[] = {
  40. [0] = {
  41. .start = UART3_BASE_ADDR,
  42. .end = UART3_BASE_ADDR + SZ_4K - 1,
  43. .flags = IORESOURCE_MEM,
  44. },
  45. [1] = {
  46. .start = MXC_INT_UART3,
  47. .end = MXC_INT_UART3,
  48. .flags = IORESOURCE_IRQ,
  49. },
  50. };
  51. /* Platform Data for MXC IrDA */
  52. struct platform_device mxc_irda_device = {
  53. .name = "mxc_irda",
  54. .id = 0,
  55. .num_resources = ARRAY_SIZE(mxc_irda_resources),
  56. .resource = mxc_irda_resources,
  57. };
  58. /*
  59. * General Purpose Timer
  60. * - i.MX1: 2 timer (slighly different register handling)
  61. * - i.MX21: 3 timer
  62. * - i.MX27: 6 timer
  63. */
  64. /* We use gpt0 as system timer, so do not add a device for this one */
  65. static struct resource timer1_resources[] = {
  66. [0] = {
  67. .start = GPT2_BASE_ADDR,
  68. .end = GPT2_BASE_ADDR + 0x17,
  69. .flags = IORESOURCE_MEM
  70. },
  71. [1] = {
  72. .start = MXC_INT_GPT2,
  73. .end = MXC_INT_GPT2,
  74. .flags = IORESOURCE_IRQ,
  75. }
  76. };
  77. struct platform_device mxc_gpt1 = {
  78. .name = "imx_gpt",
  79. .id = 1,
  80. .num_resources = ARRAY_SIZE(timer1_resources),
  81. .resource = timer1_resources
  82. };
  83. static struct resource timer2_resources[] = {
  84. [0] = {
  85. .start = GPT3_BASE_ADDR,
  86. .end = GPT3_BASE_ADDR + 0x17,
  87. .flags = IORESOURCE_MEM
  88. },
  89. [1] = {
  90. .start = MXC_INT_GPT3,
  91. .end = MXC_INT_GPT3,
  92. .flags = IORESOURCE_IRQ,
  93. }
  94. };
  95. struct platform_device mxc_gpt2 = {
  96. .name = "imx_gpt",
  97. .id = 2,
  98. .num_resources = ARRAY_SIZE(timer2_resources),
  99. .resource = timer2_resources
  100. };
  101. #ifdef CONFIG_MACH_MX27
  102. static struct resource timer3_resources[] = {
  103. [0] = {
  104. .start = GPT4_BASE_ADDR,
  105. .end = GPT4_BASE_ADDR + 0x17,
  106. .flags = IORESOURCE_MEM
  107. },
  108. [1] = {
  109. .start = MXC_INT_GPT4,
  110. .end = MXC_INT_GPT4,
  111. .flags = IORESOURCE_IRQ,
  112. }
  113. };
  114. struct platform_device mxc_gpt3 = {
  115. .name = "imx_gpt",
  116. .id = 3,
  117. .num_resources = ARRAY_SIZE(timer3_resources),
  118. .resource = timer3_resources
  119. };
  120. static struct resource timer4_resources[] = {
  121. [0] = {
  122. .start = GPT5_BASE_ADDR,
  123. .end = GPT5_BASE_ADDR + 0x17,
  124. .flags = IORESOURCE_MEM
  125. },
  126. [1] = {
  127. .start = MXC_INT_GPT5,
  128. .end = MXC_INT_GPT5,
  129. .flags = IORESOURCE_IRQ,
  130. }
  131. };
  132. struct platform_device mxc_gpt4 = {
  133. .name = "imx_gpt",
  134. .id = 4,
  135. .num_resources = ARRAY_SIZE(timer4_resources),
  136. .resource = timer4_resources
  137. };
  138. static struct resource timer5_resources[] = {
  139. [0] = {
  140. .start = GPT6_BASE_ADDR,
  141. .end = GPT6_BASE_ADDR + 0x17,
  142. .flags = IORESOURCE_MEM
  143. },
  144. [1] = {
  145. .start = MXC_INT_GPT6,
  146. .end = MXC_INT_GPT6,
  147. .flags = IORESOURCE_IRQ,
  148. }
  149. };
  150. struct platform_device mxc_gpt5 = {
  151. .name = "imx_gpt",
  152. .id = 5,
  153. .num_resources = ARRAY_SIZE(timer5_resources),
  154. .resource = timer5_resources
  155. };
  156. #endif
  157. /*
  158. * Watchdog:
  159. * - i.MX1
  160. * - i.MX21
  161. * - i.MX27
  162. */
  163. static struct resource mxc_wdt_resources[] = {
  164. {
  165. .start = WDOG_BASE_ADDR,
  166. .end = WDOG_BASE_ADDR + 0x30,
  167. .flags = IORESOURCE_MEM,
  168. },
  169. };
  170. struct platform_device mxc_wdt = {
  171. .name = "mxc_wdt",
  172. .id = 0,
  173. .num_resources = ARRAY_SIZE(mxc_wdt_resources),
  174. .resource = mxc_wdt_resources,
  175. };
  176. static struct resource mxc_w1_master_resources[] = {
  177. {
  178. .start = OWIRE_BASE_ADDR,
  179. .end = OWIRE_BASE_ADDR + SZ_4K - 1,
  180. .flags = IORESOURCE_MEM,
  181. },
  182. };
  183. struct platform_device mxc_w1_master_device = {
  184. .name = "mxc_w1",
  185. .id = 0,
  186. .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
  187. .resource = mxc_w1_master_resources,
  188. };
  189. static struct resource mxc_nand_resources[] = {
  190. {
  191. .start = NFC_BASE_ADDR,
  192. .end = NFC_BASE_ADDR + 0xfff,
  193. .flags = IORESOURCE_MEM
  194. }, {
  195. .start = MXC_INT_NANDFC,
  196. .end = MXC_INT_NANDFC,
  197. .flags = IORESOURCE_IRQ
  198. },
  199. };
  200. struct platform_device mxc_nand_device = {
  201. .name = "mxc_nand",
  202. .id = 0,
  203. .num_resources = ARRAY_SIZE(mxc_nand_resources),
  204. .resource = mxc_nand_resources,
  205. };
  206. /* GPIO port description */
  207. static struct mxc_gpio_port imx_gpio_ports[] = {
  208. [0] = {
  209. .chip.label = "gpio-0",
  210. .irq = MXC_INT_GPIO,
  211. .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0),
  212. .virtual_irq_start = MXC_GPIO_IRQ_START,
  213. },
  214. [1] = {
  215. .chip.label = "gpio-1",
  216. .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1),
  217. .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
  218. },
  219. [2] = {
  220. .chip.label = "gpio-2",
  221. .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2),
  222. .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
  223. },
  224. [3] = {
  225. .chip.label = "gpio-3",
  226. .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3),
  227. .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
  228. },
  229. [4] = {
  230. .chip.label = "gpio-4",
  231. .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4),
  232. .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
  233. },
  234. [5] = {
  235. .chip.label = "gpio-5",
  236. .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5),
  237. .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
  238. }
  239. };
  240. int __init mxc_register_gpios(void)
  241. {
  242. return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
  243. }