main.c 50 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. #include "btcoex.h"
  19. static void ath_cache_conf_rate(struct ath_softc *sc,
  20. struct ieee80211_conf *conf)
  21. {
  22. switch (conf->channel->band) {
  23. case IEEE80211_BAND_2GHZ:
  24. if (conf_is_ht20(conf))
  25. sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
  26. else if (conf_is_ht40_minus(conf))
  27. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
  28. else if (conf_is_ht40_plus(conf))
  29. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
  30. else
  31. sc->cur_rate_mode = ATH9K_MODE_11G;
  32. break;
  33. case IEEE80211_BAND_5GHZ:
  34. if (conf_is_ht20(conf))
  35. sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
  36. else if (conf_is_ht40_minus(conf))
  37. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
  38. else if (conf_is_ht40_plus(conf))
  39. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
  40. else
  41. sc->cur_rate_mode = ATH9K_MODE_11A;
  42. break;
  43. default:
  44. BUG_ON(1);
  45. break;
  46. }
  47. }
  48. static void ath_update_txpow(struct ath_softc *sc)
  49. {
  50. struct ath_hw *ah = sc->sc_ah;
  51. u32 txpow;
  52. if (sc->curtxpow != sc->config.txpowlimit) {
  53. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
  54. /* read back in case value is clamped */
  55. ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
  56. sc->curtxpow = txpow;
  57. }
  58. }
  59. static u8 parse_mpdudensity(u8 mpdudensity)
  60. {
  61. /*
  62. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  63. * 0 for no restriction
  64. * 1 for 1/4 us
  65. * 2 for 1/2 us
  66. * 3 for 1 us
  67. * 4 for 2 us
  68. * 5 for 4 us
  69. * 6 for 8 us
  70. * 7 for 16 us
  71. */
  72. switch (mpdudensity) {
  73. case 0:
  74. return 0;
  75. case 1:
  76. case 2:
  77. case 3:
  78. /* Our lower layer calculations limit our precision to
  79. 1 microsecond */
  80. return 1;
  81. case 4:
  82. return 2;
  83. case 5:
  84. return 4;
  85. case 6:
  86. return 8;
  87. case 7:
  88. return 16;
  89. default:
  90. return 0;
  91. }
  92. }
  93. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  94. struct ieee80211_hw *hw)
  95. {
  96. struct ieee80211_channel *curchan = hw->conf.channel;
  97. struct ath9k_channel *channel;
  98. u8 chan_idx;
  99. chan_idx = curchan->hw_value;
  100. channel = &sc->sc_ah->channels[chan_idx];
  101. ath9k_update_ichannel(sc, hw, channel);
  102. return channel;
  103. }
  104. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  105. {
  106. unsigned long flags;
  107. bool ret;
  108. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  109. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  110. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  111. return ret;
  112. }
  113. void ath9k_ps_wakeup(struct ath_softc *sc)
  114. {
  115. unsigned long flags;
  116. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  117. if (++sc->ps_usecount != 1)
  118. goto unlock;
  119. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  120. unlock:
  121. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  122. }
  123. void ath9k_ps_restore(struct ath_softc *sc)
  124. {
  125. unsigned long flags;
  126. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  127. if (--sc->ps_usecount != 0)
  128. goto unlock;
  129. if (sc->ps_idle)
  130. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  131. else if (sc->ps_enabled &&
  132. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  133. PS_WAIT_FOR_CAB |
  134. PS_WAIT_FOR_PSPOLL_DATA |
  135. PS_WAIT_FOR_TX_ACK)))
  136. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  137. unlock:
  138. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  139. }
  140. /*
  141. * Set/change channels. If the channel is really being changed, it's done
  142. * by reseting the chip. To accomplish this we must first cleanup any pending
  143. * DMA, then restart stuff.
  144. */
  145. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  146. struct ath9k_channel *hchan)
  147. {
  148. struct ath_hw *ah = sc->sc_ah;
  149. struct ath_common *common = ath9k_hw_common(ah);
  150. struct ieee80211_conf *conf = &common->hw->conf;
  151. bool fastcc = true, stopped;
  152. struct ieee80211_channel *channel = hw->conf.channel;
  153. int r;
  154. if (sc->sc_flags & SC_OP_INVALID)
  155. return -EIO;
  156. ath9k_ps_wakeup(sc);
  157. /*
  158. * This is only performed if the channel settings have
  159. * actually changed.
  160. *
  161. * To switch channels clear any pending DMA operations;
  162. * wait long enough for the RX fifo to drain, reset the
  163. * hardware at the new frequency, and then re-enable
  164. * the relevant bits of the h/w.
  165. */
  166. ath9k_hw_set_interrupts(ah, 0);
  167. ath_drain_all_txq(sc, false);
  168. stopped = ath_stoprecv(sc);
  169. /* XXX: do not flush receive queue here. We don't want
  170. * to flush data frames already in queue because of
  171. * changing channel. */
  172. if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
  173. fastcc = false;
  174. ath_print(common, ATH_DBG_CONFIG,
  175. "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
  176. sc->sc_ah->curchan->channel,
  177. channel->center_freq, conf_is_ht40(conf));
  178. spin_lock_bh(&sc->sc_resetlock);
  179. r = ath9k_hw_reset(ah, hchan, fastcc);
  180. if (r) {
  181. ath_print(common, ATH_DBG_FATAL,
  182. "Unable to reset channel (%u MHz), "
  183. "reset status %d\n",
  184. channel->center_freq, r);
  185. spin_unlock_bh(&sc->sc_resetlock);
  186. goto ps_restore;
  187. }
  188. spin_unlock_bh(&sc->sc_resetlock);
  189. sc->sc_flags &= ~SC_OP_FULL_RESET;
  190. if (ath_startrecv(sc) != 0) {
  191. ath_print(common, ATH_DBG_FATAL,
  192. "Unable to restart recv logic\n");
  193. r = -EIO;
  194. goto ps_restore;
  195. }
  196. ath_cache_conf_rate(sc, &hw->conf);
  197. ath_update_txpow(sc);
  198. ath9k_hw_set_interrupts(ah, ah->imask);
  199. ps_restore:
  200. ath9k_ps_restore(sc);
  201. return r;
  202. }
  203. static void ath_paprd_activate(struct ath_softc *sc)
  204. {
  205. struct ath_hw *ah = sc->sc_ah;
  206. int chain;
  207. if (!ah->curchan->paprd_done)
  208. return;
  209. ath9k_ps_wakeup(sc);
  210. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  211. if (!(ah->caps.tx_chainmask & BIT(chain)))
  212. continue;
  213. ar9003_paprd_populate_single_table(ah, ah->curchan, chain);
  214. }
  215. ar9003_paprd_enable(ah, true);
  216. ath9k_ps_restore(sc);
  217. }
  218. void ath_paprd_calibrate(struct work_struct *work)
  219. {
  220. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  221. struct ieee80211_hw *hw = sc->hw;
  222. struct ath_hw *ah = sc->sc_ah;
  223. struct ieee80211_hdr *hdr;
  224. struct sk_buff *skb = NULL;
  225. struct ieee80211_tx_info *tx_info;
  226. int band = hw->conf.channel->band;
  227. struct ieee80211_supported_band *sband = &sc->sbands[band];
  228. struct ath_tx_control txctl;
  229. int qnum, ftype;
  230. int chain_ok = 0;
  231. int chain;
  232. int len = 1800;
  233. int time_left;
  234. int i;
  235. ath9k_ps_wakeup(sc);
  236. skb = alloc_skb(len, GFP_KERNEL);
  237. if (!skb)
  238. return;
  239. tx_info = IEEE80211_SKB_CB(skb);
  240. skb_put(skb, len);
  241. memset(skb->data, 0, len);
  242. hdr = (struct ieee80211_hdr *)skb->data;
  243. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  244. hdr->frame_control = cpu_to_le16(ftype);
  245. hdr->duration_id = 10;
  246. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  247. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  248. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  249. memset(&txctl, 0, sizeof(txctl));
  250. qnum = sc->tx.hwq_map[WME_AC_BE];
  251. txctl.txq = &sc->tx.txq[qnum];
  252. ar9003_paprd_init_table(ah);
  253. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  254. if (!(ah->caps.tx_chainmask & BIT(chain)))
  255. continue;
  256. chain_ok = 0;
  257. memset(tx_info, 0, sizeof(*tx_info));
  258. tx_info->band = band;
  259. for (i = 0; i < 4; i++) {
  260. tx_info->control.rates[i].idx = sband->n_bitrates - 1;
  261. tx_info->control.rates[i].count = 6;
  262. }
  263. init_completion(&sc->paprd_complete);
  264. ar9003_paprd_setup_gain_table(ah, chain);
  265. txctl.paprd = BIT(chain);
  266. if (ath_tx_start(hw, skb, &txctl) != 0)
  267. break;
  268. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  269. 100);
  270. if (!time_left) {
  271. ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
  272. "Timeout waiting for paprd training on "
  273. "TX chain %d\n",
  274. chain);
  275. break;
  276. }
  277. if (!ar9003_paprd_is_done(ah))
  278. break;
  279. if (ar9003_paprd_create_curve(ah, ah->curchan, chain) != 0)
  280. break;
  281. chain_ok = 1;
  282. }
  283. kfree_skb(skb);
  284. if (chain_ok) {
  285. ah->curchan->paprd_done = true;
  286. ath_paprd_activate(sc);
  287. }
  288. ath9k_ps_restore(sc);
  289. }
  290. /*
  291. * This routine performs the periodic noise floor calibration function
  292. * that is used to adjust and optimize the chip performance. This
  293. * takes environmental changes (location, temperature) into account.
  294. * When the task is complete, it reschedules itself depending on the
  295. * appropriate interval that was calculated.
  296. */
  297. void ath_ani_calibrate(unsigned long data)
  298. {
  299. struct ath_softc *sc = (struct ath_softc *)data;
  300. struct ath_hw *ah = sc->sc_ah;
  301. struct ath_common *common = ath9k_hw_common(ah);
  302. bool longcal = false;
  303. bool shortcal = false;
  304. bool aniflag = false;
  305. unsigned int timestamp = jiffies_to_msecs(jiffies);
  306. u32 cal_interval, short_cal_interval;
  307. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  308. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  309. /* Only calibrate if awake */
  310. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  311. goto set_timer;
  312. ath9k_ps_wakeup(sc);
  313. /* Long calibration runs independently of short calibration. */
  314. if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
  315. longcal = true;
  316. ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  317. common->ani.longcal_timer = timestamp;
  318. }
  319. /* Short calibration applies only while caldone is false */
  320. if (!common->ani.caldone) {
  321. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  322. shortcal = true;
  323. ath_print(common, ATH_DBG_ANI,
  324. "shortcal @%lu\n", jiffies);
  325. common->ani.shortcal_timer = timestamp;
  326. common->ani.resetcal_timer = timestamp;
  327. }
  328. } else {
  329. if ((timestamp - common->ani.resetcal_timer) >=
  330. ATH_RESTART_CALINTERVAL) {
  331. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  332. if (common->ani.caldone)
  333. common->ani.resetcal_timer = timestamp;
  334. }
  335. }
  336. /* Verify whether we must check ANI */
  337. if ((timestamp - common->ani.checkani_timer) >=
  338. ah->config.ani_poll_interval) {
  339. aniflag = true;
  340. common->ani.checkani_timer = timestamp;
  341. }
  342. /* Skip all processing if there's nothing to do. */
  343. if (longcal || shortcal || aniflag) {
  344. /* Call ANI routine if necessary */
  345. if (aniflag)
  346. ath9k_hw_ani_monitor(ah, ah->curchan);
  347. /* Perform calibration if necessary */
  348. if (longcal || shortcal) {
  349. common->ani.caldone =
  350. ath9k_hw_calibrate(ah,
  351. ah->curchan,
  352. common->rx_chainmask,
  353. longcal);
  354. if (longcal)
  355. common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
  356. ah->curchan);
  357. ath_print(common, ATH_DBG_ANI,
  358. " calibrate chan %u/%x nf: %d\n",
  359. ah->curchan->channel,
  360. ah->curchan->channelFlags,
  361. common->ani.noise_floor);
  362. }
  363. }
  364. ath9k_ps_restore(sc);
  365. set_timer:
  366. /*
  367. * Set timer interval based on previous results.
  368. * The interval must be the shortest necessary to satisfy ANI,
  369. * short calibration and long calibration.
  370. */
  371. cal_interval = ATH_LONG_CALINTERVAL;
  372. if (sc->sc_ah->config.enable_ani)
  373. cal_interval = min(cal_interval,
  374. (u32)ah->config.ani_poll_interval);
  375. if (!common->ani.caldone)
  376. cal_interval = min(cal_interval, (u32)short_cal_interval);
  377. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  378. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) &&
  379. !(sc->sc_flags & SC_OP_SCANNING)) {
  380. if (!sc->sc_ah->curchan->paprd_done)
  381. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  382. else
  383. ath_paprd_activate(sc);
  384. }
  385. }
  386. static void ath_start_ani(struct ath_common *common)
  387. {
  388. struct ath_hw *ah = common->ah;
  389. unsigned long timestamp = jiffies_to_msecs(jiffies);
  390. common->ani.longcal_timer = timestamp;
  391. common->ani.shortcal_timer = timestamp;
  392. common->ani.checkani_timer = timestamp;
  393. mod_timer(&common->ani.timer,
  394. jiffies +
  395. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  396. }
  397. /*
  398. * Update tx/rx chainmask. For legacy association,
  399. * hard code chainmask to 1x1, for 11n association, use
  400. * the chainmask configuration, for bt coexistence, use
  401. * the chainmask configuration even in legacy mode.
  402. */
  403. void ath_update_chainmask(struct ath_softc *sc, int is_ht)
  404. {
  405. struct ath_hw *ah = sc->sc_ah;
  406. struct ath_common *common = ath9k_hw_common(ah);
  407. if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
  408. (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
  409. common->tx_chainmask = ah->caps.tx_chainmask;
  410. common->rx_chainmask = ah->caps.rx_chainmask;
  411. } else {
  412. common->tx_chainmask = 1;
  413. common->rx_chainmask = 1;
  414. }
  415. ath_print(common, ATH_DBG_CONFIG,
  416. "tx chmask: %d, rx chmask: %d\n",
  417. common->tx_chainmask,
  418. common->rx_chainmask);
  419. }
  420. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  421. {
  422. struct ath_node *an;
  423. an = (struct ath_node *)sta->drv_priv;
  424. if (sc->sc_flags & SC_OP_TXAGGR) {
  425. ath_tx_node_init(sc, an);
  426. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  427. sta->ht_cap.ampdu_factor);
  428. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  429. an->last_rssi = ATH_RSSI_DUMMY_MARKER;
  430. }
  431. }
  432. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  433. {
  434. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  435. if (sc->sc_flags & SC_OP_TXAGGR)
  436. ath_tx_node_cleanup(sc, an);
  437. }
  438. void ath9k_tasklet(unsigned long data)
  439. {
  440. struct ath_softc *sc = (struct ath_softc *)data;
  441. struct ath_hw *ah = sc->sc_ah;
  442. struct ath_common *common = ath9k_hw_common(ah);
  443. u32 status = sc->intrstatus;
  444. u32 rxmask;
  445. ath9k_ps_wakeup(sc);
  446. if ((status & ATH9K_INT_FATAL) ||
  447. !ath9k_hw_check_alive(ah)) {
  448. ath_reset(sc, false);
  449. ath9k_ps_restore(sc);
  450. return;
  451. }
  452. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  453. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  454. ATH9K_INT_RXORN);
  455. else
  456. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  457. if (status & rxmask) {
  458. spin_lock_bh(&sc->rx.rxflushlock);
  459. /* Check for high priority Rx first */
  460. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  461. (status & ATH9K_INT_RXHP))
  462. ath_rx_tasklet(sc, 0, true);
  463. ath_rx_tasklet(sc, 0, false);
  464. spin_unlock_bh(&sc->rx.rxflushlock);
  465. }
  466. if (status & ATH9K_INT_TX) {
  467. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  468. ath_tx_edma_tasklet(sc);
  469. else
  470. ath_tx_tasklet(sc);
  471. }
  472. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  473. /*
  474. * TSF sync does not look correct; remain awake to sync with
  475. * the next Beacon.
  476. */
  477. ath_print(common, ATH_DBG_PS,
  478. "TSFOOR - Sync with next Beacon\n");
  479. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  480. }
  481. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  482. if (status & ATH9K_INT_GENTIMER)
  483. ath_gen_timer_isr(sc->sc_ah);
  484. /* re-enable hardware interrupt */
  485. ath9k_hw_set_interrupts(ah, ah->imask);
  486. ath9k_ps_restore(sc);
  487. }
  488. irqreturn_t ath_isr(int irq, void *dev)
  489. {
  490. #define SCHED_INTR ( \
  491. ATH9K_INT_FATAL | \
  492. ATH9K_INT_RXORN | \
  493. ATH9K_INT_RXEOL | \
  494. ATH9K_INT_RX | \
  495. ATH9K_INT_RXLP | \
  496. ATH9K_INT_RXHP | \
  497. ATH9K_INT_TX | \
  498. ATH9K_INT_BMISS | \
  499. ATH9K_INT_CST | \
  500. ATH9K_INT_TSFOOR | \
  501. ATH9K_INT_GENTIMER)
  502. struct ath_softc *sc = dev;
  503. struct ath_hw *ah = sc->sc_ah;
  504. enum ath9k_int status;
  505. bool sched = false;
  506. /*
  507. * The hardware is not ready/present, don't
  508. * touch anything. Note this can happen early
  509. * on if the IRQ is shared.
  510. */
  511. if (sc->sc_flags & SC_OP_INVALID)
  512. return IRQ_NONE;
  513. /* shared irq, not for us */
  514. if (!ath9k_hw_intrpend(ah))
  515. return IRQ_NONE;
  516. /*
  517. * Figure out the reason(s) for the interrupt. Note
  518. * that the hal returns a pseudo-ISR that may include
  519. * bits we haven't explicitly enabled so we mask the
  520. * value to insure we only process bits we requested.
  521. */
  522. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  523. status &= ah->imask; /* discard unasked-for bits */
  524. /*
  525. * If there are no status bits set, then this interrupt was not
  526. * for me (should have been caught above).
  527. */
  528. if (!status)
  529. return IRQ_NONE;
  530. /* Cache the status */
  531. sc->intrstatus = status;
  532. if (status & SCHED_INTR)
  533. sched = true;
  534. /*
  535. * If a FATAL or RXORN interrupt is received, we have to reset the
  536. * chip immediately.
  537. */
  538. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  539. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  540. goto chip_reset;
  541. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  542. (status & ATH9K_INT_BB_WATCHDOG)) {
  543. ar9003_hw_bb_watchdog_dbg_info(ah);
  544. goto chip_reset;
  545. }
  546. if (status & ATH9K_INT_SWBA)
  547. tasklet_schedule(&sc->bcon_tasklet);
  548. if (status & ATH9K_INT_TXURN)
  549. ath9k_hw_updatetxtriglevel(ah, true);
  550. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  551. if (status & ATH9K_INT_RXEOL) {
  552. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  553. ath9k_hw_set_interrupts(ah, ah->imask);
  554. }
  555. }
  556. if (status & ATH9K_INT_MIB) {
  557. /*
  558. * Disable interrupts until we service the MIB
  559. * interrupt; otherwise it will continue to
  560. * fire.
  561. */
  562. ath9k_hw_set_interrupts(ah, 0);
  563. /*
  564. * Let the hal handle the event. We assume
  565. * it will clear whatever condition caused
  566. * the interrupt.
  567. */
  568. ath9k_hw_procmibevent(ah);
  569. ath9k_hw_set_interrupts(ah, ah->imask);
  570. }
  571. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  572. if (status & ATH9K_INT_TIM_TIMER) {
  573. /* Clear RxAbort bit so that we can
  574. * receive frames */
  575. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  576. ath9k_hw_setrxabort(sc->sc_ah, 0);
  577. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  578. }
  579. chip_reset:
  580. ath_debug_stat_interrupt(sc, status);
  581. if (sched) {
  582. /* turn off every interrupt except SWBA */
  583. ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
  584. tasklet_schedule(&sc->intr_tq);
  585. }
  586. return IRQ_HANDLED;
  587. #undef SCHED_INTR
  588. }
  589. static u32 ath_get_extchanmode(struct ath_softc *sc,
  590. struct ieee80211_channel *chan,
  591. enum nl80211_channel_type channel_type)
  592. {
  593. u32 chanmode = 0;
  594. switch (chan->band) {
  595. case IEEE80211_BAND_2GHZ:
  596. switch(channel_type) {
  597. case NL80211_CHAN_NO_HT:
  598. case NL80211_CHAN_HT20:
  599. chanmode = CHANNEL_G_HT20;
  600. break;
  601. case NL80211_CHAN_HT40PLUS:
  602. chanmode = CHANNEL_G_HT40PLUS;
  603. break;
  604. case NL80211_CHAN_HT40MINUS:
  605. chanmode = CHANNEL_G_HT40MINUS;
  606. break;
  607. }
  608. break;
  609. case IEEE80211_BAND_5GHZ:
  610. switch(channel_type) {
  611. case NL80211_CHAN_NO_HT:
  612. case NL80211_CHAN_HT20:
  613. chanmode = CHANNEL_A_HT20;
  614. break;
  615. case NL80211_CHAN_HT40PLUS:
  616. chanmode = CHANNEL_A_HT40PLUS;
  617. break;
  618. case NL80211_CHAN_HT40MINUS:
  619. chanmode = CHANNEL_A_HT40MINUS;
  620. break;
  621. }
  622. break;
  623. default:
  624. break;
  625. }
  626. return chanmode;
  627. }
  628. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  629. struct ieee80211_vif *vif,
  630. struct ieee80211_bss_conf *bss_conf)
  631. {
  632. struct ath_hw *ah = sc->sc_ah;
  633. struct ath_common *common = ath9k_hw_common(ah);
  634. if (bss_conf->assoc) {
  635. ath_print(common, ATH_DBG_CONFIG,
  636. "Bss Info ASSOC %d, bssid: %pM\n",
  637. bss_conf->aid, common->curbssid);
  638. /* New association, store aid */
  639. common->curaid = bss_conf->aid;
  640. ath9k_hw_write_associd(ah);
  641. /*
  642. * Request a re-configuration of Beacon related timers
  643. * on the receipt of the first Beacon frame (i.e.,
  644. * after time sync with the AP).
  645. */
  646. sc->ps_flags |= PS_BEACON_SYNC;
  647. /* Configure the beacon */
  648. ath_beacon_config(sc, vif);
  649. /* Reset rssi stats */
  650. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  651. ath_start_ani(common);
  652. } else {
  653. ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  654. common->curaid = 0;
  655. /* Stop ANI */
  656. del_timer_sync(&common->ani.timer);
  657. }
  658. }
  659. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  660. {
  661. struct ath_hw *ah = sc->sc_ah;
  662. struct ath_common *common = ath9k_hw_common(ah);
  663. struct ieee80211_channel *channel = hw->conf.channel;
  664. int r;
  665. ath9k_ps_wakeup(sc);
  666. ath9k_hw_configpcipowersave(ah, 0, 0);
  667. if (!ah->curchan)
  668. ah->curchan = ath_get_curchannel(sc, sc->hw);
  669. spin_lock_bh(&sc->sc_resetlock);
  670. r = ath9k_hw_reset(ah, ah->curchan, false);
  671. if (r) {
  672. ath_print(common, ATH_DBG_FATAL,
  673. "Unable to reset channel (%u MHz), "
  674. "reset status %d\n",
  675. channel->center_freq, r);
  676. }
  677. spin_unlock_bh(&sc->sc_resetlock);
  678. ath_update_txpow(sc);
  679. if (ath_startrecv(sc) != 0) {
  680. ath_print(common, ATH_DBG_FATAL,
  681. "Unable to restart recv logic\n");
  682. return;
  683. }
  684. if (sc->sc_flags & SC_OP_BEACONS)
  685. ath_beacon_config(sc, NULL); /* restart beacons */
  686. /* Re-Enable interrupts */
  687. ath9k_hw_set_interrupts(ah, ah->imask);
  688. /* Enable LED */
  689. ath9k_hw_cfg_output(ah, ah->led_pin,
  690. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  691. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  692. ieee80211_wake_queues(hw);
  693. ath9k_ps_restore(sc);
  694. }
  695. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  696. {
  697. struct ath_hw *ah = sc->sc_ah;
  698. struct ieee80211_channel *channel = hw->conf.channel;
  699. int r;
  700. ath9k_ps_wakeup(sc);
  701. ieee80211_stop_queues(hw);
  702. /* Disable LED */
  703. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  704. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  705. /* Disable interrupts */
  706. ath9k_hw_set_interrupts(ah, 0);
  707. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  708. ath_stoprecv(sc); /* turn off frame recv */
  709. ath_flushrecv(sc); /* flush recv queue */
  710. if (!ah->curchan)
  711. ah->curchan = ath_get_curchannel(sc, hw);
  712. spin_lock_bh(&sc->sc_resetlock);
  713. r = ath9k_hw_reset(ah, ah->curchan, false);
  714. if (r) {
  715. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  716. "Unable to reset channel (%u MHz), "
  717. "reset status %d\n",
  718. channel->center_freq, r);
  719. }
  720. spin_unlock_bh(&sc->sc_resetlock);
  721. ath9k_hw_phy_disable(ah);
  722. ath9k_hw_configpcipowersave(ah, 1, 1);
  723. ath9k_ps_restore(sc);
  724. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  725. }
  726. int ath_reset(struct ath_softc *sc, bool retry_tx)
  727. {
  728. struct ath_hw *ah = sc->sc_ah;
  729. struct ath_common *common = ath9k_hw_common(ah);
  730. struct ieee80211_hw *hw = sc->hw;
  731. int r;
  732. /* Stop ANI */
  733. del_timer_sync(&common->ani.timer);
  734. ieee80211_stop_queues(hw);
  735. ath9k_hw_set_interrupts(ah, 0);
  736. ath_drain_all_txq(sc, retry_tx);
  737. ath_stoprecv(sc);
  738. ath_flushrecv(sc);
  739. spin_lock_bh(&sc->sc_resetlock);
  740. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
  741. if (r)
  742. ath_print(common, ATH_DBG_FATAL,
  743. "Unable to reset hardware; reset status %d\n", r);
  744. spin_unlock_bh(&sc->sc_resetlock);
  745. if (ath_startrecv(sc) != 0)
  746. ath_print(common, ATH_DBG_FATAL,
  747. "Unable to start recv logic\n");
  748. /*
  749. * We may be doing a reset in response to a request
  750. * that changes the channel so update any state that
  751. * might change as a result.
  752. */
  753. ath_cache_conf_rate(sc, &hw->conf);
  754. ath_update_txpow(sc);
  755. if (sc->sc_flags & SC_OP_BEACONS)
  756. ath_beacon_config(sc, NULL); /* restart beacons */
  757. ath9k_hw_set_interrupts(ah, ah->imask);
  758. if (retry_tx) {
  759. int i;
  760. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  761. if (ATH_TXQ_SETUP(sc, i)) {
  762. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  763. ath_txq_schedule(sc, &sc->tx.txq[i]);
  764. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  765. }
  766. }
  767. }
  768. ieee80211_wake_queues(hw);
  769. /* Start ANI */
  770. ath_start_ani(common);
  771. return r;
  772. }
  773. static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
  774. {
  775. int qnum;
  776. switch (queue) {
  777. case 0:
  778. qnum = sc->tx.hwq_map[WME_AC_VO];
  779. break;
  780. case 1:
  781. qnum = sc->tx.hwq_map[WME_AC_VI];
  782. break;
  783. case 2:
  784. qnum = sc->tx.hwq_map[WME_AC_BE];
  785. break;
  786. case 3:
  787. qnum = sc->tx.hwq_map[WME_AC_BK];
  788. break;
  789. default:
  790. qnum = sc->tx.hwq_map[WME_AC_BE];
  791. break;
  792. }
  793. return qnum;
  794. }
  795. int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
  796. {
  797. int qnum;
  798. switch (queue) {
  799. case WME_AC_VO:
  800. qnum = 0;
  801. break;
  802. case WME_AC_VI:
  803. qnum = 1;
  804. break;
  805. case WME_AC_BE:
  806. qnum = 2;
  807. break;
  808. case WME_AC_BK:
  809. qnum = 3;
  810. break;
  811. default:
  812. qnum = -1;
  813. break;
  814. }
  815. return qnum;
  816. }
  817. /* XXX: Remove me once we don't depend on ath9k_channel for all
  818. * this redundant data */
  819. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  820. struct ath9k_channel *ichan)
  821. {
  822. struct ieee80211_channel *chan = hw->conf.channel;
  823. struct ieee80211_conf *conf = &hw->conf;
  824. ichan->channel = chan->center_freq;
  825. ichan->chan = chan;
  826. if (chan->band == IEEE80211_BAND_2GHZ) {
  827. ichan->chanmode = CHANNEL_G;
  828. ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
  829. } else {
  830. ichan->chanmode = CHANNEL_A;
  831. ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
  832. }
  833. if (conf_is_ht(conf))
  834. ichan->chanmode = ath_get_extchanmode(sc, chan,
  835. conf->channel_type);
  836. }
  837. /**********************/
  838. /* mac80211 callbacks */
  839. /**********************/
  840. static int ath9k_start(struct ieee80211_hw *hw)
  841. {
  842. struct ath_wiphy *aphy = hw->priv;
  843. struct ath_softc *sc = aphy->sc;
  844. struct ath_hw *ah = sc->sc_ah;
  845. struct ath_common *common = ath9k_hw_common(ah);
  846. struct ieee80211_channel *curchan = hw->conf.channel;
  847. struct ath9k_channel *init_channel;
  848. int r;
  849. ath_print(common, ATH_DBG_CONFIG,
  850. "Starting driver with initial channel: %d MHz\n",
  851. curchan->center_freq);
  852. mutex_lock(&sc->mutex);
  853. if (ath9k_wiphy_started(sc)) {
  854. if (sc->chan_idx == curchan->hw_value) {
  855. /*
  856. * Already on the operational channel, the new wiphy
  857. * can be marked active.
  858. */
  859. aphy->state = ATH_WIPHY_ACTIVE;
  860. ieee80211_wake_queues(hw);
  861. } else {
  862. /*
  863. * Another wiphy is on another channel, start the new
  864. * wiphy in paused state.
  865. */
  866. aphy->state = ATH_WIPHY_PAUSED;
  867. ieee80211_stop_queues(hw);
  868. }
  869. mutex_unlock(&sc->mutex);
  870. return 0;
  871. }
  872. aphy->state = ATH_WIPHY_ACTIVE;
  873. /* setup initial channel */
  874. sc->chan_idx = curchan->hw_value;
  875. init_channel = ath_get_curchannel(sc, hw);
  876. /* Reset SERDES registers */
  877. ath9k_hw_configpcipowersave(ah, 0, 0);
  878. /*
  879. * The basic interface to setting the hardware in a good
  880. * state is ``reset''. On return the hardware is known to
  881. * be powered up and with interrupts disabled. This must
  882. * be followed by initialization of the appropriate bits
  883. * and then setup of the interrupt mask.
  884. */
  885. spin_lock_bh(&sc->sc_resetlock);
  886. r = ath9k_hw_reset(ah, init_channel, false);
  887. if (r) {
  888. ath_print(common, ATH_DBG_FATAL,
  889. "Unable to reset hardware; reset status %d "
  890. "(freq %u MHz)\n", r,
  891. curchan->center_freq);
  892. spin_unlock_bh(&sc->sc_resetlock);
  893. goto mutex_unlock;
  894. }
  895. spin_unlock_bh(&sc->sc_resetlock);
  896. /*
  897. * This is needed only to setup initial state
  898. * but it's best done after a reset.
  899. */
  900. ath_update_txpow(sc);
  901. /*
  902. * Setup the hardware after reset:
  903. * The receive engine is set going.
  904. * Frame transmit is handled entirely
  905. * in the frame output path; there's nothing to do
  906. * here except setup the interrupt mask.
  907. */
  908. if (ath_startrecv(sc) != 0) {
  909. ath_print(common, ATH_DBG_FATAL,
  910. "Unable to start recv logic\n");
  911. r = -EIO;
  912. goto mutex_unlock;
  913. }
  914. /* Setup our intr mask. */
  915. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  916. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  917. ATH9K_INT_GLOBAL;
  918. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  919. ah->imask |= ATH9K_INT_RXHP |
  920. ATH9K_INT_RXLP |
  921. ATH9K_INT_BB_WATCHDOG;
  922. else
  923. ah->imask |= ATH9K_INT_RX;
  924. if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
  925. ah->imask |= ATH9K_INT_GTT;
  926. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  927. ah->imask |= ATH9K_INT_CST;
  928. ath_cache_conf_rate(sc, &hw->conf);
  929. sc->sc_flags &= ~SC_OP_INVALID;
  930. /* Disable BMISS interrupt when we're not associated */
  931. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  932. ath9k_hw_set_interrupts(ah, ah->imask);
  933. ieee80211_wake_queues(hw);
  934. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  935. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  936. !ah->btcoex_hw.enabled) {
  937. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  938. AR_STOMP_LOW_WLAN_WGHT);
  939. ath9k_hw_btcoex_enable(ah);
  940. if (common->bus_ops->bt_coex_prep)
  941. common->bus_ops->bt_coex_prep(common);
  942. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  943. ath9k_btcoex_timer_resume(sc);
  944. }
  945. mutex_unlock:
  946. mutex_unlock(&sc->mutex);
  947. return r;
  948. }
  949. static int ath9k_tx(struct ieee80211_hw *hw,
  950. struct sk_buff *skb)
  951. {
  952. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  953. struct ath_wiphy *aphy = hw->priv;
  954. struct ath_softc *sc = aphy->sc;
  955. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  956. struct ath_tx_control txctl;
  957. int padpos, padsize;
  958. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  959. int qnum;
  960. if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
  961. ath_print(common, ATH_DBG_XMIT,
  962. "ath9k: %s: TX in unexpected wiphy state "
  963. "%d\n", wiphy_name(hw->wiphy), aphy->state);
  964. goto exit;
  965. }
  966. if (sc->ps_enabled) {
  967. /*
  968. * mac80211 does not set PM field for normal data frames, so we
  969. * need to update that based on the current PS mode.
  970. */
  971. if (ieee80211_is_data(hdr->frame_control) &&
  972. !ieee80211_is_nullfunc(hdr->frame_control) &&
  973. !ieee80211_has_pm(hdr->frame_control)) {
  974. ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
  975. "while in PS mode\n");
  976. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  977. }
  978. }
  979. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  980. /*
  981. * We are using PS-Poll and mac80211 can request TX while in
  982. * power save mode. Need to wake up hardware for the TX to be
  983. * completed and if needed, also for RX of buffered frames.
  984. */
  985. ath9k_ps_wakeup(sc);
  986. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  987. ath9k_hw_setrxabort(sc->sc_ah, 0);
  988. if (ieee80211_is_pspoll(hdr->frame_control)) {
  989. ath_print(common, ATH_DBG_PS,
  990. "Sending PS-Poll to pick a buffered frame\n");
  991. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  992. } else {
  993. ath_print(common, ATH_DBG_PS,
  994. "Wake up to complete TX\n");
  995. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  996. }
  997. /*
  998. * The actual restore operation will happen only after
  999. * the sc_flags bit is cleared. We are just dropping
  1000. * the ps_usecount here.
  1001. */
  1002. ath9k_ps_restore(sc);
  1003. }
  1004. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1005. /*
  1006. * As a temporary workaround, assign seq# here; this will likely need
  1007. * to be cleaned up to work better with Beacon transmission and virtual
  1008. * BSSes.
  1009. */
  1010. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1011. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1012. sc->tx.seq_no += 0x10;
  1013. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1014. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1015. }
  1016. /* Add the padding after the header if this is not already done */
  1017. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1018. padsize = padpos & 3;
  1019. if (padsize && skb->len>padpos) {
  1020. if (skb_headroom(skb) < padsize)
  1021. return -1;
  1022. skb_push(skb, padsize);
  1023. memmove(skb->data, skb->data + padsize, padpos);
  1024. }
  1025. qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
  1026. txctl.txq = &sc->tx.txq[qnum];
  1027. ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  1028. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1029. ath_print(common, ATH_DBG_XMIT, "TX failed\n");
  1030. goto exit;
  1031. }
  1032. return 0;
  1033. exit:
  1034. dev_kfree_skb_any(skb);
  1035. return 0;
  1036. }
  1037. static void ath9k_stop(struct ieee80211_hw *hw)
  1038. {
  1039. struct ath_wiphy *aphy = hw->priv;
  1040. struct ath_softc *sc = aphy->sc;
  1041. struct ath_hw *ah = sc->sc_ah;
  1042. struct ath_common *common = ath9k_hw_common(ah);
  1043. mutex_lock(&sc->mutex);
  1044. aphy->state = ATH_WIPHY_INACTIVE;
  1045. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  1046. cancel_delayed_work_sync(&sc->tx_complete_work);
  1047. cancel_work_sync(&sc->paprd_work);
  1048. if (!sc->num_sec_wiphy) {
  1049. cancel_delayed_work_sync(&sc->wiphy_work);
  1050. cancel_work_sync(&sc->chan_work);
  1051. }
  1052. if (sc->sc_flags & SC_OP_INVALID) {
  1053. ath_print(common, ATH_DBG_ANY, "Device not present\n");
  1054. mutex_unlock(&sc->mutex);
  1055. return;
  1056. }
  1057. if (ath9k_wiphy_started(sc)) {
  1058. mutex_unlock(&sc->mutex);
  1059. return; /* another wiphy still in use */
  1060. }
  1061. /* Ensure HW is awake when we try to shut it down. */
  1062. ath9k_ps_wakeup(sc);
  1063. if (ah->btcoex_hw.enabled) {
  1064. ath9k_hw_btcoex_disable(ah);
  1065. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1066. ath9k_btcoex_timer_pause(sc);
  1067. }
  1068. /* make sure h/w will not generate any interrupt
  1069. * before setting the invalid flag. */
  1070. ath9k_hw_set_interrupts(ah, 0);
  1071. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1072. ath_drain_all_txq(sc, false);
  1073. ath_stoprecv(sc);
  1074. ath9k_hw_phy_disable(ah);
  1075. } else
  1076. sc->rx.rxlink = NULL;
  1077. /* disable HAL and put h/w to sleep */
  1078. ath9k_hw_disable(ah);
  1079. ath9k_hw_configpcipowersave(ah, 1, 1);
  1080. ath9k_ps_restore(sc);
  1081. /* Finally, put the chip in FULL SLEEP mode */
  1082. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  1083. sc->sc_flags |= SC_OP_INVALID;
  1084. mutex_unlock(&sc->mutex);
  1085. ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
  1086. }
  1087. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1088. struct ieee80211_vif *vif)
  1089. {
  1090. struct ath_wiphy *aphy = hw->priv;
  1091. struct ath_softc *sc = aphy->sc;
  1092. struct ath_hw *ah = sc->sc_ah;
  1093. struct ath_common *common = ath9k_hw_common(ah);
  1094. struct ath_vif *avp = (void *)vif->drv_priv;
  1095. enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
  1096. int ret = 0;
  1097. mutex_lock(&sc->mutex);
  1098. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
  1099. sc->nvifs > 0) {
  1100. ret = -ENOBUFS;
  1101. goto out;
  1102. }
  1103. switch (vif->type) {
  1104. case NL80211_IFTYPE_STATION:
  1105. ic_opmode = NL80211_IFTYPE_STATION;
  1106. break;
  1107. case NL80211_IFTYPE_ADHOC:
  1108. case NL80211_IFTYPE_AP:
  1109. case NL80211_IFTYPE_MESH_POINT:
  1110. if (sc->nbcnvifs >= ATH_BCBUF) {
  1111. ret = -ENOBUFS;
  1112. goto out;
  1113. }
  1114. ic_opmode = vif->type;
  1115. break;
  1116. default:
  1117. ath_print(common, ATH_DBG_FATAL,
  1118. "Interface type %d not yet supported\n", vif->type);
  1119. ret = -EOPNOTSUPP;
  1120. goto out;
  1121. }
  1122. ath_print(common, ATH_DBG_CONFIG,
  1123. "Attach a VIF of type: %d\n", ic_opmode);
  1124. /* Set the VIF opmode */
  1125. avp->av_opmode = ic_opmode;
  1126. avp->av_bslot = -1;
  1127. sc->nvifs++;
  1128. if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  1129. ath9k_set_bssid_mask(hw);
  1130. if (sc->nvifs > 1)
  1131. goto out; /* skip global settings for secondary vif */
  1132. if (ic_opmode == NL80211_IFTYPE_AP) {
  1133. ath9k_hw_set_tsfadjust(ah, 1);
  1134. sc->sc_flags |= SC_OP_TSF_RESET;
  1135. }
  1136. /* Set the device opmode */
  1137. ah->opmode = ic_opmode;
  1138. /*
  1139. * Enable MIB interrupts when there are hardware phy counters.
  1140. * Note we only do this (at the moment) for station mode.
  1141. */
  1142. if ((vif->type == NL80211_IFTYPE_STATION) ||
  1143. (vif->type == NL80211_IFTYPE_ADHOC) ||
  1144. (vif->type == NL80211_IFTYPE_MESH_POINT)) {
  1145. if (ah->config.enable_ani)
  1146. ah->imask |= ATH9K_INT_MIB;
  1147. ah->imask |= ATH9K_INT_TSFOOR;
  1148. }
  1149. ath9k_hw_set_interrupts(ah, ah->imask);
  1150. if (vif->type == NL80211_IFTYPE_AP ||
  1151. vif->type == NL80211_IFTYPE_ADHOC ||
  1152. vif->type == NL80211_IFTYPE_MONITOR)
  1153. ath_start_ani(common);
  1154. out:
  1155. mutex_unlock(&sc->mutex);
  1156. return ret;
  1157. }
  1158. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1159. struct ieee80211_vif *vif)
  1160. {
  1161. struct ath_wiphy *aphy = hw->priv;
  1162. struct ath_softc *sc = aphy->sc;
  1163. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1164. struct ath_vif *avp = (void *)vif->drv_priv;
  1165. int i;
  1166. ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1167. mutex_lock(&sc->mutex);
  1168. /* Stop ANI */
  1169. del_timer_sync(&common->ani.timer);
  1170. /* Reclaim beacon resources */
  1171. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  1172. (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1173. (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
  1174. ath9k_ps_wakeup(sc);
  1175. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1176. ath9k_ps_restore(sc);
  1177. }
  1178. ath_beacon_return(sc, avp);
  1179. sc->sc_flags &= ~SC_OP_BEACONS;
  1180. for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
  1181. if (sc->beacon.bslot[i] == vif) {
  1182. printk(KERN_DEBUG "%s: vif had allocated beacon "
  1183. "slot\n", __func__);
  1184. sc->beacon.bslot[i] = NULL;
  1185. sc->beacon.bslot_aphy[i] = NULL;
  1186. }
  1187. }
  1188. sc->nvifs--;
  1189. mutex_unlock(&sc->mutex);
  1190. }
  1191. void ath9k_enable_ps(struct ath_softc *sc)
  1192. {
  1193. struct ath_hw *ah = sc->sc_ah;
  1194. sc->ps_enabled = true;
  1195. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1196. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1197. ah->imask |= ATH9K_INT_TIM_TIMER;
  1198. ath9k_hw_set_interrupts(ah, ah->imask);
  1199. }
  1200. ath9k_hw_setrxabort(ah, 1);
  1201. }
  1202. }
  1203. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1204. {
  1205. struct ath_wiphy *aphy = hw->priv;
  1206. struct ath_softc *sc = aphy->sc;
  1207. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1208. struct ieee80211_conf *conf = &hw->conf;
  1209. struct ath_hw *ah = sc->sc_ah;
  1210. bool disable_radio;
  1211. mutex_lock(&sc->mutex);
  1212. /*
  1213. * Leave this as the first check because we need to turn on the
  1214. * radio if it was disabled before prior to processing the rest
  1215. * of the changes. Likewise we must only disable the radio towards
  1216. * the end.
  1217. */
  1218. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1219. bool enable_radio;
  1220. bool all_wiphys_idle;
  1221. bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1222. spin_lock_bh(&sc->wiphy_lock);
  1223. all_wiphys_idle = ath9k_all_wiphys_idle(sc);
  1224. ath9k_set_wiphy_idle(aphy, idle);
  1225. enable_radio = (!idle && all_wiphys_idle);
  1226. /*
  1227. * After we unlock here its possible another wiphy
  1228. * can be re-renabled so to account for that we will
  1229. * only disable the radio toward the end of this routine
  1230. * if by then all wiphys are still idle.
  1231. */
  1232. spin_unlock_bh(&sc->wiphy_lock);
  1233. if (enable_radio) {
  1234. sc->ps_idle = false;
  1235. ath_radio_enable(sc, hw);
  1236. ath_print(common, ATH_DBG_CONFIG,
  1237. "not-idle: enabling radio\n");
  1238. }
  1239. }
  1240. /*
  1241. * We just prepare to enable PS. We have to wait until our AP has
  1242. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1243. * those ACKs and end up retransmitting the same null data frames.
  1244. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1245. */
  1246. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1247. if (conf->flags & IEEE80211_CONF_PS) {
  1248. sc->ps_flags |= PS_ENABLED;
  1249. /*
  1250. * At this point we know hardware has received an ACK
  1251. * of a previously sent null data frame.
  1252. */
  1253. if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
  1254. sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
  1255. ath9k_enable_ps(sc);
  1256. }
  1257. } else {
  1258. sc->ps_enabled = false;
  1259. sc->ps_flags &= ~(PS_ENABLED |
  1260. PS_NULLFUNC_COMPLETED);
  1261. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  1262. if (!(ah->caps.hw_caps &
  1263. ATH9K_HW_CAP_AUTOSLEEP)) {
  1264. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1265. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1266. PS_WAIT_FOR_CAB |
  1267. PS_WAIT_FOR_PSPOLL_DATA |
  1268. PS_WAIT_FOR_TX_ACK);
  1269. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1270. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1271. ath9k_hw_set_interrupts(sc->sc_ah,
  1272. ah->imask);
  1273. }
  1274. }
  1275. }
  1276. }
  1277. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1278. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1279. ath_print(common, ATH_DBG_CONFIG,
  1280. "HW opmode set to Monitor mode\n");
  1281. sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
  1282. }
  1283. }
  1284. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1285. struct ieee80211_channel *curchan = hw->conf.channel;
  1286. int pos = curchan->hw_value;
  1287. aphy->chan_idx = pos;
  1288. aphy->chan_is_ht = conf_is_ht(conf);
  1289. if (aphy->state == ATH_WIPHY_SCAN ||
  1290. aphy->state == ATH_WIPHY_ACTIVE)
  1291. ath9k_wiphy_pause_all_forced(sc, aphy);
  1292. else {
  1293. /*
  1294. * Do not change operational channel based on a paused
  1295. * wiphy changes.
  1296. */
  1297. goto skip_chan_change;
  1298. }
  1299. ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1300. curchan->center_freq);
  1301. /* XXX: remove me eventualy */
  1302. ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
  1303. ath_update_chainmask(sc, conf_is_ht(conf));
  1304. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1305. ath_print(common, ATH_DBG_FATAL,
  1306. "Unable to set channel\n");
  1307. mutex_unlock(&sc->mutex);
  1308. return -EINVAL;
  1309. }
  1310. }
  1311. skip_chan_change:
  1312. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1313. sc->config.txpowlimit = 2 * conf->power_level;
  1314. ath_update_txpow(sc);
  1315. }
  1316. spin_lock_bh(&sc->wiphy_lock);
  1317. disable_radio = ath9k_all_wiphys_idle(sc);
  1318. spin_unlock_bh(&sc->wiphy_lock);
  1319. if (disable_radio) {
  1320. ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1321. sc->ps_idle = true;
  1322. ath_radio_disable(sc, hw);
  1323. }
  1324. mutex_unlock(&sc->mutex);
  1325. return 0;
  1326. }
  1327. #define SUPPORTED_FILTERS \
  1328. (FIF_PROMISC_IN_BSS | \
  1329. FIF_ALLMULTI | \
  1330. FIF_CONTROL | \
  1331. FIF_PSPOLL | \
  1332. FIF_OTHER_BSS | \
  1333. FIF_BCN_PRBRESP_PROMISC | \
  1334. FIF_FCSFAIL)
  1335. /* FIXME: sc->sc_full_reset ? */
  1336. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1337. unsigned int changed_flags,
  1338. unsigned int *total_flags,
  1339. u64 multicast)
  1340. {
  1341. struct ath_wiphy *aphy = hw->priv;
  1342. struct ath_softc *sc = aphy->sc;
  1343. u32 rfilt;
  1344. changed_flags &= SUPPORTED_FILTERS;
  1345. *total_flags &= SUPPORTED_FILTERS;
  1346. sc->rx.rxfilter = *total_flags;
  1347. ath9k_ps_wakeup(sc);
  1348. rfilt = ath_calcrxfilter(sc);
  1349. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1350. ath9k_ps_restore(sc);
  1351. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1352. "Set HW RX filter: 0x%x\n", rfilt);
  1353. }
  1354. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1355. struct ieee80211_vif *vif,
  1356. struct ieee80211_sta *sta)
  1357. {
  1358. struct ath_wiphy *aphy = hw->priv;
  1359. struct ath_softc *sc = aphy->sc;
  1360. ath_node_attach(sc, sta);
  1361. return 0;
  1362. }
  1363. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1364. struct ieee80211_vif *vif,
  1365. struct ieee80211_sta *sta)
  1366. {
  1367. struct ath_wiphy *aphy = hw->priv;
  1368. struct ath_softc *sc = aphy->sc;
  1369. ath_node_detach(sc, sta);
  1370. return 0;
  1371. }
  1372. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1373. const struct ieee80211_tx_queue_params *params)
  1374. {
  1375. struct ath_wiphy *aphy = hw->priv;
  1376. struct ath_softc *sc = aphy->sc;
  1377. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1378. struct ath9k_tx_queue_info qi;
  1379. int ret = 0, qnum;
  1380. if (queue >= WME_NUM_AC)
  1381. return 0;
  1382. mutex_lock(&sc->mutex);
  1383. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1384. qi.tqi_aifs = params->aifs;
  1385. qi.tqi_cwmin = params->cw_min;
  1386. qi.tqi_cwmax = params->cw_max;
  1387. qi.tqi_burstTime = params->txop;
  1388. qnum = ath_get_hal_qnum(queue, sc);
  1389. ath_print(common, ATH_DBG_CONFIG,
  1390. "Configure tx [queue/halq] [%d/%d], "
  1391. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1392. queue, qnum, params->aifs, params->cw_min,
  1393. params->cw_max, params->txop);
  1394. ret = ath_txq_update(sc, qnum, &qi);
  1395. if (ret)
  1396. ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
  1397. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1398. if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
  1399. ath_beaconq_config(sc);
  1400. mutex_unlock(&sc->mutex);
  1401. return ret;
  1402. }
  1403. static int ath9k_set_key(struct ieee80211_hw *hw,
  1404. enum set_key_cmd cmd,
  1405. struct ieee80211_vif *vif,
  1406. struct ieee80211_sta *sta,
  1407. struct ieee80211_key_conf *key)
  1408. {
  1409. struct ath_wiphy *aphy = hw->priv;
  1410. struct ath_softc *sc = aphy->sc;
  1411. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1412. int ret = 0;
  1413. if (modparam_nohwcrypt)
  1414. return -ENOSPC;
  1415. mutex_lock(&sc->mutex);
  1416. ath9k_ps_wakeup(sc);
  1417. ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1418. switch (cmd) {
  1419. case SET_KEY:
  1420. ret = ath9k_cmn_key_config(common, vif, sta, key);
  1421. if (ret >= 0) {
  1422. key->hw_key_idx = ret;
  1423. /* push IV and Michael MIC generation to stack */
  1424. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1425. if (key->alg == ALG_TKIP)
  1426. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1427. if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
  1428. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1429. ret = 0;
  1430. }
  1431. break;
  1432. case DISABLE_KEY:
  1433. ath9k_cmn_key_delete(common, key);
  1434. break;
  1435. default:
  1436. ret = -EINVAL;
  1437. }
  1438. ath9k_ps_restore(sc);
  1439. mutex_unlock(&sc->mutex);
  1440. return ret;
  1441. }
  1442. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1443. struct ieee80211_vif *vif,
  1444. struct ieee80211_bss_conf *bss_conf,
  1445. u32 changed)
  1446. {
  1447. struct ath_wiphy *aphy = hw->priv;
  1448. struct ath_softc *sc = aphy->sc;
  1449. struct ath_hw *ah = sc->sc_ah;
  1450. struct ath_common *common = ath9k_hw_common(ah);
  1451. struct ath_vif *avp = (void *)vif->drv_priv;
  1452. int slottime;
  1453. int error;
  1454. mutex_lock(&sc->mutex);
  1455. if (changed & BSS_CHANGED_BSSID) {
  1456. /* Set BSSID */
  1457. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1458. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1459. common->curaid = 0;
  1460. ath9k_hw_write_associd(ah);
  1461. /* Set aggregation protection mode parameters */
  1462. sc->config.ath_aggr_prot = 0;
  1463. /* Only legacy IBSS for now */
  1464. if (vif->type == NL80211_IFTYPE_ADHOC)
  1465. ath_update_chainmask(sc, 0);
  1466. ath_print(common, ATH_DBG_CONFIG,
  1467. "BSSID: %pM aid: 0x%x\n",
  1468. common->curbssid, common->curaid);
  1469. /* need to reconfigure the beacon */
  1470. sc->sc_flags &= ~SC_OP_BEACONS ;
  1471. }
  1472. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1473. if ((changed & BSS_CHANGED_BEACON) ||
  1474. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1475. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1476. error = ath_beacon_alloc(aphy, vif);
  1477. if (!error)
  1478. ath_beacon_config(sc, vif);
  1479. }
  1480. if (changed & BSS_CHANGED_ERP_SLOT) {
  1481. if (bss_conf->use_short_slot)
  1482. slottime = 9;
  1483. else
  1484. slottime = 20;
  1485. if (vif->type == NL80211_IFTYPE_AP) {
  1486. /*
  1487. * Defer update, so that connected stations can adjust
  1488. * their settings at the same time.
  1489. * See beacon.c for more details
  1490. */
  1491. sc->beacon.slottime = slottime;
  1492. sc->beacon.updateslot = UPDATE;
  1493. } else {
  1494. ah->slottime = slottime;
  1495. ath9k_hw_init_global_settings(ah);
  1496. }
  1497. }
  1498. /* Disable transmission of beacons */
  1499. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1500. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1501. if (changed & BSS_CHANGED_BEACON_INT) {
  1502. sc->beacon_interval = bss_conf->beacon_int;
  1503. /*
  1504. * In case of AP mode, the HW TSF has to be reset
  1505. * when the beacon interval changes.
  1506. */
  1507. if (vif->type == NL80211_IFTYPE_AP) {
  1508. sc->sc_flags |= SC_OP_TSF_RESET;
  1509. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1510. error = ath_beacon_alloc(aphy, vif);
  1511. if (!error)
  1512. ath_beacon_config(sc, vif);
  1513. } else {
  1514. ath_beacon_config(sc, vif);
  1515. }
  1516. }
  1517. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1518. ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1519. bss_conf->use_short_preamble);
  1520. if (bss_conf->use_short_preamble)
  1521. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1522. else
  1523. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1524. }
  1525. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1526. ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1527. bss_conf->use_cts_prot);
  1528. if (bss_conf->use_cts_prot &&
  1529. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1530. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1531. else
  1532. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1533. }
  1534. if (changed & BSS_CHANGED_ASSOC) {
  1535. ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1536. bss_conf->assoc);
  1537. ath9k_bss_assoc_info(sc, vif, bss_conf);
  1538. }
  1539. mutex_unlock(&sc->mutex);
  1540. }
  1541. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1542. {
  1543. u64 tsf;
  1544. struct ath_wiphy *aphy = hw->priv;
  1545. struct ath_softc *sc = aphy->sc;
  1546. mutex_lock(&sc->mutex);
  1547. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1548. mutex_unlock(&sc->mutex);
  1549. return tsf;
  1550. }
  1551. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1552. {
  1553. struct ath_wiphy *aphy = hw->priv;
  1554. struct ath_softc *sc = aphy->sc;
  1555. mutex_lock(&sc->mutex);
  1556. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1557. mutex_unlock(&sc->mutex);
  1558. }
  1559. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1560. {
  1561. struct ath_wiphy *aphy = hw->priv;
  1562. struct ath_softc *sc = aphy->sc;
  1563. mutex_lock(&sc->mutex);
  1564. ath9k_ps_wakeup(sc);
  1565. ath9k_hw_reset_tsf(sc->sc_ah);
  1566. ath9k_ps_restore(sc);
  1567. mutex_unlock(&sc->mutex);
  1568. }
  1569. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1570. struct ieee80211_vif *vif,
  1571. enum ieee80211_ampdu_mlme_action action,
  1572. struct ieee80211_sta *sta,
  1573. u16 tid, u16 *ssn)
  1574. {
  1575. struct ath_wiphy *aphy = hw->priv;
  1576. struct ath_softc *sc = aphy->sc;
  1577. int ret = 0;
  1578. local_bh_disable();
  1579. switch (action) {
  1580. case IEEE80211_AMPDU_RX_START:
  1581. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1582. ret = -ENOTSUPP;
  1583. break;
  1584. case IEEE80211_AMPDU_RX_STOP:
  1585. break;
  1586. case IEEE80211_AMPDU_TX_START:
  1587. ath9k_ps_wakeup(sc);
  1588. ath_tx_aggr_start(sc, sta, tid, ssn);
  1589. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1590. ath9k_ps_restore(sc);
  1591. break;
  1592. case IEEE80211_AMPDU_TX_STOP:
  1593. ath9k_ps_wakeup(sc);
  1594. ath_tx_aggr_stop(sc, sta, tid);
  1595. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1596. ath9k_ps_restore(sc);
  1597. break;
  1598. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1599. ath9k_ps_wakeup(sc);
  1600. ath_tx_aggr_resume(sc, sta, tid);
  1601. ath9k_ps_restore(sc);
  1602. break;
  1603. default:
  1604. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  1605. "Unknown AMPDU action\n");
  1606. }
  1607. local_bh_enable();
  1608. return ret;
  1609. }
  1610. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1611. struct survey_info *survey)
  1612. {
  1613. struct ath_wiphy *aphy = hw->priv;
  1614. struct ath_softc *sc = aphy->sc;
  1615. struct ath_hw *ah = sc->sc_ah;
  1616. struct ath_common *common = ath9k_hw_common(ah);
  1617. struct ieee80211_conf *conf = &hw->conf;
  1618. if (idx != 0)
  1619. return -ENOENT;
  1620. survey->channel = conf->channel;
  1621. survey->filled = SURVEY_INFO_NOISE_DBM;
  1622. survey->noise = common->ani.noise_floor;
  1623. return 0;
  1624. }
  1625. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1626. {
  1627. struct ath_wiphy *aphy = hw->priv;
  1628. struct ath_softc *sc = aphy->sc;
  1629. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1630. mutex_lock(&sc->mutex);
  1631. if (ath9k_wiphy_scanning(sc)) {
  1632. printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
  1633. "same time\n");
  1634. /*
  1635. * Do not allow the concurrent scanning state for now. This
  1636. * could be improved with scanning control moved into ath9k.
  1637. */
  1638. mutex_unlock(&sc->mutex);
  1639. return;
  1640. }
  1641. aphy->state = ATH_WIPHY_SCAN;
  1642. ath9k_wiphy_pause_all_forced(sc, aphy);
  1643. sc->sc_flags |= SC_OP_SCANNING;
  1644. del_timer_sync(&common->ani.timer);
  1645. cancel_work_sync(&sc->paprd_work);
  1646. cancel_delayed_work_sync(&sc->tx_complete_work);
  1647. mutex_unlock(&sc->mutex);
  1648. }
  1649. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1650. {
  1651. struct ath_wiphy *aphy = hw->priv;
  1652. struct ath_softc *sc = aphy->sc;
  1653. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1654. mutex_lock(&sc->mutex);
  1655. aphy->state = ATH_WIPHY_ACTIVE;
  1656. sc->sc_flags &= ~SC_OP_SCANNING;
  1657. sc->sc_flags |= SC_OP_FULL_RESET;
  1658. ath_start_ani(common);
  1659. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  1660. ath_beacon_config(sc, NULL);
  1661. mutex_unlock(&sc->mutex);
  1662. }
  1663. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1664. {
  1665. struct ath_wiphy *aphy = hw->priv;
  1666. struct ath_softc *sc = aphy->sc;
  1667. struct ath_hw *ah = sc->sc_ah;
  1668. mutex_lock(&sc->mutex);
  1669. ah->coverage_class = coverage_class;
  1670. ath9k_hw_init_global_settings(ah);
  1671. mutex_unlock(&sc->mutex);
  1672. }
  1673. struct ieee80211_ops ath9k_ops = {
  1674. .tx = ath9k_tx,
  1675. .start = ath9k_start,
  1676. .stop = ath9k_stop,
  1677. .add_interface = ath9k_add_interface,
  1678. .remove_interface = ath9k_remove_interface,
  1679. .config = ath9k_config,
  1680. .configure_filter = ath9k_configure_filter,
  1681. .sta_add = ath9k_sta_add,
  1682. .sta_remove = ath9k_sta_remove,
  1683. .conf_tx = ath9k_conf_tx,
  1684. .bss_info_changed = ath9k_bss_info_changed,
  1685. .set_key = ath9k_set_key,
  1686. .get_tsf = ath9k_get_tsf,
  1687. .set_tsf = ath9k_set_tsf,
  1688. .reset_tsf = ath9k_reset_tsf,
  1689. .ampdu_action = ath9k_ampdu_action,
  1690. .get_survey = ath9k_get_survey,
  1691. .sw_scan_start = ath9k_sw_scan_start,
  1692. .sw_scan_complete = ath9k_sw_scan_complete,
  1693. .rfkill_poll = ath9k_rfkill_poll_state,
  1694. .set_coverage_class = ath9k_set_coverage_class,
  1695. };