main.c 58 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static u8 parse_mpdudensity(u8 mpdudensity)
  21. {
  22. /*
  23. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  24. * 0 for no restriction
  25. * 1 for 1/4 us
  26. * 2 for 1/2 us
  27. * 3 for 1 us
  28. * 4 for 2 us
  29. * 5 for 4 us
  30. * 6 for 8 us
  31. * 7 for 16 us
  32. */
  33. switch (mpdudensity) {
  34. case 0:
  35. return 0;
  36. case 1:
  37. case 2:
  38. case 3:
  39. /* Our lower layer calculations limit our precision to
  40. 1 microsecond */
  41. return 1;
  42. case 4:
  43. return 2;
  44. case 5:
  45. return 4;
  46. case 6:
  47. return 8;
  48. case 7:
  49. return 16;
  50. default:
  51. return 0;
  52. }
  53. }
  54. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  55. {
  56. bool pending = false;
  57. spin_lock_bh(&txq->axq_lock);
  58. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  59. pending = true;
  60. else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  61. pending = !list_empty(&txq->txq_fifo_pending);
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. spin_unlock(&common->cc_lock);
  94. }
  95. unlock:
  96. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  97. }
  98. void ath9k_ps_restore(struct ath_softc *sc)
  99. {
  100. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  101. unsigned long flags;
  102. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  103. if (--sc->ps_usecount != 0)
  104. goto unlock;
  105. spin_lock(&common->cc_lock);
  106. ath_hw_cycle_counters_update(common);
  107. spin_unlock(&common->cc_lock);
  108. if (sc->ps_idle)
  109. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  110. else if (sc->ps_enabled &&
  111. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  112. PS_WAIT_FOR_CAB |
  113. PS_WAIT_FOR_PSPOLL_DATA |
  114. PS_WAIT_FOR_TX_ACK)))
  115. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  116. unlock:
  117. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  118. }
  119. static void ath_start_ani(struct ath_common *common)
  120. {
  121. struct ath_hw *ah = common->ah;
  122. unsigned long timestamp = jiffies_to_msecs(jiffies);
  123. struct ath_softc *sc = (struct ath_softc *) common->priv;
  124. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  125. return;
  126. if (sc->sc_flags & SC_OP_OFFCHANNEL)
  127. return;
  128. common->ani.longcal_timer = timestamp;
  129. common->ani.shortcal_timer = timestamp;
  130. common->ani.checkani_timer = timestamp;
  131. mod_timer(&common->ani.timer,
  132. jiffies +
  133. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  134. }
  135. static void ath_update_survey_nf(struct ath_softc *sc, int channel)
  136. {
  137. struct ath_hw *ah = sc->sc_ah;
  138. struct ath9k_channel *chan = &ah->channels[channel];
  139. struct survey_info *survey = &sc->survey[channel];
  140. if (chan->noisefloor) {
  141. survey->filled |= SURVEY_INFO_NOISE_DBM;
  142. survey->noise = chan->noisefloor;
  143. }
  144. }
  145. /*
  146. * Updates the survey statistics and returns the busy time since last
  147. * update in %, if the measurement duration was long enough for the
  148. * result to be useful, -1 otherwise.
  149. */
  150. static int ath_update_survey_stats(struct ath_softc *sc)
  151. {
  152. struct ath_hw *ah = sc->sc_ah;
  153. struct ath_common *common = ath9k_hw_common(ah);
  154. int pos = ah->curchan - &ah->channels[0];
  155. struct survey_info *survey = &sc->survey[pos];
  156. struct ath_cycle_counters *cc = &common->cc_survey;
  157. unsigned int div = common->clockrate * 1000;
  158. int ret = 0;
  159. if (!ah->curchan)
  160. return -1;
  161. if (ah->power_mode == ATH9K_PM_AWAKE)
  162. ath_hw_cycle_counters_update(common);
  163. if (cc->cycles > 0) {
  164. survey->filled |= SURVEY_INFO_CHANNEL_TIME |
  165. SURVEY_INFO_CHANNEL_TIME_BUSY |
  166. SURVEY_INFO_CHANNEL_TIME_RX |
  167. SURVEY_INFO_CHANNEL_TIME_TX;
  168. survey->channel_time += cc->cycles / div;
  169. survey->channel_time_busy += cc->rx_busy / div;
  170. survey->channel_time_rx += cc->rx_frame / div;
  171. survey->channel_time_tx += cc->tx_frame / div;
  172. }
  173. if (cc->cycles < div)
  174. return -1;
  175. if (cc->cycles > 0)
  176. ret = cc->rx_busy * 100 / cc->cycles;
  177. memset(cc, 0, sizeof(*cc));
  178. ath_update_survey_nf(sc, pos);
  179. return ret;
  180. }
  181. /*
  182. * Set/change channels. If the channel is really being changed, it's done
  183. * by reseting the chip. To accomplish this we must first cleanup any pending
  184. * DMA, then restart stuff.
  185. */
  186. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  187. struct ath9k_channel *hchan)
  188. {
  189. struct ath_hw *ah = sc->sc_ah;
  190. struct ath_common *common = ath9k_hw_common(ah);
  191. struct ieee80211_conf *conf = &common->hw->conf;
  192. bool fastcc = true, stopped;
  193. struct ieee80211_channel *channel = hw->conf.channel;
  194. struct ath9k_hw_cal_data *caldata = NULL;
  195. int r;
  196. if (sc->sc_flags & SC_OP_INVALID)
  197. return -EIO;
  198. sc->hw_busy_count = 0;
  199. del_timer_sync(&common->ani.timer);
  200. cancel_work_sync(&sc->paprd_work);
  201. cancel_work_sync(&sc->hw_check_work);
  202. cancel_delayed_work_sync(&sc->tx_complete_work);
  203. cancel_delayed_work_sync(&sc->hw_pll_work);
  204. ath9k_ps_wakeup(sc);
  205. spin_lock_bh(&sc->sc_pcu_lock);
  206. /*
  207. * This is only performed if the channel settings have
  208. * actually changed.
  209. *
  210. * To switch channels clear any pending DMA operations;
  211. * wait long enough for the RX fifo to drain, reset the
  212. * hardware at the new frequency, and then re-enable
  213. * the relevant bits of the h/w.
  214. */
  215. ath9k_hw_disable_interrupts(ah);
  216. stopped = ath_drain_all_txq(sc, false);
  217. if (!ath_stoprecv(sc))
  218. stopped = false;
  219. if (!ath9k_hw_check_alive(ah))
  220. stopped = false;
  221. /* XXX: do not flush receive queue here. We don't want
  222. * to flush data frames already in queue because of
  223. * changing channel. */
  224. if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
  225. fastcc = false;
  226. if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
  227. caldata = &sc->caldata;
  228. ath_dbg(common, ATH_DBG_CONFIG,
  229. "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
  230. sc->sc_ah->curchan->channel,
  231. channel->center_freq, conf_is_ht40(conf),
  232. fastcc);
  233. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  234. if (r) {
  235. ath_err(common,
  236. "Unable to reset channel (%u MHz), reset status %d\n",
  237. channel->center_freq, r);
  238. goto ps_restore;
  239. }
  240. if (ath_startrecv(sc) != 0) {
  241. ath_err(common, "Unable to restart recv logic\n");
  242. r = -EIO;
  243. goto ps_restore;
  244. }
  245. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  246. sc->config.txpowlimit, &sc->curtxpow);
  247. ath9k_hw_set_interrupts(ah, ah->imask);
  248. if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
  249. if (sc->sc_flags & SC_OP_BEACONS)
  250. ath_set_beacon(sc);
  251. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  252. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
  253. ath_start_ani(common);
  254. }
  255. ps_restore:
  256. ieee80211_wake_queues(hw);
  257. spin_unlock_bh(&sc->sc_pcu_lock);
  258. ath9k_ps_restore(sc);
  259. return r;
  260. }
  261. static void ath_paprd_activate(struct ath_softc *sc)
  262. {
  263. struct ath_hw *ah = sc->sc_ah;
  264. struct ath9k_hw_cal_data *caldata = ah->caldata;
  265. struct ath_common *common = ath9k_hw_common(ah);
  266. int chain;
  267. if (!caldata || !caldata->paprd_done)
  268. return;
  269. ath9k_ps_wakeup(sc);
  270. ar9003_paprd_enable(ah, false);
  271. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  272. if (!(common->tx_chainmask & BIT(chain)))
  273. continue;
  274. ar9003_paprd_populate_single_table(ah, caldata, chain);
  275. }
  276. ar9003_paprd_enable(ah, true);
  277. ath9k_ps_restore(sc);
  278. }
  279. static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
  280. {
  281. struct ieee80211_hw *hw = sc->hw;
  282. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
  283. struct ath_hw *ah = sc->sc_ah;
  284. struct ath_common *common = ath9k_hw_common(ah);
  285. struct ath_tx_control txctl;
  286. int time_left;
  287. memset(&txctl, 0, sizeof(txctl));
  288. txctl.txq = sc->tx.txq_map[WME_AC_BE];
  289. memset(tx_info, 0, sizeof(*tx_info));
  290. tx_info->band = hw->conf.channel->band;
  291. tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
  292. tx_info->control.rates[0].idx = 0;
  293. tx_info->control.rates[0].count = 1;
  294. tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
  295. tx_info->control.rates[1].idx = -1;
  296. init_completion(&sc->paprd_complete);
  297. txctl.paprd = BIT(chain);
  298. if (ath_tx_start(hw, skb, &txctl) != 0) {
  299. ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n");
  300. dev_kfree_skb_any(skb);
  301. return false;
  302. }
  303. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  304. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  305. if (!time_left)
  306. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
  307. "Timeout waiting for paprd training on TX chain %d\n",
  308. chain);
  309. return !!time_left;
  310. }
  311. void ath_paprd_calibrate(struct work_struct *work)
  312. {
  313. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  314. struct ieee80211_hw *hw = sc->hw;
  315. struct ath_hw *ah = sc->sc_ah;
  316. struct ieee80211_hdr *hdr;
  317. struct sk_buff *skb = NULL;
  318. struct ath9k_hw_cal_data *caldata = ah->caldata;
  319. struct ath_common *common = ath9k_hw_common(ah);
  320. int ftype;
  321. int chain_ok = 0;
  322. int chain;
  323. int len = 1800;
  324. if (!caldata)
  325. return;
  326. if (ar9003_paprd_init_table(ah) < 0)
  327. return;
  328. skb = alloc_skb(len, GFP_KERNEL);
  329. if (!skb)
  330. return;
  331. skb_put(skb, len);
  332. memset(skb->data, 0, len);
  333. hdr = (struct ieee80211_hdr *)skb->data;
  334. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  335. hdr->frame_control = cpu_to_le16(ftype);
  336. hdr->duration_id = cpu_to_le16(10);
  337. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  338. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  339. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  340. ath9k_ps_wakeup(sc);
  341. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  342. if (!(common->tx_chainmask & BIT(chain)))
  343. continue;
  344. chain_ok = 0;
  345. ath_dbg(common, ATH_DBG_CALIBRATE,
  346. "Sending PAPRD frame for thermal measurement "
  347. "on chain %d\n", chain);
  348. if (!ath_paprd_send_frame(sc, skb, chain))
  349. goto fail_paprd;
  350. ar9003_paprd_setup_gain_table(ah, chain);
  351. ath_dbg(common, ATH_DBG_CALIBRATE,
  352. "Sending PAPRD training frame on chain %d\n", chain);
  353. if (!ath_paprd_send_frame(sc, skb, chain))
  354. goto fail_paprd;
  355. if (!ar9003_paprd_is_done(ah))
  356. break;
  357. if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
  358. break;
  359. chain_ok = 1;
  360. }
  361. kfree_skb(skb);
  362. if (chain_ok) {
  363. caldata->paprd_done = true;
  364. ath_paprd_activate(sc);
  365. }
  366. fail_paprd:
  367. ath9k_ps_restore(sc);
  368. }
  369. /*
  370. * This routine performs the periodic noise floor calibration function
  371. * that is used to adjust and optimize the chip performance. This
  372. * takes environmental changes (location, temperature) into account.
  373. * When the task is complete, it reschedules itself depending on the
  374. * appropriate interval that was calculated.
  375. */
  376. void ath_ani_calibrate(unsigned long data)
  377. {
  378. struct ath_softc *sc = (struct ath_softc *)data;
  379. struct ath_hw *ah = sc->sc_ah;
  380. struct ath_common *common = ath9k_hw_common(ah);
  381. bool longcal = false;
  382. bool shortcal = false;
  383. bool aniflag = false;
  384. unsigned int timestamp = jiffies_to_msecs(jiffies);
  385. u32 cal_interval, short_cal_interval, long_cal_interval;
  386. unsigned long flags;
  387. if (ah->caldata && ah->caldata->nfcal_interference)
  388. long_cal_interval = ATH_LONG_CALINTERVAL_INT;
  389. else
  390. long_cal_interval = ATH_LONG_CALINTERVAL;
  391. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  392. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  393. /* Only calibrate if awake */
  394. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  395. goto set_timer;
  396. ath9k_ps_wakeup(sc);
  397. /* Long calibration runs independently of short calibration. */
  398. if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
  399. longcal = true;
  400. ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  401. common->ani.longcal_timer = timestamp;
  402. }
  403. /* Short calibration applies only while caldone is false */
  404. if (!common->ani.caldone) {
  405. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  406. shortcal = true;
  407. ath_dbg(common, ATH_DBG_ANI,
  408. "shortcal @%lu\n", jiffies);
  409. common->ani.shortcal_timer = timestamp;
  410. common->ani.resetcal_timer = timestamp;
  411. }
  412. } else {
  413. if ((timestamp - common->ani.resetcal_timer) >=
  414. ATH_RESTART_CALINTERVAL) {
  415. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  416. if (common->ani.caldone)
  417. common->ani.resetcal_timer = timestamp;
  418. }
  419. }
  420. /* Verify whether we must check ANI */
  421. if ((timestamp - common->ani.checkani_timer) >=
  422. ah->config.ani_poll_interval) {
  423. aniflag = true;
  424. common->ani.checkani_timer = timestamp;
  425. }
  426. /* Skip all processing if there's nothing to do. */
  427. if (longcal || shortcal || aniflag) {
  428. /* Call ANI routine if necessary */
  429. if (aniflag) {
  430. spin_lock_irqsave(&common->cc_lock, flags);
  431. ath9k_hw_ani_monitor(ah, ah->curchan);
  432. ath_update_survey_stats(sc);
  433. spin_unlock_irqrestore(&common->cc_lock, flags);
  434. }
  435. /* Perform calibration if necessary */
  436. if (longcal || shortcal) {
  437. common->ani.caldone =
  438. ath9k_hw_calibrate(ah,
  439. ah->curchan,
  440. common->rx_chainmask,
  441. longcal);
  442. }
  443. }
  444. ath9k_ps_restore(sc);
  445. set_timer:
  446. /*
  447. * Set timer interval based on previous results.
  448. * The interval must be the shortest necessary to satisfy ANI,
  449. * short calibration and long calibration.
  450. */
  451. cal_interval = ATH_LONG_CALINTERVAL;
  452. if (sc->sc_ah->config.enable_ani)
  453. cal_interval = min(cal_interval,
  454. (u32)ah->config.ani_poll_interval);
  455. if (!common->ani.caldone)
  456. cal_interval = min(cal_interval, (u32)short_cal_interval);
  457. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  458. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
  459. if (!ah->caldata->paprd_done)
  460. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  461. else if (!ah->paprd_table_write_done)
  462. ath_paprd_activate(sc);
  463. }
  464. }
  465. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  466. {
  467. struct ath_node *an;
  468. struct ath_hw *ah = sc->sc_ah;
  469. an = (struct ath_node *)sta->drv_priv;
  470. #ifdef CONFIG_ATH9K_DEBUGFS
  471. spin_lock(&sc->nodes_lock);
  472. list_add(&an->list, &sc->nodes);
  473. spin_unlock(&sc->nodes_lock);
  474. an->sta = sta;
  475. #endif
  476. if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
  477. sc->sc_flags |= SC_OP_ENABLE_APM;
  478. if (sc->sc_flags & SC_OP_TXAGGR) {
  479. ath_tx_node_init(sc, an);
  480. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  481. sta->ht_cap.ampdu_factor);
  482. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  483. }
  484. }
  485. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  486. {
  487. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  488. #ifdef CONFIG_ATH9K_DEBUGFS
  489. spin_lock(&sc->nodes_lock);
  490. list_del(&an->list);
  491. spin_unlock(&sc->nodes_lock);
  492. an->sta = NULL;
  493. #endif
  494. if (sc->sc_flags & SC_OP_TXAGGR)
  495. ath_tx_node_cleanup(sc, an);
  496. }
  497. void ath_hw_check(struct work_struct *work)
  498. {
  499. struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
  500. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  501. unsigned long flags;
  502. int busy;
  503. ath9k_ps_wakeup(sc);
  504. if (ath9k_hw_check_alive(sc->sc_ah))
  505. goto out;
  506. spin_lock_irqsave(&common->cc_lock, flags);
  507. busy = ath_update_survey_stats(sc);
  508. spin_unlock_irqrestore(&common->cc_lock, flags);
  509. ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
  510. "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
  511. if (busy >= 99) {
  512. if (++sc->hw_busy_count >= 3)
  513. ath_reset(sc, true);
  514. } else if (busy >= 0)
  515. sc->hw_busy_count = 0;
  516. out:
  517. ath9k_ps_restore(sc);
  518. }
  519. void ath_hw_pll_work(struct work_struct *work)
  520. {
  521. struct ath_softc *sc = container_of(work, struct ath_softc,
  522. hw_pll_work.work);
  523. static int count;
  524. if (AR_SREV_9485(sc->sc_ah)) {
  525. if (ar9003_get_pll_sqsum_dvc(sc->sc_ah) >= 0x40000) {
  526. count++;
  527. if (count == 3) {
  528. /* Rx is hung for more than 500ms. Reset it */
  529. ath_reset(sc, true);
  530. count = 0;
  531. }
  532. } else
  533. count = 0;
  534. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
  535. }
  536. }
  537. void ath9k_tasklet(unsigned long data)
  538. {
  539. struct ath_softc *sc = (struct ath_softc *)data;
  540. struct ath_hw *ah = sc->sc_ah;
  541. struct ath_common *common = ath9k_hw_common(ah);
  542. u32 status = sc->intrstatus;
  543. u32 rxmask;
  544. if (status & ATH9K_INT_FATAL) {
  545. ath_reset(sc, true);
  546. return;
  547. }
  548. ath9k_ps_wakeup(sc);
  549. spin_lock(&sc->sc_pcu_lock);
  550. /*
  551. * Only run the baseband hang check if beacons stop working in AP or
  552. * IBSS mode, because it has a high false positive rate. For station
  553. * mode it should not be necessary, since the upper layers will detect
  554. * this through a beacon miss automatically and the following channel
  555. * change will trigger a hardware reset anyway
  556. */
  557. if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
  558. !ath9k_hw_check_alive(ah))
  559. ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  560. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  561. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  562. ATH9K_INT_RXORN);
  563. else
  564. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  565. if (status & rxmask) {
  566. /* Check for high priority Rx first */
  567. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  568. (status & ATH9K_INT_RXHP))
  569. ath_rx_tasklet(sc, 0, true);
  570. ath_rx_tasklet(sc, 0, false);
  571. }
  572. if (status & ATH9K_INT_TX) {
  573. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  574. ath_tx_edma_tasklet(sc);
  575. else
  576. ath_tx_tasklet(sc);
  577. }
  578. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  579. /*
  580. * TSF sync does not look correct; remain awake to sync with
  581. * the next Beacon.
  582. */
  583. ath_dbg(common, ATH_DBG_PS,
  584. "TSFOOR - Sync with next Beacon\n");
  585. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  586. }
  587. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  588. if (status & ATH9K_INT_GENTIMER)
  589. ath_gen_timer_isr(sc->sc_ah);
  590. /* re-enable hardware interrupt */
  591. ath9k_hw_enable_interrupts(ah);
  592. spin_unlock(&sc->sc_pcu_lock);
  593. ath9k_ps_restore(sc);
  594. }
  595. irqreturn_t ath_isr(int irq, void *dev)
  596. {
  597. #define SCHED_INTR ( \
  598. ATH9K_INT_FATAL | \
  599. ATH9K_INT_RXORN | \
  600. ATH9K_INT_RXEOL | \
  601. ATH9K_INT_RX | \
  602. ATH9K_INT_RXLP | \
  603. ATH9K_INT_RXHP | \
  604. ATH9K_INT_TX | \
  605. ATH9K_INT_BMISS | \
  606. ATH9K_INT_CST | \
  607. ATH9K_INT_TSFOOR | \
  608. ATH9K_INT_GENTIMER)
  609. struct ath_softc *sc = dev;
  610. struct ath_hw *ah = sc->sc_ah;
  611. struct ath_common *common = ath9k_hw_common(ah);
  612. enum ath9k_int status;
  613. bool sched = false;
  614. /*
  615. * The hardware is not ready/present, don't
  616. * touch anything. Note this can happen early
  617. * on if the IRQ is shared.
  618. */
  619. if (sc->sc_flags & SC_OP_INVALID)
  620. return IRQ_NONE;
  621. /* shared irq, not for us */
  622. if (!ath9k_hw_intrpend(ah))
  623. return IRQ_NONE;
  624. /*
  625. * Figure out the reason(s) for the interrupt. Note
  626. * that the hal returns a pseudo-ISR that may include
  627. * bits we haven't explicitly enabled so we mask the
  628. * value to insure we only process bits we requested.
  629. */
  630. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  631. status &= ah->imask; /* discard unasked-for bits */
  632. /*
  633. * If there are no status bits set, then this interrupt was not
  634. * for me (should have been caught above).
  635. */
  636. if (!status)
  637. return IRQ_NONE;
  638. /* Cache the status */
  639. sc->intrstatus = status;
  640. if (status & SCHED_INTR)
  641. sched = true;
  642. /*
  643. * If a FATAL or RXORN interrupt is received, we have to reset the
  644. * chip immediately.
  645. */
  646. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  647. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  648. goto chip_reset;
  649. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  650. (status & ATH9K_INT_BB_WATCHDOG)) {
  651. spin_lock(&common->cc_lock);
  652. ath_hw_cycle_counters_update(common);
  653. ar9003_hw_bb_watchdog_dbg_info(ah);
  654. spin_unlock(&common->cc_lock);
  655. goto chip_reset;
  656. }
  657. if (status & ATH9K_INT_SWBA)
  658. tasklet_schedule(&sc->bcon_tasklet);
  659. if (status & ATH9K_INT_TXURN)
  660. ath9k_hw_updatetxtriglevel(ah, true);
  661. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  662. if (status & ATH9K_INT_RXEOL) {
  663. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  664. ath9k_hw_set_interrupts(ah, ah->imask);
  665. }
  666. }
  667. if (status & ATH9K_INT_MIB) {
  668. /*
  669. * Disable interrupts until we service the MIB
  670. * interrupt; otherwise it will continue to
  671. * fire.
  672. */
  673. ath9k_hw_disable_interrupts(ah);
  674. /*
  675. * Let the hal handle the event. We assume
  676. * it will clear whatever condition caused
  677. * the interrupt.
  678. */
  679. spin_lock(&common->cc_lock);
  680. ath9k_hw_proc_mib_event(ah);
  681. spin_unlock(&common->cc_lock);
  682. ath9k_hw_enable_interrupts(ah);
  683. }
  684. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  685. if (status & ATH9K_INT_TIM_TIMER) {
  686. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  687. goto chip_reset;
  688. /* Clear RxAbort bit so that we can
  689. * receive frames */
  690. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  691. ath9k_hw_setrxabort(sc->sc_ah, 0);
  692. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  693. }
  694. chip_reset:
  695. ath_debug_stat_interrupt(sc, status);
  696. if (sched) {
  697. /* turn off every interrupt */
  698. ath9k_hw_disable_interrupts(ah);
  699. tasklet_schedule(&sc->intr_tq);
  700. }
  701. return IRQ_HANDLED;
  702. #undef SCHED_INTR
  703. }
  704. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  705. {
  706. struct ath_hw *ah = sc->sc_ah;
  707. struct ath_common *common = ath9k_hw_common(ah);
  708. struct ieee80211_channel *channel = hw->conf.channel;
  709. int r;
  710. ath9k_ps_wakeup(sc);
  711. spin_lock_bh(&sc->sc_pcu_lock);
  712. ath9k_hw_configpcipowersave(ah, 0, 0);
  713. if (!ah->curchan)
  714. ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
  715. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  716. if (r) {
  717. ath_err(common,
  718. "Unable to reset channel (%u MHz), reset status %d\n",
  719. channel->center_freq, r);
  720. }
  721. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  722. sc->config.txpowlimit, &sc->curtxpow);
  723. if (ath_startrecv(sc) != 0) {
  724. ath_err(common, "Unable to restart recv logic\n");
  725. goto out;
  726. }
  727. if (sc->sc_flags & SC_OP_BEACONS)
  728. ath_set_beacon(sc); /* restart beacons */
  729. /* Re-Enable interrupts */
  730. ath9k_hw_set_interrupts(ah, ah->imask);
  731. /* Enable LED */
  732. ath9k_hw_cfg_output(ah, ah->led_pin,
  733. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  734. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  735. ieee80211_wake_queues(hw);
  736. ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);
  737. out:
  738. spin_unlock_bh(&sc->sc_pcu_lock);
  739. ath9k_ps_restore(sc);
  740. }
  741. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  742. {
  743. struct ath_hw *ah = sc->sc_ah;
  744. struct ieee80211_channel *channel = hw->conf.channel;
  745. int r;
  746. ath9k_ps_wakeup(sc);
  747. cancel_delayed_work_sync(&sc->hw_pll_work);
  748. spin_lock_bh(&sc->sc_pcu_lock);
  749. ieee80211_stop_queues(hw);
  750. /*
  751. * Keep the LED on when the radio is disabled
  752. * during idle unassociated state.
  753. */
  754. if (!sc->ps_idle) {
  755. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  756. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  757. }
  758. /* Disable interrupts */
  759. ath9k_hw_disable_interrupts(ah);
  760. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  761. ath_stoprecv(sc); /* turn off frame recv */
  762. ath_flushrecv(sc); /* flush recv queue */
  763. if (!ah->curchan)
  764. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  765. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  766. if (r) {
  767. ath_err(ath9k_hw_common(sc->sc_ah),
  768. "Unable to reset channel (%u MHz), reset status %d\n",
  769. channel->center_freq, r);
  770. }
  771. ath9k_hw_phy_disable(ah);
  772. ath9k_hw_configpcipowersave(ah, 1, 1);
  773. spin_unlock_bh(&sc->sc_pcu_lock);
  774. ath9k_ps_restore(sc);
  775. }
  776. int ath_reset(struct ath_softc *sc, bool retry_tx)
  777. {
  778. struct ath_hw *ah = sc->sc_ah;
  779. struct ath_common *common = ath9k_hw_common(ah);
  780. struct ieee80211_hw *hw = sc->hw;
  781. int r;
  782. sc->hw_busy_count = 0;
  783. /* Stop ANI */
  784. del_timer_sync(&common->ani.timer);
  785. ath9k_ps_wakeup(sc);
  786. spin_lock_bh(&sc->sc_pcu_lock);
  787. ieee80211_stop_queues(hw);
  788. ath9k_hw_disable_interrupts(ah);
  789. ath_drain_all_txq(sc, retry_tx);
  790. ath_stoprecv(sc);
  791. ath_flushrecv(sc);
  792. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
  793. if (r)
  794. ath_err(common,
  795. "Unable to reset hardware; reset status %d\n", r);
  796. if (ath_startrecv(sc) != 0)
  797. ath_err(common, "Unable to start recv logic\n");
  798. /*
  799. * We may be doing a reset in response to a request
  800. * that changes the channel so update any state that
  801. * might change as a result.
  802. */
  803. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  804. sc->config.txpowlimit, &sc->curtxpow);
  805. if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
  806. ath_set_beacon(sc); /* restart beacons */
  807. ath9k_hw_set_interrupts(ah, ah->imask);
  808. if (retry_tx) {
  809. int i;
  810. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  811. if (ATH_TXQ_SETUP(sc, i)) {
  812. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  813. ath_txq_schedule(sc, &sc->tx.txq[i]);
  814. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  815. }
  816. }
  817. }
  818. ieee80211_wake_queues(hw);
  819. spin_unlock_bh(&sc->sc_pcu_lock);
  820. /* Start ANI */
  821. ath_start_ani(common);
  822. ath9k_ps_restore(sc);
  823. return r;
  824. }
  825. /**********************/
  826. /* mac80211 callbacks */
  827. /**********************/
  828. static int ath9k_start(struct ieee80211_hw *hw)
  829. {
  830. struct ath_softc *sc = hw->priv;
  831. struct ath_hw *ah = sc->sc_ah;
  832. struct ath_common *common = ath9k_hw_common(ah);
  833. struct ieee80211_channel *curchan = hw->conf.channel;
  834. struct ath9k_channel *init_channel;
  835. int r;
  836. ath_dbg(common, ATH_DBG_CONFIG,
  837. "Starting driver with initial channel: %d MHz\n",
  838. curchan->center_freq);
  839. ath9k_ps_wakeup(sc);
  840. mutex_lock(&sc->mutex);
  841. /* setup initial channel */
  842. sc->chan_idx = curchan->hw_value;
  843. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  844. /* Reset SERDES registers */
  845. ath9k_hw_configpcipowersave(ah, 0, 0);
  846. /*
  847. * The basic interface to setting the hardware in a good
  848. * state is ``reset''. On return the hardware is known to
  849. * be powered up and with interrupts disabled. This must
  850. * be followed by initialization of the appropriate bits
  851. * and then setup of the interrupt mask.
  852. */
  853. spin_lock_bh(&sc->sc_pcu_lock);
  854. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  855. if (r) {
  856. ath_err(common,
  857. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  858. r, curchan->center_freq);
  859. spin_unlock_bh(&sc->sc_pcu_lock);
  860. goto mutex_unlock;
  861. }
  862. /*
  863. * This is needed only to setup initial state
  864. * but it's best done after a reset.
  865. */
  866. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  867. sc->config.txpowlimit, &sc->curtxpow);
  868. /*
  869. * Setup the hardware after reset:
  870. * The receive engine is set going.
  871. * Frame transmit is handled entirely
  872. * in the frame output path; there's nothing to do
  873. * here except setup the interrupt mask.
  874. */
  875. if (ath_startrecv(sc) != 0) {
  876. ath_err(common, "Unable to start recv logic\n");
  877. r = -EIO;
  878. spin_unlock_bh(&sc->sc_pcu_lock);
  879. goto mutex_unlock;
  880. }
  881. spin_unlock_bh(&sc->sc_pcu_lock);
  882. /* Setup our intr mask. */
  883. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  884. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  885. ATH9K_INT_GLOBAL;
  886. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  887. ah->imask |= ATH9K_INT_RXHP |
  888. ATH9K_INT_RXLP |
  889. ATH9K_INT_BB_WATCHDOG;
  890. else
  891. ah->imask |= ATH9K_INT_RX;
  892. ah->imask |= ATH9K_INT_GTT;
  893. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  894. ah->imask |= ATH9K_INT_CST;
  895. sc->sc_flags &= ~SC_OP_INVALID;
  896. sc->sc_ah->is_monitoring = false;
  897. /* Disable BMISS interrupt when we're not associated */
  898. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  899. ath9k_hw_set_interrupts(ah, ah->imask);
  900. ieee80211_wake_queues(hw);
  901. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  902. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  903. !ah->btcoex_hw.enabled) {
  904. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  905. AR_STOMP_LOW_WLAN_WGHT);
  906. ath9k_hw_btcoex_enable(ah);
  907. if (common->bus_ops->bt_coex_prep)
  908. common->bus_ops->bt_coex_prep(common);
  909. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  910. ath9k_btcoex_timer_resume(sc);
  911. }
  912. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  913. common->bus_ops->extn_synch_en(common);
  914. mutex_unlock:
  915. mutex_unlock(&sc->mutex);
  916. ath9k_ps_restore(sc);
  917. return r;
  918. }
  919. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  920. {
  921. struct ath_softc *sc = hw->priv;
  922. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  923. struct ath_tx_control txctl;
  924. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  925. if (sc->ps_enabled) {
  926. /*
  927. * mac80211 does not set PM field for normal data frames, so we
  928. * need to update that based on the current PS mode.
  929. */
  930. if (ieee80211_is_data(hdr->frame_control) &&
  931. !ieee80211_is_nullfunc(hdr->frame_control) &&
  932. !ieee80211_has_pm(hdr->frame_control)) {
  933. ath_dbg(common, ATH_DBG_PS,
  934. "Add PM=1 for a TX frame while in PS mode\n");
  935. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  936. }
  937. }
  938. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  939. /*
  940. * We are using PS-Poll and mac80211 can request TX while in
  941. * power save mode. Need to wake up hardware for the TX to be
  942. * completed and if needed, also for RX of buffered frames.
  943. */
  944. ath9k_ps_wakeup(sc);
  945. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  946. ath9k_hw_setrxabort(sc->sc_ah, 0);
  947. if (ieee80211_is_pspoll(hdr->frame_control)) {
  948. ath_dbg(common, ATH_DBG_PS,
  949. "Sending PS-Poll to pick a buffered frame\n");
  950. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  951. } else {
  952. ath_dbg(common, ATH_DBG_PS,
  953. "Wake up to complete TX\n");
  954. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  955. }
  956. /*
  957. * The actual restore operation will happen only after
  958. * the sc_flags bit is cleared. We are just dropping
  959. * the ps_usecount here.
  960. */
  961. ath9k_ps_restore(sc);
  962. }
  963. memset(&txctl, 0, sizeof(struct ath_tx_control));
  964. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  965. ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  966. if (ath_tx_start(hw, skb, &txctl) != 0) {
  967. ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
  968. goto exit;
  969. }
  970. return;
  971. exit:
  972. dev_kfree_skb_any(skb);
  973. }
  974. static void ath9k_stop(struct ieee80211_hw *hw)
  975. {
  976. struct ath_softc *sc = hw->priv;
  977. struct ath_hw *ah = sc->sc_ah;
  978. struct ath_common *common = ath9k_hw_common(ah);
  979. mutex_lock(&sc->mutex);
  980. cancel_delayed_work_sync(&sc->tx_complete_work);
  981. cancel_delayed_work_sync(&sc->hw_pll_work);
  982. cancel_work_sync(&sc->paprd_work);
  983. cancel_work_sync(&sc->hw_check_work);
  984. if (sc->sc_flags & SC_OP_INVALID) {
  985. ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
  986. mutex_unlock(&sc->mutex);
  987. return;
  988. }
  989. /* Ensure HW is awake when we try to shut it down. */
  990. ath9k_ps_wakeup(sc);
  991. if (ah->btcoex_hw.enabled) {
  992. ath9k_hw_btcoex_disable(ah);
  993. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  994. ath9k_btcoex_timer_pause(sc);
  995. }
  996. spin_lock_bh(&sc->sc_pcu_lock);
  997. /* prevent tasklets to enable interrupts once we disable them */
  998. ah->imask &= ~ATH9K_INT_GLOBAL;
  999. /* make sure h/w will not generate any interrupt
  1000. * before setting the invalid flag. */
  1001. ath9k_hw_disable_interrupts(ah);
  1002. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1003. ath_drain_all_txq(sc, false);
  1004. ath_stoprecv(sc);
  1005. ath9k_hw_phy_disable(ah);
  1006. } else
  1007. sc->rx.rxlink = NULL;
  1008. if (sc->rx.frag) {
  1009. dev_kfree_skb_any(sc->rx.frag);
  1010. sc->rx.frag = NULL;
  1011. }
  1012. /* disable HAL and put h/w to sleep */
  1013. ath9k_hw_disable(ah);
  1014. ath9k_hw_configpcipowersave(ah, 1, 1);
  1015. spin_unlock_bh(&sc->sc_pcu_lock);
  1016. /* we can now sync irq and kill any running tasklets, since we already
  1017. * disabled interrupts and not holding a spin lock */
  1018. synchronize_irq(sc->irq);
  1019. tasklet_kill(&sc->intr_tq);
  1020. tasklet_kill(&sc->bcon_tasklet);
  1021. ath9k_ps_restore(sc);
  1022. sc->ps_idle = true;
  1023. ath_radio_disable(sc, hw);
  1024. sc->sc_flags |= SC_OP_INVALID;
  1025. mutex_unlock(&sc->mutex);
  1026. ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
  1027. }
  1028. bool ath9k_uses_beacons(int type)
  1029. {
  1030. switch (type) {
  1031. case NL80211_IFTYPE_AP:
  1032. case NL80211_IFTYPE_ADHOC:
  1033. case NL80211_IFTYPE_MESH_POINT:
  1034. return true;
  1035. default:
  1036. return false;
  1037. }
  1038. }
  1039. static void ath9k_reclaim_beacon(struct ath_softc *sc,
  1040. struct ieee80211_vif *vif)
  1041. {
  1042. struct ath_vif *avp = (void *)vif->drv_priv;
  1043. ath9k_set_beaconing_status(sc, false);
  1044. ath_beacon_return(sc, avp);
  1045. ath9k_set_beaconing_status(sc, true);
  1046. sc->sc_flags &= ~SC_OP_BEACONS;
  1047. }
  1048. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1049. {
  1050. struct ath9k_vif_iter_data *iter_data = data;
  1051. int i;
  1052. if (iter_data->hw_macaddr)
  1053. for (i = 0; i < ETH_ALEN; i++)
  1054. iter_data->mask[i] &=
  1055. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  1056. switch (vif->type) {
  1057. case NL80211_IFTYPE_AP:
  1058. iter_data->naps++;
  1059. break;
  1060. case NL80211_IFTYPE_STATION:
  1061. iter_data->nstations++;
  1062. break;
  1063. case NL80211_IFTYPE_ADHOC:
  1064. iter_data->nadhocs++;
  1065. break;
  1066. case NL80211_IFTYPE_MESH_POINT:
  1067. iter_data->nmeshes++;
  1068. break;
  1069. case NL80211_IFTYPE_WDS:
  1070. iter_data->nwds++;
  1071. break;
  1072. default:
  1073. iter_data->nothers++;
  1074. break;
  1075. }
  1076. }
  1077. /* Called with sc->mutex held. */
  1078. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  1079. struct ieee80211_vif *vif,
  1080. struct ath9k_vif_iter_data *iter_data)
  1081. {
  1082. struct ath_softc *sc = hw->priv;
  1083. struct ath_hw *ah = sc->sc_ah;
  1084. struct ath_common *common = ath9k_hw_common(ah);
  1085. /*
  1086. * Use the hardware MAC address as reference, the hardware uses it
  1087. * together with the BSSID mask when matching addresses.
  1088. */
  1089. memset(iter_data, 0, sizeof(*iter_data));
  1090. iter_data->hw_macaddr = common->macaddr;
  1091. memset(&iter_data->mask, 0xff, ETH_ALEN);
  1092. if (vif)
  1093. ath9k_vif_iter(iter_data, vif->addr, vif);
  1094. /* Get list of all active MAC addresses */
  1095. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  1096. iter_data);
  1097. }
  1098. /* Called with sc->mutex held. */
  1099. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  1100. struct ieee80211_vif *vif)
  1101. {
  1102. struct ath_softc *sc = hw->priv;
  1103. struct ath_hw *ah = sc->sc_ah;
  1104. struct ath_common *common = ath9k_hw_common(ah);
  1105. struct ath9k_vif_iter_data iter_data;
  1106. ath9k_calculate_iter_data(hw, vif, &iter_data);
  1107. ath9k_ps_wakeup(sc);
  1108. /* Set BSSID mask. */
  1109. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  1110. ath_hw_setbssidmask(common);
  1111. /* Set op-mode & TSF */
  1112. if (iter_data.naps > 0) {
  1113. ath9k_hw_set_tsfadjust(ah, 1);
  1114. sc->sc_flags |= SC_OP_TSF_RESET;
  1115. ah->opmode = NL80211_IFTYPE_AP;
  1116. } else {
  1117. ath9k_hw_set_tsfadjust(ah, 0);
  1118. sc->sc_flags &= ~SC_OP_TSF_RESET;
  1119. if (iter_data.nwds + iter_data.nmeshes)
  1120. ah->opmode = NL80211_IFTYPE_AP;
  1121. else if (iter_data.nadhocs)
  1122. ah->opmode = NL80211_IFTYPE_ADHOC;
  1123. else
  1124. ah->opmode = NL80211_IFTYPE_STATION;
  1125. }
  1126. /*
  1127. * Enable MIB interrupts when there are hardware phy counters.
  1128. */
  1129. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
  1130. if (ah->config.enable_ani)
  1131. ah->imask |= ATH9K_INT_MIB;
  1132. ah->imask |= ATH9K_INT_TSFOOR;
  1133. } else {
  1134. ah->imask &= ~ATH9K_INT_MIB;
  1135. ah->imask &= ~ATH9K_INT_TSFOOR;
  1136. }
  1137. ath9k_hw_set_interrupts(ah, ah->imask);
  1138. ath9k_ps_restore(sc);
  1139. /* Set up ANI */
  1140. if ((iter_data.naps + iter_data.nadhocs) > 0) {
  1141. sc->sc_flags |= SC_OP_ANI_RUN;
  1142. ath_start_ani(common);
  1143. } else {
  1144. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1145. del_timer_sync(&common->ani.timer);
  1146. }
  1147. }
  1148. /* Called with sc->mutex held, vif counts set up properly. */
  1149. static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
  1150. struct ieee80211_vif *vif)
  1151. {
  1152. struct ath_softc *sc = hw->priv;
  1153. ath9k_calculate_summary_state(hw, vif);
  1154. if (ath9k_uses_beacons(vif->type)) {
  1155. int error;
  1156. /* This may fail because upper levels do not have beacons
  1157. * properly configured yet. That's OK, we assume it
  1158. * will be properly configured and then we will be notified
  1159. * in the info_changed method and set up beacons properly
  1160. * there.
  1161. */
  1162. ath9k_set_beaconing_status(sc, false);
  1163. error = ath_beacon_alloc(sc, vif);
  1164. if (!error)
  1165. ath_beacon_config(sc, vif);
  1166. ath9k_set_beaconing_status(sc, true);
  1167. }
  1168. }
  1169. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1170. struct ieee80211_vif *vif)
  1171. {
  1172. struct ath_softc *sc = hw->priv;
  1173. struct ath_hw *ah = sc->sc_ah;
  1174. struct ath_common *common = ath9k_hw_common(ah);
  1175. int ret = 0;
  1176. mutex_lock(&sc->mutex);
  1177. switch (vif->type) {
  1178. case NL80211_IFTYPE_STATION:
  1179. case NL80211_IFTYPE_WDS:
  1180. case NL80211_IFTYPE_ADHOC:
  1181. case NL80211_IFTYPE_AP:
  1182. case NL80211_IFTYPE_MESH_POINT:
  1183. break;
  1184. default:
  1185. ath_err(common, "Interface type %d not yet supported\n",
  1186. vif->type);
  1187. ret = -EOPNOTSUPP;
  1188. goto out;
  1189. }
  1190. if (ath9k_uses_beacons(vif->type)) {
  1191. if (sc->nbcnvifs >= ATH_BCBUF) {
  1192. ath_err(common, "Not enough beacon buffers when adding"
  1193. " new interface of type: %i\n",
  1194. vif->type);
  1195. ret = -ENOBUFS;
  1196. goto out;
  1197. }
  1198. }
  1199. if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1200. ((vif->type == NL80211_IFTYPE_ADHOC) &&
  1201. sc->nvifs > 0)) {
  1202. ath_err(common, "Cannot create ADHOC interface when other"
  1203. " interfaces already exist.\n");
  1204. ret = -EINVAL;
  1205. goto out;
  1206. }
  1207. ath_dbg(common, ATH_DBG_CONFIG,
  1208. "Attach a VIF of type: %d\n", vif->type);
  1209. sc->nvifs++;
  1210. ath9k_do_vif_add_setup(hw, vif);
  1211. out:
  1212. mutex_unlock(&sc->mutex);
  1213. return ret;
  1214. }
  1215. static int ath9k_change_interface(struct ieee80211_hw *hw,
  1216. struct ieee80211_vif *vif,
  1217. enum nl80211_iftype new_type,
  1218. bool p2p)
  1219. {
  1220. struct ath_softc *sc = hw->priv;
  1221. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1222. int ret = 0;
  1223. ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
  1224. mutex_lock(&sc->mutex);
  1225. /* See if new interface type is valid. */
  1226. if ((new_type == NL80211_IFTYPE_ADHOC) &&
  1227. (sc->nvifs > 1)) {
  1228. ath_err(common, "When using ADHOC, it must be the only"
  1229. " interface.\n");
  1230. ret = -EINVAL;
  1231. goto out;
  1232. }
  1233. if (ath9k_uses_beacons(new_type) &&
  1234. !ath9k_uses_beacons(vif->type)) {
  1235. if (sc->nbcnvifs >= ATH_BCBUF) {
  1236. ath_err(common, "No beacon slot available\n");
  1237. ret = -ENOBUFS;
  1238. goto out;
  1239. }
  1240. }
  1241. /* Clean up old vif stuff */
  1242. if (ath9k_uses_beacons(vif->type))
  1243. ath9k_reclaim_beacon(sc, vif);
  1244. /* Add new settings */
  1245. vif->type = new_type;
  1246. vif->p2p = p2p;
  1247. ath9k_do_vif_add_setup(hw, vif);
  1248. out:
  1249. mutex_unlock(&sc->mutex);
  1250. return ret;
  1251. }
  1252. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1253. struct ieee80211_vif *vif)
  1254. {
  1255. struct ath_softc *sc = hw->priv;
  1256. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1257. ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1258. mutex_lock(&sc->mutex);
  1259. sc->nvifs--;
  1260. /* Reclaim beacon resources */
  1261. if (ath9k_uses_beacons(vif->type))
  1262. ath9k_reclaim_beacon(sc, vif);
  1263. ath9k_calculate_summary_state(hw, NULL);
  1264. mutex_unlock(&sc->mutex);
  1265. }
  1266. static void ath9k_enable_ps(struct ath_softc *sc)
  1267. {
  1268. struct ath_hw *ah = sc->sc_ah;
  1269. sc->ps_enabled = true;
  1270. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1271. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1272. ah->imask |= ATH9K_INT_TIM_TIMER;
  1273. ath9k_hw_set_interrupts(ah, ah->imask);
  1274. }
  1275. ath9k_hw_setrxabort(ah, 1);
  1276. }
  1277. }
  1278. static void ath9k_disable_ps(struct ath_softc *sc)
  1279. {
  1280. struct ath_hw *ah = sc->sc_ah;
  1281. sc->ps_enabled = false;
  1282. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  1283. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1284. ath9k_hw_setrxabort(ah, 0);
  1285. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1286. PS_WAIT_FOR_CAB |
  1287. PS_WAIT_FOR_PSPOLL_DATA |
  1288. PS_WAIT_FOR_TX_ACK);
  1289. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1290. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1291. ath9k_hw_set_interrupts(ah, ah->imask);
  1292. }
  1293. }
  1294. }
  1295. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1296. {
  1297. struct ath_softc *sc = hw->priv;
  1298. struct ath_hw *ah = sc->sc_ah;
  1299. struct ath_common *common = ath9k_hw_common(ah);
  1300. struct ieee80211_conf *conf = &hw->conf;
  1301. bool disable_radio = false;
  1302. mutex_lock(&sc->mutex);
  1303. /*
  1304. * Leave this as the first check because we need to turn on the
  1305. * radio if it was disabled before prior to processing the rest
  1306. * of the changes. Likewise we must only disable the radio towards
  1307. * the end.
  1308. */
  1309. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1310. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1311. if (!sc->ps_idle) {
  1312. ath_radio_enable(sc, hw);
  1313. ath_dbg(common, ATH_DBG_CONFIG,
  1314. "not-idle: enabling radio\n");
  1315. } else {
  1316. disable_radio = true;
  1317. }
  1318. }
  1319. /*
  1320. * We just prepare to enable PS. We have to wait until our AP has
  1321. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1322. * those ACKs and end up retransmitting the same null data frames.
  1323. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1324. */
  1325. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1326. unsigned long flags;
  1327. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1328. if (conf->flags & IEEE80211_CONF_PS)
  1329. ath9k_enable_ps(sc);
  1330. else
  1331. ath9k_disable_ps(sc);
  1332. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1333. }
  1334. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1335. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1336. ath_dbg(common, ATH_DBG_CONFIG,
  1337. "Monitor mode is enabled\n");
  1338. sc->sc_ah->is_monitoring = true;
  1339. } else {
  1340. ath_dbg(common, ATH_DBG_CONFIG,
  1341. "Monitor mode is disabled\n");
  1342. sc->sc_ah->is_monitoring = false;
  1343. }
  1344. }
  1345. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1346. struct ieee80211_channel *curchan = hw->conf.channel;
  1347. int pos = curchan->hw_value;
  1348. int old_pos = -1;
  1349. unsigned long flags;
  1350. if (ah->curchan)
  1351. old_pos = ah->curchan - &ah->channels[0];
  1352. if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  1353. sc->sc_flags |= SC_OP_OFFCHANNEL;
  1354. else
  1355. sc->sc_flags &= ~SC_OP_OFFCHANNEL;
  1356. ath_dbg(common, ATH_DBG_CONFIG,
  1357. "Set channel: %d MHz type: %d\n",
  1358. curchan->center_freq, conf->channel_type);
  1359. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  1360. curchan, conf->channel_type);
  1361. /* update survey stats for the old channel before switching */
  1362. spin_lock_irqsave(&common->cc_lock, flags);
  1363. ath_update_survey_stats(sc);
  1364. spin_unlock_irqrestore(&common->cc_lock, flags);
  1365. /*
  1366. * If the operating channel changes, change the survey in-use flags
  1367. * along with it.
  1368. * Reset the survey data for the new channel, unless we're switching
  1369. * back to the operating channel from an off-channel operation.
  1370. */
  1371. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  1372. sc->cur_survey != &sc->survey[pos]) {
  1373. if (sc->cur_survey)
  1374. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  1375. sc->cur_survey = &sc->survey[pos];
  1376. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  1377. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  1378. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  1379. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1380. }
  1381. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1382. ath_err(common, "Unable to set channel\n");
  1383. mutex_unlock(&sc->mutex);
  1384. return -EINVAL;
  1385. }
  1386. /*
  1387. * The most recent snapshot of channel->noisefloor for the old
  1388. * channel is only available after the hardware reset. Copy it to
  1389. * the survey stats now.
  1390. */
  1391. if (old_pos >= 0)
  1392. ath_update_survey_nf(sc, old_pos);
  1393. }
  1394. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1395. ath_dbg(common, ATH_DBG_CONFIG,
  1396. "Set power: %d\n", conf->power_level);
  1397. sc->config.txpowlimit = 2 * conf->power_level;
  1398. ath9k_ps_wakeup(sc);
  1399. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1400. sc->config.txpowlimit, &sc->curtxpow);
  1401. ath9k_ps_restore(sc);
  1402. }
  1403. if (disable_radio) {
  1404. ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1405. ath_radio_disable(sc, hw);
  1406. }
  1407. mutex_unlock(&sc->mutex);
  1408. return 0;
  1409. }
  1410. #define SUPPORTED_FILTERS \
  1411. (FIF_PROMISC_IN_BSS | \
  1412. FIF_ALLMULTI | \
  1413. FIF_CONTROL | \
  1414. FIF_PSPOLL | \
  1415. FIF_OTHER_BSS | \
  1416. FIF_BCN_PRBRESP_PROMISC | \
  1417. FIF_PROBE_REQ | \
  1418. FIF_FCSFAIL)
  1419. /* FIXME: sc->sc_full_reset ? */
  1420. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1421. unsigned int changed_flags,
  1422. unsigned int *total_flags,
  1423. u64 multicast)
  1424. {
  1425. struct ath_softc *sc = hw->priv;
  1426. u32 rfilt;
  1427. changed_flags &= SUPPORTED_FILTERS;
  1428. *total_flags &= SUPPORTED_FILTERS;
  1429. sc->rx.rxfilter = *total_flags;
  1430. ath9k_ps_wakeup(sc);
  1431. rfilt = ath_calcrxfilter(sc);
  1432. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1433. ath9k_ps_restore(sc);
  1434. ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1435. "Set HW RX filter: 0x%x\n", rfilt);
  1436. }
  1437. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1438. struct ieee80211_vif *vif,
  1439. struct ieee80211_sta *sta)
  1440. {
  1441. struct ath_softc *sc = hw->priv;
  1442. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1443. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1444. struct ieee80211_key_conf ps_key = { };
  1445. ath_node_attach(sc, sta);
  1446. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1447. return 0;
  1448. }
  1449. static void ath9k_del_ps_key(struct ath_softc *sc,
  1450. struct ieee80211_vif *vif,
  1451. struct ieee80211_sta *sta)
  1452. {
  1453. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1454. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1455. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1456. if (!an->ps_key)
  1457. return;
  1458. ath_key_delete(common, &ps_key);
  1459. }
  1460. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1461. struct ieee80211_vif *vif,
  1462. struct ieee80211_sta *sta)
  1463. {
  1464. struct ath_softc *sc = hw->priv;
  1465. ath9k_del_ps_key(sc, vif, sta);
  1466. ath_node_detach(sc, sta);
  1467. return 0;
  1468. }
  1469. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1470. struct ieee80211_vif *vif,
  1471. enum sta_notify_cmd cmd,
  1472. struct ieee80211_sta *sta)
  1473. {
  1474. struct ath_softc *sc = hw->priv;
  1475. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1476. switch (cmd) {
  1477. case STA_NOTIFY_SLEEP:
  1478. an->sleeping = true;
  1479. if (ath_tx_aggr_sleep(sc, an))
  1480. ieee80211_sta_set_tim(sta);
  1481. break;
  1482. case STA_NOTIFY_AWAKE:
  1483. an->sleeping = false;
  1484. ath_tx_aggr_wakeup(sc, an);
  1485. break;
  1486. }
  1487. }
  1488. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1489. const struct ieee80211_tx_queue_params *params)
  1490. {
  1491. struct ath_softc *sc = hw->priv;
  1492. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1493. struct ath_txq *txq;
  1494. struct ath9k_tx_queue_info qi;
  1495. int ret = 0;
  1496. if (queue >= WME_NUM_AC)
  1497. return 0;
  1498. txq = sc->tx.txq_map[queue];
  1499. mutex_lock(&sc->mutex);
  1500. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1501. qi.tqi_aifs = params->aifs;
  1502. qi.tqi_cwmin = params->cw_min;
  1503. qi.tqi_cwmax = params->cw_max;
  1504. qi.tqi_burstTime = params->txop;
  1505. ath_dbg(common, ATH_DBG_CONFIG,
  1506. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1507. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1508. params->cw_max, params->txop);
  1509. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1510. if (ret)
  1511. ath_err(common, "TXQ Update failed\n");
  1512. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1513. if (queue == WME_AC_BE && !ret)
  1514. ath_beaconq_config(sc);
  1515. mutex_unlock(&sc->mutex);
  1516. return ret;
  1517. }
  1518. static int ath9k_set_key(struct ieee80211_hw *hw,
  1519. enum set_key_cmd cmd,
  1520. struct ieee80211_vif *vif,
  1521. struct ieee80211_sta *sta,
  1522. struct ieee80211_key_conf *key)
  1523. {
  1524. struct ath_softc *sc = hw->priv;
  1525. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1526. int ret = 0;
  1527. if (ath9k_modparam_nohwcrypt)
  1528. return -ENOSPC;
  1529. if (vif->type == NL80211_IFTYPE_ADHOC &&
  1530. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1531. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1532. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1533. /*
  1534. * For now, disable hw crypto for the RSN IBSS group keys. This
  1535. * could be optimized in the future to use a modified key cache
  1536. * design to support per-STA RX GTK, but until that gets
  1537. * implemented, use of software crypto for group addressed
  1538. * frames is a acceptable to allow RSN IBSS to be used.
  1539. */
  1540. return -EOPNOTSUPP;
  1541. }
  1542. mutex_lock(&sc->mutex);
  1543. ath9k_ps_wakeup(sc);
  1544. ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1545. switch (cmd) {
  1546. case SET_KEY:
  1547. if (sta)
  1548. ath9k_del_ps_key(sc, vif, sta);
  1549. ret = ath_key_config(common, vif, sta, key);
  1550. if (ret >= 0) {
  1551. key->hw_key_idx = ret;
  1552. /* push IV and Michael MIC generation to stack */
  1553. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1554. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1555. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1556. if (sc->sc_ah->sw_mgmt_crypto &&
  1557. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1558. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1559. ret = 0;
  1560. }
  1561. break;
  1562. case DISABLE_KEY:
  1563. ath_key_delete(common, key);
  1564. break;
  1565. default:
  1566. ret = -EINVAL;
  1567. }
  1568. ath9k_ps_restore(sc);
  1569. mutex_unlock(&sc->mutex);
  1570. return ret;
  1571. }
  1572. static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1573. {
  1574. struct ath_softc *sc = data;
  1575. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1576. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1577. struct ath_vif *avp = (void *)vif->drv_priv;
  1578. switch (sc->sc_ah->opmode) {
  1579. case NL80211_IFTYPE_ADHOC:
  1580. /* There can be only one vif available */
  1581. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1582. common->curaid = bss_conf->aid;
  1583. ath9k_hw_write_associd(sc->sc_ah);
  1584. /* configure beacon */
  1585. if (bss_conf->enable_beacon)
  1586. ath_beacon_config(sc, vif);
  1587. break;
  1588. case NL80211_IFTYPE_STATION:
  1589. /*
  1590. * Skip iteration if primary station vif's bss info
  1591. * was not changed
  1592. */
  1593. if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
  1594. break;
  1595. if (bss_conf->assoc) {
  1596. sc->sc_flags |= SC_OP_PRIM_STA_VIF;
  1597. avp->primary_sta_vif = true;
  1598. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1599. common->curaid = bss_conf->aid;
  1600. ath9k_hw_write_associd(sc->sc_ah);
  1601. ath_dbg(common, ATH_DBG_CONFIG,
  1602. "Bss Info ASSOC %d, bssid: %pM\n",
  1603. bss_conf->aid, common->curbssid);
  1604. ath_beacon_config(sc, vif);
  1605. /* Reset rssi stats */
  1606. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1607. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1608. sc->sc_flags |= SC_OP_ANI_RUN;
  1609. ath_start_ani(common);
  1610. }
  1611. break;
  1612. default:
  1613. break;
  1614. }
  1615. }
  1616. static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
  1617. {
  1618. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1619. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1620. struct ath_vif *avp = (void *)vif->drv_priv;
  1621. /* Reconfigure bss info */
  1622. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1623. ath_dbg(common, ATH_DBG_CONFIG,
  1624. "Bss Info DISASSOC %d, bssid %pM\n",
  1625. common->curaid, common->curbssid);
  1626. sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
  1627. avp->primary_sta_vif = false;
  1628. memset(common->curbssid, 0, ETH_ALEN);
  1629. common->curaid = 0;
  1630. }
  1631. ieee80211_iterate_active_interfaces_atomic(
  1632. sc->hw, ath9k_bss_iter, sc);
  1633. /*
  1634. * None of station vifs are associated.
  1635. * Clear bssid & aid
  1636. */
  1637. if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
  1638. !(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
  1639. ath9k_hw_write_associd(sc->sc_ah);
  1640. /* Stop ANI */
  1641. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1642. del_timer_sync(&common->ani.timer);
  1643. }
  1644. }
  1645. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1646. struct ieee80211_vif *vif,
  1647. struct ieee80211_bss_conf *bss_conf,
  1648. u32 changed)
  1649. {
  1650. struct ath_softc *sc = hw->priv;
  1651. struct ath_hw *ah = sc->sc_ah;
  1652. struct ath_common *common = ath9k_hw_common(ah);
  1653. struct ath_vif *avp = (void *)vif->drv_priv;
  1654. int slottime;
  1655. int error;
  1656. mutex_lock(&sc->mutex);
  1657. if (changed & BSS_CHANGED_BSSID) {
  1658. ath9k_config_bss(sc, vif);
  1659. /* Set aggregation protection mode parameters */
  1660. sc->config.ath_aggr_prot = 0;
  1661. ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
  1662. common->curbssid, common->curaid);
  1663. }
  1664. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1665. if ((changed & BSS_CHANGED_BEACON) ||
  1666. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1667. ath9k_set_beaconing_status(sc, false);
  1668. error = ath_beacon_alloc(sc, vif);
  1669. if (!error)
  1670. ath_beacon_config(sc, vif);
  1671. ath9k_set_beaconing_status(sc, true);
  1672. }
  1673. if (changed & BSS_CHANGED_ERP_SLOT) {
  1674. if (bss_conf->use_short_slot)
  1675. slottime = 9;
  1676. else
  1677. slottime = 20;
  1678. if (vif->type == NL80211_IFTYPE_AP) {
  1679. /*
  1680. * Defer update, so that connected stations can adjust
  1681. * their settings at the same time.
  1682. * See beacon.c for more details
  1683. */
  1684. sc->beacon.slottime = slottime;
  1685. sc->beacon.updateslot = UPDATE;
  1686. } else {
  1687. ah->slottime = slottime;
  1688. ath9k_hw_init_global_settings(ah);
  1689. }
  1690. }
  1691. /* Disable transmission of beacons */
  1692. if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
  1693. !bss_conf->enable_beacon) {
  1694. ath9k_set_beaconing_status(sc, false);
  1695. avp->is_bslot_active = false;
  1696. ath9k_set_beaconing_status(sc, true);
  1697. }
  1698. if (changed & BSS_CHANGED_BEACON_INT) {
  1699. /*
  1700. * In case of AP mode, the HW TSF has to be reset
  1701. * when the beacon interval changes.
  1702. */
  1703. if (vif->type == NL80211_IFTYPE_AP) {
  1704. sc->sc_flags |= SC_OP_TSF_RESET;
  1705. ath9k_set_beaconing_status(sc, false);
  1706. error = ath_beacon_alloc(sc, vif);
  1707. if (!error)
  1708. ath_beacon_config(sc, vif);
  1709. ath9k_set_beaconing_status(sc, true);
  1710. } else
  1711. ath_beacon_config(sc, vif);
  1712. }
  1713. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1714. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1715. bss_conf->use_short_preamble);
  1716. if (bss_conf->use_short_preamble)
  1717. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1718. else
  1719. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1720. }
  1721. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1722. ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1723. bss_conf->use_cts_prot);
  1724. if (bss_conf->use_cts_prot &&
  1725. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1726. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1727. else
  1728. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1729. }
  1730. mutex_unlock(&sc->mutex);
  1731. }
  1732. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1733. {
  1734. struct ath_softc *sc = hw->priv;
  1735. u64 tsf;
  1736. mutex_lock(&sc->mutex);
  1737. ath9k_ps_wakeup(sc);
  1738. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1739. ath9k_ps_restore(sc);
  1740. mutex_unlock(&sc->mutex);
  1741. return tsf;
  1742. }
  1743. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1744. {
  1745. struct ath_softc *sc = hw->priv;
  1746. mutex_lock(&sc->mutex);
  1747. ath9k_ps_wakeup(sc);
  1748. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1749. ath9k_ps_restore(sc);
  1750. mutex_unlock(&sc->mutex);
  1751. }
  1752. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1753. {
  1754. struct ath_softc *sc = hw->priv;
  1755. mutex_lock(&sc->mutex);
  1756. ath9k_ps_wakeup(sc);
  1757. ath9k_hw_reset_tsf(sc->sc_ah);
  1758. ath9k_ps_restore(sc);
  1759. mutex_unlock(&sc->mutex);
  1760. }
  1761. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1762. struct ieee80211_vif *vif,
  1763. enum ieee80211_ampdu_mlme_action action,
  1764. struct ieee80211_sta *sta,
  1765. u16 tid, u16 *ssn, u8 buf_size)
  1766. {
  1767. struct ath_softc *sc = hw->priv;
  1768. int ret = 0;
  1769. local_bh_disable();
  1770. switch (action) {
  1771. case IEEE80211_AMPDU_RX_START:
  1772. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1773. ret = -ENOTSUPP;
  1774. break;
  1775. case IEEE80211_AMPDU_RX_STOP:
  1776. break;
  1777. case IEEE80211_AMPDU_TX_START:
  1778. if (!(sc->sc_flags & SC_OP_TXAGGR))
  1779. return -EOPNOTSUPP;
  1780. ath9k_ps_wakeup(sc);
  1781. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1782. if (!ret)
  1783. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1784. ath9k_ps_restore(sc);
  1785. break;
  1786. case IEEE80211_AMPDU_TX_STOP:
  1787. ath9k_ps_wakeup(sc);
  1788. ath_tx_aggr_stop(sc, sta, tid);
  1789. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1790. ath9k_ps_restore(sc);
  1791. break;
  1792. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1793. ath9k_ps_wakeup(sc);
  1794. ath_tx_aggr_resume(sc, sta, tid);
  1795. ath9k_ps_restore(sc);
  1796. break;
  1797. default:
  1798. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1799. }
  1800. local_bh_enable();
  1801. return ret;
  1802. }
  1803. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1804. struct survey_info *survey)
  1805. {
  1806. struct ath_softc *sc = hw->priv;
  1807. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1808. struct ieee80211_supported_band *sband;
  1809. struct ieee80211_channel *chan;
  1810. unsigned long flags;
  1811. int pos;
  1812. spin_lock_irqsave(&common->cc_lock, flags);
  1813. if (idx == 0)
  1814. ath_update_survey_stats(sc);
  1815. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1816. if (sband && idx >= sband->n_channels) {
  1817. idx -= sband->n_channels;
  1818. sband = NULL;
  1819. }
  1820. if (!sband)
  1821. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1822. if (!sband || idx >= sband->n_channels) {
  1823. spin_unlock_irqrestore(&common->cc_lock, flags);
  1824. return -ENOENT;
  1825. }
  1826. chan = &sband->channels[idx];
  1827. pos = chan->hw_value;
  1828. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1829. survey->channel = chan;
  1830. spin_unlock_irqrestore(&common->cc_lock, flags);
  1831. return 0;
  1832. }
  1833. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1834. {
  1835. struct ath_softc *sc = hw->priv;
  1836. struct ath_hw *ah = sc->sc_ah;
  1837. mutex_lock(&sc->mutex);
  1838. ah->coverage_class = coverage_class;
  1839. ath9k_hw_init_global_settings(ah);
  1840. mutex_unlock(&sc->mutex);
  1841. }
  1842. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1843. {
  1844. struct ath_softc *sc = hw->priv;
  1845. int timeout = 200; /* ms */
  1846. int i, j;
  1847. mutex_lock(&sc->mutex);
  1848. cancel_delayed_work_sync(&sc->tx_complete_work);
  1849. if (drop)
  1850. timeout = 1;
  1851. for (j = 0; j < timeout; j++) {
  1852. int npend = 0;
  1853. if (j)
  1854. usleep_range(1000, 2000);
  1855. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1856. if (!ATH_TXQ_SETUP(sc, i))
  1857. continue;
  1858. npend += ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1859. }
  1860. if (!npend)
  1861. goto out;
  1862. }
  1863. ath9k_ps_wakeup(sc);
  1864. if (!ath_drain_all_txq(sc, false))
  1865. ath_reset(sc, false);
  1866. ath9k_ps_restore(sc);
  1867. ieee80211_wake_queues(hw);
  1868. out:
  1869. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1870. mutex_unlock(&sc->mutex);
  1871. }
  1872. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1873. {
  1874. struct ath_softc *sc = hw->priv;
  1875. int i;
  1876. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1877. if (!ATH_TXQ_SETUP(sc, i))
  1878. continue;
  1879. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1880. return true;
  1881. }
  1882. return false;
  1883. }
  1884. struct ieee80211_ops ath9k_ops = {
  1885. .tx = ath9k_tx,
  1886. .start = ath9k_start,
  1887. .stop = ath9k_stop,
  1888. .add_interface = ath9k_add_interface,
  1889. .change_interface = ath9k_change_interface,
  1890. .remove_interface = ath9k_remove_interface,
  1891. .config = ath9k_config,
  1892. .configure_filter = ath9k_configure_filter,
  1893. .sta_add = ath9k_sta_add,
  1894. .sta_remove = ath9k_sta_remove,
  1895. .sta_notify = ath9k_sta_notify,
  1896. .conf_tx = ath9k_conf_tx,
  1897. .bss_info_changed = ath9k_bss_info_changed,
  1898. .set_key = ath9k_set_key,
  1899. .get_tsf = ath9k_get_tsf,
  1900. .set_tsf = ath9k_set_tsf,
  1901. .reset_tsf = ath9k_reset_tsf,
  1902. .ampdu_action = ath9k_ampdu_action,
  1903. .get_survey = ath9k_get_survey,
  1904. .rfkill_poll = ath9k_rfkill_poll_state,
  1905. .set_coverage_class = ath9k_set_coverage_class,
  1906. .flush = ath9k_flush,
  1907. .tx_frames_pending = ath9k_tx_frames_pending,
  1908. };