zc0301_pas202bcb.c 11 KB

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  1. /***************************************************************************
  2. * Plug-in for PAS202BCB image sensor connected to the ZC030! Image *
  3. * Processor and Control Chip *
  4. * *
  5. * Copyright (C) 2006 by Luca Risolia <luca.risolia@studio.unibo.it> *
  6. * *
  7. * Initialization values of the ZC0301 have been taken from the SPCA5XX *
  8. * driver maintained by Michel Xhaard <mxhaard@magic.fr> *
  9. * *
  10. * This program is free software; you can redistribute it and/or modify *
  11. * it under the terms of the GNU General Public License as published by *
  12. * the Free Software Foundation; either version 2 of the License, or *
  13. * (at your option) any later version. *
  14. * *
  15. * This program is distributed in the hope that it will be useful, *
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  18. * GNU General Public License for more details. *
  19. * *
  20. * You should have received a copy of the GNU General Public License *
  21. * along with this program; if not, write to the Free Software *
  22. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  23. ***************************************************************************/
  24. #include <linux/delay.h>
  25. #include "zc0301_sensor.h"
  26. static struct zc0301_sensor pas202bcb;
  27. static int pas202bcb_init(struct zc0301_device* cam)
  28. {
  29. int err = 0;
  30. err += zc0301_write_reg(cam, 0x0002, 0x00);
  31. err += zc0301_write_reg(cam, 0x0003, 0x02);
  32. err += zc0301_write_reg(cam, 0x0004, 0x80);
  33. err += zc0301_write_reg(cam, 0x0005, 0x01);
  34. err += zc0301_write_reg(cam, 0x0006, 0xE0);
  35. err += zc0301_write_reg(cam, 0x0098, 0x00);
  36. err += zc0301_write_reg(cam, 0x009A, 0x03);
  37. err += zc0301_write_reg(cam, 0x011A, 0x00);
  38. err += zc0301_write_reg(cam, 0x011C, 0x03);
  39. err += zc0301_write_reg(cam, 0x009B, 0x01);
  40. err += zc0301_write_reg(cam, 0x009C, 0xE6);
  41. err += zc0301_write_reg(cam, 0x009D, 0x02);
  42. err += zc0301_write_reg(cam, 0x009E, 0x86);
  43. err += zc0301_i2c_write(cam, 0x02, 0x02);
  44. err += zc0301_i2c_write(cam, 0x0A, 0x01);
  45. err += zc0301_i2c_write(cam, 0x0B, 0x01);
  46. err += zc0301_i2c_write(cam, 0x0D, 0x00);
  47. err += zc0301_i2c_write(cam, 0x12, 0x05);
  48. err += zc0301_i2c_write(cam, 0x13, 0x63);
  49. err += zc0301_i2c_write(cam, 0x15, 0x70);
  50. err += zc0301_write_reg(cam, 0x0101, 0xB7);
  51. err += zc0301_write_reg(cam, 0x0100, 0x0D);
  52. err += zc0301_write_reg(cam, 0x0189, 0x06);
  53. err += zc0301_write_reg(cam, 0x01AD, 0x00);
  54. err += zc0301_write_reg(cam, 0x01C5, 0x03);
  55. err += zc0301_write_reg(cam, 0x01CB, 0x13);
  56. err += zc0301_write_reg(cam, 0x0250, 0x08);
  57. err += zc0301_write_reg(cam, 0x0301, 0x08);
  58. err += zc0301_write_reg(cam, 0x018D, 0x70);
  59. err += zc0301_write_reg(cam, 0x0008, 0x03);
  60. err += zc0301_write_reg(cam, 0x01C6, 0x04);
  61. err += zc0301_write_reg(cam, 0x01CB, 0x07);
  62. err += zc0301_write_reg(cam, 0x0120, 0x11);
  63. err += zc0301_write_reg(cam, 0x0121, 0x37);
  64. err += zc0301_write_reg(cam, 0x0122, 0x58);
  65. err += zc0301_write_reg(cam, 0x0123, 0x79);
  66. err += zc0301_write_reg(cam, 0x0124, 0x91);
  67. err += zc0301_write_reg(cam, 0x0125, 0xA6);
  68. err += zc0301_write_reg(cam, 0x0126, 0xB8);
  69. err += zc0301_write_reg(cam, 0x0127, 0xC7);
  70. err += zc0301_write_reg(cam, 0x0128, 0xD3);
  71. err += zc0301_write_reg(cam, 0x0129, 0xDE);
  72. err += zc0301_write_reg(cam, 0x012A, 0xE6);
  73. err += zc0301_write_reg(cam, 0x012B, 0xED);
  74. err += zc0301_write_reg(cam, 0x012C, 0xF3);
  75. err += zc0301_write_reg(cam, 0x012D, 0xF8);
  76. err += zc0301_write_reg(cam, 0x012E, 0xFB);
  77. err += zc0301_write_reg(cam, 0x012F, 0xFF);
  78. err += zc0301_write_reg(cam, 0x0130, 0x26);
  79. err += zc0301_write_reg(cam, 0x0131, 0x23);
  80. err += zc0301_write_reg(cam, 0x0132, 0x20);
  81. err += zc0301_write_reg(cam, 0x0133, 0x1C);
  82. err += zc0301_write_reg(cam, 0x0134, 0x16);
  83. err += zc0301_write_reg(cam, 0x0135, 0x13);
  84. err += zc0301_write_reg(cam, 0x0136, 0x10);
  85. err += zc0301_write_reg(cam, 0x0137, 0x0D);
  86. err += zc0301_write_reg(cam, 0x0138, 0x0B);
  87. err += zc0301_write_reg(cam, 0x0139, 0x09);
  88. err += zc0301_write_reg(cam, 0x013A, 0x07);
  89. err += zc0301_write_reg(cam, 0x013B, 0x06);
  90. err += zc0301_write_reg(cam, 0x013C, 0x05);
  91. err += zc0301_write_reg(cam, 0x013D, 0x04);
  92. err += zc0301_write_reg(cam, 0x013E, 0x03);
  93. err += zc0301_write_reg(cam, 0x013F, 0x02);
  94. err += zc0301_write_reg(cam, 0x010A, 0x4C);
  95. err += zc0301_write_reg(cam, 0x010B, 0xF5);
  96. err += zc0301_write_reg(cam, 0x010C, 0xFF);
  97. err += zc0301_write_reg(cam, 0x010D, 0xF9);
  98. err += zc0301_write_reg(cam, 0x010E, 0x51);
  99. err += zc0301_write_reg(cam, 0x010F, 0xF5);
  100. err += zc0301_write_reg(cam, 0x0110, 0xFB);
  101. err += zc0301_write_reg(cam, 0x0111, 0xED);
  102. err += zc0301_write_reg(cam, 0x0112, 0x5F);
  103. err += zc0301_write_reg(cam, 0x0180, 0x00);
  104. err += zc0301_write_reg(cam, 0x0019, 0x00);
  105. err += zc0301_write_reg(cam, 0x0087, 0x20);
  106. err += zc0301_write_reg(cam, 0x0088, 0x21);
  107. err += zc0301_i2c_write(cam, 0x20, 0x02);
  108. err += zc0301_i2c_write(cam, 0x21, 0x1B);
  109. err += zc0301_i2c_write(cam, 0x03, 0x44);
  110. err += zc0301_i2c_write(cam, 0x0E, 0x01);
  111. err += zc0301_i2c_write(cam, 0x0F, 0x00);
  112. err += zc0301_write_reg(cam, 0x01A9, 0x14);
  113. err += zc0301_write_reg(cam, 0x01AA, 0x24);
  114. err += zc0301_write_reg(cam, 0x0190, 0x00);
  115. err += zc0301_write_reg(cam, 0x0191, 0x02);
  116. err += zc0301_write_reg(cam, 0x0192, 0x1B);
  117. err += zc0301_write_reg(cam, 0x0195, 0x00);
  118. err += zc0301_write_reg(cam, 0x0196, 0x00);
  119. err += zc0301_write_reg(cam, 0x0197, 0x4D);
  120. err += zc0301_write_reg(cam, 0x018C, 0x10);
  121. err += zc0301_write_reg(cam, 0x018F, 0x20);
  122. err += zc0301_write_reg(cam, 0x001D, 0x44);
  123. err += zc0301_write_reg(cam, 0x001E, 0x6F);
  124. err += zc0301_write_reg(cam, 0x001F, 0xAD);
  125. err += zc0301_write_reg(cam, 0x0020, 0xEB);
  126. err += zc0301_write_reg(cam, 0x0087, 0x0F);
  127. err += zc0301_write_reg(cam, 0x0088, 0x0E);
  128. err += zc0301_write_reg(cam, 0x0180, 0x40);
  129. err += zc0301_write_reg(cam, 0x0192, 0x1B);
  130. err += zc0301_write_reg(cam, 0x0191, 0x02);
  131. err += zc0301_write_reg(cam, 0x0190, 0x00);
  132. err += zc0301_write_reg(cam, 0x0116, 0x1D);
  133. err += zc0301_write_reg(cam, 0x0117, 0x40);
  134. err += zc0301_write_reg(cam, 0x0118, 0x99);
  135. err += zc0301_write_reg(cam, 0x0180, 0x42);
  136. err += zc0301_write_reg(cam, 0x0116, 0x1D);
  137. err += zc0301_write_reg(cam, 0x0117, 0x40);
  138. err += zc0301_write_reg(cam, 0x0118, 0x99);
  139. err += zc0301_write_reg(cam, 0x0007, 0x00);
  140. err += zc0301_i2c_write(cam, 0x11, 0x01);
  141. msleep(100);
  142. return err;
  143. }
  144. static int pas202bcb_get_ctrl(struct zc0301_device* cam,
  145. struct v4l2_control* ctrl)
  146. {
  147. switch (ctrl->id) {
  148. case V4L2_CID_EXPOSURE:
  149. {
  150. int r1 = zc0301_i2c_read(cam, 0x04, 1),
  151. r2 = zc0301_i2c_read(cam, 0x05, 1);
  152. if (r1 < 0 || r2 < 0)
  153. return -EIO;
  154. ctrl->value = (r1 << 6) | (r2 & 0x3f);
  155. }
  156. return 0;
  157. case V4L2_CID_RED_BALANCE:
  158. if ((ctrl->value = zc0301_i2c_read(cam, 0x09, 1)) < 0)
  159. return -EIO;
  160. ctrl->value &= 0x0f;
  161. return 0;
  162. case V4L2_CID_BLUE_BALANCE:
  163. if ((ctrl->value = zc0301_i2c_read(cam, 0x07, 1)) < 0)
  164. return -EIO;
  165. ctrl->value &= 0x0f;
  166. return 0;
  167. case V4L2_CID_GAIN:
  168. if ((ctrl->value = zc0301_i2c_read(cam, 0x10, 1)) < 0)
  169. return -EIO;
  170. ctrl->value &= 0x1f;
  171. return 0;
  172. case ZC0301_V4L2_CID_GREEN_BALANCE:
  173. if ((ctrl->value = zc0301_i2c_read(cam, 0x08, 1)) < 0)
  174. return -EIO;
  175. ctrl->value &= 0x0f;
  176. return 0;
  177. case ZC0301_V4L2_CID_DAC_MAGNITUDE:
  178. if ((ctrl->value = zc0301_i2c_read(cam, 0x0c, 1)) < 0)
  179. return -EIO;
  180. return 0;
  181. default:
  182. return -EINVAL;
  183. }
  184. }
  185. static int pas202bcb_set_ctrl(struct zc0301_device* cam,
  186. const struct v4l2_control* ctrl)
  187. {
  188. int err = 0;
  189. switch (ctrl->id) {
  190. case V4L2_CID_EXPOSURE:
  191. err += zc0301_i2c_write(cam, 0x04, ctrl->value >> 6);
  192. err += zc0301_i2c_write(cam, 0x05, ctrl->value & 0x3f);
  193. break;
  194. case V4L2_CID_RED_BALANCE:
  195. err += zc0301_i2c_write(cam, 0x09, ctrl->value);
  196. break;
  197. case V4L2_CID_BLUE_BALANCE:
  198. err += zc0301_i2c_write(cam, 0x07, ctrl->value);
  199. break;
  200. case V4L2_CID_GAIN:
  201. err += zc0301_i2c_write(cam, 0x10, ctrl->value);
  202. break;
  203. case ZC0301_V4L2_CID_GREEN_BALANCE:
  204. err += zc0301_i2c_write(cam, 0x08, ctrl->value);
  205. break;
  206. case ZC0301_V4L2_CID_DAC_MAGNITUDE:
  207. err += zc0301_i2c_write(cam, 0x0c, ctrl->value);
  208. break;
  209. default:
  210. return -EINVAL;
  211. }
  212. err += zc0301_i2c_write(cam, 0x11, 0x01);
  213. return err ? -EIO : 0;
  214. }
  215. static struct zc0301_sensor pas202bcb = {
  216. .name = "PAS202BCB",
  217. .init = &pas202bcb_init,
  218. .qctrl = {
  219. {
  220. .id = V4L2_CID_EXPOSURE,
  221. .type = V4L2_CTRL_TYPE_INTEGER,
  222. .name = "exposure",
  223. .minimum = 0x01e5,
  224. .maximum = 0x3fff,
  225. .step = 0x0001,
  226. .default_value = 0x01e5,
  227. .flags = 0,
  228. },
  229. {
  230. .id = V4L2_CID_GAIN,
  231. .type = V4L2_CTRL_TYPE_INTEGER,
  232. .name = "global gain",
  233. .minimum = 0x00,
  234. .maximum = 0x1f,
  235. .step = 0x01,
  236. .default_value = 0x0c,
  237. .flags = 0,
  238. },
  239. {
  240. .id = V4L2_CID_RED_BALANCE,
  241. .type = V4L2_CTRL_TYPE_INTEGER,
  242. .name = "red balance",
  243. .minimum = 0x00,
  244. .maximum = 0x0f,
  245. .step = 0x01,
  246. .default_value = 0x01,
  247. .flags = 0,
  248. },
  249. {
  250. .id = V4L2_CID_BLUE_BALANCE,
  251. .type = V4L2_CTRL_TYPE_INTEGER,
  252. .name = "blue balance",
  253. .minimum = 0x00,
  254. .maximum = 0x0f,
  255. .step = 0x01,
  256. .default_value = 0x05,
  257. .flags = 0,
  258. },
  259. {
  260. .id = ZC0301_V4L2_CID_GREEN_BALANCE,
  261. .type = V4L2_CTRL_TYPE_INTEGER,
  262. .name = "green balance",
  263. .minimum = 0x00,
  264. .maximum = 0x0f,
  265. .step = 0x01,
  266. .default_value = 0x00,
  267. .flags = 0,
  268. },
  269. {
  270. .id = ZC0301_V4L2_CID_DAC_MAGNITUDE,
  271. .type = V4L2_CTRL_TYPE_INTEGER,
  272. .name = "DAC magnitude",
  273. .minimum = 0x00,
  274. .maximum = 0xff,
  275. .step = 0x01,
  276. .default_value = 0x04,
  277. .flags = 0,
  278. },
  279. },
  280. .get_ctrl = &pas202bcb_get_ctrl,
  281. .set_ctrl = &pas202bcb_set_ctrl,
  282. .cropcap = {
  283. .bounds = {
  284. .left = 0,
  285. .top = 0,
  286. .width = 640,
  287. .height = 480,
  288. },
  289. .defrect = {
  290. .left = 0,
  291. .top = 0,
  292. .width = 640,
  293. .height = 480,
  294. },
  295. },
  296. .pix_format = {
  297. .width = 640,
  298. .height = 480,
  299. .pixelformat = V4L2_PIX_FMT_JPEG,
  300. .priv = 8,
  301. },
  302. };
  303. int zc0301_probe_pas202bcb(struct zc0301_device* cam)
  304. {
  305. int r0 = 0, r1 = 0, err = 0;
  306. unsigned int pid = 0;
  307. err += zc0301_write_reg(cam, 0x0000, 0x01);
  308. err += zc0301_write_reg(cam, 0x0010, 0x0e);
  309. err += zc0301_write_reg(cam, 0x0001, 0x01);
  310. err += zc0301_write_reg(cam, 0x0012, 0x03);
  311. err += zc0301_write_reg(cam, 0x0012, 0x01);
  312. err += zc0301_write_reg(cam, 0x008d, 0x08);
  313. msleep(10);
  314. r0 = zc0301_i2c_read(cam, 0x00, 1);
  315. r1 = zc0301_i2c_read(cam, 0x01, 1);
  316. if (r0 < 0 || r1 < 0 || err)
  317. return -EIO;
  318. pid = (r0 << 4) | ((r1 & 0xf0) >> 4);
  319. if (pid != 0x017)
  320. return -ENODEV;
  321. zc0301_attach_sensor(cam, &pas202bcb);
  322. return 0;
  323. }