at91sam9263.dtsi 8.0 KB

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  1. /*
  2. * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
  3. *
  4. * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5. *
  6. * Licensed under GPLv2 only.
  7. */
  8. /include/ "skeleton.dtsi"
  9. / {
  10. model = "Atmel AT91SAM9263 family SoC";
  11. compatible = "atmel,at91sam9263";
  12. interrupt-parent = <&aic>;
  13. aliases {
  14. serial0 = &dbgu;
  15. serial1 = &usart0;
  16. serial2 = &usart1;
  17. serial3 = &usart2;
  18. gpio0 = &pioA;
  19. gpio1 = &pioB;
  20. gpio2 = &pioC;
  21. gpio3 = &pioD;
  22. gpio4 = &pioE;
  23. tcb0 = &tcb0;
  24. i2c0 = &i2c0;
  25. };
  26. cpus {
  27. cpu@0 {
  28. compatible = "arm,arm926ejs";
  29. };
  30. };
  31. memory {
  32. reg = <0x20000000 0x08000000>;
  33. };
  34. ahb {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. ranges;
  39. apb {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. ranges;
  44. aic: interrupt-controller@fffff000 {
  45. #interrupt-cells = <3>;
  46. compatible = "atmel,at91rm9200-aic";
  47. interrupt-controller;
  48. reg = <0xfffff000 0x200>;
  49. atmel,external-irqs = <30 31>;
  50. };
  51. pmc: pmc@fffffc00 {
  52. compatible = "atmel,at91rm9200-pmc";
  53. reg = <0xfffffc00 0x100>;
  54. };
  55. ramc: ramc@ffffe200 {
  56. compatible = "atmel,at91sam9260-sdramc";
  57. reg = <0xffffe200 0x200
  58. 0xffffe800 0x200>;
  59. };
  60. pit: timer@fffffd30 {
  61. compatible = "atmel,at91sam9260-pit";
  62. reg = <0xfffffd30 0xf>;
  63. interrupts = <1 4 7>;
  64. };
  65. tcb0: timer@fff7c000 {
  66. compatible = "atmel,at91rm9200-tcb";
  67. reg = <0xfff7c000 0x100>;
  68. interrupts = <19 4 0>;
  69. };
  70. rstc@fffffd00 {
  71. compatible = "atmel,at91sam9260-rstc";
  72. reg = <0xfffffd00 0x10>;
  73. };
  74. shdwc@fffffd10 {
  75. compatible = "atmel,at91sam9260-shdwc";
  76. reg = <0xfffffd10 0x10>;
  77. };
  78. pinctrl@fffff200 {
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  82. ranges = <0xfffff200 0xfffff200 0xa00>;
  83. atmel,mux-mask = <
  84. /* A B */
  85. 0xfffffffb 0xffffe07f /* pioA */
  86. 0x0007ffff 0x39072fff /* pioB */
  87. 0xffffffff 0x3ffffff8 /* pioC */
  88. 0xfffffbff 0xffffffff /* pioD */
  89. 0xffe00fff 0xfbfcff00 /* pioE */
  90. >;
  91. /* shared pinctrl settings */
  92. dbgu {
  93. pinctrl_dbgu: dbgu-0 {
  94. atmel,pins =
  95. <2 30 0x1 0x0 /* PC30 periph A */
  96. 2 31 0x1 0x1>; /* PC31 periph with pullup */
  97. };
  98. };
  99. usart0 {
  100. pinctrl_usart0: usart0-0 {
  101. atmel,pins =
  102. <0 26 0x1 0x1 /* PA26 periph A with pullup */
  103. 0 27 0x1 0x0>; /* PA27 periph A */
  104. };
  105. pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
  106. atmel,pins =
  107. <0 28 0x1 0x0 /* PA28 periph A */
  108. 0 29 0x1 0x0>; /* PA29 periph A */
  109. };
  110. };
  111. usart1 {
  112. pinctrl_usart1: usart1-0 {
  113. atmel,pins =
  114. <3 0 0x1 0x1 /* PD0 periph A with pullup */
  115. 3 1 0x1 0x0>; /* PD1 periph A */
  116. };
  117. pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
  118. atmel,pins =
  119. <3 7 0x2 0x0 /* PD7 periph B */
  120. 3 8 0x2 0x0>; /* PD8 periph B */
  121. };
  122. };
  123. usart2 {
  124. pinctrl_usart2: usart2-0 {
  125. atmel,pins =
  126. <3 2 0x1 0x1 /* PD2 periph A with pullup */
  127. 3 3 0x1 0x0>; /* PD3 periph A */
  128. };
  129. pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
  130. atmel,pins =
  131. <3 5 0x2 0x0 /* PD5 periph B */
  132. 4 6 0x2 0x0>; /* PD6 periph B */
  133. };
  134. };
  135. nand {
  136. pinctrl_nand: nand-0 {
  137. atmel,pins =
  138. <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
  139. 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
  140. };
  141. };
  142. macb {
  143. pinctrl_macb_rmii: macb_rmii-0 {
  144. atmel,pins =
  145. <2 25 0x2 0x0 /* PC25 periph B */
  146. 4 21 0x1 0x0 /* PE21 periph A */
  147. 4 23 0x1 0x0 /* PE23 periph A */
  148. 4 24 0x1 0x0 /* PE24 periph A */
  149. 4 25 0x1 0x0 /* PE25 periph A */
  150. 4 26 0x1 0x0 /* PE26 periph A */
  151. 4 27 0x1 0x0 /* PE27 periph A */
  152. 4 28 0x1 0x0 /* PE28 periph A */
  153. 4 29 0x1 0x0 /* PE29 periph A */
  154. 4 30 0x1 0x0>; /* PE30 periph A */
  155. };
  156. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  157. atmel,pins =
  158. <2 20 0x2 0x0 /* PC20 periph B */
  159. 2 21 0x2 0x0 /* PC21 periph B */
  160. 2 22 0x2 0x0 /* PC22 periph B */
  161. 2 23 0x2 0x0 /* PC23 periph B */
  162. 2 24 0x2 0x0 /* PC24 periph B */
  163. 2 25 0x2 0x0 /* PC25 periph B */
  164. 2 27 0x2 0x0 /* PC27 periph B */
  165. 4 22 0x2 0x0>; /* PE22 periph B */
  166. };
  167. };
  168. pioA: gpio@fffff200 {
  169. compatible = "atmel,at91rm9200-gpio";
  170. reg = <0xfffff200 0x200>;
  171. interrupts = <2 4 1>;
  172. #gpio-cells = <2>;
  173. gpio-controller;
  174. interrupt-controller;
  175. #interrupt-cells = <2>;
  176. };
  177. pioB: gpio@fffff400 {
  178. compatible = "atmel,at91rm9200-gpio";
  179. reg = <0xfffff400 0x200>;
  180. interrupts = <3 4 1>;
  181. #gpio-cells = <2>;
  182. gpio-controller;
  183. interrupt-controller;
  184. #interrupt-cells = <2>;
  185. };
  186. pioC: gpio@fffff600 {
  187. compatible = "atmel,at91rm9200-gpio";
  188. reg = <0xfffff600 0x200>;
  189. interrupts = <4 4 1>;
  190. #gpio-cells = <2>;
  191. gpio-controller;
  192. interrupt-controller;
  193. #interrupt-cells = <2>;
  194. };
  195. pioD: gpio@fffff800 {
  196. compatible = "atmel,at91rm9200-gpio";
  197. reg = <0xfffff800 0x200>;
  198. interrupts = <4 4 1>;
  199. #gpio-cells = <2>;
  200. gpio-controller;
  201. interrupt-controller;
  202. #interrupt-cells = <2>;
  203. };
  204. pioE: gpio@fffffa00 {
  205. compatible = "atmel,at91rm9200-gpio";
  206. reg = <0xfffffa00 0x200>;
  207. interrupts = <4 4 1>;
  208. #gpio-cells = <2>;
  209. gpio-controller;
  210. interrupt-controller;
  211. #interrupt-cells = <2>;
  212. };
  213. };
  214. dbgu: serial@ffffee00 {
  215. compatible = "atmel,at91sam9260-usart";
  216. reg = <0xffffee00 0x200>;
  217. interrupts = <1 4 7>;
  218. pinctrl-names = "default";
  219. pinctrl-0 = <&pinctrl_dbgu>;
  220. status = "disabled";
  221. };
  222. usart0: serial@fff8c000 {
  223. compatible = "atmel,at91sam9260-usart";
  224. reg = <0xfff8c000 0x200>;
  225. interrupts = <7 4 5>;
  226. atmel,use-dma-rx;
  227. atmel,use-dma-tx;
  228. pinctrl-names = "default";
  229. pinctrl-0 = <&pinctrl_usart0>;
  230. status = "disabled";
  231. };
  232. usart1: serial@fff90000 {
  233. compatible = "atmel,at91sam9260-usart";
  234. reg = <0xfff90000 0x200>;
  235. interrupts = <8 4 5>;
  236. atmel,use-dma-rx;
  237. atmel,use-dma-tx;
  238. pinctrl-names = "default";
  239. pinctrl-0 = <&pinctrl_usart1>;
  240. status = "disabled";
  241. };
  242. usart2: serial@fff94000 {
  243. compatible = "atmel,at91sam9260-usart";
  244. reg = <0xfff94000 0x200>;
  245. interrupts = <9 4 5>;
  246. atmel,use-dma-rx;
  247. atmel,use-dma-tx;
  248. pinctrl-names = "default";
  249. pinctrl-0 = <&pinctrl_usart2>;
  250. status = "disabled";
  251. };
  252. macb0: ethernet@fffbc000 {
  253. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  254. reg = <0xfffbc000 0x100>;
  255. interrupts = <21 4 3>;
  256. pinctrl-names = "default";
  257. pinctrl-0 = <&pinctrl_macb_rmii>;
  258. status = "disabled";
  259. };
  260. usb1: gadget@fff78000 {
  261. compatible = "atmel,at91rm9200-udc";
  262. reg = <0xfff78000 0x4000>;
  263. interrupts = <24 4 2>;
  264. status = "disabled";
  265. };
  266. i2c0: i2c@fff88000 {
  267. compatible = "atmel,at91sam9263-i2c";
  268. reg = <0xfff88000 0x100>;
  269. interrupts = <13 4 6>;
  270. #address-cells = <1>;
  271. #size-cells = <0>;
  272. status = "disabled";
  273. };
  274. };
  275. nand0: nand@40000000 {
  276. compatible = "atmel,at91rm9200-nand";
  277. #address-cells = <1>;
  278. #size-cells = <1>;
  279. reg = <0x40000000 0x10000000
  280. 0xffffe000 0x200
  281. >;
  282. atmel,nand-addr-offset = <21>;
  283. atmel,nand-cmd-offset = <22>;
  284. pinctrl-names = "default";
  285. pinctrl-0 = <&pinctrl_nand>;
  286. gpios = <&pioA 22 0
  287. &pioD 15 0
  288. 0
  289. >;
  290. status = "disabled";
  291. };
  292. usb0: ohci@00a00000 {
  293. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  294. reg = <0x00a00000 0x100000>;
  295. interrupts = <29 4 2>;
  296. status = "disabled";
  297. };
  298. };
  299. i2c@0 {
  300. compatible = "i2c-gpio";
  301. gpios = <&pioB 4 0 /* sda */
  302. &pioB 5 0 /* scl */
  303. >;
  304. i2c-gpio,sda-open-drain;
  305. i2c-gpio,scl-open-drain;
  306. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  307. #address-cells = <1>;
  308. #size-cells = <0>;
  309. status = "disabled";
  310. };
  311. };