mci.c 15 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include <linux/slab.h>
  18. #include "ath9k.h"
  19. #include "mci.h"
  20. static const u8 ath_mci_duty_cycle[] = { 0, 50, 60, 70, 80, 85, 90, 95, 98 };
  21. static struct ath_mci_profile_info*
  22. ath_mci_find_profile(struct ath_mci_profile *mci,
  23. struct ath_mci_profile_info *info)
  24. {
  25. struct ath_mci_profile_info *entry;
  26. if (list_empty(&mci->info))
  27. return NULL;
  28. list_for_each_entry(entry, &mci->info, list) {
  29. if (entry->conn_handle == info->conn_handle)
  30. return entry;
  31. }
  32. return NULL;
  33. }
  34. static bool ath_mci_add_profile(struct ath_common *common,
  35. struct ath_mci_profile *mci,
  36. struct ath_mci_profile_info *info)
  37. {
  38. struct ath_mci_profile_info *entry;
  39. if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
  40. (info->type == MCI_GPM_COEX_PROFILE_VOICE))
  41. return false;
  42. if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
  43. (info->type != MCI_GPM_COEX_PROFILE_VOICE))
  44. return false;
  45. entry = kzalloc(sizeof(*entry), GFP_KERNEL);
  46. if (!entry)
  47. return false;
  48. memcpy(entry, info, 10);
  49. INC_PROF(mci, info);
  50. list_add_tail(&entry->list, &mci->info);
  51. return true;
  52. }
  53. static void ath_mci_del_profile(struct ath_common *common,
  54. struct ath_mci_profile *mci,
  55. struct ath_mci_profile_info *entry)
  56. {
  57. if (!entry)
  58. return;
  59. DEC_PROF(mci, entry);
  60. list_del(&entry->list);
  61. kfree(entry);
  62. }
  63. void ath_mci_flush_profile(struct ath_mci_profile *mci)
  64. {
  65. struct ath_mci_profile_info *info, *tinfo;
  66. mci->aggr_limit = 0;
  67. if (list_empty(&mci->info))
  68. return;
  69. list_for_each_entry_safe(info, tinfo, &mci->info, list) {
  70. list_del(&info->list);
  71. DEC_PROF(mci, info);
  72. kfree(info);
  73. }
  74. }
  75. static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
  76. {
  77. struct ath_mci_profile *mci = &btcoex->mci;
  78. u32 wlan_airtime = btcoex->btcoex_period *
  79. (100 - btcoex->duty_cycle) / 100;
  80. /*
  81. * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
  82. * When wlan_airtime is less than 4ms, aggregation limit has to be
  83. * adjusted half of wlan_airtime to ensure that the aggregation can fit
  84. * without collision with BT traffic.
  85. */
  86. if ((wlan_airtime <= 4) &&
  87. (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
  88. mci->aggr_limit = 2 * wlan_airtime;
  89. }
  90. static void ath_mci_update_scheme(struct ath_softc *sc)
  91. {
  92. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  93. struct ath_btcoex *btcoex = &sc->btcoex;
  94. struct ath_mci_profile *mci = &btcoex->mci;
  95. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  96. struct ath_mci_profile_info *info;
  97. u32 num_profile = NUM_PROF(mci);
  98. if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
  99. goto skip_tuning;
  100. if (num_profile == 1) {
  101. info = list_first_entry(&mci->info,
  102. struct ath_mci_profile_info,
  103. list);
  104. if (mci->num_sco) {
  105. if (info->T == 12)
  106. mci->aggr_limit = 8;
  107. else if (info->T == 6) {
  108. mci->aggr_limit = 6;
  109. btcoex->duty_cycle = 30;
  110. }
  111. ath_dbg(common, MCI,
  112. "Single SCO, aggregation limit %d 1/4 ms\n",
  113. mci->aggr_limit);
  114. } else if (mci->num_pan || mci->num_other_acl) {
  115. /*
  116. * For single PAN/FTP profile, allocate 35% for BT
  117. * to improve WLAN throughput.
  118. */
  119. btcoex->duty_cycle = 35;
  120. btcoex->btcoex_period = 53;
  121. ath_dbg(common, MCI,
  122. "Single PAN/FTP bt period %d ms dutycycle %d\n",
  123. btcoex->duty_cycle, btcoex->btcoex_period);
  124. } else if (mci->num_hid) {
  125. btcoex->duty_cycle = 30;
  126. mci->aggr_limit = 6;
  127. ath_dbg(common, MCI,
  128. "Multiple attempt/timeout single HID "
  129. "aggregation limit 1.5 ms dutycycle 30%%\n");
  130. }
  131. } else if (num_profile == 2) {
  132. if (mci->num_hid == 2)
  133. btcoex->duty_cycle = 30;
  134. mci->aggr_limit = 6;
  135. ath_dbg(common, MCI,
  136. "Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
  137. btcoex->duty_cycle);
  138. } else if (num_profile >= 3) {
  139. mci->aggr_limit = 4;
  140. ath_dbg(common, MCI,
  141. "Three or more profiles aggregation limit 1 ms\n");
  142. }
  143. skip_tuning:
  144. if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
  145. if (IS_CHAN_HT(sc->sc_ah->curchan))
  146. ath_mci_adjust_aggr_limit(btcoex);
  147. else
  148. btcoex->btcoex_period >>= 1;
  149. }
  150. ath9k_hw_btcoex_disable(sc->sc_ah);
  151. ath9k_btcoex_timer_pause(sc);
  152. if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
  153. return;
  154. btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_MAX_DUTY_CYCLE : 0);
  155. if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
  156. btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
  157. btcoex->btcoex_period *= 1000;
  158. btcoex->btcoex_no_stomp = btcoex->btcoex_period *
  159. (100 - btcoex->duty_cycle) / 100;
  160. ath9k_hw_btcoex_enable(sc->sc_ah);
  161. ath9k_btcoex_timer_resume(sc);
  162. }
  163. static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  164. {
  165. struct ath_hw *ah = sc->sc_ah;
  166. struct ath_common *common = ath9k_hw_common(ah);
  167. u32 payload[4] = {0, 0, 0, 0};
  168. switch (opcode) {
  169. case MCI_GPM_BT_CAL_REQ:
  170. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
  171. ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL);
  172. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  173. } else {
  174. ath_dbg(common, MCI, "MCI State mismatch: %d\n",
  175. ar9003_mci_state(ah, MCI_STATE_BT, NULL));
  176. }
  177. break;
  178. case MCI_GPM_BT_CAL_DONE:
  179. ar9003_mci_state(ah, MCI_STATE_BT, NULL);
  180. break;
  181. case MCI_GPM_BT_CAL_GRANT:
  182. MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
  183. ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
  184. 16, false, true);
  185. break;
  186. default:
  187. ath_dbg(common, MCI, "Unknown GPM CAL message\n");
  188. break;
  189. }
  190. }
  191. static void ath_mci_process_profile(struct ath_softc *sc,
  192. struct ath_mci_profile_info *info)
  193. {
  194. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  195. struct ath_btcoex *btcoex = &sc->btcoex;
  196. struct ath_mci_profile *mci = &btcoex->mci;
  197. struct ath_mci_profile_info *entry = NULL;
  198. entry = ath_mci_find_profile(mci, info);
  199. if (entry)
  200. memcpy(entry, info, 10);
  201. if (info->start) {
  202. if (!entry && !ath_mci_add_profile(common, mci, info))
  203. return;
  204. } else
  205. ath_mci_del_profile(common, mci, entry);
  206. btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
  207. mci->aggr_limit = mci->num_sco ? 6 : 0;
  208. if (NUM_PROF(mci)) {
  209. btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
  210. btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
  211. } else {
  212. btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
  213. ATH_BTCOEX_STOMP_LOW;
  214. btcoex->duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE;
  215. }
  216. ath_mci_update_scheme(sc);
  217. }
  218. static void ath_mci_process_status(struct ath_softc *sc,
  219. struct ath_mci_profile_status *status)
  220. {
  221. struct ath_btcoex *btcoex = &sc->btcoex;
  222. struct ath_mci_profile *mci = &btcoex->mci;
  223. struct ath_mci_profile_info info;
  224. int i = 0, old_num_mgmt = mci->num_mgmt;
  225. /* Link status type are not handled */
  226. if (status->is_link)
  227. return;
  228. info.conn_handle = status->conn_handle;
  229. if (ath_mci_find_profile(mci, &info))
  230. return;
  231. if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
  232. return;
  233. if (status->is_critical)
  234. __set_bit(status->conn_handle, mci->status);
  235. else
  236. __clear_bit(status->conn_handle, mci->status);
  237. mci->num_mgmt = 0;
  238. do {
  239. if (test_bit(i, mci->status))
  240. mci->num_mgmt++;
  241. } while (++i < ATH_MCI_MAX_PROFILE);
  242. if (old_num_mgmt != mci->num_mgmt)
  243. ath_mci_update_scheme(sc);
  244. }
  245. static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  246. {
  247. struct ath_hw *ah = sc->sc_ah;
  248. struct ath_mci_profile_info profile_info;
  249. struct ath_mci_profile_status profile_status;
  250. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  251. u32 version;
  252. u8 major;
  253. u8 minor;
  254. u32 seq_num;
  255. switch (opcode) {
  256. case MCI_GPM_COEX_VERSION_QUERY:
  257. version = ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION,
  258. NULL);
  259. break;
  260. case MCI_GPM_COEX_VERSION_RESPONSE:
  261. major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
  262. minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
  263. version = (major << 8) + minor;
  264. version = ar9003_mci_state(ah, MCI_STATE_SET_BT_COEX_VERSION,
  265. &version);
  266. break;
  267. case MCI_GPM_COEX_STATUS_QUERY:
  268. ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_CHANNELS, NULL);
  269. break;
  270. case MCI_GPM_COEX_BT_PROFILE_INFO:
  271. memcpy(&profile_info,
  272. (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
  273. if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
  274. (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
  275. ath_dbg(common, MCI,
  276. "Illegal profile type = %d, state = %d\n",
  277. profile_info.type,
  278. profile_info.start);
  279. break;
  280. }
  281. ath_mci_process_profile(sc, &profile_info);
  282. break;
  283. case MCI_GPM_COEX_BT_STATUS_UPDATE:
  284. profile_status.is_link = *(rx_payload +
  285. MCI_GPM_COEX_B_STATUS_TYPE);
  286. profile_status.conn_handle = *(rx_payload +
  287. MCI_GPM_COEX_B_STATUS_LINKID);
  288. profile_status.is_critical = *(rx_payload +
  289. MCI_GPM_COEX_B_STATUS_STATE);
  290. seq_num = *((u32 *)(rx_payload + 12));
  291. ath_dbg(common, MCI,
  292. "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n",
  293. profile_status.is_link, profile_status.conn_handle,
  294. profile_status.is_critical, seq_num);
  295. ath_mci_process_status(sc, &profile_status);
  296. break;
  297. default:
  298. ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
  299. break;
  300. }
  301. }
  302. int ath_mci_setup(struct ath_softc *sc)
  303. {
  304. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  305. struct ath_mci_coex *mci = &sc->mci_coex;
  306. struct ath_mci_buf *buf = &mci->sched_buf;
  307. buf->bf_addr = dma_alloc_coherent(sc->dev,
  308. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  309. &buf->bf_paddr, GFP_KERNEL);
  310. if (buf->bf_addr == NULL) {
  311. ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
  312. return -ENOMEM;
  313. }
  314. memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
  315. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
  316. mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
  317. mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
  318. mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
  319. mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
  320. ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
  321. mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
  322. mci->sched_buf.bf_paddr);
  323. ath_dbg(common, MCI, "MCI Initialized\n");
  324. return 0;
  325. }
  326. void ath_mci_cleanup(struct ath_softc *sc)
  327. {
  328. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  329. struct ath_hw *ah = sc->sc_ah;
  330. struct ath_mci_coex *mci = &sc->mci_coex;
  331. struct ath_mci_buf *buf = &mci->sched_buf;
  332. if (buf->bf_addr)
  333. dma_free_coherent(sc->dev,
  334. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  335. buf->bf_addr, buf->bf_paddr);
  336. ar9003_mci_cleanup(ah);
  337. ath_dbg(common, MCI, "MCI De-Initialized\n");
  338. }
  339. void ath_mci_intr(struct ath_softc *sc)
  340. {
  341. struct ath_mci_coex *mci = &sc->mci_coex;
  342. struct ath_hw *ah = sc->sc_ah;
  343. struct ath_common *common = ath9k_hw_common(ah);
  344. u32 mci_int, mci_int_rxmsg;
  345. u32 offset, subtype, opcode;
  346. u32 *pgpm;
  347. u32 more_data = MCI_GPM_MORE;
  348. bool skip_gpm = false;
  349. ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
  350. if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) {
  351. ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL);
  352. return;
  353. }
  354. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
  355. u32 payload[4] = { 0xffffffff, 0xffffffff,
  356. 0xffffffff, 0xffffff00};
  357. /*
  358. * The following REMOTE_RESET and SYS_WAKING used to sent
  359. * only when BT wake up. Now they are always sent, as a
  360. * recovery method to reset BT MCI's RX alignment.
  361. */
  362. ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
  363. payload, 16, true, false);
  364. ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
  365. NULL, 0, true, false);
  366. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
  367. ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE, NULL);
  368. /*
  369. * always do this for recovery and 2G/5G toggling and LNA_TRANS
  370. */
  371. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL);
  372. }
  373. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
  374. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
  375. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_SLEEP) {
  376. if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) !=
  377. MCI_BT_SLEEP)
  378. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE,
  379. NULL);
  380. }
  381. }
  382. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
  383. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
  384. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
  385. if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) !=
  386. MCI_BT_AWAKE)
  387. ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP,
  388. NULL);
  389. }
  390. }
  391. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  392. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  393. ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL);
  394. skip_gpm = true;
  395. }
  396. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
  397. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
  398. offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET,
  399. NULL);
  400. }
  401. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
  402. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
  403. while (more_data == MCI_GPM_MORE) {
  404. pgpm = mci->gpm_buf.bf_addr;
  405. offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET,
  406. &more_data);
  407. if (offset == MCI_GPM_INVALID)
  408. break;
  409. pgpm += (offset >> 2);
  410. /*
  411. * The first dword is timer.
  412. * The real data starts from 2nd dword.
  413. */
  414. subtype = MCI_GPM_TYPE(pgpm);
  415. opcode = MCI_GPM_OPCODE(pgpm);
  416. if (skip_gpm)
  417. goto recycle;
  418. if (MCI_GPM_IS_CAL_TYPE(subtype)) {
  419. ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
  420. } else {
  421. switch (subtype) {
  422. case MCI_GPM_COEX_AGENT:
  423. ath_mci_msg(sc, opcode, (u8 *)pgpm);
  424. break;
  425. default:
  426. break;
  427. }
  428. }
  429. recycle:
  430. MCI_GPM_RECYCLE(pgpm);
  431. }
  432. }
  433. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
  434. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
  435. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
  436. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
  437. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
  438. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
  439. int value_dbm = ar9003_mci_state(ah,
  440. MCI_STATE_CONT_RSSI_POWER, NULL);
  441. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
  442. if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL))
  443. ath_dbg(common, MCI,
  444. "MCI CONT_INFO: (tx) pri = %d, pwr = %d dBm\n",
  445. ar9003_mci_state(ah,
  446. MCI_STATE_CONT_PRIORITY, NULL),
  447. value_dbm);
  448. else
  449. ath_dbg(common, MCI,
  450. "MCI CONT_INFO: (rx) pri = %d,pwr = %d dBm\n",
  451. ar9003_mci_state(ah,
  452. MCI_STATE_CONT_PRIORITY, NULL),
  453. value_dbm);
  454. }
  455. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
  456. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
  457. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
  458. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
  459. }
  460. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  461. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT))
  462. mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
  463. AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
  464. }
  465. void ath_mci_enable(struct ath_softc *sc)
  466. {
  467. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  468. if (!common->btcoex_enabled)
  469. return;
  470. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
  471. sc->sc_ah->imask |= ATH9K_INT_MCI;
  472. }