intel_dp.c 53 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Keith Packard <keithp@keithp.com>
  25. *
  26. */
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include "drmP.h"
  30. #include "drm.h"
  31. #include "drm_crtc.h"
  32. #include "drm_crtc_helper.h"
  33. #include "intel_drv.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36. #include "drm_dp_helper.h"
  37. #define DP_LINK_STATUS_SIZE 6
  38. #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
  39. #define DP_LINK_CONFIGURATION_SIZE 9
  40. struct intel_dp {
  41. struct intel_encoder base;
  42. uint32_t output_reg;
  43. uint32_t DP;
  44. uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
  45. bool has_audio;
  46. int force_audio;
  47. uint32_t color_range;
  48. uint8_t link_bw;
  49. uint8_t lane_count;
  50. uint8_t dpcd[8];
  51. struct i2c_adapter adapter;
  52. struct i2c_algo_dp_aux_data algo;
  53. bool is_pch_edp;
  54. uint8_t train_set[4];
  55. uint8_t link_status[DP_LINK_STATUS_SIZE];
  56. };
  57. /**
  58. * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  59. * @intel_dp: DP struct
  60. *
  61. * If a CPU or PCH DP output is attached to an eDP panel, this function
  62. * will return true, and false otherwise.
  63. */
  64. static bool is_edp(struct intel_dp *intel_dp)
  65. {
  66. return intel_dp->base.type == INTEL_OUTPUT_EDP;
  67. }
  68. /**
  69. * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  70. * @intel_dp: DP struct
  71. *
  72. * Returns true if the given DP struct corresponds to a PCH DP port attached
  73. * to an eDP panel, false otherwise. Helpful for determining whether we
  74. * may need FDI resources for a given DP output or not.
  75. */
  76. static bool is_pch_edp(struct intel_dp *intel_dp)
  77. {
  78. return intel_dp->is_pch_edp;
  79. }
  80. static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  81. {
  82. return container_of(encoder, struct intel_dp, base.base);
  83. }
  84. static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  85. {
  86. return container_of(intel_attached_encoder(connector),
  87. struct intel_dp, base);
  88. }
  89. /**
  90. * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  91. * @encoder: DRM encoder
  92. *
  93. * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
  94. * by intel_display.c.
  95. */
  96. bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  97. {
  98. struct intel_dp *intel_dp;
  99. if (!encoder)
  100. return false;
  101. intel_dp = enc_to_intel_dp(encoder);
  102. return is_pch_edp(intel_dp);
  103. }
  104. static void intel_dp_start_link_train(struct intel_dp *intel_dp);
  105. static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
  106. static void intel_dp_link_down(struct intel_dp *intel_dp);
  107. void
  108. intel_edp_link_config (struct intel_encoder *intel_encoder,
  109. int *lane_num, int *link_bw)
  110. {
  111. struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
  112. *lane_num = intel_dp->lane_count;
  113. if (intel_dp->link_bw == DP_LINK_BW_1_62)
  114. *link_bw = 162000;
  115. else if (intel_dp->link_bw == DP_LINK_BW_2_7)
  116. *link_bw = 270000;
  117. }
  118. static int
  119. intel_dp_max_lane_count(struct intel_dp *intel_dp)
  120. {
  121. int max_lane_count = 4;
  122. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
  123. max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
  124. switch (max_lane_count) {
  125. case 1: case 2: case 4:
  126. break;
  127. default:
  128. max_lane_count = 4;
  129. }
  130. }
  131. return max_lane_count;
  132. }
  133. static int
  134. intel_dp_max_link_bw(struct intel_dp *intel_dp)
  135. {
  136. int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  137. switch (max_link_bw) {
  138. case DP_LINK_BW_1_62:
  139. case DP_LINK_BW_2_7:
  140. break;
  141. default:
  142. max_link_bw = DP_LINK_BW_1_62;
  143. break;
  144. }
  145. return max_link_bw;
  146. }
  147. static int
  148. intel_dp_link_clock(uint8_t link_bw)
  149. {
  150. if (link_bw == DP_LINK_BW_2_7)
  151. return 270000;
  152. else
  153. return 162000;
  154. }
  155. /* I think this is a fiction */
  156. static int
  157. intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
  158. {
  159. struct drm_i915_private *dev_priv = dev->dev_private;
  160. if (is_edp(intel_dp))
  161. return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
  162. else
  163. return pixel_clock * 3;
  164. }
  165. static int
  166. intel_dp_max_data_rate(int max_link_clock, int max_lanes)
  167. {
  168. return (max_link_clock * max_lanes * 8) / 10;
  169. }
  170. static int
  171. intel_dp_mode_valid(struct drm_connector *connector,
  172. struct drm_display_mode *mode)
  173. {
  174. struct intel_dp *intel_dp = intel_attached_dp(connector);
  175. struct drm_device *dev = connector->dev;
  176. struct drm_i915_private *dev_priv = dev->dev_private;
  177. int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
  178. int max_lanes = intel_dp_max_lane_count(intel_dp);
  179. if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
  180. if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
  181. return MODE_PANEL;
  182. if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
  183. return MODE_PANEL;
  184. }
  185. /* only refuse the mode on non eDP since we have seen some weird eDP panels
  186. which are outside spec tolerances but somehow work by magic */
  187. if (!is_edp(intel_dp) &&
  188. (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
  189. > intel_dp_max_data_rate(max_link_clock, max_lanes)))
  190. return MODE_CLOCK_HIGH;
  191. if (mode->clock < 10000)
  192. return MODE_CLOCK_LOW;
  193. return MODE_OK;
  194. }
  195. static uint32_t
  196. pack_aux(uint8_t *src, int src_bytes)
  197. {
  198. int i;
  199. uint32_t v = 0;
  200. if (src_bytes > 4)
  201. src_bytes = 4;
  202. for (i = 0; i < src_bytes; i++)
  203. v |= ((uint32_t) src[i]) << ((3-i) * 8);
  204. return v;
  205. }
  206. static void
  207. unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
  208. {
  209. int i;
  210. if (dst_bytes > 4)
  211. dst_bytes = 4;
  212. for (i = 0; i < dst_bytes; i++)
  213. dst[i] = src >> ((3-i) * 8);
  214. }
  215. /* hrawclock is 1/4 the FSB frequency */
  216. static int
  217. intel_hrawclk(struct drm_device *dev)
  218. {
  219. struct drm_i915_private *dev_priv = dev->dev_private;
  220. uint32_t clkcfg;
  221. clkcfg = I915_READ(CLKCFG);
  222. switch (clkcfg & CLKCFG_FSB_MASK) {
  223. case CLKCFG_FSB_400:
  224. return 100;
  225. case CLKCFG_FSB_533:
  226. return 133;
  227. case CLKCFG_FSB_667:
  228. return 166;
  229. case CLKCFG_FSB_800:
  230. return 200;
  231. case CLKCFG_FSB_1067:
  232. return 266;
  233. case CLKCFG_FSB_1333:
  234. return 333;
  235. /* these two are just a guess; one of them might be right */
  236. case CLKCFG_FSB_1600:
  237. case CLKCFG_FSB_1600_ALT:
  238. return 400;
  239. default:
  240. return 133;
  241. }
  242. }
  243. static int
  244. intel_dp_aux_ch(struct intel_dp *intel_dp,
  245. uint8_t *send, int send_bytes,
  246. uint8_t *recv, int recv_size)
  247. {
  248. uint32_t output_reg = intel_dp->output_reg;
  249. struct drm_device *dev = intel_dp->base.base.dev;
  250. struct drm_i915_private *dev_priv = dev->dev_private;
  251. uint32_t ch_ctl = output_reg + 0x10;
  252. uint32_t ch_data = ch_ctl + 4;
  253. int i;
  254. int recv_bytes;
  255. uint32_t status;
  256. uint32_t aux_clock_divider;
  257. int try, precharge;
  258. /* The clock divider is based off the hrawclk,
  259. * and would like to run at 2MHz. So, take the
  260. * hrawclk value and divide by 2 and use that
  261. *
  262. * Note that PCH attached eDP panels should use a 125MHz input
  263. * clock divider.
  264. */
  265. if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
  266. if (IS_GEN6(dev))
  267. aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
  268. else
  269. aux_clock_divider = 225; /* eDP input clock at 450Mhz */
  270. } else if (HAS_PCH_SPLIT(dev))
  271. aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
  272. else
  273. aux_clock_divider = intel_hrawclk(dev) / 2;
  274. if (IS_GEN6(dev))
  275. precharge = 3;
  276. else
  277. precharge = 5;
  278. if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
  279. DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
  280. I915_READ(ch_ctl));
  281. return -EBUSY;
  282. }
  283. /* Must try at least 3 times according to DP spec */
  284. for (try = 0; try < 5; try++) {
  285. /* Load the send data into the aux channel data registers */
  286. for (i = 0; i < send_bytes; i += 4)
  287. I915_WRITE(ch_data + i,
  288. pack_aux(send + i, send_bytes - i));
  289. /* Send the command and wait for it to complete */
  290. I915_WRITE(ch_ctl,
  291. DP_AUX_CH_CTL_SEND_BUSY |
  292. DP_AUX_CH_CTL_TIME_OUT_400us |
  293. (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
  294. (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
  295. (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
  296. DP_AUX_CH_CTL_DONE |
  297. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  298. DP_AUX_CH_CTL_RECEIVE_ERROR);
  299. for (;;) {
  300. status = I915_READ(ch_ctl);
  301. if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  302. break;
  303. udelay(100);
  304. }
  305. /* Clear done status and any errors */
  306. I915_WRITE(ch_ctl,
  307. status |
  308. DP_AUX_CH_CTL_DONE |
  309. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  310. DP_AUX_CH_CTL_RECEIVE_ERROR);
  311. if (status & DP_AUX_CH_CTL_DONE)
  312. break;
  313. }
  314. if ((status & DP_AUX_CH_CTL_DONE) == 0) {
  315. DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
  316. return -EBUSY;
  317. }
  318. /* Check for timeout or receive error.
  319. * Timeouts occur when the sink is not connected
  320. */
  321. if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
  322. DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
  323. return -EIO;
  324. }
  325. /* Timeouts occur when the device isn't connected, so they're
  326. * "normal" -- don't fill the kernel log with these */
  327. if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
  328. DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
  329. return -ETIMEDOUT;
  330. }
  331. /* Unload any bytes sent back from the other side */
  332. recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
  333. DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
  334. if (recv_bytes > recv_size)
  335. recv_bytes = recv_size;
  336. for (i = 0; i < recv_bytes; i += 4)
  337. unpack_aux(I915_READ(ch_data + i),
  338. recv + i, recv_bytes - i);
  339. return recv_bytes;
  340. }
  341. /* Write data to the aux channel in native mode */
  342. static int
  343. intel_dp_aux_native_write(struct intel_dp *intel_dp,
  344. uint16_t address, uint8_t *send, int send_bytes)
  345. {
  346. int ret;
  347. uint8_t msg[20];
  348. int msg_bytes;
  349. uint8_t ack;
  350. if (send_bytes > 16)
  351. return -1;
  352. msg[0] = AUX_NATIVE_WRITE << 4;
  353. msg[1] = address >> 8;
  354. msg[2] = address & 0xff;
  355. msg[3] = send_bytes - 1;
  356. memcpy(&msg[4], send, send_bytes);
  357. msg_bytes = send_bytes + 4;
  358. for (;;) {
  359. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
  360. if (ret < 0)
  361. return ret;
  362. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
  363. break;
  364. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  365. udelay(100);
  366. else
  367. return -EIO;
  368. }
  369. return send_bytes;
  370. }
  371. /* Write a single byte to the aux channel in native mode */
  372. static int
  373. intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
  374. uint16_t address, uint8_t byte)
  375. {
  376. return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
  377. }
  378. /* read bytes from a native aux channel */
  379. static int
  380. intel_dp_aux_native_read(struct intel_dp *intel_dp,
  381. uint16_t address, uint8_t *recv, int recv_bytes)
  382. {
  383. uint8_t msg[4];
  384. int msg_bytes;
  385. uint8_t reply[20];
  386. int reply_bytes;
  387. uint8_t ack;
  388. int ret;
  389. msg[0] = AUX_NATIVE_READ << 4;
  390. msg[1] = address >> 8;
  391. msg[2] = address & 0xff;
  392. msg[3] = recv_bytes - 1;
  393. msg_bytes = 4;
  394. reply_bytes = recv_bytes + 1;
  395. for (;;) {
  396. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
  397. reply, reply_bytes);
  398. if (ret == 0)
  399. return -EPROTO;
  400. if (ret < 0)
  401. return ret;
  402. ack = reply[0];
  403. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
  404. memcpy(recv, reply + 1, ret - 1);
  405. return ret - 1;
  406. }
  407. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  408. udelay(100);
  409. else
  410. return -EIO;
  411. }
  412. }
  413. static int
  414. intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
  415. uint8_t write_byte, uint8_t *read_byte)
  416. {
  417. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  418. struct intel_dp *intel_dp = container_of(adapter,
  419. struct intel_dp,
  420. adapter);
  421. uint16_t address = algo_data->address;
  422. uint8_t msg[5];
  423. uint8_t reply[2];
  424. unsigned retry;
  425. int msg_bytes;
  426. int reply_bytes;
  427. int ret;
  428. /* Set up the command byte */
  429. if (mode & MODE_I2C_READ)
  430. msg[0] = AUX_I2C_READ << 4;
  431. else
  432. msg[0] = AUX_I2C_WRITE << 4;
  433. if (!(mode & MODE_I2C_STOP))
  434. msg[0] |= AUX_I2C_MOT << 4;
  435. msg[1] = address >> 8;
  436. msg[2] = address;
  437. switch (mode) {
  438. case MODE_I2C_WRITE:
  439. msg[3] = 0;
  440. msg[4] = write_byte;
  441. msg_bytes = 5;
  442. reply_bytes = 1;
  443. break;
  444. case MODE_I2C_READ:
  445. msg[3] = 0;
  446. msg_bytes = 4;
  447. reply_bytes = 2;
  448. break;
  449. default:
  450. msg_bytes = 3;
  451. reply_bytes = 1;
  452. break;
  453. }
  454. for (retry = 0; retry < 5; retry++) {
  455. ret = intel_dp_aux_ch(intel_dp,
  456. msg, msg_bytes,
  457. reply, reply_bytes);
  458. if (ret < 0) {
  459. DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
  460. return ret;
  461. }
  462. switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
  463. case AUX_NATIVE_REPLY_ACK:
  464. /* I2C-over-AUX Reply field is only valid
  465. * when paired with AUX ACK.
  466. */
  467. break;
  468. case AUX_NATIVE_REPLY_NACK:
  469. DRM_DEBUG_KMS("aux_ch native nack\n");
  470. return -EREMOTEIO;
  471. case AUX_NATIVE_REPLY_DEFER:
  472. udelay(100);
  473. continue;
  474. default:
  475. DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
  476. reply[0]);
  477. return -EREMOTEIO;
  478. }
  479. switch (reply[0] & AUX_I2C_REPLY_MASK) {
  480. case AUX_I2C_REPLY_ACK:
  481. if (mode == MODE_I2C_READ) {
  482. *read_byte = reply[1];
  483. }
  484. return reply_bytes - 1;
  485. case AUX_I2C_REPLY_NACK:
  486. DRM_DEBUG_KMS("aux_i2c nack\n");
  487. return -EREMOTEIO;
  488. case AUX_I2C_REPLY_DEFER:
  489. DRM_DEBUG_KMS("aux_i2c defer\n");
  490. udelay(100);
  491. break;
  492. default:
  493. DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
  494. return -EREMOTEIO;
  495. }
  496. }
  497. DRM_ERROR("too many retries, giving up\n");
  498. return -EREMOTEIO;
  499. }
  500. static int
  501. intel_dp_i2c_init(struct intel_dp *intel_dp,
  502. struct intel_connector *intel_connector, const char *name)
  503. {
  504. DRM_DEBUG_KMS("i2c_init %s\n", name);
  505. intel_dp->algo.running = false;
  506. intel_dp->algo.address = 0;
  507. intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
  508. memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
  509. intel_dp->adapter.owner = THIS_MODULE;
  510. intel_dp->adapter.class = I2C_CLASS_DDC;
  511. strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
  512. intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
  513. intel_dp->adapter.algo_data = &intel_dp->algo;
  514. intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
  515. return i2c_dp_aux_add_bus(&intel_dp->adapter);
  516. }
  517. static bool
  518. intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
  519. struct drm_display_mode *adjusted_mode)
  520. {
  521. struct drm_device *dev = encoder->dev;
  522. struct drm_i915_private *dev_priv = dev->dev_private;
  523. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  524. int lane_count, clock;
  525. int max_lane_count = intel_dp_max_lane_count(intel_dp);
  526. int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
  527. static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
  528. if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
  529. intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
  530. intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
  531. mode, adjusted_mode);
  532. /*
  533. * the mode->clock is used to calculate the Data&Link M/N
  534. * of the pipe. For the eDP the fixed clock should be used.
  535. */
  536. mode->clock = dev_priv->panel_fixed_mode->clock;
  537. }
  538. for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
  539. for (clock = 0; clock <= max_clock; clock++) {
  540. int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
  541. if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
  542. <= link_avail) {
  543. intel_dp->link_bw = bws[clock];
  544. intel_dp->lane_count = lane_count;
  545. adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
  546. DRM_DEBUG_KMS("Display port link bw %02x lane "
  547. "count %d clock %d\n",
  548. intel_dp->link_bw, intel_dp->lane_count,
  549. adjusted_mode->clock);
  550. return true;
  551. }
  552. }
  553. }
  554. if (is_edp(intel_dp)) {
  555. /* okay we failed just pick the highest */
  556. intel_dp->lane_count = max_lane_count;
  557. intel_dp->link_bw = bws[max_clock];
  558. adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
  559. DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
  560. "count %d clock %d\n",
  561. intel_dp->link_bw, intel_dp->lane_count,
  562. adjusted_mode->clock);
  563. return true;
  564. }
  565. return false;
  566. }
  567. struct intel_dp_m_n {
  568. uint32_t tu;
  569. uint32_t gmch_m;
  570. uint32_t gmch_n;
  571. uint32_t link_m;
  572. uint32_t link_n;
  573. };
  574. static void
  575. intel_reduce_ratio(uint32_t *num, uint32_t *den)
  576. {
  577. while (*num > 0xffffff || *den > 0xffffff) {
  578. *num >>= 1;
  579. *den >>= 1;
  580. }
  581. }
  582. static void
  583. intel_dp_compute_m_n(int bpp,
  584. int nlanes,
  585. int pixel_clock,
  586. int link_clock,
  587. struct intel_dp_m_n *m_n)
  588. {
  589. m_n->tu = 64;
  590. m_n->gmch_m = (pixel_clock * bpp) >> 3;
  591. m_n->gmch_n = link_clock * nlanes;
  592. intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  593. m_n->link_m = pixel_clock;
  594. m_n->link_n = link_clock;
  595. intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
  596. }
  597. void
  598. intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
  599. struct drm_display_mode *adjusted_mode)
  600. {
  601. struct drm_device *dev = crtc->dev;
  602. struct drm_mode_config *mode_config = &dev->mode_config;
  603. struct drm_encoder *encoder;
  604. struct drm_i915_private *dev_priv = dev->dev_private;
  605. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  606. int lane_count = 4, bpp = 24;
  607. struct intel_dp_m_n m_n;
  608. int pipe = intel_crtc->pipe;
  609. /*
  610. * Find the lane count in the intel_encoder private
  611. */
  612. list_for_each_entry(encoder, &mode_config->encoder_list, head) {
  613. struct intel_dp *intel_dp;
  614. if (encoder->crtc != crtc)
  615. continue;
  616. intel_dp = enc_to_intel_dp(encoder);
  617. if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
  618. lane_count = intel_dp->lane_count;
  619. break;
  620. } else if (is_edp(intel_dp)) {
  621. lane_count = dev_priv->edp.lanes;
  622. bpp = dev_priv->edp.bpp;
  623. break;
  624. }
  625. }
  626. /*
  627. * Compute the GMCH and Link ratios. The '3' here is
  628. * the number of bytes_per_pixel post-LUT, which we always
  629. * set up for 8-bits of R/G/B, or 3 bytes total.
  630. */
  631. intel_dp_compute_m_n(bpp, lane_count,
  632. mode->clock, adjusted_mode->clock, &m_n);
  633. if (HAS_PCH_SPLIT(dev)) {
  634. I915_WRITE(TRANSDATA_M1(pipe),
  635. ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
  636. m_n.gmch_m);
  637. I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
  638. I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
  639. I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
  640. } else {
  641. I915_WRITE(PIPE_GMCH_DATA_M(pipe),
  642. ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
  643. m_n.gmch_m);
  644. I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
  645. I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
  646. I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
  647. }
  648. }
  649. static void
  650. intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
  651. struct drm_display_mode *adjusted_mode)
  652. {
  653. struct drm_device *dev = encoder->dev;
  654. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  655. struct drm_crtc *crtc = intel_dp->base.base.crtc;
  656. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  657. intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  658. intel_dp->DP |= intel_dp->color_range;
  659. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  660. intel_dp->DP |= DP_SYNC_HS_HIGH;
  661. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  662. intel_dp->DP |= DP_SYNC_VS_HIGH;
  663. if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
  664. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  665. else
  666. intel_dp->DP |= DP_LINK_TRAIN_OFF;
  667. switch (intel_dp->lane_count) {
  668. case 1:
  669. intel_dp->DP |= DP_PORT_WIDTH_1;
  670. break;
  671. case 2:
  672. intel_dp->DP |= DP_PORT_WIDTH_2;
  673. break;
  674. case 4:
  675. intel_dp->DP |= DP_PORT_WIDTH_4;
  676. break;
  677. }
  678. if (intel_dp->has_audio)
  679. intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
  680. memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
  681. intel_dp->link_configuration[0] = intel_dp->link_bw;
  682. intel_dp->link_configuration[1] = intel_dp->lane_count;
  683. /*
  684. * Check for DPCD version > 1.1 and enhanced framing support
  685. */
  686. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  687. (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
  688. intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  689. intel_dp->DP |= DP_ENHANCED_FRAMING;
  690. }
  691. /* CPT DP's pipe select is decided in TRANS_DP_CTL */
  692. if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
  693. intel_dp->DP |= DP_PIPEB_SELECT;
  694. if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
  695. /* don't miss out required setting for eDP */
  696. intel_dp->DP |= DP_PLL_ENABLE;
  697. if (adjusted_mode->clock < 200000)
  698. intel_dp->DP |= DP_PLL_FREQ_160MHZ;
  699. else
  700. intel_dp->DP |= DP_PLL_FREQ_270MHZ;
  701. }
  702. }
  703. static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
  704. {
  705. struct drm_device *dev = intel_dp->base.base.dev;
  706. struct drm_i915_private *dev_priv = dev->dev_private;
  707. u32 pp;
  708. /*
  709. * If the panel wasn't on, make sure there's not a currently
  710. * active PP sequence before enabling AUX VDD.
  711. */
  712. if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
  713. msleep(dev_priv->panel_t3);
  714. pp = I915_READ(PCH_PP_CONTROL);
  715. pp |= EDP_FORCE_VDD;
  716. I915_WRITE(PCH_PP_CONTROL, pp);
  717. POSTING_READ(PCH_PP_CONTROL);
  718. }
  719. static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
  720. {
  721. struct drm_device *dev = intel_dp->base.base.dev;
  722. struct drm_i915_private *dev_priv = dev->dev_private;
  723. u32 pp;
  724. pp = I915_READ(PCH_PP_CONTROL);
  725. pp &= ~EDP_FORCE_VDD;
  726. I915_WRITE(PCH_PP_CONTROL, pp);
  727. POSTING_READ(PCH_PP_CONTROL);
  728. /* Make sure sequencer is idle before allowing subsequent activity */
  729. msleep(dev_priv->panel_t12);
  730. }
  731. /* Returns true if the panel was already on when called */
  732. static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
  733. {
  734. struct drm_device *dev = intel_dp->base.base.dev;
  735. struct drm_i915_private *dev_priv = dev->dev_private;
  736. u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
  737. if (I915_READ(PCH_PP_STATUS) & PP_ON)
  738. return true;
  739. pp = I915_READ(PCH_PP_CONTROL);
  740. /* ILK workaround: disable reset around power sequence */
  741. pp &= ~PANEL_POWER_RESET;
  742. I915_WRITE(PCH_PP_CONTROL, pp);
  743. POSTING_READ(PCH_PP_CONTROL);
  744. pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
  745. I915_WRITE(PCH_PP_CONTROL, pp);
  746. POSTING_READ(PCH_PP_CONTROL);
  747. if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
  748. 5000))
  749. DRM_ERROR("panel on wait timed out: 0x%08x\n",
  750. I915_READ(PCH_PP_STATUS));
  751. pp |= PANEL_POWER_RESET; /* restore panel reset bit */
  752. I915_WRITE(PCH_PP_CONTROL, pp);
  753. POSTING_READ(PCH_PP_CONTROL);
  754. return false;
  755. }
  756. static void ironlake_edp_panel_off (struct drm_device *dev)
  757. {
  758. struct drm_i915_private *dev_priv = dev->dev_private;
  759. u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
  760. PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
  761. pp = I915_READ(PCH_PP_CONTROL);
  762. /* ILK workaround: disable reset around power sequence */
  763. pp &= ~PANEL_POWER_RESET;
  764. I915_WRITE(PCH_PP_CONTROL, pp);
  765. POSTING_READ(PCH_PP_CONTROL);
  766. pp &= ~POWER_TARGET_ON;
  767. I915_WRITE(PCH_PP_CONTROL, pp);
  768. POSTING_READ(PCH_PP_CONTROL);
  769. if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
  770. DRM_ERROR("panel off wait timed out: 0x%08x\n",
  771. I915_READ(PCH_PP_STATUS));
  772. pp |= PANEL_POWER_RESET; /* restore panel reset bit */
  773. I915_WRITE(PCH_PP_CONTROL, pp);
  774. POSTING_READ(PCH_PP_CONTROL);
  775. }
  776. static void ironlake_edp_backlight_on (struct drm_device *dev)
  777. {
  778. struct drm_i915_private *dev_priv = dev->dev_private;
  779. u32 pp;
  780. DRM_DEBUG_KMS("\n");
  781. /*
  782. * If we enable the backlight right away following a panel power
  783. * on, we may see slight flicker as the panel syncs with the eDP
  784. * link. So delay a bit to make sure the image is solid before
  785. * allowing it to appear.
  786. */
  787. msleep(300);
  788. pp = I915_READ(PCH_PP_CONTROL);
  789. pp |= EDP_BLC_ENABLE;
  790. I915_WRITE(PCH_PP_CONTROL, pp);
  791. }
  792. static void ironlake_edp_backlight_off (struct drm_device *dev)
  793. {
  794. struct drm_i915_private *dev_priv = dev->dev_private;
  795. u32 pp;
  796. DRM_DEBUG_KMS("\n");
  797. pp = I915_READ(PCH_PP_CONTROL);
  798. pp &= ~EDP_BLC_ENABLE;
  799. I915_WRITE(PCH_PP_CONTROL, pp);
  800. }
  801. static void ironlake_edp_pll_on(struct drm_encoder *encoder)
  802. {
  803. struct drm_device *dev = encoder->dev;
  804. struct drm_i915_private *dev_priv = dev->dev_private;
  805. u32 dpa_ctl;
  806. DRM_DEBUG_KMS("\n");
  807. dpa_ctl = I915_READ(DP_A);
  808. dpa_ctl |= DP_PLL_ENABLE;
  809. I915_WRITE(DP_A, dpa_ctl);
  810. POSTING_READ(DP_A);
  811. udelay(200);
  812. }
  813. static void ironlake_edp_pll_off(struct drm_encoder *encoder)
  814. {
  815. struct drm_device *dev = encoder->dev;
  816. struct drm_i915_private *dev_priv = dev->dev_private;
  817. u32 dpa_ctl;
  818. dpa_ctl = I915_READ(DP_A);
  819. dpa_ctl &= ~DP_PLL_ENABLE;
  820. I915_WRITE(DP_A, dpa_ctl);
  821. POSTING_READ(DP_A);
  822. udelay(200);
  823. }
  824. /* If the sink supports it, try to set the power state appropriately */
  825. static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
  826. {
  827. int ret, i;
  828. /* Should have a valid DPCD by this point */
  829. if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
  830. return;
  831. if (mode != DRM_MODE_DPMS_ON) {
  832. ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
  833. DP_SET_POWER_D3);
  834. if (ret != 1)
  835. DRM_DEBUG_DRIVER("failed to write sink power state\n");
  836. } else {
  837. /*
  838. * When turning on, we need to retry for 1ms to give the sink
  839. * time to wake up.
  840. */
  841. for (i = 0; i < 3; i++) {
  842. ret = intel_dp_aux_native_write_1(intel_dp,
  843. DP_SET_POWER,
  844. DP_SET_POWER_D0);
  845. if (ret == 1)
  846. break;
  847. msleep(1);
  848. }
  849. }
  850. }
  851. static void intel_dp_prepare(struct drm_encoder *encoder)
  852. {
  853. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  854. struct drm_device *dev = encoder->dev;
  855. /* Wake up the sink first */
  856. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  857. if (is_edp(intel_dp)) {
  858. ironlake_edp_backlight_off(dev);
  859. ironlake_edp_panel_off(dev);
  860. if (!is_pch_edp(intel_dp))
  861. ironlake_edp_pll_on(encoder);
  862. else
  863. ironlake_edp_pll_off(encoder);
  864. }
  865. intel_dp_link_down(intel_dp);
  866. }
  867. static void intel_dp_commit(struct drm_encoder *encoder)
  868. {
  869. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  870. struct drm_device *dev = encoder->dev;
  871. if (is_edp(intel_dp))
  872. ironlake_edp_panel_vdd_on(intel_dp);
  873. intel_dp_start_link_train(intel_dp);
  874. if (is_edp(intel_dp)) {
  875. ironlake_edp_panel_on(intel_dp);
  876. ironlake_edp_panel_vdd_off(intel_dp);
  877. }
  878. intel_dp_complete_link_train(intel_dp);
  879. if (is_edp(intel_dp))
  880. ironlake_edp_backlight_on(dev);
  881. }
  882. static void
  883. intel_dp_dpms(struct drm_encoder *encoder, int mode)
  884. {
  885. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  886. struct drm_device *dev = encoder->dev;
  887. struct drm_i915_private *dev_priv = dev->dev_private;
  888. uint32_t dp_reg = I915_READ(intel_dp->output_reg);
  889. if (mode != DRM_MODE_DPMS_ON) {
  890. if (is_edp(intel_dp))
  891. ironlake_edp_backlight_off(dev);
  892. intel_dp_sink_dpms(intel_dp, mode);
  893. intel_dp_link_down(intel_dp);
  894. if (is_edp(intel_dp))
  895. ironlake_edp_panel_off(dev);
  896. if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
  897. ironlake_edp_pll_off(encoder);
  898. } else {
  899. if (is_edp(intel_dp))
  900. ironlake_edp_panel_vdd_on(intel_dp);
  901. intel_dp_sink_dpms(intel_dp, mode);
  902. if (!(dp_reg & DP_PORT_EN)) {
  903. intel_dp_start_link_train(intel_dp);
  904. if (is_edp(intel_dp)) {
  905. ironlake_edp_panel_on(intel_dp);
  906. ironlake_edp_panel_vdd_off(intel_dp);
  907. }
  908. intel_dp_complete_link_train(intel_dp);
  909. }
  910. if (is_edp(intel_dp))
  911. ironlake_edp_backlight_on(dev);
  912. }
  913. }
  914. /*
  915. * Native read with retry for link status and receiver capability reads for
  916. * cases where the sink may still be asleep.
  917. */
  918. static bool
  919. intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
  920. uint8_t *recv, int recv_bytes)
  921. {
  922. int ret, i;
  923. /*
  924. * Sinks are *supposed* to come up within 1ms from an off state,
  925. * but we're also supposed to retry 3 times per the spec.
  926. */
  927. for (i = 0; i < 3; i++) {
  928. ret = intel_dp_aux_native_read(intel_dp, address, recv,
  929. recv_bytes);
  930. if (ret == recv_bytes)
  931. return true;
  932. msleep(1);
  933. }
  934. return false;
  935. }
  936. /*
  937. * Fetch AUX CH registers 0x202 - 0x207 which contain
  938. * link status information
  939. */
  940. static bool
  941. intel_dp_get_link_status(struct intel_dp *intel_dp)
  942. {
  943. return intel_dp_aux_native_read_retry(intel_dp,
  944. DP_LANE0_1_STATUS,
  945. intel_dp->link_status,
  946. DP_LINK_STATUS_SIZE);
  947. }
  948. static uint8_t
  949. intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
  950. int r)
  951. {
  952. return link_status[r - DP_LANE0_1_STATUS];
  953. }
  954. static uint8_t
  955. intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
  956. int lane)
  957. {
  958. int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
  959. int s = ((lane & 1) ?
  960. DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
  961. DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
  962. uint8_t l = intel_dp_link_status(link_status, i);
  963. return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
  964. }
  965. static uint8_t
  966. intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
  967. int lane)
  968. {
  969. int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
  970. int s = ((lane & 1) ?
  971. DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
  972. DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
  973. uint8_t l = intel_dp_link_status(link_status, i);
  974. return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
  975. }
  976. #if 0
  977. static char *voltage_names[] = {
  978. "0.4V", "0.6V", "0.8V", "1.2V"
  979. };
  980. static char *pre_emph_names[] = {
  981. "0dB", "3.5dB", "6dB", "9.5dB"
  982. };
  983. static char *link_train_names[] = {
  984. "pattern 1", "pattern 2", "idle", "off"
  985. };
  986. #endif
  987. /*
  988. * These are source-specific values; current Intel hardware supports
  989. * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
  990. */
  991. #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
  992. static uint8_t
  993. intel_dp_pre_emphasis_max(uint8_t voltage_swing)
  994. {
  995. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  996. case DP_TRAIN_VOLTAGE_SWING_400:
  997. return DP_TRAIN_PRE_EMPHASIS_6;
  998. case DP_TRAIN_VOLTAGE_SWING_600:
  999. return DP_TRAIN_PRE_EMPHASIS_6;
  1000. case DP_TRAIN_VOLTAGE_SWING_800:
  1001. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1002. case DP_TRAIN_VOLTAGE_SWING_1200:
  1003. default:
  1004. return DP_TRAIN_PRE_EMPHASIS_0;
  1005. }
  1006. }
  1007. static void
  1008. intel_get_adjust_train(struct intel_dp *intel_dp)
  1009. {
  1010. uint8_t v = 0;
  1011. uint8_t p = 0;
  1012. int lane;
  1013. for (lane = 0; lane < intel_dp->lane_count; lane++) {
  1014. uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
  1015. uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
  1016. if (this_v > v)
  1017. v = this_v;
  1018. if (this_p > p)
  1019. p = this_p;
  1020. }
  1021. if (v >= I830_DP_VOLTAGE_MAX)
  1022. v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
  1023. if (p >= intel_dp_pre_emphasis_max(v))
  1024. p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  1025. for (lane = 0; lane < 4; lane++)
  1026. intel_dp->train_set[lane] = v | p;
  1027. }
  1028. static uint32_t
  1029. intel_dp_signal_levels(uint8_t train_set, int lane_count)
  1030. {
  1031. uint32_t signal_levels = 0;
  1032. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1033. case DP_TRAIN_VOLTAGE_SWING_400:
  1034. default:
  1035. signal_levels |= DP_VOLTAGE_0_4;
  1036. break;
  1037. case DP_TRAIN_VOLTAGE_SWING_600:
  1038. signal_levels |= DP_VOLTAGE_0_6;
  1039. break;
  1040. case DP_TRAIN_VOLTAGE_SWING_800:
  1041. signal_levels |= DP_VOLTAGE_0_8;
  1042. break;
  1043. case DP_TRAIN_VOLTAGE_SWING_1200:
  1044. signal_levels |= DP_VOLTAGE_1_2;
  1045. break;
  1046. }
  1047. switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
  1048. case DP_TRAIN_PRE_EMPHASIS_0:
  1049. default:
  1050. signal_levels |= DP_PRE_EMPHASIS_0;
  1051. break;
  1052. case DP_TRAIN_PRE_EMPHASIS_3_5:
  1053. signal_levels |= DP_PRE_EMPHASIS_3_5;
  1054. break;
  1055. case DP_TRAIN_PRE_EMPHASIS_6:
  1056. signal_levels |= DP_PRE_EMPHASIS_6;
  1057. break;
  1058. case DP_TRAIN_PRE_EMPHASIS_9_5:
  1059. signal_levels |= DP_PRE_EMPHASIS_9_5;
  1060. break;
  1061. }
  1062. return signal_levels;
  1063. }
  1064. /* Gen6's DP voltage swing and pre-emphasis control */
  1065. static uint32_t
  1066. intel_gen6_edp_signal_levels(uint8_t train_set)
  1067. {
  1068. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1069. DP_TRAIN_PRE_EMPHASIS_MASK);
  1070. switch (signal_levels) {
  1071. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1072. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1073. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1074. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1075. return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
  1076. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1077. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  1078. return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
  1079. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1080. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1081. return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
  1082. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1083. case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
  1084. return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
  1085. default:
  1086. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1087. "0x%x\n", signal_levels);
  1088. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1089. }
  1090. }
  1091. static uint8_t
  1092. intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
  1093. int lane)
  1094. {
  1095. int i = DP_LANE0_1_STATUS + (lane >> 1);
  1096. int s = (lane & 1) * 4;
  1097. uint8_t l = intel_dp_link_status(link_status, i);
  1098. return (l >> s) & 0xf;
  1099. }
  1100. /* Check for clock recovery is done on all channels */
  1101. static bool
  1102. intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
  1103. {
  1104. int lane;
  1105. uint8_t lane_status;
  1106. for (lane = 0; lane < lane_count; lane++) {
  1107. lane_status = intel_get_lane_status(link_status, lane);
  1108. if ((lane_status & DP_LANE_CR_DONE) == 0)
  1109. return false;
  1110. }
  1111. return true;
  1112. }
  1113. /* Check to see if channel eq is done on all channels */
  1114. #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
  1115. DP_LANE_CHANNEL_EQ_DONE|\
  1116. DP_LANE_SYMBOL_LOCKED)
  1117. static bool
  1118. intel_channel_eq_ok(struct intel_dp *intel_dp)
  1119. {
  1120. uint8_t lane_align;
  1121. uint8_t lane_status;
  1122. int lane;
  1123. lane_align = intel_dp_link_status(intel_dp->link_status,
  1124. DP_LANE_ALIGN_STATUS_UPDATED);
  1125. if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
  1126. return false;
  1127. for (lane = 0; lane < intel_dp->lane_count; lane++) {
  1128. lane_status = intel_get_lane_status(intel_dp->link_status, lane);
  1129. if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
  1130. return false;
  1131. }
  1132. return true;
  1133. }
  1134. static bool
  1135. intel_dp_set_link_train(struct intel_dp *intel_dp,
  1136. uint32_t dp_reg_value,
  1137. uint8_t dp_train_pat)
  1138. {
  1139. struct drm_device *dev = intel_dp->base.base.dev;
  1140. struct drm_i915_private *dev_priv = dev->dev_private;
  1141. int ret;
  1142. I915_WRITE(intel_dp->output_reg, dp_reg_value);
  1143. POSTING_READ(intel_dp->output_reg);
  1144. intel_dp_aux_native_write_1(intel_dp,
  1145. DP_TRAINING_PATTERN_SET,
  1146. dp_train_pat);
  1147. ret = intel_dp_aux_native_write(intel_dp,
  1148. DP_TRAINING_LANE0_SET,
  1149. intel_dp->train_set, 4);
  1150. if (ret != 4)
  1151. return false;
  1152. return true;
  1153. }
  1154. /* Enable corresponding port and start training pattern 1 */
  1155. static void
  1156. intel_dp_start_link_train(struct intel_dp *intel_dp)
  1157. {
  1158. struct drm_device *dev = intel_dp->base.base.dev;
  1159. struct drm_i915_private *dev_priv = dev->dev_private;
  1160. struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
  1161. int i;
  1162. uint8_t voltage;
  1163. bool clock_recovery = false;
  1164. int tries;
  1165. u32 reg;
  1166. uint32_t DP = intel_dp->DP;
  1167. /* Enable output, wait for it to become active */
  1168. I915_WRITE(intel_dp->output_reg, intel_dp->DP);
  1169. POSTING_READ(intel_dp->output_reg);
  1170. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1171. /* Write the link configuration data */
  1172. intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
  1173. intel_dp->link_configuration,
  1174. DP_LINK_CONFIGURATION_SIZE);
  1175. DP |= DP_PORT_EN;
  1176. if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
  1177. DP &= ~DP_LINK_TRAIN_MASK_CPT;
  1178. else
  1179. DP &= ~DP_LINK_TRAIN_MASK;
  1180. memset(intel_dp->train_set, 0, 4);
  1181. voltage = 0xff;
  1182. tries = 0;
  1183. clock_recovery = false;
  1184. for (;;) {
  1185. /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
  1186. uint32_t signal_levels;
  1187. if (IS_GEN6(dev) && is_edp(intel_dp)) {
  1188. signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
  1189. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
  1190. } else {
  1191. signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
  1192. DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
  1193. }
  1194. if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
  1195. reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
  1196. else
  1197. reg = DP | DP_LINK_TRAIN_PAT_1;
  1198. if (!intel_dp_set_link_train(intel_dp, reg,
  1199. DP_TRAINING_PATTERN_1))
  1200. break;
  1201. /* Set training pattern 1 */
  1202. udelay(100);
  1203. if (!intel_dp_get_link_status(intel_dp))
  1204. break;
  1205. if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
  1206. clock_recovery = true;
  1207. break;
  1208. }
  1209. /* Check to see if we've tried the max voltage */
  1210. for (i = 0; i < intel_dp->lane_count; i++)
  1211. if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
  1212. break;
  1213. if (i == intel_dp->lane_count)
  1214. break;
  1215. /* Check to see if we've tried the same voltage 5 times */
  1216. if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
  1217. ++tries;
  1218. if (tries == 5)
  1219. break;
  1220. } else
  1221. tries = 0;
  1222. voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  1223. /* Compute new intel_dp->train_set as requested by target */
  1224. intel_get_adjust_train(intel_dp);
  1225. }
  1226. intel_dp->DP = DP;
  1227. }
  1228. static void
  1229. intel_dp_complete_link_train(struct intel_dp *intel_dp)
  1230. {
  1231. struct drm_device *dev = intel_dp->base.base.dev;
  1232. struct drm_i915_private *dev_priv = dev->dev_private;
  1233. bool channel_eq = false;
  1234. int tries, cr_tries;
  1235. u32 reg;
  1236. uint32_t DP = intel_dp->DP;
  1237. /* channel equalization */
  1238. tries = 0;
  1239. cr_tries = 0;
  1240. channel_eq = false;
  1241. for (;;) {
  1242. /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
  1243. uint32_t signal_levels;
  1244. if (cr_tries > 5) {
  1245. DRM_ERROR("failed to train DP, aborting\n");
  1246. intel_dp_link_down(intel_dp);
  1247. break;
  1248. }
  1249. if (IS_GEN6(dev) && is_edp(intel_dp)) {
  1250. signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
  1251. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
  1252. } else {
  1253. signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
  1254. DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
  1255. }
  1256. if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
  1257. reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
  1258. else
  1259. reg = DP | DP_LINK_TRAIN_PAT_2;
  1260. /* channel eq pattern */
  1261. if (!intel_dp_set_link_train(intel_dp, reg,
  1262. DP_TRAINING_PATTERN_2))
  1263. break;
  1264. udelay(400);
  1265. if (!intel_dp_get_link_status(intel_dp))
  1266. break;
  1267. /* Make sure clock is still ok */
  1268. if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
  1269. intel_dp_start_link_train(intel_dp);
  1270. cr_tries++;
  1271. continue;
  1272. }
  1273. if (intel_channel_eq_ok(intel_dp)) {
  1274. channel_eq = true;
  1275. break;
  1276. }
  1277. /* Try 5 times, then try clock recovery if that fails */
  1278. if (tries > 5) {
  1279. intel_dp_link_down(intel_dp);
  1280. intel_dp_start_link_train(intel_dp);
  1281. tries = 0;
  1282. cr_tries++;
  1283. continue;
  1284. }
  1285. /* Compute new intel_dp->train_set as requested by target */
  1286. intel_get_adjust_train(intel_dp);
  1287. ++tries;
  1288. }
  1289. if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
  1290. reg = DP | DP_LINK_TRAIN_OFF_CPT;
  1291. else
  1292. reg = DP | DP_LINK_TRAIN_OFF;
  1293. I915_WRITE(intel_dp->output_reg, reg);
  1294. POSTING_READ(intel_dp->output_reg);
  1295. intel_dp_aux_native_write_1(intel_dp,
  1296. DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
  1297. }
  1298. static void
  1299. intel_dp_link_down(struct intel_dp *intel_dp)
  1300. {
  1301. struct drm_device *dev = intel_dp->base.base.dev;
  1302. struct drm_i915_private *dev_priv = dev->dev_private;
  1303. uint32_t DP = intel_dp->DP;
  1304. if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
  1305. return;
  1306. DRM_DEBUG_KMS("\n");
  1307. if (is_edp(intel_dp)) {
  1308. DP &= ~DP_PLL_ENABLE;
  1309. I915_WRITE(intel_dp->output_reg, DP);
  1310. POSTING_READ(intel_dp->output_reg);
  1311. udelay(100);
  1312. }
  1313. if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
  1314. DP &= ~DP_LINK_TRAIN_MASK_CPT;
  1315. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
  1316. } else {
  1317. DP &= ~DP_LINK_TRAIN_MASK;
  1318. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
  1319. }
  1320. POSTING_READ(intel_dp->output_reg);
  1321. msleep(17);
  1322. if (is_edp(intel_dp))
  1323. DP |= DP_LINK_TRAIN_OFF;
  1324. if (!HAS_PCH_CPT(dev) &&
  1325. I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
  1326. struct drm_crtc *crtc = intel_dp->base.base.crtc;
  1327. /* Hardware workaround: leaving our transcoder select
  1328. * set to transcoder B while it's off will prevent the
  1329. * corresponding HDMI output on transcoder A.
  1330. *
  1331. * Combine this with another hardware workaround:
  1332. * transcoder select bit can only be cleared while the
  1333. * port is enabled.
  1334. */
  1335. DP &= ~DP_PIPEB_SELECT;
  1336. I915_WRITE(intel_dp->output_reg, DP);
  1337. /* Changes to enable or select take place the vblank
  1338. * after being written.
  1339. */
  1340. if (crtc == NULL) {
  1341. /* We can arrive here never having been attached
  1342. * to a CRTC, for instance, due to inheriting
  1343. * random state from the BIOS.
  1344. *
  1345. * If the pipe is not running, play safe and
  1346. * wait for the clocks to stabilise before
  1347. * continuing.
  1348. */
  1349. POSTING_READ(intel_dp->output_reg);
  1350. msleep(50);
  1351. } else
  1352. intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
  1353. }
  1354. I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
  1355. POSTING_READ(intel_dp->output_reg);
  1356. }
  1357. /*
  1358. * According to DP spec
  1359. * 5.1.2:
  1360. * 1. Read DPCD
  1361. * 2. Configure link according to Receiver Capabilities
  1362. * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
  1363. * 4. Check link status on receipt of hot-plug interrupt
  1364. */
  1365. static void
  1366. intel_dp_check_link_status(struct intel_dp *intel_dp)
  1367. {
  1368. int ret;
  1369. if (!intel_dp->base.base.crtc)
  1370. return;
  1371. if (!intel_dp_get_link_status(intel_dp)) {
  1372. intel_dp_link_down(intel_dp);
  1373. return;
  1374. }
  1375. /* Try to read receiver status if the link appears to be up */
  1376. ret = intel_dp_aux_native_read(intel_dp,
  1377. 0x000, intel_dp->dpcd,
  1378. sizeof (intel_dp->dpcd));
  1379. if (ret != sizeof(intel_dp->dpcd)) {
  1380. intel_dp_link_down(intel_dp);
  1381. return;
  1382. }
  1383. if (!intel_channel_eq_ok(intel_dp)) {
  1384. intel_dp_start_link_train(intel_dp);
  1385. intel_dp_complete_link_train(intel_dp);
  1386. }
  1387. }
  1388. static enum drm_connector_status
  1389. ironlake_dp_detect(struct intel_dp *intel_dp)
  1390. {
  1391. enum drm_connector_status status;
  1392. bool ret;
  1393. /* Can't disconnect eDP, but you can close the lid... */
  1394. if (is_edp(intel_dp)) {
  1395. status = intel_panel_detect(intel_dp->base.base.dev);
  1396. if (status == connector_status_unknown)
  1397. status = connector_status_connected;
  1398. return status;
  1399. }
  1400. status = connector_status_disconnected;
  1401. ret = intel_dp_aux_native_read_retry(intel_dp,
  1402. 0x000, intel_dp->dpcd,
  1403. sizeof (intel_dp->dpcd));
  1404. if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0)
  1405. status = connector_status_connected;
  1406. return status;
  1407. }
  1408. static enum drm_connector_status
  1409. g4x_dp_detect(struct intel_dp *intel_dp)
  1410. {
  1411. struct drm_device *dev = intel_dp->base.base.dev;
  1412. struct drm_i915_private *dev_priv = dev->dev_private;
  1413. enum drm_connector_status status;
  1414. uint32_t temp, bit;
  1415. switch (intel_dp->output_reg) {
  1416. case DP_B:
  1417. bit = DPB_HOTPLUG_INT_STATUS;
  1418. break;
  1419. case DP_C:
  1420. bit = DPC_HOTPLUG_INT_STATUS;
  1421. break;
  1422. case DP_D:
  1423. bit = DPD_HOTPLUG_INT_STATUS;
  1424. break;
  1425. default:
  1426. return connector_status_unknown;
  1427. }
  1428. temp = I915_READ(PORT_HOTPLUG_STAT);
  1429. if ((temp & bit) == 0)
  1430. return connector_status_disconnected;
  1431. status = connector_status_disconnected;
  1432. if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
  1433. sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
  1434. {
  1435. if (intel_dp->dpcd[DP_DPCD_REV] != 0)
  1436. status = connector_status_connected;
  1437. }
  1438. return status;
  1439. }
  1440. /**
  1441. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
  1442. *
  1443. * \return true if DP port is connected.
  1444. * \return false if DP port is disconnected.
  1445. */
  1446. static enum drm_connector_status
  1447. intel_dp_detect(struct drm_connector *connector, bool force)
  1448. {
  1449. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1450. struct drm_device *dev = intel_dp->base.base.dev;
  1451. enum drm_connector_status status;
  1452. struct edid *edid = NULL;
  1453. intel_dp->has_audio = false;
  1454. memset(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd));
  1455. if (HAS_PCH_SPLIT(dev))
  1456. status = ironlake_dp_detect(intel_dp);
  1457. else
  1458. status = g4x_dp_detect(intel_dp);
  1459. DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx%hx%hx%hx%hx\n", intel_dp->dpcd[0],
  1460. intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3],
  1461. intel_dp->dpcd[4], intel_dp->dpcd[5], intel_dp->dpcd[6],
  1462. intel_dp->dpcd[7]);
  1463. if (status != connector_status_connected)
  1464. return status;
  1465. if (intel_dp->force_audio) {
  1466. intel_dp->has_audio = intel_dp->force_audio > 0;
  1467. } else {
  1468. edid = drm_get_edid(connector, &intel_dp->adapter);
  1469. if (edid) {
  1470. intel_dp->has_audio = drm_detect_monitor_audio(edid);
  1471. connector->display_info.raw_edid = NULL;
  1472. kfree(edid);
  1473. }
  1474. }
  1475. return connector_status_connected;
  1476. }
  1477. static int intel_dp_get_modes(struct drm_connector *connector)
  1478. {
  1479. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1480. struct drm_device *dev = intel_dp->base.base.dev;
  1481. struct drm_i915_private *dev_priv = dev->dev_private;
  1482. int ret;
  1483. /* We should parse the EDID data and find out if it has an audio sink
  1484. */
  1485. ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
  1486. if (ret) {
  1487. if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
  1488. struct drm_display_mode *newmode;
  1489. list_for_each_entry(newmode, &connector->probed_modes,
  1490. head) {
  1491. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1492. dev_priv->panel_fixed_mode =
  1493. drm_mode_duplicate(dev, newmode);
  1494. break;
  1495. }
  1496. }
  1497. }
  1498. return ret;
  1499. }
  1500. /* if eDP has no EDID, try to use fixed panel mode from VBT */
  1501. if (is_edp(intel_dp)) {
  1502. if (dev_priv->panel_fixed_mode != NULL) {
  1503. struct drm_display_mode *mode;
  1504. mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
  1505. drm_mode_probed_add(connector, mode);
  1506. return 1;
  1507. }
  1508. }
  1509. return 0;
  1510. }
  1511. static bool
  1512. intel_dp_detect_audio(struct drm_connector *connector)
  1513. {
  1514. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1515. struct edid *edid;
  1516. bool has_audio = false;
  1517. edid = drm_get_edid(connector, &intel_dp->adapter);
  1518. if (edid) {
  1519. has_audio = drm_detect_monitor_audio(edid);
  1520. connector->display_info.raw_edid = NULL;
  1521. kfree(edid);
  1522. }
  1523. return has_audio;
  1524. }
  1525. static int
  1526. intel_dp_set_property(struct drm_connector *connector,
  1527. struct drm_property *property,
  1528. uint64_t val)
  1529. {
  1530. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1531. struct intel_dp *intel_dp = intel_attached_dp(connector);
  1532. int ret;
  1533. ret = drm_connector_property_set_value(connector, property, val);
  1534. if (ret)
  1535. return ret;
  1536. if (property == dev_priv->force_audio_property) {
  1537. int i = val;
  1538. bool has_audio;
  1539. if (i == intel_dp->force_audio)
  1540. return 0;
  1541. intel_dp->force_audio = i;
  1542. if (i == 0)
  1543. has_audio = intel_dp_detect_audio(connector);
  1544. else
  1545. has_audio = i > 0;
  1546. if (has_audio == intel_dp->has_audio)
  1547. return 0;
  1548. intel_dp->has_audio = has_audio;
  1549. goto done;
  1550. }
  1551. if (property == dev_priv->broadcast_rgb_property) {
  1552. if (val == !!intel_dp->color_range)
  1553. return 0;
  1554. intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
  1555. goto done;
  1556. }
  1557. return -EINVAL;
  1558. done:
  1559. if (intel_dp->base.base.crtc) {
  1560. struct drm_crtc *crtc = intel_dp->base.base.crtc;
  1561. drm_crtc_helper_set_mode(crtc, &crtc->mode,
  1562. crtc->x, crtc->y,
  1563. crtc->fb);
  1564. }
  1565. return 0;
  1566. }
  1567. static void
  1568. intel_dp_destroy (struct drm_connector *connector)
  1569. {
  1570. drm_sysfs_connector_remove(connector);
  1571. drm_connector_cleanup(connector);
  1572. kfree(connector);
  1573. }
  1574. static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
  1575. {
  1576. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  1577. i2c_del_adapter(&intel_dp->adapter);
  1578. drm_encoder_cleanup(encoder);
  1579. kfree(intel_dp);
  1580. }
  1581. static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
  1582. .dpms = intel_dp_dpms,
  1583. .mode_fixup = intel_dp_mode_fixup,
  1584. .prepare = intel_dp_prepare,
  1585. .mode_set = intel_dp_mode_set,
  1586. .commit = intel_dp_commit,
  1587. };
  1588. static const struct drm_connector_funcs intel_dp_connector_funcs = {
  1589. .dpms = drm_helper_connector_dpms,
  1590. .detect = intel_dp_detect,
  1591. .fill_modes = drm_helper_probe_single_connector_modes,
  1592. .set_property = intel_dp_set_property,
  1593. .destroy = intel_dp_destroy,
  1594. };
  1595. static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
  1596. .get_modes = intel_dp_get_modes,
  1597. .mode_valid = intel_dp_mode_valid,
  1598. .best_encoder = intel_best_encoder,
  1599. };
  1600. static const struct drm_encoder_funcs intel_dp_enc_funcs = {
  1601. .destroy = intel_dp_encoder_destroy,
  1602. };
  1603. static void
  1604. intel_dp_hot_plug(struct intel_encoder *intel_encoder)
  1605. {
  1606. struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
  1607. intel_dp_check_link_status(intel_dp);
  1608. }
  1609. /* Return which DP Port should be selected for Transcoder DP control */
  1610. int
  1611. intel_trans_dp_port_sel (struct drm_crtc *crtc)
  1612. {
  1613. struct drm_device *dev = crtc->dev;
  1614. struct drm_mode_config *mode_config = &dev->mode_config;
  1615. struct drm_encoder *encoder;
  1616. list_for_each_entry(encoder, &mode_config->encoder_list, head) {
  1617. struct intel_dp *intel_dp;
  1618. if (encoder->crtc != crtc)
  1619. continue;
  1620. intel_dp = enc_to_intel_dp(encoder);
  1621. if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
  1622. return intel_dp->output_reg;
  1623. }
  1624. return -1;
  1625. }
  1626. /* check the VBT to see whether the eDP is on DP-D port */
  1627. bool intel_dpd_is_edp(struct drm_device *dev)
  1628. {
  1629. struct drm_i915_private *dev_priv = dev->dev_private;
  1630. struct child_device_config *p_child;
  1631. int i;
  1632. if (!dev_priv->child_dev_num)
  1633. return false;
  1634. for (i = 0; i < dev_priv->child_dev_num; i++) {
  1635. p_child = dev_priv->child_dev + i;
  1636. if (p_child->dvo_port == PORT_IDPD &&
  1637. p_child->device_type == DEVICE_TYPE_eDP)
  1638. return true;
  1639. }
  1640. return false;
  1641. }
  1642. static void
  1643. intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
  1644. {
  1645. intel_attach_force_audio_property(connector);
  1646. intel_attach_broadcast_rgb_property(connector);
  1647. }
  1648. void
  1649. intel_dp_init(struct drm_device *dev, int output_reg)
  1650. {
  1651. struct drm_i915_private *dev_priv = dev->dev_private;
  1652. struct drm_connector *connector;
  1653. struct intel_dp *intel_dp;
  1654. struct intel_encoder *intel_encoder;
  1655. struct intel_connector *intel_connector;
  1656. const char *name = NULL;
  1657. int type;
  1658. intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
  1659. if (!intel_dp)
  1660. return;
  1661. intel_dp->output_reg = output_reg;
  1662. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  1663. if (!intel_connector) {
  1664. kfree(intel_dp);
  1665. return;
  1666. }
  1667. intel_encoder = &intel_dp->base;
  1668. if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
  1669. if (intel_dpd_is_edp(dev))
  1670. intel_dp->is_pch_edp = true;
  1671. if (output_reg == DP_A || is_pch_edp(intel_dp)) {
  1672. type = DRM_MODE_CONNECTOR_eDP;
  1673. intel_encoder->type = INTEL_OUTPUT_EDP;
  1674. } else {
  1675. type = DRM_MODE_CONNECTOR_DisplayPort;
  1676. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  1677. }
  1678. connector = &intel_connector->base;
  1679. drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
  1680. drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
  1681. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1682. if (output_reg == DP_B || output_reg == PCH_DP_B)
  1683. intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
  1684. else if (output_reg == DP_C || output_reg == PCH_DP_C)
  1685. intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
  1686. else if (output_reg == DP_D || output_reg == PCH_DP_D)
  1687. intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
  1688. if (is_edp(intel_dp))
  1689. intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
  1690. intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
  1691. connector->interlace_allowed = true;
  1692. connector->doublescan_allowed = 0;
  1693. drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
  1694. DRM_MODE_ENCODER_TMDS);
  1695. drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
  1696. intel_connector_attach_encoder(intel_connector, intel_encoder);
  1697. drm_sysfs_connector_add(connector);
  1698. /* Set up the DDC bus. */
  1699. switch (output_reg) {
  1700. case DP_A:
  1701. name = "DPDDC-A";
  1702. break;
  1703. case DP_B:
  1704. case PCH_DP_B:
  1705. dev_priv->hotplug_supported_mask |=
  1706. HDMIB_HOTPLUG_INT_STATUS;
  1707. name = "DPDDC-B";
  1708. break;
  1709. case DP_C:
  1710. case PCH_DP_C:
  1711. dev_priv->hotplug_supported_mask |=
  1712. HDMIC_HOTPLUG_INT_STATUS;
  1713. name = "DPDDC-C";
  1714. break;
  1715. case DP_D:
  1716. case PCH_DP_D:
  1717. dev_priv->hotplug_supported_mask |=
  1718. HDMID_HOTPLUG_INT_STATUS;
  1719. name = "DPDDC-D";
  1720. break;
  1721. }
  1722. intel_dp_i2c_init(intel_dp, intel_connector, name);
  1723. /* Cache some DPCD data in the eDP case */
  1724. if (is_edp(intel_dp)) {
  1725. int ret;
  1726. u32 pp_on, pp_div;
  1727. pp_on = I915_READ(PCH_PP_ON_DELAYS);
  1728. pp_div = I915_READ(PCH_PP_DIVISOR);
  1729. /* Get T3 & T12 values (note: VESA not bspec terminology) */
  1730. dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
  1731. dev_priv->panel_t3 /= 10; /* t3 in 100us units */
  1732. dev_priv->panel_t12 = pp_div & 0xf;
  1733. dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
  1734. ironlake_edp_panel_vdd_on(intel_dp);
  1735. ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
  1736. intel_dp->dpcd,
  1737. sizeof(intel_dp->dpcd));
  1738. ironlake_edp_panel_vdd_off(intel_dp);
  1739. if (ret == sizeof(intel_dp->dpcd)) {
  1740. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
  1741. dev_priv->no_aux_handshake =
  1742. intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
  1743. DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
  1744. } else {
  1745. /* if this fails, presume the device is a ghost */
  1746. DRM_INFO("failed to retrieve link info, disabling eDP\n");
  1747. intel_dp_encoder_destroy(&intel_dp->base.base);
  1748. intel_dp_destroy(&intel_connector->base);
  1749. return;
  1750. }
  1751. }
  1752. intel_encoder->hot_plug = intel_dp_hot_plug;
  1753. if (is_edp(intel_dp)) {
  1754. /* initialize panel mode from VBT if available for eDP */
  1755. if (dev_priv->lfp_lvds_vbt_mode) {
  1756. dev_priv->panel_fixed_mode =
  1757. drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
  1758. if (dev_priv->panel_fixed_mode) {
  1759. dev_priv->panel_fixed_mode->type |=
  1760. DRM_MODE_TYPE_PREFERRED;
  1761. }
  1762. }
  1763. }
  1764. intel_dp_add_properties(intel_dp, connector);
  1765. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  1766. * 0xd. Failure to do so will result in spurious interrupts being
  1767. * generated on the port when a cable is not attached.
  1768. */
  1769. if (IS_G4X(dev) && !IS_GM45(dev)) {
  1770. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  1771. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  1772. }
  1773. }