fsi.c 18 KB

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  1. /*
  2. * Fifo-attached Serial Interface (FSI) support for SH7724
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on ssi.c
  8. * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/module.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/delay.h>
  18. #include <linux/list.h>
  19. #include <linux/clk.h>
  20. #include <linux/io.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/initval.h>
  24. #include <sound/soc.h>
  25. #include <sound/pcm_params.h>
  26. #include <sound/sh_fsi.h>
  27. #include <asm/atomic.h>
  28. #define DO_FMT 0x0000
  29. #define DOFF_CTL 0x0004
  30. #define DOFF_ST 0x0008
  31. #define DI_FMT 0x000C
  32. #define DIFF_CTL 0x0010
  33. #define DIFF_ST 0x0014
  34. #define CKG1 0x0018
  35. #define CKG2 0x001C
  36. #define DIDT 0x0020
  37. #define DODT 0x0024
  38. #define MUTE_ST 0x0028
  39. #define REG_END MUTE_ST
  40. #define INT_ST 0x0200
  41. #define IEMSK 0x0204
  42. #define IMSK 0x0208
  43. #define MUTE 0x020C
  44. #define CLK_RST 0x0210
  45. #define SOFT_RST 0x0214
  46. #define MREG_START INT_ST
  47. #define MREG_END SOFT_RST
  48. /* DO_FMT */
  49. /* DI_FMT */
  50. #define CR_FMT(param) ((param) << 4)
  51. # define CR_MONO 0x0
  52. # define CR_MONO_D 0x1
  53. # define CR_PCM 0x2
  54. # define CR_I2S 0x3
  55. # define CR_TDM 0x4
  56. # define CR_TDM_D 0x5
  57. /* DOFF_CTL */
  58. /* DIFF_CTL */
  59. #define IRQ_HALF 0x00100000
  60. #define FIFO_CLR 0x00000001
  61. /* DOFF_ST */
  62. #define ERR_OVER 0x00000010
  63. #define ERR_UNDER 0x00000001
  64. /* CLK_RST */
  65. #define B_CLK 0x00000010
  66. #define A_CLK 0x00000001
  67. /* INT_ST */
  68. #define INT_B_IN (1 << 12)
  69. #define INT_B_OUT (1 << 8)
  70. #define INT_A_IN (1 << 4)
  71. #define INT_A_OUT (1 << 0)
  72. #define FSI_RATES SNDRV_PCM_RATE_8000_96000
  73. #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
  74. /************************************************************************
  75. struct
  76. ************************************************************************/
  77. struct fsi_priv {
  78. void __iomem *base;
  79. struct snd_pcm_substream *substream;
  80. int fifo_max;
  81. int chan;
  82. int byte_offset;
  83. int period_len;
  84. int buffer_len;
  85. int periods;
  86. };
  87. struct fsi_master {
  88. void __iomem *base;
  89. int irq;
  90. struct clk *clk;
  91. struct fsi_priv fsia;
  92. struct fsi_priv fsib;
  93. struct sh_fsi_platform_info *info;
  94. };
  95. static struct fsi_master *master;
  96. /************************************************************************
  97. basic read write function
  98. ************************************************************************/
  99. static int __fsi_reg_write(u32 reg, u32 data)
  100. {
  101. /* valid data area is 24bit */
  102. data &= 0x00ffffff;
  103. return ctrl_outl(data, reg);
  104. }
  105. static u32 __fsi_reg_read(u32 reg)
  106. {
  107. return ctrl_inl(reg);
  108. }
  109. static int __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
  110. {
  111. u32 val = __fsi_reg_read(reg);
  112. val &= ~mask;
  113. val |= data & mask;
  114. return __fsi_reg_write(reg, val);
  115. }
  116. static int fsi_reg_write(struct fsi_priv *fsi, u32 reg, u32 data)
  117. {
  118. if (reg > REG_END)
  119. return -1;
  120. return __fsi_reg_write((u32)(fsi->base + reg), data);
  121. }
  122. static u32 fsi_reg_read(struct fsi_priv *fsi, u32 reg)
  123. {
  124. if (reg > REG_END)
  125. return 0;
  126. return __fsi_reg_read((u32)(fsi->base + reg));
  127. }
  128. static int fsi_reg_mask_set(struct fsi_priv *fsi, u32 reg, u32 mask, u32 data)
  129. {
  130. if (reg > REG_END)
  131. return -1;
  132. return __fsi_reg_mask_set((u32)(fsi->base + reg), mask, data);
  133. }
  134. static int fsi_master_write(u32 reg, u32 data)
  135. {
  136. if ((reg < MREG_START) ||
  137. (reg > MREG_END))
  138. return -1;
  139. return __fsi_reg_write((u32)(master->base + reg), data);
  140. }
  141. static u32 fsi_master_read(u32 reg)
  142. {
  143. if ((reg < MREG_START) ||
  144. (reg > MREG_END))
  145. return 0;
  146. return __fsi_reg_read((u32)(master->base + reg));
  147. }
  148. static int fsi_master_mask_set(u32 reg, u32 mask, u32 data)
  149. {
  150. if ((reg < MREG_START) ||
  151. (reg > MREG_END))
  152. return -1;
  153. return __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
  154. }
  155. /************************************************************************
  156. basic function
  157. ************************************************************************/
  158. static struct fsi_priv *fsi_get(struct snd_pcm_substream *substream)
  159. {
  160. struct snd_soc_pcm_runtime *rtd;
  161. struct fsi_priv *fsi = NULL;
  162. if (!substream || !master)
  163. return NULL;
  164. rtd = substream->private_data;
  165. switch (rtd->dai->cpu_dai->id) {
  166. case 0:
  167. fsi = &master->fsia;
  168. break;
  169. case 1:
  170. fsi = &master->fsib;
  171. break;
  172. }
  173. return fsi;
  174. }
  175. static int fsi_is_port_a(struct fsi_priv *fsi)
  176. {
  177. /* return
  178. * 1 : port a
  179. * 0 : port b
  180. */
  181. if (fsi == &master->fsia)
  182. return 1;
  183. return 0;
  184. }
  185. static u32 fsi_get_info_flags(struct fsi_priv *fsi)
  186. {
  187. int is_porta = fsi_is_port_a(fsi);
  188. return is_porta ? master->info->porta_flags :
  189. master->info->portb_flags;
  190. }
  191. static int fsi_is_master_mode(struct fsi_priv *fsi, int is_play)
  192. {
  193. u32 mode;
  194. u32 flags = fsi_get_info_flags(fsi);
  195. mode = is_play ? SH_FSI_OUT_SLAVE_MODE : SH_FSI_IN_SLAVE_MODE;
  196. /* return
  197. * 1 : master mode
  198. * 0 : slave mode
  199. */
  200. return (mode & flags) != mode;
  201. }
  202. static u32 fsi_port_ab_io_bit(struct fsi_priv *fsi, int is_play)
  203. {
  204. int is_porta = fsi_is_port_a(fsi);
  205. u32 data;
  206. if (is_porta)
  207. data = is_play ? (1 << 0) : (1 << 4);
  208. else
  209. data = is_play ? (1 << 8) : (1 << 12);
  210. return data;
  211. }
  212. static void fsi_stream_push(struct fsi_priv *fsi,
  213. struct snd_pcm_substream *substream,
  214. u32 buffer_len,
  215. u32 period_len)
  216. {
  217. fsi->substream = substream;
  218. fsi->buffer_len = buffer_len;
  219. fsi->period_len = period_len;
  220. fsi->byte_offset = 0;
  221. fsi->periods = 0;
  222. }
  223. static void fsi_stream_pop(struct fsi_priv *fsi)
  224. {
  225. fsi->substream = NULL;
  226. fsi->buffer_len = 0;
  227. fsi->period_len = 0;
  228. fsi->byte_offset = 0;
  229. fsi->periods = 0;
  230. }
  231. static int fsi_get_fifo_residue(struct fsi_priv *fsi, int is_play)
  232. {
  233. u32 status;
  234. u32 reg = is_play ? DOFF_ST : DIFF_ST;
  235. int residue;
  236. status = fsi_reg_read(fsi, reg);
  237. residue = 0x1ff & (status >> 8);
  238. residue *= fsi->chan;
  239. return residue;
  240. }
  241. /************************************************************************
  242. ctrl function
  243. ************************************************************************/
  244. static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
  245. {
  246. u32 data = fsi_port_ab_io_bit(fsi, is_play);
  247. fsi_master_mask_set(IMSK, data, data);
  248. fsi_master_mask_set(IEMSK, data, data);
  249. }
  250. static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
  251. {
  252. u32 data = fsi_port_ab_io_bit(fsi, is_play);
  253. fsi_master_mask_set(IMSK, data, 0);
  254. fsi_master_mask_set(IEMSK, data, 0);
  255. }
  256. static void fsi_clk_ctrl(struct fsi_priv *fsi, int enable)
  257. {
  258. u32 val = fsi_is_port_a(fsi) ? (1 << 0) : (1 << 4);
  259. if (enable)
  260. fsi_master_mask_set(CLK_RST, val, val);
  261. else
  262. fsi_master_mask_set(CLK_RST, val, 0);
  263. }
  264. static void fsi_irq_init(struct fsi_priv *fsi, int is_play)
  265. {
  266. u32 data;
  267. u32 ctrl;
  268. data = fsi_port_ab_io_bit(fsi, is_play);
  269. ctrl = is_play ? DOFF_CTL : DIFF_CTL;
  270. /* set IMSK */
  271. fsi_irq_disable(fsi, is_play);
  272. /* set interrupt generation factor */
  273. fsi_reg_write(fsi, ctrl, IRQ_HALF);
  274. /* clear FIFO */
  275. fsi_reg_mask_set(fsi, ctrl, FIFO_CLR, FIFO_CLR);
  276. /* clear interrupt factor */
  277. fsi_master_mask_set(INT_ST, data, 0);
  278. }
  279. static void fsi_soft_all_reset(void)
  280. {
  281. u32 status = fsi_master_read(SOFT_RST);
  282. /* port AB reset */
  283. status &= 0x000000ff;
  284. fsi_master_write(SOFT_RST, status);
  285. mdelay(10);
  286. /* soft reset */
  287. status &= 0x000000f0;
  288. fsi_master_write(SOFT_RST, status);
  289. status |= 0x00000001;
  290. fsi_master_write(SOFT_RST, status);
  291. mdelay(10);
  292. }
  293. /* playback interrupt */
  294. static int fsi_data_push(struct fsi_priv *fsi)
  295. {
  296. struct snd_pcm_runtime *runtime;
  297. struct snd_pcm_substream *substream = NULL;
  298. int send;
  299. int fifo_free;
  300. int width;
  301. u8 *start;
  302. int i;
  303. if (!fsi ||
  304. !fsi->substream ||
  305. !fsi->substream->runtime)
  306. return -EINVAL;
  307. runtime = fsi->substream->runtime;
  308. /* FSI FIFO has limit.
  309. * So, this driver can not send periods data at a time
  310. */
  311. if (fsi->byte_offset >=
  312. fsi->period_len * (fsi->periods + 1)) {
  313. substream = fsi->substream;
  314. fsi->periods = (fsi->periods + 1) % runtime->periods;
  315. if (0 == fsi->periods)
  316. fsi->byte_offset = 0;
  317. }
  318. /* get 1 channel data width */
  319. width = frames_to_bytes(runtime, 1) / fsi->chan;
  320. /* get send size for alsa */
  321. send = (fsi->buffer_len - fsi->byte_offset) / width;
  322. /* get FIFO free size */
  323. fifo_free = (fsi->fifo_max * fsi->chan) - fsi_get_fifo_residue(fsi, 1);
  324. /* size check */
  325. if (fifo_free < send)
  326. send = fifo_free;
  327. start = runtime->dma_area;
  328. start += fsi->byte_offset;
  329. switch (width) {
  330. case 2:
  331. for (i = 0; i < send; i++)
  332. fsi_reg_write(fsi, DODT,
  333. ((u32)*((u16 *)start + i) << 8));
  334. break;
  335. case 4:
  336. for (i = 0; i < send; i++)
  337. fsi_reg_write(fsi, DODT, *((u32 *)start + i));
  338. break;
  339. default:
  340. return -EINVAL;
  341. }
  342. fsi->byte_offset += send * width;
  343. fsi_irq_enable(fsi, 1);
  344. if (substream)
  345. snd_pcm_period_elapsed(substream);
  346. return 0;
  347. }
  348. static irqreturn_t fsi_interrupt(int irq, void *data)
  349. {
  350. u32 status = fsi_master_read(SOFT_RST) & ~0x00000010;
  351. u32 int_st = fsi_master_read(INT_ST);
  352. /* clear irq status */
  353. fsi_master_write(SOFT_RST, status);
  354. fsi_master_write(SOFT_RST, status | 0x00000010);
  355. if (int_st & INT_A_OUT)
  356. fsi_data_push(&master->fsia);
  357. if (int_st & INT_B_OUT)
  358. fsi_data_push(&master->fsib);
  359. fsi_master_write(INT_ST, 0x0000000);
  360. return IRQ_HANDLED;
  361. }
  362. /************************************************************************
  363. dai ops
  364. ************************************************************************/
  365. static int fsi_dai_startup(struct snd_pcm_substream *substream,
  366. struct snd_soc_dai *dai)
  367. {
  368. struct fsi_priv *fsi = fsi_get(substream);
  369. const char *msg;
  370. u32 flags = fsi_get_info_flags(fsi);
  371. u32 fmt;
  372. u32 reg;
  373. u32 data;
  374. int is_play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
  375. int is_master;
  376. int ret = 0;
  377. clk_enable(master->clk);
  378. /* CKG1 */
  379. data = is_play ? (1 << 0) : (1 << 4);
  380. is_master = fsi_is_master_mode(fsi, is_play);
  381. if (is_master)
  382. fsi_reg_mask_set(fsi, CKG1, data, data);
  383. else
  384. fsi_reg_mask_set(fsi, CKG1, data, 0);
  385. /* clock inversion (CKG2) */
  386. data = 0;
  387. switch (SH_FSI_INVERSION_MASK & flags) {
  388. case SH_FSI_LRM_INV:
  389. data = 1 << 12;
  390. break;
  391. case SH_FSI_BRM_INV:
  392. data = 1 << 8;
  393. break;
  394. case SH_FSI_LRS_INV:
  395. data = 1 << 4;
  396. break;
  397. case SH_FSI_BRS_INV:
  398. data = 1 << 0;
  399. break;
  400. }
  401. fsi_reg_write(fsi, CKG2, data);
  402. /* do fmt, di fmt */
  403. data = 0;
  404. reg = is_play ? DO_FMT : DI_FMT;
  405. fmt = is_play ? SH_FSI_GET_OFMT(flags) : SH_FSI_GET_IFMT(flags);
  406. switch (fmt) {
  407. case SH_FSI_FMT_MONO:
  408. msg = "MONO";
  409. data = CR_FMT(CR_MONO);
  410. fsi->chan = 1;
  411. break;
  412. case SH_FSI_FMT_MONO_DELAY:
  413. msg = "MONO Delay";
  414. data = CR_FMT(CR_MONO_D);
  415. fsi->chan = 1;
  416. break;
  417. case SH_FSI_FMT_PCM:
  418. msg = "PCM";
  419. data = CR_FMT(CR_PCM);
  420. fsi->chan = 2;
  421. break;
  422. case SH_FSI_FMT_I2S:
  423. msg = "I2S";
  424. data = CR_FMT(CR_I2S);
  425. fsi->chan = 2;
  426. break;
  427. case SH_FSI_FMT_TDM:
  428. msg = "TDM";
  429. data = CR_FMT(CR_TDM) | (fsi->chan - 1);
  430. fsi->chan = is_play ?
  431. SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
  432. break;
  433. case SH_FSI_FMT_TDM_DELAY:
  434. msg = "TDM Delay";
  435. data = CR_FMT(CR_TDM_D) | (fsi->chan - 1);
  436. fsi->chan = is_play ?
  437. SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
  438. break;
  439. default:
  440. dev_err(dai->dev, "unknown format.\n");
  441. return -EINVAL;
  442. }
  443. switch (fsi->chan) {
  444. case 1:
  445. fsi->fifo_max = 256;
  446. break;
  447. case 2:
  448. fsi->fifo_max = 128;
  449. break;
  450. case 3:
  451. case 4:
  452. fsi->fifo_max = 64;
  453. break;
  454. case 5:
  455. case 6:
  456. case 7:
  457. case 8:
  458. fsi->fifo_max = 32;
  459. break;
  460. default:
  461. dev_err(dai->dev, "channel size error.\n");
  462. return -EINVAL;
  463. }
  464. fsi_reg_write(fsi, reg, data);
  465. /*
  466. * clear clk reset if master mode
  467. */
  468. if (is_master)
  469. fsi_clk_ctrl(fsi, 1);
  470. /* irq setting */
  471. fsi_irq_init(fsi, is_play);
  472. return ret;
  473. }
  474. static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
  475. struct snd_soc_dai *dai)
  476. {
  477. struct fsi_priv *fsi = fsi_get(substream);
  478. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  479. fsi_irq_disable(fsi, is_play);
  480. fsi_clk_ctrl(fsi, 0);
  481. clk_disable(master->clk);
  482. }
  483. static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  484. struct snd_soc_dai *dai)
  485. {
  486. struct fsi_priv *fsi = fsi_get(substream);
  487. struct snd_pcm_runtime *runtime = substream->runtime;
  488. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  489. int ret = 0;
  490. /* capture not supported */
  491. if (!is_play)
  492. return -ENODEV;
  493. switch (cmd) {
  494. case SNDRV_PCM_TRIGGER_START:
  495. fsi_stream_push(fsi, substream,
  496. frames_to_bytes(runtime, runtime->buffer_size),
  497. frames_to_bytes(runtime, runtime->period_size));
  498. ret = fsi_data_push(fsi);
  499. break;
  500. case SNDRV_PCM_TRIGGER_STOP:
  501. fsi_irq_disable(fsi, is_play);
  502. fsi_stream_pop(fsi);
  503. break;
  504. }
  505. return ret;
  506. }
  507. static struct snd_soc_dai_ops fsi_dai_ops = {
  508. .startup = fsi_dai_startup,
  509. .shutdown = fsi_dai_shutdown,
  510. .trigger = fsi_dai_trigger,
  511. };
  512. /************************************************************************
  513. pcm ops
  514. ************************************************************************/
  515. static struct snd_pcm_hardware fsi_pcm_hardware = {
  516. .info = SNDRV_PCM_INFO_INTERLEAVED |
  517. SNDRV_PCM_INFO_MMAP |
  518. SNDRV_PCM_INFO_MMAP_VALID |
  519. SNDRV_PCM_INFO_PAUSE,
  520. .formats = FSI_FMTS,
  521. .rates = FSI_RATES,
  522. .rate_min = 8000,
  523. .rate_max = 192000,
  524. .channels_min = 1,
  525. .channels_max = 2,
  526. .buffer_bytes_max = 64 * 1024,
  527. .period_bytes_min = 32,
  528. .period_bytes_max = 8192,
  529. .periods_min = 1,
  530. .periods_max = 32,
  531. .fifo_size = 256,
  532. };
  533. static int fsi_pcm_open(struct snd_pcm_substream *substream)
  534. {
  535. struct snd_pcm_runtime *runtime = substream->runtime;
  536. int ret = 0;
  537. snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
  538. ret = snd_pcm_hw_constraint_integer(runtime,
  539. SNDRV_PCM_HW_PARAM_PERIODS);
  540. return ret;
  541. }
  542. static int fsi_hw_params(struct snd_pcm_substream *substream,
  543. struct snd_pcm_hw_params *hw_params)
  544. {
  545. return snd_pcm_lib_malloc_pages(substream,
  546. params_buffer_bytes(hw_params));
  547. }
  548. static int fsi_hw_free(struct snd_pcm_substream *substream)
  549. {
  550. return snd_pcm_lib_free_pages(substream);
  551. }
  552. static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
  553. {
  554. struct snd_pcm_runtime *runtime = substream->runtime;
  555. struct fsi_priv *fsi = fsi_get(substream);
  556. long location;
  557. location = (fsi->byte_offset - 1);
  558. if (location < 0)
  559. location = 0;
  560. return bytes_to_frames(runtime, location);
  561. }
  562. static struct snd_pcm_ops fsi_pcm_ops = {
  563. .open = fsi_pcm_open,
  564. .ioctl = snd_pcm_lib_ioctl,
  565. .hw_params = fsi_hw_params,
  566. .hw_free = fsi_hw_free,
  567. .pointer = fsi_pointer,
  568. };
  569. /************************************************************************
  570. snd_soc_platform
  571. ************************************************************************/
  572. #define PREALLOC_BUFFER (32 * 1024)
  573. #define PREALLOC_BUFFER_MAX (32 * 1024)
  574. static void fsi_pcm_free(struct snd_pcm *pcm)
  575. {
  576. snd_pcm_lib_preallocate_free_for_all(pcm);
  577. }
  578. static int fsi_pcm_new(struct snd_card *card,
  579. struct snd_soc_dai *dai,
  580. struct snd_pcm *pcm)
  581. {
  582. /*
  583. * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
  584. * in MMAP mode (i.e. aplay -M)
  585. */
  586. return snd_pcm_lib_preallocate_pages_for_all(
  587. pcm,
  588. SNDRV_DMA_TYPE_CONTINUOUS,
  589. snd_dma_continuous_data(GFP_KERNEL),
  590. PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
  591. }
  592. /************************************************************************
  593. alsa struct
  594. ************************************************************************/
  595. struct snd_soc_dai fsi_soc_dai[] = {
  596. {
  597. .name = "FSIA",
  598. .id = 0,
  599. .playback = {
  600. .rates = FSI_RATES,
  601. .formats = FSI_FMTS,
  602. .channels_min = 1,
  603. .channels_max = 8,
  604. },
  605. /* capture not supported */
  606. .ops = &fsi_dai_ops,
  607. },
  608. {
  609. .name = "FSIB",
  610. .id = 1,
  611. .playback = {
  612. .rates = FSI_RATES,
  613. .formats = FSI_FMTS,
  614. .channels_min = 1,
  615. .channels_max = 8,
  616. },
  617. /* capture not supported */
  618. .ops = &fsi_dai_ops,
  619. },
  620. };
  621. EXPORT_SYMBOL_GPL(fsi_soc_dai);
  622. struct snd_soc_platform fsi_soc_platform = {
  623. .name = "fsi-pcm",
  624. .pcm_ops = &fsi_pcm_ops,
  625. .pcm_new = fsi_pcm_new,
  626. .pcm_free = fsi_pcm_free,
  627. };
  628. EXPORT_SYMBOL_GPL(fsi_soc_platform);
  629. /************************************************************************
  630. platform function
  631. ************************************************************************/
  632. static int fsi_probe(struct platform_device *pdev)
  633. {
  634. struct resource *res;
  635. char clk_name[8];
  636. unsigned int irq;
  637. int ret;
  638. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  639. irq = platform_get_irq(pdev, 0);
  640. if (!res || !irq) {
  641. dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
  642. ret = -ENODEV;
  643. goto exit;
  644. }
  645. master = kzalloc(sizeof(*master), GFP_KERNEL);
  646. if (!master) {
  647. dev_err(&pdev->dev, "Could not allocate master\n");
  648. ret = -ENOMEM;
  649. goto exit;
  650. }
  651. master->base = ioremap_nocache(res->start, resource_size(res));
  652. if (!master->base) {
  653. ret = -ENXIO;
  654. dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
  655. goto exit_kfree;
  656. }
  657. master->irq = irq;
  658. master->info = pdev->dev.platform_data;
  659. master->fsia.base = master->base;
  660. master->fsib.base = master->base + 0x40;
  661. /* FSI is based on SPU mstp */
  662. snprintf(clk_name, sizeof(clk_name), "spu%d", pdev->id);
  663. master->clk = clk_get(NULL, clk_name);
  664. if (IS_ERR(master->clk)) {
  665. dev_err(&pdev->dev, "cannot get %s mstp\n", clk_name);
  666. ret = -EIO;
  667. goto exit_iounmap;
  668. }
  669. fsi_soc_dai[0].dev = &pdev->dev;
  670. fsi_soc_dai[1].dev = &pdev->dev;
  671. fsi_soft_all_reset();
  672. ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED, "fsi", master);
  673. if (ret) {
  674. dev_err(&pdev->dev, "irq request err\n");
  675. goto exit_iounmap;
  676. }
  677. ret = snd_soc_register_platform(&fsi_soc_platform);
  678. if (ret < 0) {
  679. dev_err(&pdev->dev, "cannot snd soc register\n");
  680. goto exit_free_irq;
  681. }
  682. return snd_soc_register_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
  683. exit_free_irq:
  684. free_irq(irq, master);
  685. exit_iounmap:
  686. iounmap(master->base);
  687. exit_kfree:
  688. kfree(master);
  689. master = NULL;
  690. exit:
  691. return ret;
  692. }
  693. static int fsi_remove(struct platform_device *pdev)
  694. {
  695. snd_soc_unregister_dais(fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
  696. snd_soc_unregister_platform(&fsi_soc_platform);
  697. clk_put(master->clk);
  698. free_irq(master->irq, master);
  699. iounmap(master->base);
  700. kfree(master);
  701. master = NULL;
  702. return 0;
  703. }
  704. static struct platform_driver fsi_driver = {
  705. .driver = {
  706. .name = "sh_fsi",
  707. },
  708. .probe = fsi_probe,
  709. .remove = fsi_remove,
  710. };
  711. static int __init fsi_mobile_init(void)
  712. {
  713. return platform_driver_register(&fsi_driver);
  714. }
  715. static void __exit fsi_mobile_exit(void)
  716. {
  717. platform_driver_unregister(&fsi_driver);
  718. }
  719. module_init(fsi_mobile_init);
  720. module_exit(fsi_mobile_exit);
  721. MODULE_LICENSE("GPL");
  722. MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
  723. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");