rtc-s3c.c 17 KB

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  1. /* drivers/rtc/rtc-s3c.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * Copyright (c) 2004,2006 Simtec Electronics
  7. * Ben Dooks, <ben@simtec.co.uk>
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * S3C2410/S3C2440/S3C24XX Internal RTC Driver
  15. */
  16. #include <linux/module.h>
  17. #include <linux/fs.h>
  18. #include <linux/string.h>
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/rtc.h>
  23. #include <linux/bcd.h>
  24. #include <linux/clk.h>
  25. #include <linux/log2.h>
  26. #include <linux/slab.h>
  27. #include <linux/of.h>
  28. #include <linux/uaccess.h>
  29. #include <linux/io.h>
  30. #include <mach/hardware.h>
  31. #include <asm/irq.h>
  32. #include <plat/regs-rtc.h>
  33. enum s3c_cpu_type {
  34. TYPE_S3C2410,
  35. TYPE_S3C2416,
  36. TYPE_S3C2443,
  37. TYPE_S3C64XX,
  38. };
  39. struct s3c_rtc_drv_data {
  40. int cpu_type;
  41. };
  42. /* I have yet to find an S3C implementation with more than one
  43. * of these rtc blocks in */
  44. static struct clk *rtc_clk;
  45. static void __iomem *s3c_rtc_base;
  46. static int s3c_rtc_alarmno = NO_IRQ;
  47. static int s3c_rtc_tickno = NO_IRQ;
  48. static enum s3c_cpu_type s3c_rtc_cpu_type;
  49. static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
  50. static void s3c_rtc_alarm_clk_enable(bool enable)
  51. {
  52. static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock);
  53. static bool alarm_clk_enabled;
  54. unsigned long irq_flags;
  55. spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags);
  56. if (enable) {
  57. if (!alarm_clk_enabled) {
  58. clk_enable(rtc_clk);
  59. alarm_clk_enabled = true;
  60. }
  61. } else {
  62. if (alarm_clk_enabled) {
  63. clk_disable(rtc_clk);
  64. alarm_clk_enabled = false;
  65. }
  66. }
  67. spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags);
  68. }
  69. /* IRQ Handlers */
  70. static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
  71. {
  72. struct rtc_device *rdev = id;
  73. clk_enable(rtc_clk);
  74. rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
  75. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  76. writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
  77. clk_disable(rtc_clk);
  78. s3c_rtc_alarm_clk_enable(false);
  79. return IRQ_HANDLED;
  80. }
  81. static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
  82. {
  83. struct rtc_device *rdev = id;
  84. clk_enable(rtc_clk);
  85. rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
  86. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  87. writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
  88. clk_disable(rtc_clk);
  89. return IRQ_HANDLED;
  90. }
  91. /* Update control registers */
  92. static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
  93. {
  94. unsigned int tmp;
  95. dev_dbg(dev, "%s: aie=%d\n", __func__, enabled);
  96. clk_enable(rtc_clk);
  97. tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
  98. if (enabled)
  99. tmp |= S3C2410_RTCALM_ALMEN;
  100. writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
  101. clk_disable(rtc_clk);
  102. s3c_rtc_alarm_clk_enable(enabled);
  103. return 0;
  104. }
  105. static int s3c_rtc_setfreq(struct device *dev, int freq)
  106. {
  107. struct platform_device *pdev = to_platform_device(dev);
  108. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  109. unsigned int tmp = 0;
  110. int val;
  111. if (!is_power_of_2(freq))
  112. return -EINVAL;
  113. clk_enable(rtc_clk);
  114. spin_lock_irq(&s3c_rtc_pie_lock);
  115. if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
  116. tmp = readb(s3c_rtc_base + S3C2410_TICNT);
  117. tmp &= S3C2410_TICNT_ENABLE;
  118. }
  119. val = (rtc_dev->max_user_freq / freq) - 1;
  120. if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
  121. tmp |= S3C2443_TICNT_PART(val);
  122. writel(S3C2443_TICNT1_PART(val), s3c_rtc_base + S3C2443_TICNT1);
  123. if (s3c_rtc_cpu_type == TYPE_S3C2416)
  124. writel(S3C2416_TICNT2_PART(val), s3c_rtc_base + S3C2416_TICNT2);
  125. } else {
  126. tmp |= val;
  127. }
  128. writel(tmp, s3c_rtc_base + S3C2410_TICNT);
  129. spin_unlock_irq(&s3c_rtc_pie_lock);
  130. clk_disable(rtc_clk);
  131. return 0;
  132. }
  133. /* Time read/write */
  134. static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  135. {
  136. unsigned int have_retried = 0;
  137. void __iomem *base = s3c_rtc_base;
  138. clk_enable(rtc_clk);
  139. retry_get_time:
  140. rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
  141. rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
  142. rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
  143. rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
  144. rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
  145. rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
  146. /* the only way to work out whether the system was mid-update
  147. * when we read it is to check the second counter, and if it
  148. * is zero, then we re-try the entire read
  149. */
  150. if (rtc_tm->tm_sec == 0 && !have_retried) {
  151. have_retried = 1;
  152. goto retry_get_time;
  153. }
  154. rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
  155. rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
  156. rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
  157. rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
  158. rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
  159. rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
  160. rtc_tm->tm_year += 100;
  161. dev_dbg(dev, "read time %04d.%02d.%02d %02d:%02d:%02d\n",
  162. 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
  163. rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
  164. rtc_tm->tm_mon -= 1;
  165. clk_disable(rtc_clk);
  166. return rtc_valid_tm(rtc_tm);
  167. }
  168. static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
  169. {
  170. void __iomem *base = s3c_rtc_base;
  171. int year = tm->tm_year - 100;
  172. dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n",
  173. 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
  174. tm->tm_hour, tm->tm_min, tm->tm_sec);
  175. /* we get around y2k by simply not supporting it */
  176. if (year < 0 || year >= 100) {
  177. dev_err(dev, "rtc only supports 100 years\n");
  178. return -EINVAL;
  179. }
  180. clk_enable(rtc_clk);
  181. writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
  182. writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN);
  183. writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR);
  184. writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE);
  185. writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON);
  186. writeb(bin2bcd(year), base + S3C2410_RTCYEAR);
  187. clk_disable(rtc_clk);
  188. return 0;
  189. }
  190. static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
  191. {
  192. struct rtc_time *alm_tm = &alrm->time;
  193. void __iomem *base = s3c_rtc_base;
  194. unsigned int alm_en;
  195. clk_enable(rtc_clk);
  196. alm_tm->tm_sec = readb(base + S3C2410_ALMSEC);
  197. alm_tm->tm_min = readb(base + S3C2410_ALMMIN);
  198. alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
  199. alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
  200. alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
  201. alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
  202. alm_en = readb(base + S3C2410_RTCALM);
  203. alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
  204. dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  205. alm_en,
  206. 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
  207. alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
  208. /* decode the alarm enable field */
  209. if (alm_en & S3C2410_RTCALM_SECEN)
  210. alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
  211. else
  212. alm_tm->tm_sec = -1;
  213. if (alm_en & S3C2410_RTCALM_MINEN)
  214. alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
  215. else
  216. alm_tm->tm_min = -1;
  217. if (alm_en & S3C2410_RTCALM_HOUREN)
  218. alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
  219. else
  220. alm_tm->tm_hour = -1;
  221. if (alm_en & S3C2410_RTCALM_DAYEN)
  222. alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
  223. else
  224. alm_tm->tm_mday = -1;
  225. if (alm_en & S3C2410_RTCALM_MONEN) {
  226. alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
  227. alm_tm->tm_mon -= 1;
  228. } else {
  229. alm_tm->tm_mon = -1;
  230. }
  231. if (alm_en & S3C2410_RTCALM_YEAREN)
  232. alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
  233. else
  234. alm_tm->tm_year = -1;
  235. clk_disable(rtc_clk);
  236. return 0;
  237. }
  238. static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  239. {
  240. struct rtc_time *tm = &alrm->time;
  241. void __iomem *base = s3c_rtc_base;
  242. unsigned int alrm_en;
  243. clk_enable(rtc_clk);
  244. dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  245. alrm->enabled,
  246. 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
  247. tm->tm_hour, tm->tm_min, tm->tm_sec);
  248. alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
  249. writeb(0x00, base + S3C2410_RTCALM);
  250. if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
  251. alrm_en |= S3C2410_RTCALM_SECEN;
  252. writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC);
  253. }
  254. if (tm->tm_min < 60 && tm->tm_min >= 0) {
  255. alrm_en |= S3C2410_RTCALM_MINEN;
  256. writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN);
  257. }
  258. if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
  259. alrm_en |= S3C2410_RTCALM_HOUREN;
  260. writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR);
  261. }
  262. dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en);
  263. writeb(alrm_en, base + S3C2410_RTCALM);
  264. s3c_rtc_setaie(dev, alrm->enabled);
  265. clk_disable(rtc_clk);
  266. return 0;
  267. }
  268. static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
  269. {
  270. unsigned int ticnt;
  271. clk_enable(rtc_clk);
  272. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  273. ticnt = readw(s3c_rtc_base + S3C2410_RTCCON);
  274. ticnt &= S3C64XX_RTCCON_TICEN;
  275. } else {
  276. ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
  277. ticnt &= S3C2410_TICNT_ENABLE;
  278. }
  279. seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
  280. clk_disable(rtc_clk);
  281. return 0;
  282. }
  283. static const struct rtc_class_ops s3c_rtcops = {
  284. .read_time = s3c_rtc_gettime,
  285. .set_time = s3c_rtc_settime,
  286. .read_alarm = s3c_rtc_getalarm,
  287. .set_alarm = s3c_rtc_setalarm,
  288. .proc = s3c_rtc_proc,
  289. .alarm_irq_enable = s3c_rtc_setaie,
  290. };
  291. static void s3c_rtc_enable(struct platform_device *pdev, int en)
  292. {
  293. void __iomem *base = s3c_rtc_base;
  294. unsigned int tmp;
  295. if (s3c_rtc_base == NULL)
  296. return;
  297. clk_enable(rtc_clk);
  298. if (!en) {
  299. tmp = readw(base + S3C2410_RTCCON);
  300. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  301. tmp &= ~S3C64XX_RTCCON_TICEN;
  302. tmp &= ~S3C2410_RTCCON_RTCEN;
  303. writew(tmp, base + S3C2410_RTCCON);
  304. if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
  305. tmp = readb(base + S3C2410_TICNT);
  306. tmp &= ~S3C2410_TICNT_ENABLE;
  307. writeb(tmp, base + S3C2410_TICNT);
  308. }
  309. } else {
  310. /* re-enable the device, and check it is ok */
  311. if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
  312. dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
  313. tmp = readw(base + S3C2410_RTCCON);
  314. writew(tmp | S3C2410_RTCCON_RTCEN,
  315. base + S3C2410_RTCCON);
  316. }
  317. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
  318. dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
  319. tmp = readw(base + S3C2410_RTCCON);
  320. writew(tmp & ~S3C2410_RTCCON_CNTSEL,
  321. base + S3C2410_RTCCON);
  322. }
  323. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
  324. dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
  325. tmp = readw(base + S3C2410_RTCCON);
  326. writew(tmp & ~S3C2410_RTCCON_CLKRST,
  327. base + S3C2410_RTCCON);
  328. }
  329. }
  330. clk_disable(rtc_clk);
  331. }
  332. static int s3c_rtc_remove(struct platform_device *dev)
  333. {
  334. platform_set_drvdata(dev, NULL);
  335. s3c_rtc_setaie(&dev->dev, 0);
  336. rtc_clk = NULL;
  337. return 0;
  338. }
  339. static const struct of_device_id s3c_rtc_dt_match[];
  340. static inline int s3c_rtc_get_driver_data(struct platform_device *pdev)
  341. {
  342. #ifdef CONFIG_OF
  343. struct s3c_rtc_drv_data *data;
  344. if (pdev->dev.of_node) {
  345. const struct of_device_id *match;
  346. match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
  347. data = (struct s3c_rtc_drv_data *) match->data;
  348. return data->cpu_type;
  349. }
  350. #endif
  351. return platform_get_device_id(pdev)->driver_data;
  352. }
  353. static int s3c_rtc_probe(struct platform_device *pdev)
  354. {
  355. struct rtc_device *rtc;
  356. struct rtc_time rtc_tm;
  357. struct resource *res;
  358. int ret;
  359. int tmp;
  360. dev_dbg(&pdev->dev, "%s: probe=%p\n", __func__, pdev);
  361. /* find the IRQs */
  362. s3c_rtc_tickno = platform_get_irq(pdev, 1);
  363. if (s3c_rtc_tickno < 0) {
  364. dev_err(&pdev->dev, "no irq for rtc tick\n");
  365. return s3c_rtc_tickno;
  366. }
  367. s3c_rtc_alarmno = platform_get_irq(pdev, 0);
  368. if (s3c_rtc_alarmno < 0) {
  369. dev_err(&pdev->dev, "no irq for alarm\n");
  370. return s3c_rtc_alarmno;
  371. }
  372. dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n",
  373. s3c_rtc_tickno, s3c_rtc_alarmno);
  374. /* get the memory region */
  375. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  376. if (res == NULL) {
  377. dev_err(&pdev->dev, "failed to get memory region resource\n");
  378. return -ENOENT;
  379. }
  380. s3c_rtc_base = devm_ioremap_resource(&pdev->dev, res);
  381. if (IS_ERR(s3c_rtc_base))
  382. return PTR_ERR(s3c_rtc_base);
  383. rtc_clk = devm_clk_get(&pdev->dev, "rtc");
  384. if (IS_ERR(rtc_clk)) {
  385. dev_err(&pdev->dev, "failed to find rtc clock source\n");
  386. ret = PTR_ERR(rtc_clk);
  387. rtc_clk = NULL;
  388. return ret;
  389. }
  390. clk_enable(rtc_clk);
  391. /* check to see if everything is setup correctly */
  392. s3c_rtc_enable(pdev, 1);
  393. dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n",
  394. readw(s3c_rtc_base + S3C2410_RTCCON));
  395. device_init_wakeup(&pdev->dev, 1);
  396. /* register RTC and exit */
  397. rtc = devm_rtc_device_register(&pdev->dev, "s3c", &s3c_rtcops,
  398. THIS_MODULE);
  399. if (IS_ERR(rtc)) {
  400. dev_err(&pdev->dev, "cannot attach rtc\n");
  401. ret = PTR_ERR(rtc);
  402. goto err_nortc;
  403. }
  404. s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev);
  405. /* Check RTC Time */
  406. s3c_rtc_gettime(NULL, &rtc_tm);
  407. if (rtc_valid_tm(&rtc_tm)) {
  408. rtc_tm.tm_year = 100;
  409. rtc_tm.tm_mon = 0;
  410. rtc_tm.tm_mday = 1;
  411. rtc_tm.tm_hour = 0;
  412. rtc_tm.tm_min = 0;
  413. rtc_tm.tm_sec = 0;
  414. s3c_rtc_settime(NULL, &rtc_tm);
  415. dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
  416. }
  417. if (s3c_rtc_cpu_type != TYPE_S3C2410)
  418. rtc->max_user_freq = 32768;
  419. else
  420. rtc->max_user_freq = 128;
  421. if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
  422. tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
  423. tmp |= S3C2443_RTCCON_TICSEL;
  424. writew(tmp, s3c_rtc_base + S3C2410_RTCCON);
  425. }
  426. platform_set_drvdata(pdev, rtc);
  427. s3c_rtc_setfreq(&pdev->dev, 1);
  428. ret = devm_request_irq(&pdev->dev, s3c_rtc_alarmno, s3c_rtc_alarmirq,
  429. 0, "s3c2410-rtc alarm", rtc);
  430. if (ret) {
  431. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
  432. goto err_alarm_irq;
  433. }
  434. ret = devm_request_irq(&pdev->dev, s3c_rtc_tickno, s3c_rtc_tickirq,
  435. 0, "s3c2410-rtc tick", rtc);
  436. if (ret) {
  437. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
  438. goto err_alarm_irq;
  439. }
  440. clk_disable(rtc_clk);
  441. return 0;
  442. err_alarm_irq:
  443. platform_set_drvdata(pdev, NULL);
  444. err_nortc:
  445. s3c_rtc_enable(pdev, 0);
  446. clk_disable(rtc_clk);
  447. return ret;
  448. }
  449. #ifdef CONFIG_PM_SLEEP
  450. /* RTC Power management control */
  451. static int ticnt_save, ticnt_en_save;
  452. static bool wake_en;
  453. static int s3c_rtc_suspend(struct device *dev)
  454. {
  455. struct platform_device *pdev = to_platform_device(dev);
  456. clk_enable(rtc_clk);
  457. /* save TICNT for anyone using periodic interrupts */
  458. ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
  459. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  460. ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON);
  461. ticnt_en_save &= S3C64XX_RTCCON_TICEN;
  462. }
  463. s3c_rtc_enable(pdev, 0);
  464. if (device_may_wakeup(dev) && !wake_en) {
  465. if (enable_irq_wake(s3c_rtc_alarmno) == 0)
  466. wake_en = true;
  467. else
  468. dev_err(dev, "enable_irq_wake failed\n");
  469. }
  470. clk_disable(rtc_clk);
  471. return 0;
  472. }
  473. static int s3c_rtc_resume(struct device *dev)
  474. {
  475. struct platform_device *pdev = to_platform_device(dev);
  476. unsigned int tmp;
  477. clk_enable(rtc_clk);
  478. s3c_rtc_enable(pdev, 1);
  479. writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
  480. if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) {
  481. tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
  482. writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
  483. }
  484. if (device_may_wakeup(dev) && wake_en) {
  485. disable_irq_wake(s3c_rtc_alarmno);
  486. wake_en = false;
  487. }
  488. clk_disable(rtc_clk);
  489. return 0;
  490. }
  491. #endif
  492. static SIMPLE_DEV_PM_OPS(s3c_rtc_pm_ops, s3c_rtc_suspend, s3c_rtc_resume);
  493. #ifdef CONFIG_OF
  494. static struct s3c_rtc_drv_data s3c_rtc_drv_data_array[] = {
  495. [TYPE_S3C2410] = { TYPE_S3C2410 },
  496. [TYPE_S3C2416] = { TYPE_S3C2416 },
  497. [TYPE_S3C2443] = { TYPE_S3C2443 },
  498. [TYPE_S3C64XX] = { TYPE_S3C64XX },
  499. };
  500. static const struct of_device_id s3c_rtc_dt_match[] = {
  501. {
  502. .compatible = "samsung,s3c2410-rtc",
  503. .data = &s3c_rtc_drv_data_array[TYPE_S3C2410],
  504. }, {
  505. .compatible = "samsung,s3c2416-rtc",
  506. .data = &s3c_rtc_drv_data_array[TYPE_S3C2416],
  507. }, {
  508. .compatible = "samsung,s3c2443-rtc",
  509. .data = &s3c_rtc_drv_data_array[TYPE_S3C2443],
  510. }, {
  511. .compatible = "samsung,s3c6410-rtc",
  512. .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX],
  513. },
  514. {},
  515. };
  516. MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
  517. #endif
  518. static struct platform_device_id s3c_rtc_driver_ids[] = {
  519. {
  520. .name = "s3c2410-rtc",
  521. .driver_data = TYPE_S3C2410,
  522. }, {
  523. .name = "s3c2416-rtc",
  524. .driver_data = TYPE_S3C2416,
  525. }, {
  526. .name = "s3c2443-rtc",
  527. .driver_data = TYPE_S3C2443,
  528. }, {
  529. .name = "s3c64xx-rtc",
  530. .driver_data = TYPE_S3C64XX,
  531. },
  532. { }
  533. };
  534. MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
  535. static struct platform_driver s3c_rtc_driver = {
  536. .probe = s3c_rtc_probe,
  537. .remove = s3c_rtc_remove,
  538. .id_table = s3c_rtc_driver_ids,
  539. .driver = {
  540. .name = "s3c-rtc",
  541. .owner = THIS_MODULE,
  542. .pm = &s3c_rtc_pm_ops,
  543. .of_match_table = of_match_ptr(s3c_rtc_dt_match),
  544. },
  545. };
  546. module_platform_driver(s3c_rtc_driver);
  547. MODULE_DESCRIPTION("Samsung S3C RTC Driver");
  548. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  549. MODULE_LICENSE("GPL");
  550. MODULE_ALIAS("platform:s3c2410-rtc");