Kconfig 19 KB

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  1. comment "Processor Type"
  2. config CPU_32
  3. bool
  4. default y
  5. # Select CPU types depending on the architecture selected. This selects
  6. # which CPUs we support in the kernel image, and the compiler instruction
  7. # optimiser behaviour.
  8. # ARM610
  9. config CPU_ARM610
  10. bool "Support ARM610 processor" if ARCH_RPC
  11. select CPU_32v3
  12. select CPU_CACHE_V3
  13. select CPU_CACHE_VIVT
  14. select CPU_CP15_MMU
  15. select CPU_COPY_V3 if MMU
  16. select CPU_TLB_V3 if MMU
  17. select CPU_PABRT_LEGACY
  18. help
  19. The ARM610 is the successor to the ARM3 processor
  20. and was produced by VLSI Technology Inc.
  21. Say Y if you want support for the ARM610 processor.
  22. Otherwise, say N.
  23. # ARM7TDMI
  24. config CPU_ARM7TDMI
  25. bool "Support ARM7TDMI processor"
  26. depends on !MMU
  27. select CPU_32v4T
  28. select CPU_ABRT_LV4T
  29. select CPU_PABRT_LEGACY
  30. select CPU_CACHE_V4
  31. help
  32. A 32-bit RISC microprocessor based on the ARM7 processor core
  33. which has no memory control unit and cache.
  34. Say Y if you want support for the ARM7TDMI processor.
  35. Otherwise, say N.
  36. # ARM710
  37. config CPU_ARM710
  38. bool "Support ARM710 processor" if ARCH_RPC
  39. select CPU_32v3
  40. select CPU_CACHE_V3
  41. select CPU_CACHE_VIVT
  42. select CPU_CP15_MMU
  43. select CPU_COPY_V3 if MMU
  44. select CPU_TLB_V3 if MMU
  45. select CPU_PABRT_LEGACY
  46. help
  47. A 32-bit RISC microprocessor based on the ARM7 processor core
  48. designed by Advanced RISC Machines Ltd. The ARM710 is the
  49. successor to the ARM610 processor. It was released in
  50. July 1994 by VLSI Technology Inc.
  51. Say Y if you want support for the ARM710 processor.
  52. Otherwise, say N.
  53. # ARM720T
  54. config CPU_ARM720T
  55. bool "Support ARM720T processor" if ARCH_INTEGRATOR
  56. select CPU_32v4T
  57. select CPU_ABRT_LV4T
  58. select CPU_PABRT_LEGACY
  59. select CPU_CACHE_V4
  60. select CPU_CACHE_VIVT
  61. select CPU_CP15_MMU
  62. select CPU_COPY_V4WT if MMU
  63. select CPU_TLB_V4WT if MMU
  64. help
  65. A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  66. MMU built around an ARM7TDMI core.
  67. Say Y if you want support for the ARM720T processor.
  68. Otherwise, say N.
  69. # ARM740T
  70. config CPU_ARM740T
  71. bool "Support ARM740T processor" if ARCH_INTEGRATOR
  72. depends on !MMU
  73. select CPU_32v4T
  74. select CPU_ABRT_LV4T
  75. select CPU_PABRT_LEGACY
  76. select CPU_CACHE_V3 # although the core is v4t
  77. select CPU_CP15_MPU
  78. help
  79. A 32-bit RISC processor with 8KB cache or 4KB variants,
  80. write buffer and MPU(Protection Unit) built around
  81. an ARM7TDMI core.
  82. Say Y if you want support for the ARM740T processor.
  83. Otherwise, say N.
  84. # ARM9TDMI
  85. config CPU_ARM9TDMI
  86. bool "Support ARM9TDMI processor"
  87. depends on !MMU
  88. select CPU_32v4T
  89. select CPU_ABRT_NOMMU
  90. select CPU_PABRT_LEGACY
  91. select CPU_CACHE_V4
  92. help
  93. A 32-bit RISC microprocessor based on the ARM9 processor core
  94. which has no memory control unit and cache.
  95. Say Y if you want support for the ARM9TDMI processor.
  96. Otherwise, say N.
  97. # ARM920T
  98. config CPU_ARM920T
  99. bool "Support ARM920T processor" if ARCH_INTEGRATOR
  100. select CPU_32v4T
  101. select CPU_ABRT_EV4T
  102. select CPU_PABRT_LEGACY
  103. select CPU_CACHE_V4WT
  104. select CPU_CACHE_VIVT
  105. select CPU_CP15_MMU
  106. select CPU_COPY_V4WB if MMU
  107. select CPU_TLB_V4WBI if MMU
  108. help
  109. The ARM920T is licensed to be produced by numerous vendors,
  110. and is used in the Maverick EP9312 and the Samsung S3C2410.
  111. More information on the Maverick EP9312 at
  112. <http://linuxdevices.com/products/PD2382866068.html>.
  113. Say Y if you want support for the ARM920T processor.
  114. Otherwise, say N.
  115. # ARM922T
  116. config CPU_ARM922T
  117. bool "Support ARM922T processor" if ARCH_INTEGRATOR
  118. select CPU_32v4T
  119. select CPU_ABRT_EV4T
  120. select CPU_PABRT_LEGACY
  121. select CPU_CACHE_V4WT
  122. select CPU_CACHE_VIVT
  123. select CPU_CP15_MMU
  124. select CPU_COPY_V4WB if MMU
  125. select CPU_TLB_V4WBI if MMU
  126. help
  127. The ARM922T is a version of the ARM920T, but with smaller
  128. instruction and data caches. It is used in Altera's
  129. Excalibur XA device family and Micrel's KS8695 Centaur.
  130. Say Y if you want support for the ARM922T processor.
  131. Otherwise, say N.
  132. # ARM925T
  133. config CPU_ARM925T
  134. bool "Support ARM925T processor" if ARCH_OMAP1
  135. select CPU_32v4T
  136. select CPU_ABRT_EV4T
  137. select CPU_PABRT_LEGACY
  138. select CPU_CACHE_V4WT
  139. select CPU_CACHE_VIVT
  140. select CPU_CP15_MMU
  141. select CPU_COPY_V4WB if MMU
  142. select CPU_TLB_V4WBI if MMU
  143. help
  144. The ARM925T is a mix between the ARM920T and ARM926T, but with
  145. different instruction and data caches. It is used in TI's OMAP
  146. device family.
  147. Say Y if you want support for the ARM925T processor.
  148. Otherwise, say N.
  149. # ARM926T
  150. config CPU_ARM926T
  151. bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
  152. select CPU_32v5
  153. select CPU_ABRT_EV5TJ
  154. select CPU_PABRT_LEGACY
  155. select CPU_CACHE_VIVT
  156. select CPU_CP15_MMU
  157. select CPU_COPY_V4WB if MMU
  158. select CPU_TLB_V4WBI if MMU
  159. help
  160. This is a variant of the ARM920. It has slightly different
  161. instruction sequences for cache and TLB operations. Curiously,
  162. there is no documentation on it at the ARM corporate website.
  163. Say Y if you want support for the ARM926T processor.
  164. Otherwise, say N.
  165. # FA526
  166. config CPU_FA526
  167. bool
  168. select CPU_32v4
  169. select CPU_ABRT_EV4
  170. select CPU_PABRT_LEGACY
  171. select CPU_CACHE_VIVT
  172. select CPU_CP15_MMU
  173. select CPU_CACHE_FA
  174. select CPU_COPY_FA if MMU
  175. select CPU_TLB_FA if MMU
  176. help
  177. The FA526 is a version of the ARMv4 compatible processor with
  178. Branch Target Buffer, Unified TLB and cache line size 16.
  179. Say Y if you want support for the FA526 processor.
  180. Otherwise, say N.
  181. # ARM940T
  182. config CPU_ARM940T
  183. bool "Support ARM940T processor" if ARCH_INTEGRATOR
  184. depends on !MMU
  185. select CPU_32v4T
  186. select CPU_ABRT_NOMMU
  187. select CPU_PABRT_LEGACY
  188. select CPU_CACHE_VIVT
  189. select CPU_CP15_MPU
  190. help
  191. ARM940T is a member of the ARM9TDMI family of general-
  192. purpose microprocessors with MPU and separate 4KB
  193. instruction and 4KB data cases, each with a 4-word line
  194. length.
  195. Say Y if you want support for the ARM940T processor.
  196. Otherwise, say N.
  197. # ARM946E-S
  198. config CPU_ARM946E
  199. bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
  200. depends on !MMU
  201. select CPU_32v5
  202. select CPU_ABRT_NOMMU
  203. select CPU_PABRT_LEGACY
  204. select CPU_CACHE_VIVT
  205. select CPU_CP15_MPU
  206. help
  207. ARM946E-S is a member of the ARM9E-S family of high-
  208. performance, 32-bit system-on-chip processor solutions.
  209. The TCM and ARMv5TE 32-bit instruction set is supported.
  210. Say Y if you want support for the ARM946E-S processor.
  211. Otherwise, say N.
  212. # ARM1020 - needs validating
  213. config CPU_ARM1020
  214. bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
  215. select CPU_32v5
  216. select CPU_ABRT_EV4T
  217. select CPU_PABRT_LEGACY
  218. select CPU_CACHE_V4WT
  219. select CPU_CACHE_VIVT
  220. select CPU_CP15_MMU
  221. select CPU_COPY_V4WB if MMU
  222. select CPU_TLB_V4WBI if MMU
  223. help
  224. The ARM1020 is the 32K cached version of the ARM10 processor,
  225. with an addition of a floating-point unit.
  226. Say Y if you want support for the ARM1020 processor.
  227. Otherwise, say N.
  228. # ARM1020E - needs validating
  229. config CPU_ARM1020E
  230. bool "Support ARM1020E processor" if ARCH_INTEGRATOR
  231. select CPU_32v5
  232. select CPU_ABRT_EV4T
  233. select CPU_PABRT_LEGACY
  234. select CPU_CACHE_V4WT
  235. select CPU_CACHE_VIVT
  236. select CPU_CP15_MMU
  237. select CPU_COPY_V4WB if MMU
  238. select CPU_TLB_V4WBI if MMU
  239. depends on n
  240. # ARM1022E
  241. config CPU_ARM1022
  242. bool "Support ARM1022E processor" if ARCH_INTEGRATOR
  243. select CPU_32v5
  244. select CPU_ABRT_EV4T
  245. select CPU_PABRT_LEGACY
  246. select CPU_CACHE_VIVT
  247. select CPU_CP15_MMU
  248. select CPU_COPY_V4WB if MMU # can probably do better
  249. select CPU_TLB_V4WBI if MMU
  250. help
  251. The ARM1022E is an implementation of the ARMv5TE architecture
  252. based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
  253. embedded trace macrocell, and a floating-point unit.
  254. Say Y if you want support for the ARM1022E processor.
  255. Otherwise, say N.
  256. # ARM1026EJ-S
  257. config CPU_ARM1026
  258. bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
  259. select CPU_32v5
  260. select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
  261. select CPU_PABRT_LEGACY
  262. select CPU_CACHE_VIVT
  263. select CPU_CP15_MMU
  264. select CPU_COPY_V4WB if MMU # can probably do better
  265. select CPU_TLB_V4WBI if MMU
  266. help
  267. The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
  268. based upon the ARM10 integer core.
  269. Say Y if you want support for the ARM1026EJ-S processor.
  270. Otherwise, say N.
  271. # SA110
  272. config CPU_SA110
  273. bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
  274. select CPU_32v3 if ARCH_RPC
  275. select CPU_32v4 if !ARCH_RPC
  276. select CPU_ABRT_EV4
  277. select CPU_PABRT_LEGACY
  278. select CPU_CACHE_V4WB
  279. select CPU_CACHE_VIVT
  280. select CPU_CP15_MMU
  281. select CPU_COPY_V4WB if MMU
  282. select CPU_TLB_V4WB if MMU
  283. help
  284. The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
  285. is available at five speeds ranging from 100 MHz to 233 MHz.
  286. More information is available at
  287. <http://developer.intel.com/design/strong/sa110.htm>.
  288. Say Y if you want support for the SA-110 processor.
  289. Otherwise, say N.
  290. # SA1100
  291. config CPU_SA1100
  292. bool
  293. select CPU_32v4
  294. select CPU_ABRT_EV4
  295. select CPU_PABRT_LEGACY
  296. select CPU_CACHE_V4WB
  297. select CPU_CACHE_VIVT
  298. select CPU_CP15_MMU
  299. select CPU_TLB_V4WB if MMU
  300. # XScale
  301. config CPU_XSCALE
  302. bool
  303. select CPU_32v5
  304. select CPU_ABRT_EV5T
  305. select CPU_PABRT_LEGACY
  306. select CPU_CACHE_VIVT
  307. select CPU_CP15_MMU
  308. select CPU_TLB_V4WBI if MMU
  309. # XScale Core Version 3
  310. config CPU_XSC3
  311. bool
  312. select CPU_32v5
  313. select CPU_ABRT_EV5T
  314. select CPU_PABRT_LEGACY
  315. select CPU_CACHE_VIVT
  316. select CPU_CP15_MMU
  317. select CPU_TLB_V4WBI if MMU
  318. select IO_36
  319. # Marvell PJ1 (Mohawk)
  320. config CPU_MOHAWK
  321. bool
  322. select CPU_32v5
  323. select CPU_ABRT_EV5T
  324. select CPU_PABRT_LEGACY
  325. select CPU_CACHE_VIVT
  326. select CPU_CP15_MMU
  327. select CPU_TLB_V4WBI if MMU
  328. select CPU_COPY_V4WB if MMU
  329. # Feroceon
  330. config CPU_FEROCEON
  331. bool
  332. select CPU_32v5
  333. select CPU_ABRT_EV5T
  334. select CPU_PABRT_LEGACY
  335. select CPU_CACHE_VIVT
  336. select CPU_CP15_MMU
  337. select CPU_COPY_FEROCEON if MMU
  338. select CPU_TLB_FEROCEON if MMU
  339. config CPU_FEROCEON_OLD_ID
  340. bool "Accept early Feroceon cores with an ARM926 ID"
  341. depends on CPU_FEROCEON && !CPU_ARM926T
  342. default y
  343. help
  344. This enables the usage of some old Feroceon cores
  345. for which the CPU ID is equal to the ARM926 ID.
  346. Relevant for Feroceon-1850 and early Feroceon-2850.
  347. # ARMv6
  348. config CPU_V6
  349. bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
  350. select CPU_32v6
  351. select CPU_ABRT_EV6
  352. select CPU_PABRT_V6
  353. select CPU_CACHE_V6
  354. select CPU_CACHE_VIPT
  355. select CPU_CP15_MMU
  356. select CPU_HAS_ASID if MMU
  357. select CPU_COPY_V6 if MMU
  358. select CPU_TLB_V6 if MMU
  359. # ARMv6k
  360. config CPU_32v6K
  361. bool "Support ARM V6K processor extensions" if !SMP
  362. depends on CPU_V6
  363. default y if SMP && !ARCH_MX3
  364. help
  365. Say Y here if your ARMv6 processor supports the 'K' extension.
  366. This enables the kernel to use some instructions not present
  367. on previous processors, and as such a kernel build with this
  368. enabled will not boot on processors with do not support these
  369. instructions.
  370. # ARMv7
  371. config CPU_V7
  372. bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
  373. select CPU_32v6K
  374. select CPU_32v7
  375. select CPU_ABRT_EV7
  376. select CPU_PABRT_V7
  377. select CPU_CACHE_V7
  378. select CPU_CACHE_VIPT
  379. select CPU_CP15_MMU
  380. select CPU_HAS_ASID if MMU
  381. select CPU_COPY_V6 if MMU
  382. select CPU_TLB_V7 if MMU
  383. # Figure out what processor architecture version we should be using.
  384. # This defines the compiler instruction set which depends on the machine type.
  385. config CPU_32v3
  386. bool
  387. select TLS_REG_EMUL if SMP || !MMU
  388. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  389. config CPU_32v4
  390. bool
  391. select TLS_REG_EMUL if SMP || !MMU
  392. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  393. config CPU_32v4T
  394. bool
  395. select TLS_REG_EMUL if SMP || !MMU
  396. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  397. config CPU_32v5
  398. bool
  399. select TLS_REG_EMUL if SMP || !MMU
  400. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  401. config CPU_32v6
  402. bool
  403. select TLS_REG_EMUL if !CPU_32v6K && !MMU
  404. config CPU_32v7
  405. bool
  406. # The abort model
  407. config CPU_ABRT_NOMMU
  408. bool
  409. config CPU_ABRT_EV4
  410. bool
  411. config CPU_ABRT_EV4T
  412. bool
  413. config CPU_ABRT_LV4T
  414. bool
  415. config CPU_ABRT_EV5T
  416. bool
  417. config CPU_ABRT_EV5TJ
  418. bool
  419. config CPU_ABRT_EV6
  420. bool
  421. config CPU_ABRT_EV7
  422. bool
  423. config CPU_PABRT_LEGACY
  424. bool
  425. config CPU_PABRT_V6
  426. bool
  427. config CPU_PABRT_V7
  428. bool
  429. # The cache model
  430. config CPU_CACHE_V3
  431. bool
  432. config CPU_CACHE_V4
  433. bool
  434. config CPU_CACHE_V4WT
  435. bool
  436. config CPU_CACHE_V4WB
  437. bool
  438. config CPU_CACHE_V6
  439. bool
  440. config CPU_CACHE_V7
  441. bool
  442. config CPU_CACHE_VIVT
  443. bool
  444. config CPU_CACHE_VIPT
  445. bool
  446. config CPU_CACHE_FA
  447. bool
  448. if MMU
  449. # The copy-page model
  450. config CPU_COPY_V3
  451. bool
  452. config CPU_COPY_V4WT
  453. bool
  454. config CPU_COPY_V4WB
  455. bool
  456. config CPU_COPY_FEROCEON
  457. bool
  458. config CPU_COPY_FA
  459. bool
  460. config CPU_COPY_V6
  461. bool
  462. # This selects the TLB model
  463. config CPU_TLB_V3
  464. bool
  465. help
  466. ARM Architecture Version 3 TLB.
  467. config CPU_TLB_V4WT
  468. bool
  469. help
  470. ARM Architecture Version 4 TLB with writethrough cache.
  471. config CPU_TLB_V4WB
  472. bool
  473. help
  474. ARM Architecture Version 4 TLB with writeback cache.
  475. config CPU_TLB_V4WBI
  476. bool
  477. help
  478. ARM Architecture Version 4 TLB with writeback cache and invalidate
  479. instruction cache entry.
  480. config CPU_TLB_FEROCEON
  481. bool
  482. help
  483. Feroceon TLB (v4wbi with non-outer-cachable page table walks).
  484. config CPU_TLB_FA
  485. bool
  486. help
  487. Faraday ARM FA526 architecture, unified TLB with writeback cache
  488. and invalidate instruction cache entry. Branch target buffer is
  489. also supported.
  490. config CPU_TLB_V6
  491. bool
  492. config CPU_TLB_V7
  493. bool
  494. endif
  495. config CPU_HAS_ASID
  496. bool
  497. help
  498. This indicates whether the CPU has the ASID register; used to
  499. tag TLB and possibly cache entries.
  500. config CPU_CP15
  501. bool
  502. help
  503. Processor has the CP15 register.
  504. config CPU_CP15_MMU
  505. bool
  506. select CPU_CP15
  507. help
  508. Processor has the CP15 register, which has MMU related registers.
  509. config CPU_CP15_MPU
  510. bool
  511. select CPU_CP15
  512. help
  513. Processor has the CP15 register, which has MPU related registers.
  514. #
  515. # CPU supports 36-bit I/O
  516. #
  517. config IO_36
  518. bool
  519. comment "Processor Features"
  520. config ARM_THUMB
  521. bool "Support Thumb user binaries"
  522. depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON
  523. default y
  524. help
  525. Say Y if you want to include kernel support for running user space
  526. Thumb binaries.
  527. The Thumb instruction set is a compressed form of the standard ARM
  528. instruction set resulting in smaller binaries at the expense of
  529. slightly less efficient code.
  530. If you don't know what this all is, saying Y is a safe choice.
  531. config ARM_THUMBEE
  532. bool "Enable ThumbEE CPU extension"
  533. depends on CPU_V7
  534. help
  535. Say Y here if you have a CPU with the ThumbEE extension and code to
  536. make use of it. Say N for code that can run on CPUs without ThumbEE.
  537. config CPU_BIG_ENDIAN
  538. bool "Build big-endian kernel"
  539. depends on ARCH_SUPPORTS_BIG_ENDIAN
  540. help
  541. Say Y if you plan on running a kernel in big-endian mode.
  542. Note that your board must be properly built and your board
  543. port must properly enable any big-endian related features
  544. of your chipset/board/processor.
  545. config CPU_ENDIAN_BE8
  546. bool
  547. depends on CPU_BIG_ENDIAN
  548. default CPU_V6 || CPU_V7
  549. help
  550. Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
  551. config CPU_ENDIAN_BE32
  552. bool
  553. depends on CPU_BIG_ENDIAN
  554. default !CPU_ENDIAN_BE8
  555. help
  556. Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
  557. config CPU_HIGH_VECTOR
  558. depends on !MMU && CPU_CP15 && !CPU_ARM740T
  559. bool "Select the High exception vector"
  560. help
  561. Say Y here to select high exception vector(0xFFFF0000~).
  562. The exception vector can be vary depending on the platform
  563. design in nommu mode. If your platform needs to select
  564. high exception vector, say Y.
  565. Otherwise or if you are unsure, say N, and the low exception
  566. vector (0x00000000~) will be used.
  567. config CPU_ICACHE_DISABLE
  568. bool "Disable I-Cache (I-bit)"
  569. depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
  570. help
  571. Say Y here to disable the processor instruction cache. Unless
  572. you have a reason not to or are unsure, say N.
  573. config CPU_DCACHE_DISABLE
  574. bool "Disable D-Cache (C-bit)"
  575. depends on CPU_CP15
  576. help
  577. Say Y here to disable the processor data cache. Unless
  578. you have a reason not to or are unsure, say N.
  579. config CPU_DCACHE_SIZE
  580. hex
  581. depends on CPU_ARM740T || CPU_ARM946E
  582. default 0x00001000 if CPU_ARM740T
  583. default 0x00002000 # default size for ARM946E-S
  584. help
  585. Some cores are synthesizable to have various sized cache. For
  586. ARM946E-S case, it can vary from 0KB to 1MB.
  587. To support such cache operations, it is efficient to know the size
  588. before compile time.
  589. If your SoC is configured to have a different size, define the value
  590. here with proper conditions.
  591. config CPU_DCACHE_WRITETHROUGH
  592. bool "Force write through D-cache"
  593. depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
  594. default y if CPU_ARM925T
  595. help
  596. Say Y here to use the data cache in writethrough mode. Unless you
  597. specifically require this or are unsure, say N.
  598. config CPU_CACHE_ROUND_ROBIN
  599. bool "Round robin I and D cache replacement algorithm"
  600. depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
  601. help
  602. Say Y here to use the predictable round-robin cache replacement
  603. policy. Unless you specifically require this or are unsure, say N.
  604. config CPU_BPREDICT_DISABLE
  605. bool "Disable branch prediction"
  606. depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
  607. help
  608. Say Y here to disable branch prediction. If unsure, say N.
  609. config TLS_REG_EMUL
  610. bool
  611. help
  612. An SMP system using a pre-ARMv6 processor (there are apparently
  613. a few prototypes like that in existence) and therefore access to
  614. that required register must be emulated.
  615. config HAS_TLS_REG
  616. bool
  617. depends on !TLS_REG_EMUL
  618. default y if SMP || CPU_32v7
  619. help
  620. This selects support for the CP15 thread register.
  621. It is defined to be available on some ARMv6 processors (including
  622. all SMP capable ARMv6's) or later processors. User space may
  623. assume directly accessing that register and always obtain the
  624. expected value only on ARMv7 and above.
  625. config NEEDS_SYSCALL_FOR_CMPXCHG
  626. bool
  627. help
  628. SMP on a pre-ARMv6 processor? Well OK then.
  629. Forget about fast user space cmpxchg support.
  630. It is just not possible.
  631. config OUTER_CACHE
  632. bool
  633. config CACHE_FEROCEON_L2
  634. bool "Enable the Feroceon L2 cache controller"
  635. depends on ARCH_KIRKWOOD || ARCH_MV78XX0
  636. default y
  637. select OUTER_CACHE
  638. help
  639. This option enables the Feroceon L2 cache controller.
  640. config CACHE_FEROCEON_L2_WRITETHROUGH
  641. bool "Force Feroceon L2 cache write through"
  642. depends on CACHE_FEROCEON_L2
  643. help
  644. Say Y here to use the Feroceon L2 cache in writethrough mode.
  645. Unless you specifically require this, say N for writeback mode.
  646. config CACHE_L2X0
  647. bool "Enable the L2x0 outer cache controller"
  648. depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
  649. REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK
  650. default y
  651. select OUTER_CACHE
  652. help
  653. This option enables the L2x0 PrimeCell.
  654. config CACHE_XSC3L2
  655. bool "Enable the L2 cache on XScale3"
  656. depends on CPU_XSC3
  657. default y
  658. select OUTER_CACHE
  659. help
  660. This option enables the L2 cache on XScale3.
  661. config ARM_L1_CACHE_SHIFT
  662. int
  663. default 6 if ARCH_OMAP3
  664. default 5