nxt2002.c 16 KB

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  1. /*
  2. Support for B2C2/BBTI Technisat Air2PC - ATSC
  3. Copyright (C) 2004 Taylor Jacob <rtjacob@earthlink.net>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software
  14. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  15. */
  16. /*
  17. * This driver needs external firmware. Please use the command
  18. * "<kerneldir>/Documentation/dvb/get_dvb_firmware nxt2002" to
  19. * download/extract it, and then copy it to /usr/lib/hotplug/firmware.
  20. */
  21. #define NXT2002_DEFAULT_FIRMWARE "dvb-fe-nxt2002.fw"
  22. #define CRC_CCIT_MASK 0x1021
  23. #include <linux/init.h>
  24. #include <linux/module.h>
  25. #include <linux/moduleparam.h>
  26. #include <linux/device.h>
  27. #include <linux/firmware.h>
  28. #include <linux/string.h>
  29. #include <linux/slab.h>
  30. #include "dvb_frontend.h"
  31. #include "nxt2002.h"
  32. struct nxt2002_state {
  33. struct i2c_adapter* i2c;
  34. struct dvb_frontend_ops ops;
  35. const struct nxt2002_config* config;
  36. struct dvb_frontend frontend;
  37. /* demodulator private data */
  38. u8 initialised:1;
  39. };
  40. static int debug;
  41. #define dprintk(args...) \
  42. do { \
  43. if (debug) printk(KERN_DEBUG "nxt2002: " args); \
  44. } while (0)
  45. static int i2c_writebytes (struct nxt2002_state* state, u8 reg, u8 *buf, u8 len)
  46. {
  47. /* probbably a much better way or doing this */
  48. u8 buf2 [256],x;
  49. int err;
  50. struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len + 1 };
  51. buf2[0] = reg;
  52. for (x = 0 ; x < len ; x++)
  53. buf2[x+1] = buf[x];
  54. if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
  55. printk ("%s: i2c write error (addr %02x, err == %i)\n",
  56. __FUNCTION__, state->config->demod_address, err);
  57. return -EREMOTEIO;
  58. }
  59. return 0;
  60. }
  61. static u8 i2c_readbytes (struct nxt2002_state* state, u8 reg, u8* buf, u8 len)
  62. {
  63. u8 reg2 [] = { reg };
  64. struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 },
  65. { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = buf, .len = len } };
  66. int err;
  67. if ((err = i2c_transfer (state->i2c, msg, 2)) != 2) {
  68. printk ("%s: i2c read error (addr %02x, err == %i)\n",
  69. __FUNCTION__, state->config->demod_address, err);
  70. return -EREMOTEIO;
  71. }
  72. return 0;
  73. }
  74. static u16 nxt2002_crc(u16 crc, u8 c)
  75. {
  76. u8 i;
  77. u16 input = (u16) c & 0xFF;
  78. input<<=8;
  79. for(i=0 ;i<8 ;i++) {
  80. if((crc ^ input) & 0x8000)
  81. crc=(crc<<1)^CRC_CCIT_MASK;
  82. else
  83. crc<<=1;
  84. input<<=1;
  85. }
  86. return crc;
  87. }
  88. static int nxt2002_writereg_multibyte (struct nxt2002_state* state, u8 reg, u8* data, u8 len)
  89. {
  90. u8 buf;
  91. dprintk("%s\n", __FUNCTION__);
  92. /* set multi register length */
  93. i2c_writebytes(state,0x34,&len,1);
  94. /* set mutli register register */
  95. i2c_writebytes(state,0x35,&reg,1);
  96. /* send the actual data */
  97. i2c_writebytes(state,0x36,data,len);
  98. /* toggle the multireg write bit*/
  99. buf = 0x02;
  100. i2c_writebytes(state,0x21,&buf,1);
  101. i2c_readbytes(state,0x21,&buf,1);
  102. if ((buf & 0x02) == 0)
  103. return 0;
  104. dprintk("Error writing multireg register %02X\n",reg);
  105. return 0;
  106. }
  107. static int nxt2002_readreg_multibyte (struct nxt2002_state* state, u8 reg, u8* data, u8 len)
  108. {
  109. u8 len2;
  110. dprintk("%s\n", __FUNCTION__);
  111. /* set multi register length */
  112. len2 = len & 0x80;
  113. i2c_writebytes(state,0x34,&len2,1);
  114. /* set mutli register register */
  115. i2c_writebytes(state,0x35,&reg,1);
  116. /* send the actual data */
  117. i2c_readbytes(state,reg,data,len);
  118. return 0;
  119. }
  120. static void nxt2002_microcontroller_stop (struct nxt2002_state* state)
  121. {
  122. u8 buf[2],counter = 0;
  123. dprintk("%s\n", __FUNCTION__);
  124. buf[0] = 0x80;
  125. i2c_writebytes(state,0x22,buf,1);
  126. while (counter < 20) {
  127. i2c_readbytes(state,0x31,buf,1);
  128. if (buf[0] & 0x40)
  129. return;
  130. msleep(10);
  131. counter++;
  132. }
  133. dprintk("Timeout waiting for micro to stop.. This is ok after firmware upload\n");
  134. return;
  135. }
  136. static void nxt2002_microcontroller_start (struct nxt2002_state* state)
  137. {
  138. u8 buf;
  139. dprintk("%s\n", __FUNCTION__);
  140. buf = 0x00;
  141. i2c_writebytes(state,0x22,&buf,1);
  142. }
  143. static int nxt2002_writetuner (struct nxt2002_state* state, u8* data)
  144. {
  145. u8 buf,count = 0;
  146. dprintk("Tuner Bytes: %02X %02X %02X %02X\n",data[0],data[1],data[2],data[3]);
  147. dprintk("%s\n", __FUNCTION__);
  148. /* stop the micro first */
  149. nxt2002_microcontroller_stop(state);
  150. /* set the i2c transfer speed to the tuner */
  151. buf = 0x03;
  152. i2c_writebytes(state,0x20,&buf,1);
  153. /* setup to transfer 4 bytes via i2c */
  154. buf = 0x04;
  155. i2c_writebytes(state,0x34,&buf,1);
  156. /* write actual tuner bytes */
  157. i2c_writebytes(state,0x36,data,4);
  158. /* set tuner i2c address */
  159. buf = 0xC2;
  160. i2c_writebytes(state,0x35,&buf,1);
  161. /* write UC Opmode to begin transfer */
  162. buf = 0x80;
  163. i2c_writebytes(state,0x21,&buf,1);
  164. while (count < 20) {
  165. i2c_readbytes(state,0x21,&buf,1);
  166. if ((buf & 0x80)== 0x00)
  167. return 0;
  168. msleep(100);
  169. count++;
  170. }
  171. printk("nxt2002: timeout error writing tuner\n");
  172. return 0;
  173. }
  174. static void nxt2002_agc_reset(struct nxt2002_state* state)
  175. {
  176. u8 buf;
  177. dprintk("%s\n", __FUNCTION__);
  178. buf = 0x08;
  179. i2c_writebytes(state,0x08,&buf,1);
  180. buf = 0x00;
  181. i2c_writebytes(state,0x08,&buf,1);
  182. return;
  183. }
  184. static int nxt2002_load_firmware (struct dvb_frontend* fe, const struct firmware *fw)
  185. {
  186. struct nxt2002_state* state = fe->demodulator_priv;
  187. u8 buf[256],written = 0,chunkpos = 0;
  188. u16 rambase,position,crc = 0;
  189. dprintk("%s\n", __FUNCTION__);
  190. dprintk("Firmware is %zu bytes\n",fw->size);
  191. /* Get the RAM base for this nxt2002 */
  192. i2c_readbytes(state,0x10,buf,1);
  193. if (buf[0] & 0x10)
  194. rambase = 0x1000;
  195. else
  196. rambase = 0x0000;
  197. dprintk("rambase on this nxt2002 is %04X\n",rambase);
  198. /* Hold the micro in reset while loading firmware */
  199. buf[0] = 0x80;
  200. i2c_writebytes(state,0x2B,buf,1);
  201. for (position = 0; position < fw->size ; position++) {
  202. if (written == 0) {
  203. crc = 0;
  204. chunkpos = 0x28;
  205. buf[0] = ((rambase + position) >> 8);
  206. buf[1] = (rambase + position) & 0xFF;
  207. buf[2] = 0x81;
  208. /* write starting address */
  209. i2c_writebytes(state,0x29,buf,3);
  210. }
  211. written++;
  212. chunkpos++;
  213. if ((written % 4) == 0)
  214. i2c_writebytes(state,chunkpos,&fw->data[position-3],4);
  215. crc = nxt2002_crc(crc,fw->data[position]);
  216. if ((written == 255) || (position+1 == fw->size)) {
  217. /* write remaining bytes of firmware */
  218. i2c_writebytes(state, chunkpos+4-(written %4),
  219. &fw->data[position-(written %4) + 1],
  220. written %4);
  221. buf[0] = crc << 8;
  222. buf[1] = crc & 0xFF;
  223. /* write crc */
  224. i2c_writebytes(state,0x2C,buf,2);
  225. /* do a read to stop things */
  226. i2c_readbytes(state,0x2A,buf,1);
  227. /* set transfer mode to complete */
  228. buf[0] = 0x80;
  229. i2c_writebytes(state,0x2B,buf,1);
  230. written = 0;
  231. }
  232. }
  233. printk ("done.\n");
  234. return 0;
  235. };
  236. static int nxt2002_setup_frontend_parameters (struct dvb_frontend* fe,
  237. struct dvb_frontend_parameters *p)
  238. {
  239. struct nxt2002_state* state = fe->demodulator_priv;
  240. u32 freq = 0;
  241. u16 tunerfreq = 0;
  242. u8 buf[4];
  243. freq = 44000 + ( p->frequency / 1000 );
  244. dprintk("freq = %d p->frequency = %d\n",freq,p->frequency);
  245. tunerfreq = freq * 24/4000;
  246. buf[0] = (tunerfreq >> 8) & 0x7F;
  247. buf[1] = (tunerfreq & 0xFF);
  248. if (p->frequency <= 214000000) {
  249. buf[2] = 0x84 + (0x06 << 3);
  250. buf[3] = (p->frequency <= 172000000) ? 0x01 : 0x02;
  251. } else if (p->frequency <= 721000000) {
  252. buf[2] = 0x84 + (0x07 << 3);
  253. buf[3] = (p->frequency <= 467000000) ? 0x02 : 0x08;
  254. } else if (p->frequency <= 841000000) {
  255. buf[2] = 0x84 + (0x0E << 3);
  256. buf[3] = 0x08;
  257. } else {
  258. buf[2] = 0x84 + (0x0F << 3);
  259. buf[3] = 0x02;
  260. }
  261. /* write frequency information */
  262. nxt2002_writetuner(state,buf);
  263. /* reset the agc now that tuning has been completed */
  264. nxt2002_agc_reset(state);
  265. /* set target power level */
  266. switch (p->u.vsb.modulation) {
  267. case QAM_64:
  268. case QAM_256:
  269. buf[0] = 0x74;
  270. break;
  271. case VSB_8:
  272. buf[0] = 0x70;
  273. break;
  274. default:
  275. return -EINVAL;
  276. break;
  277. }
  278. i2c_writebytes(state,0x42,buf,1);
  279. /* configure sdm */
  280. buf[0] = 0x87;
  281. i2c_writebytes(state,0x57,buf,1);
  282. /* write sdm1 input */
  283. buf[0] = 0x10;
  284. buf[1] = 0x00;
  285. nxt2002_writereg_multibyte(state,0x58,buf,2);
  286. /* write sdmx input */
  287. switch (p->u.vsb.modulation) {
  288. case QAM_64:
  289. buf[0] = 0x68;
  290. break;
  291. case QAM_256:
  292. buf[0] = 0x64;
  293. break;
  294. case VSB_8:
  295. buf[0] = 0x60;
  296. break;
  297. default:
  298. return -EINVAL;
  299. break;
  300. }
  301. buf[1] = 0x00;
  302. nxt2002_writereg_multibyte(state,0x5C,buf,2);
  303. /* write adc power lpf fc */
  304. buf[0] = 0x05;
  305. i2c_writebytes(state,0x43,buf,1);
  306. /* write adc power lpf fc */
  307. buf[0] = 0x05;
  308. i2c_writebytes(state,0x43,buf,1);
  309. /* write accumulator2 input */
  310. buf[0] = 0x80;
  311. buf[1] = 0x00;
  312. nxt2002_writereg_multibyte(state,0x4B,buf,2);
  313. /* write kg1 */
  314. buf[0] = 0x00;
  315. i2c_writebytes(state,0x4D,buf,1);
  316. /* write sdm12 lpf fc */
  317. buf[0] = 0x44;
  318. i2c_writebytes(state,0x55,buf,1);
  319. /* write agc control reg */
  320. buf[0] = 0x04;
  321. i2c_writebytes(state,0x41,buf,1);
  322. /* write agc ucgp0 */
  323. switch (p->u.vsb.modulation) {
  324. case QAM_64:
  325. buf[0] = 0x02;
  326. break;
  327. case QAM_256:
  328. buf[0] = 0x03;
  329. break;
  330. case VSB_8:
  331. buf[0] = 0x00;
  332. break;
  333. default:
  334. return -EINVAL;
  335. break;
  336. }
  337. i2c_writebytes(state,0x30,buf,1);
  338. /* write agc control reg */
  339. buf[0] = 0x00;
  340. i2c_writebytes(state,0x41,buf,1);
  341. /* write accumulator2 input */
  342. buf[0] = 0x80;
  343. buf[1] = 0x00;
  344. nxt2002_writereg_multibyte(state,0x49,buf,2);
  345. nxt2002_writereg_multibyte(state,0x4B,buf,2);
  346. /* write agc control reg */
  347. buf[0] = 0x04;
  348. i2c_writebytes(state,0x41,buf,1);
  349. nxt2002_microcontroller_start(state);
  350. /* adjacent channel detection should be done here, but I don't
  351. have any stations with this need so I cannot test it */
  352. return 0;
  353. }
  354. static int nxt2002_read_status(struct dvb_frontend* fe, fe_status_t* status)
  355. {
  356. struct nxt2002_state* state = fe->demodulator_priv;
  357. u8 lock;
  358. i2c_readbytes(state,0x31,&lock,1);
  359. *status = 0;
  360. if (lock & 0x20) {
  361. *status |= FE_HAS_SIGNAL;
  362. *status |= FE_HAS_CARRIER;
  363. *status |= FE_HAS_VITERBI;
  364. *status |= FE_HAS_SYNC;
  365. *status |= FE_HAS_LOCK;
  366. }
  367. return 0;
  368. }
  369. static int nxt2002_read_ber(struct dvb_frontend* fe, u32* ber)
  370. {
  371. struct nxt2002_state* state = fe->demodulator_priv;
  372. u8 b[3];
  373. nxt2002_readreg_multibyte(state,0xE6,b,3);
  374. *ber = ((b[0] << 8) + b[1]) * 8;
  375. return 0;
  376. }
  377. static int nxt2002_read_signal_strength(struct dvb_frontend* fe, u16* strength)
  378. {
  379. struct nxt2002_state* state = fe->demodulator_priv;
  380. u8 b[2];
  381. u16 temp = 0;
  382. /* setup to read cluster variance */
  383. b[0] = 0x00;
  384. i2c_writebytes(state,0xA1,b,1);
  385. /* get multreg val */
  386. nxt2002_readreg_multibyte(state,0xA6,b,2);
  387. temp = (b[0] << 8) | b[1];
  388. *strength = ((0x7FFF - temp) & 0x0FFF) * 16;
  389. return 0;
  390. }
  391. static int nxt2002_read_snr(struct dvb_frontend* fe, u16* snr)
  392. {
  393. struct nxt2002_state* state = fe->demodulator_priv;
  394. u8 b[2];
  395. u16 temp = 0, temp2;
  396. u32 snrdb = 0;
  397. /* setup to read cluster variance */
  398. b[0] = 0x00;
  399. i2c_writebytes(state,0xA1,b,1);
  400. /* get multreg val from 0xA6 */
  401. nxt2002_readreg_multibyte(state,0xA6,b,2);
  402. temp = (b[0] << 8) | b[1];
  403. temp2 = 0x7FFF - temp;
  404. /* snr will be in db */
  405. if (temp2 > 0x7F00)
  406. snrdb = 1000*24 + ( 1000*(30-24) * ( temp2 - 0x7F00 ) / ( 0x7FFF - 0x7F00 ) );
  407. else if (temp2 > 0x7EC0)
  408. snrdb = 1000*18 + ( 1000*(24-18) * ( temp2 - 0x7EC0 ) / ( 0x7F00 - 0x7EC0 ) );
  409. else if (temp2 > 0x7C00)
  410. snrdb = 1000*12 + ( 1000*(18-12) * ( temp2 - 0x7C00 ) / ( 0x7EC0 - 0x7C00 ) );
  411. else
  412. snrdb = 1000*0 + ( 1000*(12-0) * ( temp2 - 0 ) / ( 0x7C00 - 0 ) );
  413. /* the value reported back from the frontend will be FFFF=32db 0000=0db */
  414. *snr = snrdb * (0xFFFF/32000);
  415. return 0;
  416. }
  417. static int nxt2002_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
  418. {
  419. struct nxt2002_state* state = fe->demodulator_priv;
  420. u8 b[3];
  421. nxt2002_readreg_multibyte(state,0xE6,b,3);
  422. *ucblocks = b[2];
  423. return 0;
  424. }
  425. static int nxt2002_sleep(struct dvb_frontend* fe)
  426. {
  427. return 0;
  428. }
  429. static int nxt2002_init(struct dvb_frontend* fe)
  430. {
  431. struct nxt2002_state* state = fe->demodulator_priv;
  432. const struct firmware *fw;
  433. int ret;
  434. u8 buf[2];
  435. if (!state->initialised) {
  436. /* request the firmware, this will block until someone uploads it */
  437. printk("nxt2002: Waiting for firmware upload (%s)...\n", NXT2002_DEFAULT_FIRMWARE);
  438. ret = state->config->request_firmware(fe, &fw, NXT2002_DEFAULT_FIRMWARE);
  439. printk("nxt2002: Waiting for firmware upload(2)...\n");
  440. if (ret) {
  441. printk("nxt2002: no firmware upload (timeout or file not found?)\n");
  442. return ret;
  443. }
  444. ret = nxt2002_load_firmware(fe, fw);
  445. if (ret) {
  446. printk("nxt2002: writing firmware to device failed\n");
  447. release_firmware(fw);
  448. return ret;
  449. }
  450. printk("nxt2002: firmware upload complete\n");
  451. /* Put the micro into reset */
  452. nxt2002_microcontroller_stop(state);
  453. /* ensure transfer is complete */
  454. buf[0]=0;
  455. i2c_writebytes(state,0x2B,buf,1);
  456. /* Put the micro into reset for real this time */
  457. nxt2002_microcontroller_stop(state);
  458. /* soft reset everything (agc,frontend,eq,fec)*/
  459. buf[0] = 0x0F;
  460. i2c_writebytes(state,0x08,buf,1);
  461. buf[0] = 0x00;
  462. i2c_writebytes(state,0x08,buf,1);
  463. /* write agc sdm configure */
  464. buf[0] = 0xF1;
  465. i2c_writebytes(state,0x57,buf,1);
  466. /* write mod output format */
  467. buf[0] = 0x20;
  468. i2c_writebytes(state,0x09,buf,1);
  469. /* write fec mpeg mode */
  470. buf[0] = 0x7E;
  471. buf[1] = 0x00;
  472. i2c_writebytes(state,0xE9,buf,2);
  473. /* write mux selection */
  474. buf[0] = 0x00;
  475. i2c_writebytes(state,0xCC,buf,1);
  476. state->initialised = 1;
  477. }
  478. return 0;
  479. }
  480. static int nxt2002_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
  481. {
  482. fesettings->min_delay_ms = 500;
  483. fesettings->step_size = 0;
  484. fesettings->max_drift = 0;
  485. return 0;
  486. }
  487. static void nxt2002_release(struct dvb_frontend* fe)
  488. {
  489. struct nxt2002_state* state = fe->demodulator_priv;
  490. kfree(state);
  491. }
  492. static struct dvb_frontend_ops nxt2002_ops;
  493. struct dvb_frontend* nxt2002_attach(const struct nxt2002_config* config,
  494. struct i2c_adapter* i2c)
  495. {
  496. struct nxt2002_state* state = NULL;
  497. u8 buf [] = {0,0,0,0,0};
  498. /* allocate memory for the internal state */
  499. state = kmalloc(sizeof(struct nxt2002_state), GFP_KERNEL);
  500. if (state == NULL) goto error;
  501. /* setup the state */
  502. state->config = config;
  503. state->i2c = i2c;
  504. memcpy(&state->ops, &nxt2002_ops, sizeof(struct dvb_frontend_ops));
  505. state->initialised = 0;
  506. /* Check the first 5 registers to ensure this a revision we can handle */
  507. i2c_readbytes(state, 0x00, buf, 5);
  508. if (buf[0] != 0x04) goto error; /* device id */
  509. if (buf[1] != 0x02) goto error; /* fab id */
  510. if (buf[2] != 0x11) goto error; /* month */
  511. if (buf[3] != 0x20) goto error; /* year msb */
  512. if (buf[4] != 0x00) goto error; /* year lsb */
  513. /* create dvb_frontend */
  514. state->frontend.ops = &state->ops;
  515. state->frontend.demodulator_priv = state;
  516. return &state->frontend;
  517. error:
  518. kfree(state);
  519. return NULL;
  520. }
  521. static struct dvb_frontend_ops nxt2002_ops = {
  522. .info = {
  523. .name = "Nextwave nxt2002 VSB/QAM frontend",
  524. .type = FE_ATSC,
  525. .frequency_min = 54000000,
  526. .frequency_max = 860000000,
  527. /* stepsize is just a guess */
  528. .frequency_stepsize = 166666,
  529. .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  530. FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  531. FE_CAN_8VSB | FE_CAN_QAM_64 | FE_CAN_QAM_256
  532. },
  533. .release = nxt2002_release,
  534. .init = nxt2002_init,
  535. .sleep = nxt2002_sleep,
  536. .set_frontend = nxt2002_setup_frontend_parameters,
  537. .get_tune_settings = nxt2002_get_tune_settings,
  538. .read_status = nxt2002_read_status,
  539. .read_ber = nxt2002_read_ber,
  540. .read_signal_strength = nxt2002_read_signal_strength,
  541. .read_snr = nxt2002_read_snr,
  542. .read_ucblocks = nxt2002_read_ucblocks,
  543. };
  544. module_param(debug, int, 0644);
  545. MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
  546. MODULE_DESCRIPTION("NXT2002 ATSC (8VSB & ITU J83 AnnexB FEC QAM64/256) demodulator driver");
  547. MODULE_AUTHOR("Taylor Jacob");
  548. MODULE_LICENSE("GPL");
  549. EXPORT_SYMBOL(nxt2002_attach);