i2c-pnx.c 19 KB

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  1. /*
  2. * Provides I2C support for Philips PNX010x/PNX4008 boards.
  3. *
  4. * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
  5. * Vitaly Wool <vwool@ru.mvista.com>
  6. *
  7. * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
  8. * the terms of the GNU General Public License version 2. This program
  9. * is licensed "as is" without any warranty of any kind, whether express
  10. * or implied.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/ioport.h>
  15. #include <linux/delay.h>
  16. #include <linux/i2c.h>
  17. #include <linux/timer.h>
  18. #include <linux/completion.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/i2c-pnx.h>
  21. #include <linux/io.h>
  22. #include <linux/err.h>
  23. #include <linux/clk.h>
  24. #include <mach/hardware.h>
  25. #include <mach/i2c.h>
  26. #include <asm/irq.h>
  27. #include <asm/uaccess.h>
  28. #define I2C_PNX_TIMEOUT 10 /* msec */
  29. #define I2C_PNX_SPEED_KHZ 100
  30. #define I2C_PNX_REGION_SIZE 0x100
  31. static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data)
  32. {
  33. while (timeout > 0 &&
  34. (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
  35. mdelay(1);
  36. timeout--;
  37. }
  38. return (timeout <= 0);
  39. }
  40. static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data)
  41. {
  42. while (timeout > 0 &&
  43. (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
  44. mdelay(1);
  45. timeout--;
  46. }
  47. return (timeout <= 0);
  48. }
  49. static inline void i2c_pnx_arm_timer(struct i2c_adapter *adap)
  50. {
  51. struct i2c_pnx_algo_data *data = adap->algo_data;
  52. struct timer_list *timer = &data->mif.timer;
  53. int expires = I2C_PNX_TIMEOUT / (1000 / HZ);
  54. if (expires <= 1)
  55. expires = 2;
  56. del_timer_sync(timer);
  57. dev_dbg(&adap->dev, "Timer armed at %lu plus %u jiffies.\n",
  58. jiffies, expires);
  59. timer->expires = jiffies + expires;
  60. timer->data = (unsigned long)adap;
  61. add_timer(timer);
  62. }
  63. /**
  64. * i2c_pnx_start - start a device
  65. * @slave_addr: slave address
  66. * @adap: pointer to adapter structure
  67. *
  68. * Generate a START signal in the desired mode.
  69. */
  70. static int i2c_pnx_start(unsigned char slave_addr, struct i2c_adapter *adap)
  71. {
  72. struct i2c_pnx_algo_data *alg_data = adap->algo_data;
  73. dev_dbg(&adap->dev, "%s(): addr 0x%x mode %d\n", __func__,
  74. slave_addr, alg_data->mif.mode);
  75. /* Check for 7 bit slave addresses only */
  76. if (slave_addr & ~0x7f) {
  77. dev_err(&adap->dev, "%s: Invalid slave address %x. "
  78. "Only 7-bit addresses are supported\n",
  79. adap->name, slave_addr);
  80. return -EINVAL;
  81. }
  82. /* First, make sure bus is idle */
  83. if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) {
  84. /* Somebody else is monopolizing the bus */
  85. dev_err(&adap->dev, "%s: Bus busy. Slave addr = %02x, "
  86. "cntrl = %x, stat = %x\n",
  87. adap->name, slave_addr,
  88. ioread32(I2C_REG_CTL(alg_data)),
  89. ioread32(I2C_REG_STS(alg_data)));
  90. return -EBUSY;
  91. } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
  92. /* Sorry, we lost the bus */
  93. dev_err(&adap->dev, "%s: Arbitration failure. "
  94. "Slave addr = %02x\n", adap->name, slave_addr);
  95. return -EIO;
  96. }
  97. /*
  98. * OK, I2C is enabled and we have the bus.
  99. * Clear the current TDI and AFI status flags.
  100. */
  101. iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
  102. I2C_REG_STS(alg_data));
  103. dev_dbg(&adap->dev, "%s(): sending %#x\n", __func__,
  104. (slave_addr << 1) | start_bit | alg_data->mif.mode);
  105. /* Write the slave address, START bit and R/W bit */
  106. iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
  107. I2C_REG_TX(alg_data));
  108. dev_dbg(&adap->dev, "%s(): exit\n", __func__);
  109. return 0;
  110. }
  111. /**
  112. * i2c_pnx_stop - stop a device
  113. * @adap: pointer to I2C adapter structure
  114. *
  115. * Generate a STOP signal to terminate the master transaction.
  116. */
  117. static void i2c_pnx_stop(struct i2c_adapter *adap)
  118. {
  119. struct i2c_pnx_algo_data *alg_data = adap->algo_data;
  120. /* Only 1 msec max timeout due to interrupt context */
  121. long timeout = 1000;
  122. dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
  123. __func__, ioread32(I2C_REG_STS(alg_data)));
  124. /* Write a STOP bit to TX FIFO */
  125. iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
  126. /* Wait until the STOP is seen. */
  127. while (timeout > 0 &&
  128. (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
  129. /* may be called from interrupt context */
  130. udelay(1);
  131. timeout--;
  132. }
  133. dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
  134. __func__, ioread32(I2C_REG_STS(alg_data)));
  135. }
  136. /**
  137. * i2c_pnx_master_xmit - transmit data to slave
  138. * @adap: pointer to I2C adapter structure
  139. *
  140. * Sends one byte of data to the slave
  141. */
  142. static int i2c_pnx_master_xmit(struct i2c_adapter *adap)
  143. {
  144. struct i2c_pnx_algo_data *alg_data = adap->algo_data;
  145. u32 val;
  146. dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
  147. __func__, ioread32(I2C_REG_STS(alg_data)));
  148. if (alg_data->mif.len > 0) {
  149. /* We still have something to talk about... */
  150. val = *alg_data->mif.buf++;
  151. if (alg_data->mif.len == 1) {
  152. val |= stop_bit;
  153. if (!alg_data->last)
  154. val |= start_bit;
  155. }
  156. alg_data->mif.len--;
  157. iowrite32(val, I2C_REG_TX(alg_data));
  158. dev_dbg(&adap->dev, "%s(): xmit %#x [%d]\n", __func__,
  159. val, alg_data->mif.len + 1);
  160. if (alg_data->mif.len == 0) {
  161. if (alg_data->last) {
  162. /* Wait until the STOP is seen. */
  163. if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
  164. dev_err(&adap->dev, "The bus is still "
  165. "active after timeout\n");
  166. }
  167. /* Disable master interrupts */
  168. iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
  169. ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
  170. I2C_REG_CTL(alg_data));
  171. del_timer_sync(&alg_data->mif.timer);
  172. dev_dbg(&adap->dev, "%s(): Waking up xfer routine.\n",
  173. __func__);
  174. complete(&alg_data->mif.complete);
  175. }
  176. } else if (alg_data->mif.len == 0) {
  177. /* zero-sized transfer */
  178. i2c_pnx_stop(adap);
  179. /* Disable master interrupts. */
  180. iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
  181. ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
  182. I2C_REG_CTL(alg_data));
  183. /* Stop timer. */
  184. del_timer_sync(&alg_data->mif.timer);
  185. dev_dbg(&adap->dev, "%s(): Waking up xfer routine after "
  186. "zero-xfer.\n", __func__);
  187. complete(&alg_data->mif.complete);
  188. }
  189. dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
  190. __func__, ioread32(I2C_REG_STS(alg_data)));
  191. return 0;
  192. }
  193. /**
  194. * i2c_pnx_master_rcv - receive data from slave
  195. * @adap: pointer to I2C adapter structure
  196. *
  197. * Reads one byte data from the slave
  198. */
  199. static int i2c_pnx_master_rcv(struct i2c_adapter *adap)
  200. {
  201. struct i2c_pnx_algo_data *alg_data = adap->algo_data;
  202. unsigned int val = 0;
  203. u32 ctl = 0;
  204. dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n",
  205. __func__, ioread32(I2C_REG_STS(alg_data)));
  206. /* Check, whether there is already data,
  207. * or we didn't 'ask' for it yet.
  208. */
  209. if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
  210. dev_dbg(&adap->dev, "%s(): Write dummy data to fill "
  211. "Rx-fifo...\n", __func__);
  212. if (alg_data->mif.len == 1) {
  213. /* Last byte, do not acknowledge next rcv. */
  214. val |= stop_bit;
  215. if (!alg_data->last)
  216. val |= start_bit;
  217. /*
  218. * Enable interrupt RFDAIE (data in Rx fifo),
  219. * and disable DRMIE (need data for Tx)
  220. */
  221. ctl = ioread32(I2C_REG_CTL(alg_data));
  222. ctl |= mcntrl_rffie | mcntrl_daie;
  223. ctl &= ~mcntrl_drmie;
  224. iowrite32(ctl, I2C_REG_CTL(alg_data));
  225. }
  226. /*
  227. * Now we'll 'ask' for data:
  228. * For each byte we want to receive, we must
  229. * write a (dummy) byte to the Tx-FIFO.
  230. */
  231. iowrite32(val, I2C_REG_TX(alg_data));
  232. return 0;
  233. }
  234. /* Handle data. */
  235. if (alg_data->mif.len > 0) {
  236. val = ioread32(I2C_REG_RX(alg_data));
  237. *alg_data->mif.buf++ = (u8) (val & 0xff);
  238. dev_dbg(&adap->dev, "%s(): rcv 0x%x [%d]\n", __func__, val,
  239. alg_data->mif.len);
  240. alg_data->mif.len--;
  241. if (alg_data->mif.len == 0) {
  242. if (alg_data->last)
  243. /* Wait until the STOP is seen. */
  244. if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
  245. dev_err(&adap->dev, "The bus is still "
  246. "active after timeout\n");
  247. /* Disable master interrupts */
  248. ctl = ioread32(I2C_REG_CTL(alg_data));
  249. ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
  250. mcntrl_drmie | mcntrl_daie);
  251. iowrite32(ctl, I2C_REG_CTL(alg_data));
  252. /* Kill timer. */
  253. del_timer_sync(&alg_data->mif.timer);
  254. complete(&alg_data->mif.complete);
  255. }
  256. }
  257. dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n",
  258. __func__, ioread32(I2C_REG_STS(alg_data)));
  259. return 0;
  260. }
  261. static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
  262. {
  263. u32 stat, ctl;
  264. struct i2c_adapter *adap = dev_id;
  265. struct i2c_pnx_algo_data *alg_data = adap->algo_data;
  266. dev_dbg(&adap->dev, "%s(): mstat = %x mctrl = %x, mode = %d\n",
  267. __func__,
  268. ioread32(I2C_REG_STS(alg_data)),
  269. ioread32(I2C_REG_CTL(alg_data)),
  270. alg_data->mif.mode);
  271. stat = ioread32(I2C_REG_STS(alg_data));
  272. /* let's see what kind of event this is */
  273. if (stat & mstatus_afi) {
  274. /* We lost arbitration in the midst of a transfer */
  275. alg_data->mif.ret = -EIO;
  276. /* Disable master interrupts. */
  277. ctl = ioread32(I2C_REG_CTL(alg_data));
  278. ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
  279. mcntrl_drmie);
  280. iowrite32(ctl, I2C_REG_CTL(alg_data));
  281. /* Stop timer, to prevent timeout. */
  282. del_timer_sync(&alg_data->mif.timer);
  283. complete(&alg_data->mif.complete);
  284. } else if (stat & mstatus_nai) {
  285. /* Slave did not acknowledge, generate a STOP */
  286. dev_dbg(&adap->dev, "%s(): "
  287. "Slave did not acknowledge, generating a STOP.\n",
  288. __func__);
  289. i2c_pnx_stop(adap);
  290. /* Disable master interrupts. */
  291. ctl = ioread32(I2C_REG_CTL(alg_data));
  292. ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
  293. mcntrl_drmie);
  294. iowrite32(ctl, I2C_REG_CTL(alg_data));
  295. /* Our return value. */
  296. alg_data->mif.ret = -EIO;
  297. /* Stop timer, to prevent timeout. */
  298. del_timer_sync(&alg_data->mif.timer);
  299. complete(&alg_data->mif.complete);
  300. } else {
  301. /*
  302. * Two options:
  303. * - Master Tx needs data.
  304. * - There is data in the Rx-fifo
  305. * The latter is only the case if we have requested for data,
  306. * via a dummy write. (See 'i2c_pnx_master_rcv'.)
  307. * We therefore check, as a sanity check, whether that interrupt
  308. * has been enabled.
  309. */
  310. if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
  311. if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
  312. i2c_pnx_master_xmit(adap);
  313. } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
  314. i2c_pnx_master_rcv(adap);
  315. }
  316. }
  317. }
  318. /* Clear TDI and AFI bits */
  319. stat = ioread32(I2C_REG_STS(alg_data));
  320. iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
  321. dev_dbg(&adap->dev, "%s(): exiting, stat = %x ctrl = %x.\n",
  322. __func__, ioread32(I2C_REG_STS(alg_data)),
  323. ioread32(I2C_REG_CTL(alg_data)));
  324. return IRQ_HANDLED;
  325. }
  326. static void i2c_pnx_timeout(unsigned long data)
  327. {
  328. struct i2c_adapter *adap = (struct i2c_adapter *)data;
  329. struct i2c_pnx_algo_data *alg_data = adap->algo_data;
  330. u32 ctl;
  331. dev_err(&adap->dev, "Master timed out. stat = %04x, cntrl = %04x. "
  332. "Resetting master...\n",
  333. ioread32(I2C_REG_STS(alg_data)),
  334. ioread32(I2C_REG_CTL(alg_data)));
  335. /* Reset master and disable interrupts */
  336. ctl = ioread32(I2C_REG_CTL(alg_data));
  337. ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
  338. iowrite32(ctl, I2C_REG_CTL(alg_data));
  339. ctl |= mcntrl_reset;
  340. iowrite32(ctl, I2C_REG_CTL(alg_data));
  341. wait_reset(I2C_PNX_TIMEOUT, alg_data);
  342. alg_data->mif.ret = -EIO;
  343. complete(&alg_data->mif.complete);
  344. }
  345. static inline void bus_reset_if_active(struct i2c_adapter *adap)
  346. {
  347. struct i2c_pnx_algo_data *alg_data = adap->algo_data;
  348. u32 stat;
  349. if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
  350. dev_err(&adap->dev,
  351. "%s: Bus is still active after xfer. Reset it...\n",
  352. adap->name);
  353. iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
  354. I2C_REG_CTL(alg_data));
  355. wait_reset(I2C_PNX_TIMEOUT, alg_data);
  356. } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
  357. /* If there is data in the fifo's after transfer,
  358. * flush fifo's by reset.
  359. */
  360. iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
  361. I2C_REG_CTL(alg_data));
  362. wait_reset(I2C_PNX_TIMEOUT, alg_data);
  363. } else if (stat & mstatus_nai) {
  364. iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
  365. I2C_REG_CTL(alg_data));
  366. wait_reset(I2C_PNX_TIMEOUT, alg_data);
  367. }
  368. }
  369. /**
  370. * i2c_pnx_xfer - generic transfer entry point
  371. * @adap: pointer to I2C adapter structure
  372. * @msgs: array of messages
  373. * @num: number of messages
  374. *
  375. * Initiates the transfer
  376. */
  377. static int
  378. i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  379. {
  380. struct i2c_msg *pmsg;
  381. int rc = 0, completed = 0, i;
  382. struct i2c_pnx_algo_data *alg_data = adap->algo_data;
  383. u32 stat = ioread32(I2C_REG_STS(alg_data));
  384. dev_dbg(&adap->dev, "%s(): entering: %d messages, stat = %04x.\n",
  385. __func__, num, ioread32(I2C_REG_STS(alg_data)));
  386. bus_reset_if_active(adap);
  387. /* Process transactions in a loop. */
  388. for (i = 0; rc >= 0 && i < num; i++) {
  389. u8 addr;
  390. pmsg = &msgs[i];
  391. addr = pmsg->addr;
  392. if (pmsg->flags & I2C_M_TEN) {
  393. dev_err(&adap->dev,
  394. "%s: 10 bits addr not supported!\n",
  395. adap->name);
  396. rc = -EINVAL;
  397. break;
  398. }
  399. alg_data->mif.buf = pmsg->buf;
  400. alg_data->mif.len = pmsg->len;
  401. alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
  402. I2C_SMBUS_READ : I2C_SMBUS_WRITE;
  403. alg_data->mif.ret = 0;
  404. alg_data->last = (i == num - 1);
  405. dev_dbg(&adap->dev, "%s(): mode %d, %d bytes\n", __func__,
  406. alg_data->mif.mode,
  407. alg_data->mif.len);
  408. i2c_pnx_arm_timer(adap);
  409. /* initialize the completion var */
  410. init_completion(&alg_data->mif.complete);
  411. /* Enable master interrupt */
  412. iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
  413. mcntrl_naie | mcntrl_drmie,
  414. I2C_REG_CTL(alg_data));
  415. /* Put start-code and slave-address on the bus. */
  416. rc = i2c_pnx_start(addr, adap);
  417. if (rc < 0)
  418. break;
  419. /* Wait for completion */
  420. wait_for_completion(&alg_data->mif.complete);
  421. if (!(rc = alg_data->mif.ret))
  422. completed++;
  423. dev_dbg(&adap->dev, "%s(): Complete, return code = %d.\n",
  424. __func__, rc);
  425. /* Clear TDI and AFI bits in case they are set. */
  426. if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
  427. dev_dbg(&adap->dev,
  428. "%s: TDI still set... clearing now.\n",
  429. adap->name);
  430. iowrite32(stat, I2C_REG_STS(alg_data));
  431. }
  432. if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
  433. dev_dbg(&adap->dev,
  434. "%s: AFI still set... clearing now.\n",
  435. adap->name);
  436. iowrite32(stat, I2C_REG_STS(alg_data));
  437. }
  438. }
  439. bus_reset_if_active(adap);
  440. /* Cleanup to be sure... */
  441. alg_data->mif.buf = NULL;
  442. alg_data->mif.len = 0;
  443. dev_dbg(&adap->dev, "%s(): exiting, stat = %x\n",
  444. __func__, ioread32(I2C_REG_STS(alg_data)));
  445. if (completed != num)
  446. return ((rc < 0) ? rc : -EREMOTEIO);
  447. return num;
  448. }
  449. static u32 i2c_pnx_func(struct i2c_adapter *adapter)
  450. {
  451. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  452. }
  453. static struct i2c_algorithm pnx_algorithm = {
  454. .master_xfer = i2c_pnx_xfer,
  455. .functionality = i2c_pnx_func,
  456. };
  457. #ifdef CONFIG_PM
  458. static int i2c_pnx_controller_suspend(struct platform_device *pdev,
  459. pm_message_t state)
  460. {
  461. struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
  462. /* FIXME: shouldn't this be clk_disable? */
  463. clk_enable(alg_data->clk);
  464. return 0;
  465. }
  466. static int i2c_pnx_controller_resume(struct platform_device *pdev)
  467. {
  468. struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
  469. return clk_enable(alg_data->clk);
  470. }
  471. #else
  472. #define i2c_pnx_controller_suspend NULL
  473. #define i2c_pnx_controller_resume NULL
  474. #endif
  475. static int __devinit i2c_pnx_probe(struct platform_device *pdev)
  476. {
  477. unsigned long tmp;
  478. int ret = 0;
  479. struct i2c_pnx_algo_data *alg_data;
  480. unsigned long freq;
  481. struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data;
  482. if (!i2c_pnx || !i2c_pnx->name) {
  483. dev_err(&pdev->dev, "%s: no platform data supplied\n",
  484. __func__);
  485. ret = -EINVAL;
  486. goto out;
  487. }
  488. alg_data = kzalloc(sizeof(*alg_data), GFP_KERNEL);
  489. if (!alg_data) {
  490. ret = -ENOMEM;
  491. goto err_kzalloc;
  492. }
  493. platform_set_drvdata(pdev, alg_data);
  494. strlcpy(alg_data->adapter.name, i2c_pnx->name,
  495. sizeof(alg_data->adapter.name));
  496. alg_data->adapter.dev.parent = &pdev->dev;
  497. alg_data->adapter.algo = &pnx_algorithm;
  498. alg_data->adapter.algo_data = alg_data;
  499. alg_data->adapter.nr = pdev->id;
  500. alg_data->i2c_pnx = i2c_pnx;
  501. alg_data->clk = clk_get(&pdev->dev, NULL);
  502. if (IS_ERR(alg_data->clk)) {
  503. ret = PTR_ERR(alg_data->clk);
  504. goto out_drvdata;
  505. }
  506. init_timer(&alg_data->mif.timer);
  507. alg_data->mif.timer.function = i2c_pnx_timeout;
  508. alg_data->mif.timer.data = (unsigned long)&alg_data->adapter;
  509. /* Register I/O resource */
  510. if (!request_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE,
  511. pdev->name)) {
  512. dev_err(&pdev->dev,
  513. "I/O region 0x%08x for I2C already in use.\n",
  514. i2c_pnx->base);
  515. ret = -ENODEV;
  516. goto out_clkget;
  517. }
  518. alg_data->ioaddr = ioremap(i2c_pnx->base, I2C_PNX_REGION_SIZE);
  519. if (!alg_data->ioaddr) {
  520. dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n");
  521. ret = -ENOMEM;
  522. goto out_release;
  523. }
  524. ret = clk_enable(alg_data->clk);
  525. if (ret)
  526. goto out_unmap;
  527. freq = clk_get_rate(alg_data->clk);
  528. /*
  529. * Clock Divisor High This value is the number of system clocks
  530. * the serial clock (SCL) will be high.
  531. * For example, if the system clock period is 50 ns and the maximum
  532. * desired serial period is 10000 ns (100 kHz), then CLKHI would be
  533. * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
  534. * programmed into CLKHI will vary from this slightly due to
  535. * variations in the output pad's rise and fall times as well as
  536. * the deglitching filter length.
  537. */
  538. tmp = ((freq / 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2;
  539. iowrite32(tmp, I2C_REG_CKH(alg_data));
  540. iowrite32(tmp, I2C_REG_CKL(alg_data));
  541. iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
  542. if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) {
  543. ret = -ENODEV;
  544. goto out_clock;
  545. }
  546. init_completion(&alg_data->mif.complete);
  547. ret = request_irq(i2c_pnx->irq, i2c_pnx_interrupt,
  548. 0, pdev->name, &alg_data->adapter);
  549. if (ret)
  550. goto out_clock;
  551. /* Register this adapter with the I2C subsystem */
  552. ret = i2c_add_numbered_adapter(&alg_data->adapter);
  553. if (ret < 0) {
  554. dev_err(&pdev->dev, "I2C: Failed to add bus\n");
  555. goto out_irq;
  556. }
  557. dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
  558. alg_data->adapter.name, i2c_pnx->base, i2c_pnx->irq);
  559. return 0;
  560. out_irq:
  561. free_irq(i2c_pnx->irq, &alg_data->adapter);
  562. out_clock:
  563. clk_disable(alg_data->clk);
  564. out_unmap:
  565. iounmap(alg_data->ioaddr);
  566. out_release:
  567. release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
  568. out_clkget:
  569. clk_put(alg_data->clk);
  570. out_drvdata:
  571. kfree(alg_data);
  572. err_kzalloc:
  573. platform_set_drvdata(pdev, NULL);
  574. out:
  575. return ret;
  576. }
  577. static int __devexit i2c_pnx_remove(struct platform_device *pdev)
  578. {
  579. struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
  580. struct i2c_pnx_data *i2c_pnx = alg_data->i2c_pnx;
  581. free_irq(i2c_pnx->irq, &alg_data->adapter);
  582. i2c_del_adapter(&alg_data->adapter);
  583. clk_disable(alg_data->clk);
  584. iounmap(alg_data->ioaddr);
  585. release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
  586. clk_put(alg_data->clk);
  587. kfree(alg_data);
  588. platform_set_drvdata(pdev, NULL);
  589. return 0;
  590. }
  591. static struct platform_driver i2c_pnx_driver = {
  592. .driver = {
  593. .name = "pnx-i2c",
  594. .owner = THIS_MODULE,
  595. },
  596. .probe = i2c_pnx_probe,
  597. .remove = __devexit_p(i2c_pnx_remove),
  598. .suspend = i2c_pnx_controller_suspend,
  599. .resume = i2c_pnx_controller_resume,
  600. };
  601. static int __init i2c_adap_pnx_init(void)
  602. {
  603. return platform_driver_register(&i2c_pnx_driver);
  604. }
  605. static void __exit i2c_adap_pnx_exit(void)
  606. {
  607. platform_driver_unregister(&i2c_pnx_driver);
  608. }
  609. MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
  610. MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
  611. MODULE_LICENSE("GPL");
  612. MODULE_ALIAS("platform:pnx-i2c");
  613. /* We need to make sure I2C is initialized before USB */
  614. subsys_initcall(i2c_adap_pnx_init);
  615. module_exit(i2c_adap_pnx_exit);