arizona-core.c 17 KB

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  1. /*
  2. * Arizona core driver
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/mfd/core.h>
  17. #include <linux/module.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/regmap.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/slab.h>
  22. #include <linux/mfd/arizona/core.h>
  23. #include <linux/mfd/arizona/registers.h>
  24. #include "arizona.h"
  25. static const char *wm5102_core_supplies[] = {
  26. "AVDD",
  27. "DBVDD1",
  28. };
  29. int arizona_clk32k_enable(struct arizona *arizona)
  30. {
  31. int ret = 0;
  32. mutex_lock(&arizona->clk_lock);
  33. arizona->clk32k_ref++;
  34. if (arizona->clk32k_ref == 1) {
  35. switch (arizona->pdata.clk32k_src) {
  36. case ARIZONA_32KZ_MCLK1:
  37. ret = pm_runtime_get_sync(arizona->dev);
  38. if (ret != 0)
  39. goto out;
  40. break;
  41. }
  42. ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  43. ARIZONA_CLK_32K_ENA,
  44. ARIZONA_CLK_32K_ENA);
  45. }
  46. out:
  47. if (ret != 0)
  48. arizona->clk32k_ref--;
  49. mutex_unlock(&arizona->clk_lock);
  50. return ret;
  51. }
  52. EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
  53. int arizona_clk32k_disable(struct arizona *arizona)
  54. {
  55. int ret = 0;
  56. mutex_lock(&arizona->clk_lock);
  57. BUG_ON(arizona->clk32k_ref <= 0);
  58. arizona->clk32k_ref--;
  59. if (arizona->clk32k_ref == 0) {
  60. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  61. ARIZONA_CLK_32K_ENA, 0);
  62. switch (arizona->pdata.clk32k_src) {
  63. case ARIZONA_32KZ_MCLK1:
  64. pm_runtime_put_sync(arizona->dev);
  65. break;
  66. }
  67. }
  68. mutex_unlock(&arizona->clk_lock);
  69. return ret;
  70. }
  71. EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
  72. static irqreturn_t arizona_clkgen_err(int irq, void *data)
  73. {
  74. struct arizona *arizona = data;
  75. dev_err(arizona->dev, "CLKGEN error\n");
  76. return IRQ_HANDLED;
  77. }
  78. static irqreturn_t arizona_underclocked(int irq, void *data)
  79. {
  80. struct arizona *arizona = data;
  81. unsigned int val;
  82. int ret;
  83. ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
  84. &val);
  85. if (ret != 0) {
  86. dev_err(arizona->dev, "Failed to read underclock status: %d\n",
  87. ret);
  88. return IRQ_NONE;
  89. }
  90. if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
  91. dev_err(arizona->dev, "AIF3 underclocked\n");
  92. if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
  93. dev_err(arizona->dev, "AIF2 underclocked\n");
  94. if (val & ARIZONA_AIF1_UNDERCLOCKED_STS)
  95. dev_err(arizona->dev, "AIF1 underclocked\n");
  96. if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
  97. dev_err(arizona->dev, "ISRC2 underclocked\n");
  98. if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
  99. dev_err(arizona->dev, "ISRC1 underclocked\n");
  100. if (val & ARIZONA_FX_UNDERCLOCKED_STS)
  101. dev_err(arizona->dev, "FX underclocked\n");
  102. if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
  103. dev_err(arizona->dev, "ASRC underclocked\n");
  104. if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
  105. dev_err(arizona->dev, "DAC underclocked\n");
  106. if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
  107. dev_err(arizona->dev, "ADC underclocked\n");
  108. if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
  109. dev_err(arizona->dev, "Mixer dropped sample\n");
  110. return IRQ_HANDLED;
  111. }
  112. static irqreturn_t arizona_overclocked(int irq, void *data)
  113. {
  114. struct arizona *arizona = data;
  115. unsigned int val[2];
  116. int ret;
  117. ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
  118. &val[0], 2);
  119. if (ret != 0) {
  120. dev_err(arizona->dev, "Failed to read overclock status: %d\n",
  121. ret);
  122. return IRQ_NONE;
  123. }
  124. if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
  125. dev_err(arizona->dev, "PWM overclocked\n");
  126. if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
  127. dev_err(arizona->dev, "FX core overclocked\n");
  128. if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
  129. dev_err(arizona->dev, "DAC SYS overclocked\n");
  130. if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
  131. dev_err(arizona->dev, "DAC WARP overclocked\n");
  132. if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
  133. dev_err(arizona->dev, "ADC overclocked\n");
  134. if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
  135. dev_err(arizona->dev, "Mixer overclocked\n");
  136. if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
  137. dev_err(arizona->dev, "AIF3 overclocked\n");
  138. if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
  139. dev_err(arizona->dev, "AIF2 overclocked\n");
  140. if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
  141. dev_err(arizona->dev, "AIF1 overclocked\n");
  142. if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
  143. dev_err(arizona->dev, "Pad control overclocked\n");
  144. if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
  145. dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
  146. if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
  147. dev_err(arizona->dev, "Slimbus async overclocked\n");
  148. if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
  149. dev_err(arizona->dev, "Slimbus sync overclocked\n");
  150. if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
  151. dev_err(arizona->dev, "ASRC async system overclocked\n");
  152. if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
  153. dev_err(arizona->dev, "ASRC async WARP overclocked\n");
  154. if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
  155. dev_err(arizona->dev, "ASRC sync system overclocked\n");
  156. if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
  157. dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
  158. if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
  159. dev_err(arizona->dev, "DSP1 overclocked\n");
  160. if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
  161. dev_err(arizona->dev, "ISRC2 overclocked\n");
  162. if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
  163. dev_err(arizona->dev, "ISRC1 overclocked\n");
  164. return IRQ_HANDLED;
  165. }
  166. static int arizona_poll_reg(struct arizona *arizona,
  167. int timeout, unsigned int reg,
  168. unsigned int mask, unsigned int target)
  169. {
  170. unsigned int val = 0;
  171. int ret, i;
  172. for (i = 0; i < timeout; i++) {
  173. ret = regmap_read(arizona->regmap, reg, &val);
  174. if (ret != 0) {
  175. dev_err(arizona->dev, "Failed to read reg %u: %d\n",
  176. reg, ret);
  177. continue;
  178. }
  179. if ((val & mask) == target)
  180. return 0;
  181. msleep(1);
  182. }
  183. dev_err(arizona->dev, "Polling reg %u timed out: %x\n", reg, val);
  184. return -ETIMEDOUT;
  185. }
  186. static int arizona_wait_for_boot(struct arizona *arizona)
  187. {
  188. int ret;
  189. /*
  190. * We can't use an interrupt as we need to runtime resume to do so,
  191. * we won't race with the interrupt handler as it'll be blocked on
  192. * runtime resume.
  193. */
  194. ret = arizona_poll_reg(arizona, 5, ARIZONA_INTERRUPT_RAW_STATUS_5,
  195. ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
  196. if (!ret)
  197. regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
  198. ARIZONA_BOOT_DONE_STS);
  199. pm_runtime_mark_last_busy(arizona->dev);
  200. return ret;
  201. }
  202. #ifdef CONFIG_PM_RUNTIME
  203. static int arizona_runtime_resume(struct device *dev)
  204. {
  205. struct arizona *arizona = dev_get_drvdata(dev);
  206. int ret;
  207. dev_dbg(arizona->dev, "Leaving AoD mode\n");
  208. ret = regulator_enable(arizona->dcvdd);
  209. if (ret != 0) {
  210. dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
  211. return ret;
  212. }
  213. regcache_cache_only(arizona->regmap, false);
  214. ret = arizona_wait_for_boot(arizona);
  215. if (ret != 0) {
  216. goto err;
  217. }
  218. switch (arizona->type) {
  219. case WM5102:
  220. ret = wm5102_patch(arizona);
  221. if (ret != 0) {
  222. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  223. ret);
  224. goto err;
  225. }
  226. }
  227. ret = regcache_sync(arizona->regmap);
  228. if (ret != 0) {
  229. dev_err(arizona->dev, "Failed to restore register cache\n");
  230. goto err;
  231. }
  232. return 0;
  233. err:
  234. regcache_cache_only(arizona->regmap, true);
  235. regulator_disable(arizona->dcvdd);
  236. return ret;
  237. }
  238. static int arizona_runtime_suspend(struct device *dev)
  239. {
  240. struct arizona *arizona = dev_get_drvdata(dev);
  241. dev_dbg(arizona->dev, "Entering AoD mode\n");
  242. regulator_disable(arizona->dcvdd);
  243. regcache_cache_only(arizona->regmap, true);
  244. regcache_mark_dirty(arizona->regmap);
  245. return 0;
  246. }
  247. #endif
  248. #ifdef CONFIG_PM_SLEEP
  249. static int arizona_resume_noirq(struct device *dev)
  250. {
  251. struct arizona *arizona = dev_get_drvdata(dev);
  252. dev_dbg(arizona->dev, "Early resume, disabling IRQ\n");
  253. disable_irq(arizona->irq);
  254. return 0;
  255. }
  256. static int arizona_resume(struct device *dev)
  257. {
  258. struct arizona *arizona = dev_get_drvdata(dev);
  259. dev_dbg(arizona->dev, "Late resume, reenabling IRQ\n");
  260. enable_irq(arizona->irq);
  261. return 0;
  262. }
  263. #endif
  264. const struct dev_pm_ops arizona_pm_ops = {
  265. SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
  266. arizona_runtime_resume,
  267. NULL)
  268. SET_SYSTEM_SLEEP_PM_OPS(NULL, arizona_resume)
  269. #ifdef CONFIG_PM_SLEEP
  270. .resume_noirq = arizona_resume_noirq,
  271. #endif
  272. };
  273. EXPORT_SYMBOL_GPL(arizona_pm_ops);
  274. static struct mfd_cell early_devs[] = {
  275. { .name = "arizona-ldo1" },
  276. };
  277. static struct mfd_cell wm5102_devs[] = {
  278. { .name = "arizona-micsupp" },
  279. { .name = "arizona-extcon" },
  280. { .name = "arizona-gpio" },
  281. { .name = "arizona-haptics" },
  282. { .name = "arizona-pwm" },
  283. { .name = "wm5102-codec" },
  284. };
  285. static struct mfd_cell wm5110_devs[] = {
  286. { .name = "arizona-micsupp" },
  287. { .name = "arizona-extcon" },
  288. { .name = "arizona-gpio" },
  289. { .name = "arizona-haptics" },
  290. { .name = "arizona-pwm" },
  291. { .name = "wm5110-codec" },
  292. };
  293. int arizona_dev_init(struct arizona *arizona)
  294. {
  295. struct device *dev = arizona->dev;
  296. const char *type_name;
  297. unsigned int reg, val;
  298. int (*apply_patch)(struct arizona *) = NULL;
  299. int ret, i;
  300. dev_set_drvdata(arizona->dev, arizona);
  301. mutex_init(&arizona->clk_lock);
  302. if (dev_get_platdata(arizona->dev))
  303. memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
  304. sizeof(arizona->pdata));
  305. regcache_cache_only(arizona->regmap, true);
  306. switch (arizona->type) {
  307. case WM5102:
  308. case WM5110:
  309. for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
  310. arizona->core_supplies[i].supply
  311. = wm5102_core_supplies[i];
  312. arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
  313. break;
  314. default:
  315. dev_err(arizona->dev, "Unknown device type %d\n",
  316. arizona->type);
  317. return -EINVAL;
  318. }
  319. ret = mfd_add_devices(arizona->dev, -1, early_devs,
  320. ARRAY_SIZE(early_devs), NULL, 0, NULL);
  321. if (ret != 0) {
  322. dev_err(dev, "Failed to add early children: %d\n", ret);
  323. return ret;
  324. }
  325. ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
  326. arizona->core_supplies);
  327. if (ret != 0) {
  328. dev_err(dev, "Failed to request core supplies: %d\n",
  329. ret);
  330. goto err_early;
  331. }
  332. arizona->dcvdd = devm_regulator_get(arizona->dev, "DCVDD");
  333. if (IS_ERR(arizona->dcvdd)) {
  334. ret = PTR_ERR(arizona->dcvdd);
  335. dev_err(dev, "Failed to request DCVDD: %d\n", ret);
  336. goto err_early;
  337. }
  338. ret = regulator_bulk_enable(arizona->num_core_supplies,
  339. arizona->core_supplies);
  340. if (ret != 0) {
  341. dev_err(dev, "Failed to enable core supplies: %d\n",
  342. ret);
  343. goto err_early;
  344. }
  345. ret = regulator_enable(arizona->dcvdd);
  346. if (ret != 0) {
  347. dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
  348. goto err_enable;
  349. }
  350. if (arizona->pdata.reset) {
  351. /* Start out with /RESET low to put the chip into reset */
  352. ret = gpio_request_one(arizona->pdata.reset,
  353. GPIOF_DIR_OUT | GPIOF_INIT_LOW,
  354. "arizona /RESET");
  355. if (ret != 0) {
  356. dev_err(dev, "Failed to request /RESET: %d\n", ret);
  357. goto err_dcvdd;
  358. }
  359. gpio_set_value_cansleep(arizona->pdata.reset, 1);
  360. }
  361. regcache_cache_only(arizona->regmap, false);
  362. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  363. if (ret != 0) {
  364. dev_err(dev, "Failed to read ID register: %d\n", ret);
  365. goto err_reset;
  366. }
  367. ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
  368. &arizona->rev);
  369. if (ret != 0) {
  370. dev_err(dev, "Failed to read revision register: %d\n", ret);
  371. goto err_reset;
  372. }
  373. arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
  374. switch (reg) {
  375. #ifdef CONFIG_MFD_WM5102
  376. case 0x5102:
  377. type_name = "WM5102";
  378. if (arizona->type != WM5102) {
  379. dev_err(arizona->dev, "WM5102 registered as %d\n",
  380. arizona->type);
  381. arizona->type = WM5102;
  382. }
  383. apply_patch = wm5102_patch;
  384. arizona->rev &= 0x7;
  385. break;
  386. #endif
  387. #ifdef CONFIG_MFD_WM5110
  388. case 0x5110:
  389. type_name = "WM5110";
  390. if (arizona->type != WM5110) {
  391. dev_err(arizona->dev, "WM5110 registered as %d\n",
  392. arizona->type);
  393. arizona->type = WM5110;
  394. }
  395. apply_patch = wm5110_patch;
  396. break;
  397. #endif
  398. default:
  399. dev_err(arizona->dev, "Unknown device ID %x\n", reg);
  400. goto err_reset;
  401. }
  402. dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
  403. /* If we have a /RESET GPIO we'll already be reset */
  404. if (!arizona->pdata.reset) {
  405. regcache_mark_dirty(arizona->regmap);
  406. ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
  407. if (ret != 0) {
  408. dev_err(dev, "Failed to reset device: %d\n", ret);
  409. goto err_reset;
  410. }
  411. ret = regcache_sync(arizona->regmap);
  412. if (ret != 0) {
  413. dev_err(dev, "Failed to sync device: %d\n", ret);
  414. goto err_reset;
  415. }
  416. }
  417. ret = arizona_wait_for_boot(arizona);
  418. if (ret != 0) {
  419. dev_err(arizona->dev, "Device failed initial boot: %d\n", ret);
  420. goto err_reset;
  421. }
  422. if (apply_patch) {
  423. ret = apply_patch(arizona);
  424. if (ret != 0) {
  425. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  426. ret);
  427. goto err_reset;
  428. }
  429. }
  430. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  431. if (!arizona->pdata.gpio_defaults[i])
  432. continue;
  433. regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
  434. arizona->pdata.gpio_defaults[i]);
  435. }
  436. pm_runtime_set_autosuspend_delay(arizona->dev, 100);
  437. pm_runtime_use_autosuspend(arizona->dev);
  438. pm_runtime_enable(arizona->dev);
  439. /* Chip default */
  440. if (!arizona->pdata.clk32k_src)
  441. arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
  442. switch (arizona->pdata.clk32k_src) {
  443. case ARIZONA_32KZ_MCLK1:
  444. case ARIZONA_32KZ_MCLK2:
  445. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  446. ARIZONA_CLK_32K_SRC_MASK,
  447. arizona->pdata.clk32k_src - 1);
  448. arizona_clk32k_enable(arizona);
  449. break;
  450. case ARIZONA_32KZ_NONE:
  451. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  452. ARIZONA_CLK_32K_SRC_MASK, 2);
  453. break;
  454. default:
  455. dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
  456. arizona->pdata.clk32k_src);
  457. ret = -EINVAL;
  458. goto err_reset;
  459. }
  460. for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
  461. if (!arizona->pdata.micbias[i].mV &&
  462. !arizona->pdata.micbias[i].bypass)
  463. continue;
  464. /* Apply default for bypass mode */
  465. if (!arizona->pdata.micbias[i].mV)
  466. arizona->pdata.micbias[i].mV = 2800;
  467. val = (arizona->pdata.micbias[i].mV - 1500) / 100;
  468. val <<= ARIZONA_MICB1_LVL_SHIFT;
  469. if (arizona->pdata.micbias[i].ext_cap)
  470. val |= ARIZONA_MICB1_EXT_CAP;
  471. if (arizona->pdata.micbias[i].discharge)
  472. val |= ARIZONA_MICB1_DISCH;
  473. if (arizona->pdata.micbias[i].fast_start)
  474. val |= ARIZONA_MICB1_RATE;
  475. if (arizona->pdata.micbias[i].bypass)
  476. val |= ARIZONA_MICB1_BYPASS;
  477. regmap_update_bits(arizona->regmap,
  478. ARIZONA_MIC_BIAS_CTRL_1 + i,
  479. ARIZONA_MICB1_LVL_MASK |
  480. ARIZONA_MICB1_DISCH |
  481. ARIZONA_MICB1_BYPASS |
  482. ARIZONA_MICB1_RATE, val);
  483. }
  484. for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
  485. /* Default for both is 0 so noop with defaults */
  486. val = arizona->pdata.dmic_ref[i]
  487. << ARIZONA_IN1_DMIC_SUP_SHIFT;
  488. val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
  489. regmap_update_bits(arizona->regmap,
  490. ARIZONA_IN1L_CONTROL + (i * 8),
  491. ARIZONA_IN1_DMIC_SUP_MASK |
  492. ARIZONA_IN1_MODE_MASK, val);
  493. }
  494. for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
  495. /* Default is 0 so noop with defaults */
  496. if (arizona->pdata.out_mono[i])
  497. val = ARIZONA_OUT1_MONO;
  498. else
  499. val = 0;
  500. regmap_update_bits(arizona->regmap,
  501. ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
  502. ARIZONA_OUT1_MONO, val);
  503. }
  504. for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
  505. if (arizona->pdata.spk_mute[i])
  506. regmap_update_bits(arizona->regmap,
  507. ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
  508. ARIZONA_SPK1_MUTE_ENDIAN_MASK |
  509. ARIZONA_SPK1_MUTE_SEQ1_MASK,
  510. arizona->pdata.spk_mute[i]);
  511. if (arizona->pdata.spk_fmt[i])
  512. regmap_update_bits(arizona->regmap,
  513. ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
  514. ARIZONA_SPK1_FMT_MASK,
  515. arizona->pdata.spk_fmt[i]);
  516. }
  517. /* Set up for interrupts */
  518. ret = arizona_irq_init(arizona);
  519. if (ret != 0)
  520. goto err_reset;
  521. arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
  522. arizona_clkgen_err, arizona);
  523. arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
  524. arizona_overclocked, arizona);
  525. arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
  526. arizona_underclocked, arizona);
  527. switch (arizona->type) {
  528. case WM5102:
  529. ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
  530. ARRAY_SIZE(wm5102_devs), NULL, 0, NULL);
  531. break;
  532. case WM5110:
  533. ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
  534. ARRAY_SIZE(wm5110_devs), NULL, 0, NULL);
  535. break;
  536. }
  537. if (ret != 0) {
  538. dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
  539. goto err_irq;
  540. }
  541. #ifdef CONFIG_PM_RUNTIME
  542. regulator_disable(arizona->dcvdd);
  543. #endif
  544. return 0;
  545. err_irq:
  546. arizona_irq_exit(arizona);
  547. err_reset:
  548. if (arizona->pdata.reset) {
  549. gpio_set_value_cansleep(arizona->pdata.reset, 1);
  550. gpio_free(arizona->pdata.reset);
  551. }
  552. err_dcvdd:
  553. regulator_disable(arizona->dcvdd);
  554. err_enable:
  555. regulator_bulk_disable(arizona->num_core_supplies,
  556. arizona->core_supplies);
  557. err_early:
  558. mfd_remove_devices(dev);
  559. return ret;
  560. }
  561. EXPORT_SYMBOL_GPL(arizona_dev_init);
  562. int arizona_dev_exit(struct arizona *arizona)
  563. {
  564. mfd_remove_devices(arizona->dev);
  565. arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
  566. arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
  567. arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
  568. pm_runtime_disable(arizona->dev);
  569. arizona_irq_exit(arizona);
  570. return 0;
  571. }
  572. EXPORT_SYMBOL_GPL(arizona_dev_exit);