rt61pci.c 88 KB

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  1. /*
  2. Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt61pci
  19. Abstract: rt61pci device specific routines.
  20. Supported chipsets: RT2561, RT2561s, RT2661.
  21. */
  22. #include <linux/crc-itu-t.h>
  23. #include <linux/delay.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/init.h>
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/slab.h>
  29. #include <linux/pci.h>
  30. #include <linux/eeprom_93cx6.h>
  31. #include "rt2x00.h"
  32. #include "rt2x00pci.h"
  33. #include "rt61pci.h"
  34. /*
  35. * Allow hardware encryption to be disabled.
  36. */
  37. static int modparam_nohwcrypt = 0;
  38. module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  39. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  40. /*
  41. * Register access.
  42. * BBP and RF register require indirect register access,
  43. * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  44. * These indirect registers work with busy bits,
  45. * and we will try maximal REGISTER_BUSY_COUNT times to access
  46. * the register while taking a REGISTER_BUSY_DELAY us delay
  47. * between each attempt. When the busy bit is still set at that time,
  48. * the access attempt is considered to have failed,
  49. * and we will print an error.
  50. */
  51. #define WAIT_FOR_BBP(__dev, __reg) \
  52. rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  53. #define WAIT_FOR_RF(__dev, __reg) \
  54. rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  55. #define WAIT_FOR_MCU(__dev, __reg) \
  56. rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  57. H2M_MAILBOX_CSR_OWNER, (__reg))
  58. static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  59. const unsigned int word, const u8 value)
  60. {
  61. u32 reg;
  62. mutex_lock(&rt2x00dev->csr_mutex);
  63. /*
  64. * Wait until the BBP becomes available, afterwards we
  65. * can safely write the new data into the register.
  66. */
  67. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  68. reg = 0;
  69. rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  70. rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  71. rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  72. rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  73. rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  74. }
  75. mutex_unlock(&rt2x00dev->csr_mutex);
  76. }
  77. static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  78. const unsigned int word, u8 *value)
  79. {
  80. u32 reg;
  81. mutex_lock(&rt2x00dev->csr_mutex);
  82. /*
  83. * Wait until the BBP becomes available, afterwards we
  84. * can safely write the read request into the register.
  85. * After the data has been written, we wait until hardware
  86. * returns the correct value, if at any time the register
  87. * doesn't become available in time, reg will be 0xffffffff
  88. * which means we return 0xff to the caller.
  89. */
  90. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  91. reg = 0;
  92. rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  93. rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  94. rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
  95. rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  96. WAIT_FOR_BBP(rt2x00dev, &reg);
  97. }
  98. *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
  99. mutex_unlock(&rt2x00dev->csr_mutex);
  100. }
  101. static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
  102. const unsigned int word, const u32 value)
  103. {
  104. u32 reg;
  105. mutex_lock(&rt2x00dev->csr_mutex);
  106. /*
  107. * Wait until the RF becomes available, afterwards we
  108. * can safely write the new data into the register.
  109. */
  110. if (WAIT_FOR_RF(rt2x00dev, &reg)) {
  111. reg = 0;
  112. rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
  113. rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
  114. rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
  115. rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
  116. rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
  117. rt2x00_rf_write(rt2x00dev, word, value);
  118. }
  119. mutex_unlock(&rt2x00dev->csr_mutex);
  120. }
  121. static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
  122. const u8 command, const u8 token,
  123. const u8 arg0, const u8 arg1)
  124. {
  125. u32 reg;
  126. mutex_lock(&rt2x00dev->csr_mutex);
  127. /*
  128. * Wait until the MCU becomes available, afterwards we
  129. * can safely write the new data into the register.
  130. */
  131. if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
  132. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
  133. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
  134. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
  135. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
  136. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
  137. rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
  138. rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
  139. rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
  140. rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
  141. }
  142. mutex_unlock(&rt2x00dev->csr_mutex);
  143. }
  144. static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  145. {
  146. struct rt2x00_dev *rt2x00dev = eeprom->data;
  147. u32 reg;
  148. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  149. eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
  150. eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
  151. eeprom->reg_data_clock =
  152. !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
  153. eeprom->reg_chip_select =
  154. !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
  155. }
  156. static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
  157. {
  158. struct rt2x00_dev *rt2x00dev = eeprom->data;
  159. u32 reg = 0;
  160. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
  161. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
  162. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
  163. !!eeprom->reg_data_clock);
  164. rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
  165. !!eeprom->reg_chip_select);
  166. rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
  167. }
  168. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  169. static const struct rt2x00debug rt61pci_rt2x00debug = {
  170. .owner = THIS_MODULE,
  171. .csr = {
  172. .read = rt2x00pci_register_read,
  173. .write = rt2x00pci_register_write,
  174. .flags = RT2X00DEBUGFS_OFFSET,
  175. .word_base = CSR_REG_BASE,
  176. .word_size = sizeof(u32),
  177. .word_count = CSR_REG_SIZE / sizeof(u32),
  178. },
  179. .eeprom = {
  180. .read = rt2x00_eeprom_read,
  181. .write = rt2x00_eeprom_write,
  182. .word_base = EEPROM_BASE,
  183. .word_size = sizeof(u16),
  184. .word_count = EEPROM_SIZE / sizeof(u16),
  185. },
  186. .bbp = {
  187. .read = rt61pci_bbp_read,
  188. .write = rt61pci_bbp_write,
  189. .word_base = BBP_BASE,
  190. .word_size = sizeof(u8),
  191. .word_count = BBP_SIZE / sizeof(u8),
  192. },
  193. .rf = {
  194. .read = rt2x00_rf_read,
  195. .write = rt61pci_rf_write,
  196. .word_base = RF_BASE,
  197. .word_size = sizeof(u32),
  198. .word_count = RF_SIZE / sizeof(u32),
  199. },
  200. };
  201. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  202. static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  203. {
  204. u32 reg;
  205. rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
  206. return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
  207. }
  208. #ifdef CONFIG_RT2X00_LIB_LEDS
  209. static void rt61pci_brightness_set(struct led_classdev *led_cdev,
  210. enum led_brightness brightness)
  211. {
  212. struct rt2x00_led *led =
  213. container_of(led_cdev, struct rt2x00_led, led_dev);
  214. unsigned int enabled = brightness != LED_OFF;
  215. unsigned int a_mode =
  216. (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
  217. unsigned int bg_mode =
  218. (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
  219. if (led->type == LED_TYPE_RADIO) {
  220. rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
  221. MCU_LEDCS_RADIO_STATUS, enabled);
  222. rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
  223. (led->rt2x00dev->led_mcu_reg & 0xff),
  224. ((led->rt2x00dev->led_mcu_reg >> 8)));
  225. } else if (led->type == LED_TYPE_ASSOC) {
  226. rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
  227. MCU_LEDCS_LINK_BG_STATUS, bg_mode);
  228. rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
  229. MCU_LEDCS_LINK_A_STATUS, a_mode);
  230. rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
  231. (led->rt2x00dev->led_mcu_reg & 0xff),
  232. ((led->rt2x00dev->led_mcu_reg >> 8)));
  233. } else if (led->type == LED_TYPE_QUALITY) {
  234. /*
  235. * The brightness is divided into 6 levels (0 - 5),
  236. * this means we need to convert the brightness
  237. * argument into the matching level within that range.
  238. */
  239. rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
  240. brightness / (LED_FULL / 6), 0);
  241. }
  242. }
  243. static int rt61pci_blink_set(struct led_classdev *led_cdev,
  244. unsigned long *delay_on,
  245. unsigned long *delay_off)
  246. {
  247. struct rt2x00_led *led =
  248. container_of(led_cdev, struct rt2x00_led, led_dev);
  249. u32 reg;
  250. rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
  251. rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
  252. rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
  253. rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
  254. return 0;
  255. }
  256. static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
  257. struct rt2x00_led *led,
  258. enum led_type type)
  259. {
  260. led->rt2x00dev = rt2x00dev;
  261. led->type = type;
  262. led->led_dev.brightness_set = rt61pci_brightness_set;
  263. led->led_dev.blink_set = rt61pci_blink_set;
  264. led->flags = LED_INITIALIZED;
  265. }
  266. #endif /* CONFIG_RT2X00_LIB_LEDS */
  267. /*
  268. * Configuration handlers.
  269. */
  270. static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
  271. struct rt2x00lib_crypto *crypto,
  272. struct ieee80211_key_conf *key)
  273. {
  274. struct hw_key_entry key_entry;
  275. struct rt2x00_field32 field;
  276. u32 mask;
  277. u32 reg;
  278. if (crypto->cmd == SET_KEY) {
  279. /*
  280. * rt2x00lib can't determine the correct free
  281. * key_idx for shared keys. We have 1 register
  282. * with key valid bits. The goal is simple, read
  283. * the register, if that is full we have no slots
  284. * left.
  285. * Note that each BSS is allowed to have up to 4
  286. * shared keys, so put a mask over the allowed
  287. * entries.
  288. */
  289. mask = (0xf << crypto->bssidx);
  290. rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
  291. reg &= mask;
  292. if (reg && reg == mask)
  293. return -ENOSPC;
  294. key->hw_key_idx += reg ? ffz(reg) : 0;
  295. /*
  296. * Upload key to hardware
  297. */
  298. memcpy(key_entry.key, crypto->key,
  299. sizeof(key_entry.key));
  300. memcpy(key_entry.tx_mic, crypto->tx_mic,
  301. sizeof(key_entry.tx_mic));
  302. memcpy(key_entry.rx_mic, crypto->rx_mic,
  303. sizeof(key_entry.rx_mic));
  304. reg = SHARED_KEY_ENTRY(key->hw_key_idx);
  305. rt2x00pci_register_multiwrite(rt2x00dev, reg,
  306. &key_entry, sizeof(key_entry));
  307. /*
  308. * The cipher types are stored over 2 registers.
  309. * bssidx 0 and 1 keys are stored in SEC_CSR1 and
  310. * bssidx 1 and 2 keys are stored in SEC_CSR5.
  311. * Using the correct defines correctly will cause overhead,
  312. * so just calculate the correct offset.
  313. */
  314. if (key->hw_key_idx < 8) {
  315. field.bit_offset = (3 * key->hw_key_idx);
  316. field.bit_mask = 0x7 << field.bit_offset;
  317. rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
  318. rt2x00_set_field32(&reg, field, crypto->cipher);
  319. rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
  320. } else {
  321. field.bit_offset = (3 * (key->hw_key_idx - 8));
  322. field.bit_mask = 0x7 << field.bit_offset;
  323. rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
  324. rt2x00_set_field32(&reg, field, crypto->cipher);
  325. rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
  326. }
  327. /*
  328. * The driver does not support the IV/EIV generation
  329. * in hardware. However it doesn't support the IV/EIV
  330. * inside the ieee80211 frame either, but requires it
  331. * to be provided separately for the descriptor.
  332. * rt2x00lib will cut the IV/EIV data out of all frames
  333. * given to us by mac80211, but we must tell mac80211
  334. * to generate the IV/EIV data.
  335. */
  336. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  337. }
  338. /*
  339. * SEC_CSR0 contains only single-bit fields to indicate
  340. * a particular key is valid. Because using the FIELD32()
  341. * defines directly will cause a lot of overhead, we use
  342. * a calculation to determine the correct bit directly.
  343. */
  344. mask = 1 << key->hw_key_idx;
  345. rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
  346. if (crypto->cmd == SET_KEY)
  347. reg |= mask;
  348. else if (crypto->cmd == DISABLE_KEY)
  349. reg &= ~mask;
  350. rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
  351. return 0;
  352. }
  353. static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
  354. struct rt2x00lib_crypto *crypto,
  355. struct ieee80211_key_conf *key)
  356. {
  357. struct hw_pairwise_ta_entry addr_entry;
  358. struct hw_key_entry key_entry;
  359. u32 mask;
  360. u32 reg;
  361. if (crypto->cmd == SET_KEY) {
  362. /*
  363. * rt2x00lib can't determine the correct free
  364. * key_idx for pairwise keys. We have 2 registers
  365. * with key valid bits. The goal is simple: read
  366. * the first register. If that is full, move to
  367. * the next register.
  368. * When both registers are full, we drop the key.
  369. * Otherwise, we use the first invalid entry.
  370. */
  371. rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
  372. if (reg && reg == ~0) {
  373. key->hw_key_idx = 32;
  374. rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
  375. if (reg && reg == ~0)
  376. return -ENOSPC;
  377. }
  378. key->hw_key_idx += reg ? ffz(reg) : 0;
  379. /*
  380. * Upload key to hardware
  381. */
  382. memcpy(key_entry.key, crypto->key,
  383. sizeof(key_entry.key));
  384. memcpy(key_entry.tx_mic, crypto->tx_mic,
  385. sizeof(key_entry.tx_mic));
  386. memcpy(key_entry.rx_mic, crypto->rx_mic,
  387. sizeof(key_entry.rx_mic));
  388. memset(&addr_entry, 0, sizeof(addr_entry));
  389. memcpy(&addr_entry, crypto->address, ETH_ALEN);
  390. addr_entry.cipher = crypto->cipher;
  391. reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
  392. rt2x00pci_register_multiwrite(rt2x00dev, reg,
  393. &key_entry, sizeof(key_entry));
  394. reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
  395. rt2x00pci_register_multiwrite(rt2x00dev, reg,
  396. &addr_entry, sizeof(addr_entry));
  397. /*
  398. * Enable pairwise lookup table for given BSS idx.
  399. * Without this, received frames will not be decrypted
  400. * by the hardware.
  401. */
  402. rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
  403. reg |= (1 << crypto->bssidx);
  404. rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
  405. /*
  406. * The driver does not support the IV/EIV generation
  407. * in hardware. However it doesn't support the IV/EIV
  408. * inside the ieee80211 frame either, but requires it
  409. * to be provided separately for the descriptor.
  410. * rt2x00lib will cut the IV/EIV data out of all frames
  411. * given to us by mac80211, but we must tell mac80211
  412. * to generate the IV/EIV data.
  413. */
  414. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  415. }
  416. /*
  417. * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
  418. * a particular key is valid. Because using the FIELD32()
  419. * defines directly will cause a lot of overhead, we use
  420. * a calculation to determine the correct bit directly.
  421. */
  422. if (key->hw_key_idx < 32) {
  423. mask = 1 << key->hw_key_idx;
  424. rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
  425. if (crypto->cmd == SET_KEY)
  426. reg |= mask;
  427. else if (crypto->cmd == DISABLE_KEY)
  428. reg &= ~mask;
  429. rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
  430. } else {
  431. mask = 1 << (key->hw_key_idx - 32);
  432. rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
  433. if (crypto->cmd == SET_KEY)
  434. reg |= mask;
  435. else if (crypto->cmd == DISABLE_KEY)
  436. reg &= ~mask;
  437. rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
  438. }
  439. return 0;
  440. }
  441. static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
  442. const unsigned int filter_flags)
  443. {
  444. u32 reg;
  445. /*
  446. * Start configuration steps.
  447. * Note that the version error will always be dropped
  448. * and broadcast frames will always be accepted since
  449. * there is no filter for it at this time.
  450. */
  451. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  452. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
  453. !(filter_flags & FIF_FCSFAIL));
  454. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
  455. !(filter_flags & FIF_PLCPFAIL));
  456. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
  457. !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
  458. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
  459. !(filter_flags & FIF_PROMISC_IN_BSS));
  460. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
  461. !(filter_flags & FIF_PROMISC_IN_BSS) &&
  462. !rt2x00dev->intf_ap_count);
  463. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
  464. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
  465. !(filter_flags & FIF_ALLMULTI));
  466. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
  467. rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
  468. !(filter_flags & FIF_CONTROL));
  469. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  470. }
  471. static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
  472. struct rt2x00_intf *intf,
  473. struct rt2x00intf_conf *conf,
  474. const unsigned int flags)
  475. {
  476. unsigned int beacon_base;
  477. u32 reg;
  478. if (flags & CONFIG_UPDATE_TYPE) {
  479. /*
  480. * Clear current synchronisation setup.
  481. * For the Beacon base registers, we only need to clear
  482. * the first byte since that byte contains the VALID and OWNER
  483. * bits which (when set to 0) will invalidate the entire beacon.
  484. */
  485. beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
  486. rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
  487. /*
  488. * Enable synchronisation.
  489. */
  490. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  491. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
  492. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
  493. rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
  494. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  495. }
  496. if (flags & CONFIG_UPDATE_MAC) {
  497. reg = le32_to_cpu(conf->mac[1]);
  498. rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
  499. conf->mac[1] = cpu_to_le32(reg);
  500. rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
  501. conf->mac, sizeof(conf->mac));
  502. }
  503. if (flags & CONFIG_UPDATE_BSSID) {
  504. reg = le32_to_cpu(conf->bssid[1]);
  505. rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
  506. conf->bssid[1] = cpu_to_le32(reg);
  507. rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
  508. conf->bssid, sizeof(conf->bssid));
  509. }
  510. }
  511. static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
  512. struct rt2x00lib_erp *erp)
  513. {
  514. u32 reg;
  515. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  516. rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
  517. rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
  518. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  519. rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
  520. rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
  521. rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
  522. !!erp->short_preamble);
  523. rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
  524. rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
  525. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  526. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
  527. erp->beacon_int * 16);
  528. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  529. rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
  530. rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
  531. rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
  532. rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
  533. rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
  534. rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
  535. rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
  536. rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
  537. }
  538. static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
  539. struct antenna_setup *ant)
  540. {
  541. u8 r3;
  542. u8 r4;
  543. u8 r77;
  544. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  545. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  546. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  547. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
  548. /*
  549. * Configure the RX antenna.
  550. */
  551. switch (ant->rx) {
  552. case ANTENNA_HW_DIVERSITY:
  553. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
  554. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
  555. (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
  556. break;
  557. case ANTENNA_A:
  558. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  559. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
  560. if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
  561. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  562. else
  563. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  564. break;
  565. case ANTENNA_B:
  566. default:
  567. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  568. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
  569. if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
  570. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  571. else
  572. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  573. break;
  574. }
  575. rt61pci_bbp_write(rt2x00dev, 77, r77);
  576. rt61pci_bbp_write(rt2x00dev, 3, r3);
  577. rt61pci_bbp_write(rt2x00dev, 4, r4);
  578. }
  579. static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
  580. struct antenna_setup *ant)
  581. {
  582. u8 r3;
  583. u8 r4;
  584. u8 r77;
  585. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  586. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  587. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  588. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
  589. rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
  590. !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
  591. /*
  592. * Configure the RX antenna.
  593. */
  594. switch (ant->rx) {
  595. case ANTENNA_HW_DIVERSITY:
  596. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
  597. break;
  598. case ANTENNA_A:
  599. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  600. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  601. break;
  602. case ANTENNA_B:
  603. default:
  604. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  605. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  606. break;
  607. }
  608. rt61pci_bbp_write(rt2x00dev, 77, r77);
  609. rt61pci_bbp_write(rt2x00dev, 3, r3);
  610. rt61pci_bbp_write(rt2x00dev, 4, r4);
  611. }
  612. static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
  613. const int p1, const int p2)
  614. {
  615. u32 reg;
  616. rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
  617. rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
  618. rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
  619. rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
  620. rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
  621. rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
  622. }
  623. static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
  624. struct antenna_setup *ant)
  625. {
  626. u8 r3;
  627. u8 r4;
  628. u8 r77;
  629. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  630. rt61pci_bbp_read(rt2x00dev, 4, &r4);
  631. rt61pci_bbp_read(rt2x00dev, 77, &r77);
  632. /*
  633. * Configure the RX antenna.
  634. */
  635. switch (ant->rx) {
  636. case ANTENNA_A:
  637. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  638. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
  639. rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
  640. break;
  641. case ANTENNA_HW_DIVERSITY:
  642. /*
  643. * FIXME: Antenna selection for the rf 2529 is very confusing
  644. * in the legacy driver. Just default to antenna B until the
  645. * legacy code can be properly translated into rt2x00 code.
  646. */
  647. case ANTENNA_B:
  648. default:
  649. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
  650. rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
  651. rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
  652. break;
  653. }
  654. rt61pci_bbp_write(rt2x00dev, 77, r77);
  655. rt61pci_bbp_write(rt2x00dev, 3, r3);
  656. rt61pci_bbp_write(rt2x00dev, 4, r4);
  657. }
  658. struct antenna_sel {
  659. u8 word;
  660. /*
  661. * value[0] -> non-LNA
  662. * value[1] -> LNA
  663. */
  664. u8 value[2];
  665. };
  666. static const struct antenna_sel antenna_sel_a[] = {
  667. { 96, { 0x58, 0x78 } },
  668. { 104, { 0x38, 0x48 } },
  669. { 75, { 0xfe, 0x80 } },
  670. { 86, { 0xfe, 0x80 } },
  671. { 88, { 0xfe, 0x80 } },
  672. { 35, { 0x60, 0x60 } },
  673. { 97, { 0x58, 0x58 } },
  674. { 98, { 0x58, 0x58 } },
  675. };
  676. static const struct antenna_sel antenna_sel_bg[] = {
  677. { 96, { 0x48, 0x68 } },
  678. { 104, { 0x2c, 0x3c } },
  679. { 75, { 0xfe, 0x80 } },
  680. { 86, { 0xfe, 0x80 } },
  681. { 88, { 0xfe, 0x80 } },
  682. { 35, { 0x50, 0x50 } },
  683. { 97, { 0x48, 0x48 } },
  684. { 98, { 0x48, 0x48 } },
  685. };
  686. static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
  687. struct antenna_setup *ant)
  688. {
  689. const struct antenna_sel *sel;
  690. unsigned int lna;
  691. unsigned int i;
  692. u32 reg;
  693. /*
  694. * We should never come here because rt2x00lib is supposed
  695. * to catch this and send us the correct antenna explicitely.
  696. */
  697. BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
  698. ant->tx == ANTENNA_SW_DIVERSITY);
  699. if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
  700. sel = antenna_sel_a;
  701. lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
  702. } else {
  703. sel = antenna_sel_bg;
  704. lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
  705. }
  706. for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
  707. rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
  708. rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
  709. rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
  710. rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
  711. rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
  712. rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
  713. rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
  714. if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
  715. rt61pci_config_antenna_5x(rt2x00dev, ant);
  716. else if (rt2x00_rf(rt2x00dev, RF2527))
  717. rt61pci_config_antenna_2x(rt2x00dev, ant);
  718. else if (rt2x00_rf(rt2x00dev, RF2529)) {
  719. if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
  720. rt61pci_config_antenna_2x(rt2x00dev, ant);
  721. else
  722. rt61pci_config_antenna_2529(rt2x00dev, ant);
  723. }
  724. }
  725. static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
  726. struct rt2x00lib_conf *libconf)
  727. {
  728. u16 eeprom;
  729. short lna_gain = 0;
  730. if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
  731. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
  732. lna_gain += 14;
  733. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
  734. lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
  735. } else {
  736. if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
  737. lna_gain += 14;
  738. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
  739. lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
  740. }
  741. rt2x00dev->lna_gain = lna_gain;
  742. }
  743. static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
  744. struct rf_channel *rf, const int txpower)
  745. {
  746. u8 r3;
  747. u8 r94;
  748. u8 smart;
  749. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
  750. rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
  751. smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
  752. rt61pci_bbp_read(rt2x00dev, 3, &r3);
  753. rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
  754. rt61pci_bbp_write(rt2x00dev, 3, r3);
  755. r94 = 6;
  756. if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
  757. r94 += txpower - MAX_TXPOWER;
  758. else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
  759. r94 += txpower;
  760. rt61pci_bbp_write(rt2x00dev, 94, r94);
  761. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  762. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  763. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  764. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  765. udelay(200);
  766. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  767. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  768. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
  769. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  770. udelay(200);
  771. rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
  772. rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
  773. rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  774. rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
  775. msleep(1);
  776. }
  777. static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
  778. const int txpower)
  779. {
  780. struct rf_channel rf;
  781. rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
  782. rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
  783. rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
  784. rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
  785. rt61pci_config_channel(rt2x00dev, &rf, txpower);
  786. }
  787. static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
  788. struct rt2x00lib_conf *libconf)
  789. {
  790. u32 reg;
  791. rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
  792. rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
  793. rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
  794. rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
  795. rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
  796. libconf->conf->long_frame_max_tx_count);
  797. rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
  798. libconf->conf->short_frame_max_tx_count);
  799. rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
  800. }
  801. static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
  802. struct rt2x00lib_conf *libconf)
  803. {
  804. enum dev_state state =
  805. (libconf->conf->flags & IEEE80211_CONF_PS) ?
  806. STATE_SLEEP : STATE_AWAKE;
  807. u32 reg;
  808. if (state == STATE_SLEEP) {
  809. rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
  810. rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
  811. rt2x00dev->beacon_int - 10);
  812. rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
  813. libconf->conf->listen_interval - 1);
  814. rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
  815. /* We must first disable autowake before it can be enabled */
  816. rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
  817. rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
  818. rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
  819. rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
  820. rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
  821. rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
  822. rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
  823. rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
  824. } else {
  825. rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
  826. rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
  827. rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
  828. rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
  829. rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
  830. rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
  831. rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
  832. rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
  833. rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
  834. rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
  835. }
  836. }
  837. static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
  838. struct rt2x00lib_conf *libconf,
  839. const unsigned int flags)
  840. {
  841. /* Always recalculate LNA gain before changing configuration */
  842. rt61pci_config_lna_gain(rt2x00dev, libconf);
  843. if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
  844. rt61pci_config_channel(rt2x00dev, &libconf->rf,
  845. libconf->conf->power_level);
  846. if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
  847. !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
  848. rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
  849. if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
  850. rt61pci_config_retry_limit(rt2x00dev, libconf);
  851. if (flags & IEEE80211_CONF_CHANGE_PS)
  852. rt61pci_config_ps(rt2x00dev, libconf);
  853. }
  854. /*
  855. * Link tuning
  856. */
  857. static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
  858. struct link_qual *qual)
  859. {
  860. u32 reg;
  861. /*
  862. * Update FCS error count from register.
  863. */
  864. rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
  865. qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
  866. /*
  867. * Update False CCA count from register.
  868. */
  869. rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
  870. qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
  871. }
  872. static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
  873. struct link_qual *qual, u8 vgc_level)
  874. {
  875. if (qual->vgc_level != vgc_level) {
  876. rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
  877. qual->vgc_level = vgc_level;
  878. qual->vgc_level_reg = vgc_level;
  879. }
  880. }
  881. static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
  882. struct link_qual *qual)
  883. {
  884. rt61pci_set_vgc(rt2x00dev, qual, 0x20);
  885. }
  886. static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
  887. struct link_qual *qual, const u32 count)
  888. {
  889. u8 up_bound;
  890. u8 low_bound;
  891. /*
  892. * Determine r17 bounds.
  893. */
  894. if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
  895. low_bound = 0x28;
  896. up_bound = 0x48;
  897. if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
  898. low_bound += 0x10;
  899. up_bound += 0x10;
  900. }
  901. } else {
  902. low_bound = 0x20;
  903. up_bound = 0x40;
  904. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
  905. low_bound += 0x10;
  906. up_bound += 0x10;
  907. }
  908. }
  909. /*
  910. * If we are not associated, we should go straight to the
  911. * dynamic CCA tuning.
  912. */
  913. if (!rt2x00dev->intf_associated)
  914. goto dynamic_cca_tune;
  915. /*
  916. * Special big-R17 for very short distance
  917. */
  918. if (qual->rssi >= -35) {
  919. rt61pci_set_vgc(rt2x00dev, qual, 0x60);
  920. return;
  921. }
  922. /*
  923. * Special big-R17 for short distance
  924. */
  925. if (qual->rssi >= -58) {
  926. rt61pci_set_vgc(rt2x00dev, qual, up_bound);
  927. return;
  928. }
  929. /*
  930. * Special big-R17 for middle-short distance
  931. */
  932. if (qual->rssi >= -66) {
  933. rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
  934. return;
  935. }
  936. /*
  937. * Special mid-R17 for middle distance
  938. */
  939. if (qual->rssi >= -74) {
  940. rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
  941. return;
  942. }
  943. /*
  944. * Special case: Change up_bound based on the rssi.
  945. * Lower up_bound when rssi is weaker then -74 dBm.
  946. */
  947. up_bound -= 2 * (-74 - qual->rssi);
  948. if (low_bound > up_bound)
  949. up_bound = low_bound;
  950. if (qual->vgc_level > up_bound) {
  951. rt61pci_set_vgc(rt2x00dev, qual, up_bound);
  952. return;
  953. }
  954. dynamic_cca_tune:
  955. /*
  956. * r17 does not yet exceed upper limit, continue and base
  957. * the r17 tuning on the false CCA count.
  958. */
  959. if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
  960. rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
  961. else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
  962. rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
  963. }
  964. /*
  965. * Firmware functions
  966. */
  967. static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
  968. {
  969. u16 chip;
  970. char *fw_name;
  971. pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
  972. switch (chip) {
  973. case RT2561_PCI_ID:
  974. fw_name = FIRMWARE_RT2561;
  975. break;
  976. case RT2561s_PCI_ID:
  977. fw_name = FIRMWARE_RT2561s;
  978. break;
  979. case RT2661_PCI_ID:
  980. fw_name = FIRMWARE_RT2661;
  981. break;
  982. default:
  983. fw_name = NULL;
  984. break;
  985. }
  986. return fw_name;
  987. }
  988. static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
  989. const u8 *data, const size_t len)
  990. {
  991. u16 fw_crc;
  992. u16 crc;
  993. /*
  994. * Only support 8kb firmware files.
  995. */
  996. if (len != 8192)
  997. return FW_BAD_LENGTH;
  998. /*
  999. * The last 2 bytes in the firmware array are the crc checksum itself.
  1000. * This means that we should never pass those 2 bytes to the crc
  1001. * algorithm.
  1002. */
  1003. fw_crc = (data[len - 2] << 8 | data[len - 1]);
  1004. /*
  1005. * Use the crc itu-t algorithm.
  1006. */
  1007. crc = crc_itu_t(0, data, len - 2);
  1008. crc = crc_itu_t_byte(crc, 0);
  1009. crc = crc_itu_t_byte(crc, 0);
  1010. return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
  1011. }
  1012. static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
  1013. const u8 *data, const size_t len)
  1014. {
  1015. int i;
  1016. u32 reg;
  1017. /*
  1018. * Wait for stable hardware.
  1019. */
  1020. for (i = 0; i < 100; i++) {
  1021. rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
  1022. if (reg)
  1023. break;
  1024. msleep(1);
  1025. }
  1026. if (!reg) {
  1027. ERROR(rt2x00dev, "Unstable hardware.\n");
  1028. return -EBUSY;
  1029. }
  1030. /*
  1031. * Prepare MCU and mailbox for firmware loading.
  1032. */
  1033. reg = 0;
  1034. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
  1035. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  1036. rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
  1037. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  1038. rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
  1039. /*
  1040. * Write firmware to device.
  1041. */
  1042. reg = 0;
  1043. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
  1044. rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
  1045. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  1046. rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
  1047. data, len);
  1048. rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
  1049. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  1050. rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
  1051. rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
  1052. for (i = 0; i < 100; i++) {
  1053. rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
  1054. if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
  1055. break;
  1056. msleep(1);
  1057. }
  1058. if (i == 100) {
  1059. ERROR(rt2x00dev, "MCU Control register not ready.\n");
  1060. return -EBUSY;
  1061. }
  1062. /*
  1063. * Hardware needs another millisecond before it is ready.
  1064. */
  1065. msleep(1);
  1066. /*
  1067. * Reset MAC and BBP registers.
  1068. */
  1069. reg = 0;
  1070. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
  1071. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
  1072. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1073. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1074. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
  1075. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
  1076. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1077. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1078. rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
  1079. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1080. return 0;
  1081. }
  1082. /*
  1083. * Initialization functions.
  1084. */
  1085. static bool rt61pci_get_entry_state(struct queue_entry *entry)
  1086. {
  1087. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  1088. u32 word;
  1089. if (entry->queue->qid == QID_RX) {
  1090. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1091. return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
  1092. } else {
  1093. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1094. return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  1095. rt2x00_get_field32(word, TXD_W0_VALID));
  1096. }
  1097. }
  1098. static void rt61pci_clear_entry(struct queue_entry *entry)
  1099. {
  1100. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  1101. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  1102. u32 word;
  1103. if (entry->queue->qid == QID_RX) {
  1104. rt2x00_desc_read(entry_priv->desc, 5, &word);
  1105. rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
  1106. skbdesc->skb_dma);
  1107. rt2x00_desc_write(entry_priv->desc, 5, word);
  1108. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1109. rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
  1110. rt2x00_desc_write(entry_priv->desc, 0, word);
  1111. } else {
  1112. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1113. rt2x00_set_field32(&word, TXD_W0_VALID, 0);
  1114. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
  1115. rt2x00_desc_write(entry_priv->desc, 0, word);
  1116. }
  1117. }
  1118. static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
  1119. {
  1120. struct queue_entry_priv_pci *entry_priv;
  1121. u32 reg;
  1122. /*
  1123. * Initialize registers.
  1124. */
  1125. rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
  1126. rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
  1127. rt2x00dev->tx[0].limit);
  1128. rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
  1129. rt2x00dev->tx[1].limit);
  1130. rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
  1131. rt2x00dev->tx[2].limit);
  1132. rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
  1133. rt2x00dev->tx[3].limit);
  1134. rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
  1135. rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
  1136. rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
  1137. rt2x00dev->tx[0].desc_size / 4);
  1138. rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
  1139. entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
  1140. rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
  1141. rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
  1142. entry_priv->desc_dma);
  1143. rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
  1144. entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
  1145. rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
  1146. rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
  1147. entry_priv->desc_dma);
  1148. rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
  1149. entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
  1150. rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
  1151. rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
  1152. entry_priv->desc_dma);
  1153. rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
  1154. entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
  1155. rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
  1156. rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
  1157. entry_priv->desc_dma);
  1158. rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
  1159. rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
  1160. rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
  1161. rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
  1162. rt2x00dev->rx->desc_size / 4);
  1163. rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
  1164. rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
  1165. entry_priv = rt2x00dev->rx->entries[0].priv_data;
  1166. rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
  1167. rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
  1168. entry_priv->desc_dma);
  1169. rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
  1170. rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
  1171. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
  1172. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
  1173. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
  1174. rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
  1175. rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
  1176. rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
  1177. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
  1178. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
  1179. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
  1180. rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
  1181. rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
  1182. rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
  1183. rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
  1184. rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
  1185. return 0;
  1186. }
  1187. static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
  1188. {
  1189. u32 reg;
  1190. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  1191. rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
  1192. rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
  1193. rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
  1194. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  1195. rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
  1196. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
  1197. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
  1198. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
  1199. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
  1200. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
  1201. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
  1202. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
  1203. rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
  1204. rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
  1205. /*
  1206. * CCK TXD BBP registers
  1207. */
  1208. rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
  1209. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
  1210. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
  1211. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
  1212. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
  1213. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
  1214. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
  1215. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
  1216. rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
  1217. rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
  1218. /*
  1219. * OFDM TXD BBP registers
  1220. */
  1221. rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
  1222. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
  1223. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
  1224. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
  1225. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
  1226. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
  1227. rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
  1228. rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
  1229. rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
  1230. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
  1231. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
  1232. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
  1233. rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
  1234. rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
  1235. rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
  1236. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
  1237. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
  1238. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
  1239. rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
  1240. rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
  1241. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  1242. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
  1243. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
  1244. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
  1245. rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
  1246. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
  1247. rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
  1248. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  1249. rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
  1250. rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
  1251. rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
  1252. rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
  1253. rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
  1254. rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
  1255. if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
  1256. return -EBUSY;
  1257. rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
  1258. /*
  1259. * Invalidate all Shared Keys (SEC_CSR0),
  1260. * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
  1261. */
  1262. rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
  1263. rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
  1264. rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
  1265. rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
  1266. rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
  1267. rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
  1268. rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
  1269. rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
  1270. rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
  1271. rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
  1272. /*
  1273. * Clear all beacons
  1274. * For the Beacon base registers we only need to clear
  1275. * the first byte since that byte contains the VALID and OWNER
  1276. * bits which (when set to 0) will invalidate the entire beacon.
  1277. */
  1278. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
  1279. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
  1280. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
  1281. rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
  1282. /*
  1283. * We must clear the error counters.
  1284. * These registers are cleared on read,
  1285. * so we may pass a useless variable to store the value.
  1286. */
  1287. rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
  1288. rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
  1289. rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
  1290. /*
  1291. * Reset MAC and BBP registers.
  1292. */
  1293. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1294. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
  1295. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
  1296. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1297. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1298. rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
  1299. rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
  1300. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1301. rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
  1302. rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
  1303. rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
  1304. return 0;
  1305. }
  1306. static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
  1307. {
  1308. unsigned int i;
  1309. u8 value;
  1310. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1311. rt61pci_bbp_read(rt2x00dev, 0, &value);
  1312. if ((value != 0xff) && (value != 0x00))
  1313. return 0;
  1314. udelay(REGISTER_BUSY_DELAY);
  1315. }
  1316. ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
  1317. return -EACCES;
  1318. }
  1319. static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
  1320. {
  1321. unsigned int i;
  1322. u16 eeprom;
  1323. u8 reg_id;
  1324. u8 value;
  1325. if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
  1326. return -EACCES;
  1327. rt61pci_bbp_write(rt2x00dev, 3, 0x00);
  1328. rt61pci_bbp_write(rt2x00dev, 15, 0x30);
  1329. rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
  1330. rt61pci_bbp_write(rt2x00dev, 22, 0x38);
  1331. rt61pci_bbp_write(rt2x00dev, 23, 0x06);
  1332. rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
  1333. rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
  1334. rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
  1335. rt61pci_bbp_write(rt2x00dev, 34, 0x12);
  1336. rt61pci_bbp_write(rt2x00dev, 37, 0x07);
  1337. rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
  1338. rt61pci_bbp_write(rt2x00dev, 41, 0x60);
  1339. rt61pci_bbp_write(rt2x00dev, 53, 0x10);
  1340. rt61pci_bbp_write(rt2x00dev, 54, 0x18);
  1341. rt61pci_bbp_write(rt2x00dev, 60, 0x10);
  1342. rt61pci_bbp_write(rt2x00dev, 61, 0x04);
  1343. rt61pci_bbp_write(rt2x00dev, 62, 0x04);
  1344. rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
  1345. rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
  1346. rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
  1347. rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
  1348. rt61pci_bbp_write(rt2x00dev, 99, 0x00);
  1349. rt61pci_bbp_write(rt2x00dev, 102, 0x16);
  1350. rt61pci_bbp_write(rt2x00dev, 107, 0x04);
  1351. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  1352. rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
  1353. if (eeprom != 0xffff && eeprom != 0x0000) {
  1354. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  1355. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  1356. rt61pci_bbp_write(rt2x00dev, reg_id, value);
  1357. }
  1358. }
  1359. return 0;
  1360. }
  1361. /*
  1362. * Device state switch handlers.
  1363. */
  1364. static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
  1365. enum dev_state state)
  1366. {
  1367. u32 reg;
  1368. rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
  1369. rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
  1370. (state == STATE_RADIO_RX_OFF) ||
  1371. (state == STATE_RADIO_RX_OFF_LINK));
  1372. rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
  1373. }
  1374. static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
  1375. enum dev_state state)
  1376. {
  1377. int mask = (state == STATE_RADIO_IRQ_OFF);
  1378. u32 reg;
  1379. /*
  1380. * When interrupts are being enabled, the interrupt registers
  1381. * should clear the register to assure a clean state.
  1382. */
  1383. if (state == STATE_RADIO_IRQ_ON) {
  1384. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  1385. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  1386. rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
  1387. rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
  1388. }
  1389. /*
  1390. * Only toggle the interrupts bits we are going to use.
  1391. * Non-checked interrupt bits are disabled by default.
  1392. */
  1393. rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
  1394. rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
  1395. rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
  1396. rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
  1397. rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
  1398. rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
  1399. rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
  1400. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
  1401. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
  1402. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
  1403. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
  1404. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
  1405. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
  1406. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
  1407. rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
  1408. rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
  1409. }
  1410. static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
  1411. {
  1412. u32 reg;
  1413. /*
  1414. * Initialize all registers.
  1415. */
  1416. if (unlikely(rt61pci_init_queues(rt2x00dev) ||
  1417. rt61pci_init_registers(rt2x00dev) ||
  1418. rt61pci_init_bbp(rt2x00dev)))
  1419. return -EIO;
  1420. /*
  1421. * Enable RX.
  1422. */
  1423. rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
  1424. rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
  1425. rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
  1426. return 0;
  1427. }
  1428. static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
  1429. {
  1430. /*
  1431. * Disable power
  1432. */
  1433. rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
  1434. }
  1435. static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
  1436. {
  1437. u32 reg, reg2;
  1438. unsigned int i;
  1439. char put_to_sleep;
  1440. put_to_sleep = (state != STATE_AWAKE);
  1441. rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
  1442. rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
  1443. rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
  1444. rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
  1445. /*
  1446. * Device is not guaranteed to be in the requested state yet.
  1447. * We must wait until the register indicates that the
  1448. * device has entered the correct state.
  1449. */
  1450. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1451. rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg2);
  1452. state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
  1453. if (state == !put_to_sleep)
  1454. return 0;
  1455. rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
  1456. msleep(10);
  1457. }
  1458. return -EBUSY;
  1459. }
  1460. static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
  1461. enum dev_state state)
  1462. {
  1463. int retval = 0;
  1464. switch (state) {
  1465. case STATE_RADIO_ON:
  1466. retval = rt61pci_enable_radio(rt2x00dev);
  1467. break;
  1468. case STATE_RADIO_OFF:
  1469. rt61pci_disable_radio(rt2x00dev);
  1470. break;
  1471. case STATE_RADIO_RX_ON:
  1472. case STATE_RADIO_RX_ON_LINK:
  1473. case STATE_RADIO_RX_OFF:
  1474. case STATE_RADIO_RX_OFF_LINK:
  1475. rt61pci_toggle_rx(rt2x00dev, state);
  1476. break;
  1477. case STATE_RADIO_IRQ_ON:
  1478. case STATE_RADIO_IRQ_OFF:
  1479. rt61pci_toggle_irq(rt2x00dev, state);
  1480. break;
  1481. case STATE_DEEP_SLEEP:
  1482. case STATE_SLEEP:
  1483. case STATE_STANDBY:
  1484. case STATE_AWAKE:
  1485. retval = rt61pci_set_state(rt2x00dev, state);
  1486. break;
  1487. default:
  1488. retval = -ENOTSUPP;
  1489. break;
  1490. }
  1491. if (unlikely(retval))
  1492. ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
  1493. state, retval);
  1494. return retval;
  1495. }
  1496. /*
  1497. * TX descriptor initialization
  1498. */
  1499. static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
  1500. struct sk_buff *skb,
  1501. struct txentry_desc *txdesc)
  1502. {
  1503. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  1504. struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
  1505. __le32 *txd = entry_priv->desc;
  1506. u32 word;
  1507. /*
  1508. * Start writing the descriptor words.
  1509. */
  1510. rt2x00_desc_read(txd, 1, &word);
  1511. rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
  1512. rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
  1513. rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
  1514. rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
  1515. rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
  1516. rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
  1517. test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
  1518. rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
  1519. rt2x00_desc_write(txd, 1, word);
  1520. rt2x00_desc_read(txd, 2, &word);
  1521. rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
  1522. rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
  1523. rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
  1524. rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
  1525. rt2x00_desc_write(txd, 2, word);
  1526. if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
  1527. _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
  1528. _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
  1529. }
  1530. rt2x00_desc_read(txd, 5, &word);
  1531. rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
  1532. rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
  1533. skbdesc->entry->entry_idx);
  1534. rt2x00_set_field32(&word, TXD_W5_TX_POWER,
  1535. TXPOWER_TO_DEV(rt2x00dev->tx_power));
  1536. rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
  1537. rt2x00_desc_write(txd, 5, word);
  1538. if (txdesc->queue != QID_BEACON) {
  1539. rt2x00_desc_read(txd, 6, &word);
  1540. rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
  1541. skbdesc->skb_dma);
  1542. rt2x00_desc_write(txd, 6, word);
  1543. rt2x00_desc_read(txd, 11, &word);
  1544. rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
  1545. txdesc->length);
  1546. rt2x00_desc_write(txd, 11, word);
  1547. }
  1548. /*
  1549. * Writing TXD word 0 must the last to prevent a race condition with
  1550. * the device, whereby the device may take hold of the TXD before we
  1551. * finished updating it.
  1552. */
  1553. rt2x00_desc_read(txd, 0, &word);
  1554. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
  1555. rt2x00_set_field32(&word, TXD_W0_VALID, 1);
  1556. rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
  1557. test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  1558. rt2x00_set_field32(&word, TXD_W0_ACK,
  1559. test_bit(ENTRY_TXD_ACK, &txdesc->flags));
  1560. rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
  1561. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
  1562. rt2x00_set_field32(&word, TXD_W0_OFDM,
  1563. (txdesc->rate_mode == RATE_MODE_OFDM));
  1564. rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
  1565. rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
  1566. test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
  1567. rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
  1568. test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
  1569. rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
  1570. test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
  1571. rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
  1572. rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
  1573. rt2x00_set_field32(&word, TXD_W0_BURST,
  1574. test_bit(ENTRY_TXD_BURST, &txdesc->flags));
  1575. rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
  1576. rt2x00_desc_write(txd, 0, word);
  1577. /*
  1578. * Register descriptor details in skb frame descriptor.
  1579. */
  1580. skbdesc->desc = txd;
  1581. skbdesc->desc_len =
  1582. (txdesc->queue == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE;
  1583. }
  1584. /*
  1585. * TX data initialization
  1586. */
  1587. static void rt61pci_write_beacon(struct queue_entry *entry,
  1588. struct txentry_desc *txdesc)
  1589. {
  1590. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  1591. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  1592. unsigned int beacon_base;
  1593. u32 reg;
  1594. /*
  1595. * Disable beaconing while we are reloading the beacon data,
  1596. * otherwise we might be sending out invalid data.
  1597. */
  1598. rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
  1599. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
  1600. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  1601. /*
  1602. * Write the TX descriptor for the beacon.
  1603. */
  1604. rt61pci_write_tx_desc(rt2x00dev, entry->skb, txdesc);
  1605. /*
  1606. * Dump beacon to userspace through debugfs.
  1607. */
  1608. rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
  1609. /*
  1610. * Write entire beacon with descriptor to register.
  1611. */
  1612. beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
  1613. rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
  1614. entry_priv->desc, TXINFO_SIZE);
  1615. rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
  1616. entry->skb->data, entry->skb->len);
  1617. /*
  1618. * Enable beaconing again.
  1619. *
  1620. * For Wi-Fi faily generated beacons between participating
  1621. * stations. Set TBTT phase adaptive adjustment step to 8us.
  1622. */
  1623. rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
  1624. rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
  1625. rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
  1626. rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
  1627. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
  1628. /*
  1629. * Clean up beacon skb.
  1630. */
  1631. dev_kfree_skb_any(entry->skb);
  1632. entry->skb = NULL;
  1633. }
  1634. static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
  1635. const enum data_queue_qid queue)
  1636. {
  1637. u32 reg;
  1638. rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
  1639. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
  1640. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
  1641. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
  1642. rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
  1643. rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
  1644. }
  1645. static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
  1646. const enum data_queue_qid qid)
  1647. {
  1648. u32 reg;
  1649. if (qid == QID_BEACON) {
  1650. rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
  1651. return;
  1652. }
  1653. rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
  1654. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE));
  1655. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK));
  1656. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI));
  1657. rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO));
  1658. rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
  1659. }
  1660. /*
  1661. * RX control handlers
  1662. */
  1663. static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
  1664. {
  1665. u8 offset = rt2x00dev->lna_gain;
  1666. u8 lna;
  1667. lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
  1668. switch (lna) {
  1669. case 3:
  1670. offset += 90;
  1671. break;
  1672. case 2:
  1673. offset += 74;
  1674. break;
  1675. case 1:
  1676. offset += 64;
  1677. break;
  1678. default:
  1679. return 0;
  1680. }
  1681. if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
  1682. if (lna == 3 || lna == 2)
  1683. offset += 10;
  1684. }
  1685. return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
  1686. }
  1687. static void rt61pci_fill_rxdone(struct queue_entry *entry,
  1688. struct rxdone_entry_desc *rxdesc)
  1689. {
  1690. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  1691. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  1692. u32 word0;
  1693. u32 word1;
  1694. rt2x00_desc_read(entry_priv->desc, 0, &word0);
  1695. rt2x00_desc_read(entry_priv->desc, 1, &word1);
  1696. if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
  1697. rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
  1698. rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
  1699. rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
  1700. if (rxdesc->cipher != CIPHER_NONE) {
  1701. _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
  1702. _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
  1703. rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
  1704. _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
  1705. rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
  1706. /*
  1707. * Hardware has stripped IV/EIV data from 802.11 frame during
  1708. * decryption. It has provided the data separately but rt2x00lib
  1709. * should decide if it should be reinserted.
  1710. */
  1711. rxdesc->flags |= RX_FLAG_IV_STRIPPED;
  1712. /*
  1713. * FIXME: Legacy driver indicates that the frame does
  1714. * contain the Michael Mic. Unfortunately, in rt2x00
  1715. * the MIC seems to be missing completely...
  1716. */
  1717. rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
  1718. if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
  1719. rxdesc->flags |= RX_FLAG_DECRYPTED;
  1720. else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
  1721. rxdesc->flags |= RX_FLAG_MMIC_ERROR;
  1722. }
  1723. /*
  1724. * Obtain the status about this packet.
  1725. * When frame was received with an OFDM bitrate,
  1726. * the signal is the PLCP value. If it was received with
  1727. * a CCK bitrate the signal is the rate in 100kbit/s.
  1728. */
  1729. rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
  1730. rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
  1731. rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
  1732. if (rt2x00_get_field32(word0, RXD_W0_OFDM))
  1733. rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
  1734. else
  1735. rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
  1736. if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
  1737. rxdesc->dev_flags |= RXDONE_MY_BSS;
  1738. }
  1739. /*
  1740. * Interrupt functions.
  1741. */
  1742. static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
  1743. {
  1744. struct data_queue *queue;
  1745. struct queue_entry *entry;
  1746. struct queue_entry *entry_done;
  1747. struct queue_entry_priv_pci *entry_priv;
  1748. struct txdone_entry_desc txdesc;
  1749. u32 word;
  1750. u32 reg;
  1751. int type;
  1752. int index;
  1753. int i;
  1754. /*
  1755. * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
  1756. * at most X times and also stop processing once the TX_STA_FIFO_VALID
  1757. * flag is not set anymore.
  1758. *
  1759. * The legacy drivers use X=TX_RING_SIZE but state in a comment
  1760. * that the TX_STA_FIFO stack has a size of 16. We stick to our
  1761. * tx ring size for now.
  1762. */
  1763. for (i = 0; i < TX_ENTRIES; i++) {
  1764. rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
  1765. if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
  1766. break;
  1767. /*
  1768. * Skip this entry when it contains an invalid
  1769. * queue identication number.
  1770. */
  1771. type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
  1772. queue = rt2x00queue_get_queue(rt2x00dev, type);
  1773. if (unlikely(!queue))
  1774. continue;
  1775. /*
  1776. * Skip this entry when it contains an invalid
  1777. * index number.
  1778. */
  1779. index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
  1780. if (unlikely(index >= queue->limit))
  1781. continue;
  1782. entry = &queue->entries[index];
  1783. entry_priv = entry->priv_data;
  1784. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1785. if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  1786. !rt2x00_get_field32(word, TXD_W0_VALID))
  1787. return;
  1788. entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
  1789. while (entry != entry_done) {
  1790. /* Catch up.
  1791. * Just report any entries we missed as failed.
  1792. */
  1793. WARNING(rt2x00dev,
  1794. "TX status report missed for entry %d\n",
  1795. entry_done->entry_idx);
  1796. txdesc.flags = 0;
  1797. __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
  1798. txdesc.retry = 0;
  1799. rt2x00lib_txdone(entry_done, &txdesc);
  1800. entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
  1801. }
  1802. /*
  1803. * Obtain the status about this packet.
  1804. */
  1805. txdesc.flags = 0;
  1806. switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
  1807. case 0: /* Success, maybe with retry */
  1808. __set_bit(TXDONE_SUCCESS, &txdesc.flags);
  1809. break;
  1810. case 6: /* Failure, excessive retries */
  1811. __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
  1812. /* Don't break, this is a failed frame! */
  1813. default: /* Failure */
  1814. __set_bit(TXDONE_FAILURE, &txdesc.flags);
  1815. }
  1816. txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
  1817. /*
  1818. * the frame was retried at least once
  1819. * -> hw used fallback rates
  1820. */
  1821. if (txdesc.retry)
  1822. __set_bit(TXDONE_FALLBACK, &txdesc.flags);
  1823. rt2x00lib_txdone(entry, &txdesc);
  1824. }
  1825. }
  1826. static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
  1827. {
  1828. struct ieee80211_conf conf = { .flags = 0 };
  1829. struct rt2x00lib_conf libconf = { .conf = &conf };
  1830. rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
  1831. }
  1832. static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
  1833. {
  1834. struct rt2x00_dev *rt2x00dev = dev_instance;
  1835. u32 reg_mcu;
  1836. u32 reg;
  1837. /*
  1838. * Get the interrupt sources & saved to local variable.
  1839. * Write register value back to clear pending interrupts.
  1840. */
  1841. rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
  1842. rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
  1843. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  1844. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  1845. if (!reg && !reg_mcu)
  1846. return IRQ_NONE;
  1847. if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  1848. return IRQ_HANDLED;
  1849. /*
  1850. * Handle interrupts, walk through all bits
  1851. * and run the tasks, the bits are checked in order of
  1852. * priority.
  1853. */
  1854. /*
  1855. * 1 - Rx ring done interrupt.
  1856. */
  1857. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
  1858. rt2x00pci_rxdone(rt2x00dev);
  1859. /*
  1860. * 2 - Tx ring done interrupt.
  1861. */
  1862. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
  1863. rt61pci_txdone(rt2x00dev);
  1864. /*
  1865. * 3 - Handle MCU command done.
  1866. */
  1867. if (reg_mcu)
  1868. rt2x00pci_register_write(rt2x00dev,
  1869. M2H_CMD_DONE_CSR, 0xffffffff);
  1870. /*
  1871. * 4 - MCU Autowakeup interrupt.
  1872. */
  1873. if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
  1874. rt61pci_wakeup(rt2x00dev);
  1875. return IRQ_HANDLED;
  1876. }
  1877. /*
  1878. * Device probe functions.
  1879. */
  1880. static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1881. {
  1882. struct eeprom_93cx6 eeprom;
  1883. u32 reg;
  1884. u16 word;
  1885. u8 *mac;
  1886. s8 value;
  1887. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  1888. eeprom.data = rt2x00dev;
  1889. eeprom.register_read = rt61pci_eepromregister_read;
  1890. eeprom.register_write = rt61pci_eepromregister_write;
  1891. eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
  1892. PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
  1893. eeprom.reg_data_in = 0;
  1894. eeprom.reg_data_out = 0;
  1895. eeprom.reg_data_clock = 0;
  1896. eeprom.reg_chip_select = 0;
  1897. eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
  1898. EEPROM_SIZE / sizeof(u16));
  1899. /*
  1900. * Start validation of the data that has been read.
  1901. */
  1902. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1903. if (!is_valid_ether_addr(mac)) {
  1904. random_ether_addr(mac);
  1905. EEPROM(rt2x00dev, "MAC: %pM\n", mac);
  1906. }
  1907. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
  1908. if (word == 0xffff) {
  1909. rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
  1910. rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
  1911. ANTENNA_B);
  1912. rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
  1913. ANTENNA_B);
  1914. rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
  1915. rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
  1916. rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
  1917. rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
  1918. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1919. EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
  1920. }
  1921. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
  1922. if (word == 0xffff) {
  1923. rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
  1924. rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
  1925. rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
  1926. rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
  1927. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
  1928. rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
  1929. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
  1930. rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
  1931. EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
  1932. }
  1933. rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
  1934. if (word == 0xffff) {
  1935. rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
  1936. LED_MODE_DEFAULT);
  1937. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
  1938. EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
  1939. }
  1940. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
  1941. if (word == 0xffff) {
  1942. rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
  1943. rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
  1944. rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
  1945. EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
  1946. }
  1947. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
  1948. if (word == 0xffff) {
  1949. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
  1950. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
  1951. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
  1952. EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
  1953. } else {
  1954. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
  1955. if (value < -10 || value > 10)
  1956. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
  1957. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
  1958. if (value < -10 || value > 10)
  1959. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
  1960. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
  1961. }
  1962. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
  1963. if (word == 0xffff) {
  1964. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
  1965. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
  1966. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
  1967. EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
  1968. } else {
  1969. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
  1970. if (value < -10 || value > 10)
  1971. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
  1972. value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
  1973. if (value < -10 || value > 10)
  1974. rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
  1975. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
  1976. }
  1977. return 0;
  1978. }
  1979. static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1980. {
  1981. u32 reg;
  1982. u16 value;
  1983. u16 eeprom;
  1984. /*
  1985. * Read EEPROM word for configuration.
  1986. */
  1987. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1988. /*
  1989. * Identify RF chipset.
  1990. */
  1991. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1992. rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
  1993. rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
  1994. value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
  1995. if (!rt2x00_rf(rt2x00dev, RF5225) &&
  1996. !rt2x00_rf(rt2x00dev, RF5325) &&
  1997. !rt2x00_rf(rt2x00dev, RF2527) &&
  1998. !rt2x00_rf(rt2x00dev, RF2529)) {
  1999. ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
  2000. return -ENODEV;
  2001. }
  2002. /*
  2003. * Determine number of antennas.
  2004. */
  2005. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
  2006. __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
  2007. /*
  2008. * Identify default antenna configuration.
  2009. */
  2010. rt2x00dev->default_ant.tx =
  2011. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
  2012. rt2x00dev->default_ant.rx =
  2013. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
  2014. /*
  2015. * Read the Frame type.
  2016. */
  2017. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
  2018. __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
  2019. /*
  2020. * Detect if this device has a hardware controlled radio.
  2021. */
  2022. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
  2023. __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
  2024. /*
  2025. * Read frequency offset and RF programming sequence.
  2026. */
  2027. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
  2028. if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
  2029. __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
  2030. rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
  2031. /*
  2032. * Read external LNA informations.
  2033. */
  2034. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  2035. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
  2036. __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
  2037. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
  2038. __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
  2039. /*
  2040. * When working with a RF2529 chip without double antenna,
  2041. * the antenna settings should be gathered from the NIC
  2042. * eeprom word.
  2043. */
  2044. if (rt2x00_rf(rt2x00dev, RF2529) &&
  2045. !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
  2046. rt2x00dev->default_ant.rx =
  2047. ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
  2048. rt2x00dev->default_ant.tx =
  2049. ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
  2050. if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
  2051. rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
  2052. if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
  2053. rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
  2054. }
  2055. /*
  2056. * Store led settings, for correct led behaviour.
  2057. * If the eeprom value is invalid,
  2058. * switch to default led mode.
  2059. */
  2060. #ifdef CONFIG_RT2X00_LIB_LEDS
  2061. rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
  2062. value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
  2063. rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
  2064. rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
  2065. if (value == LED_MODE_SIGNAL_STRENGTH)
  2066. rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
  2067. LED_TYPE_QUALITY);
  2068. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
  2069. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
  2070. rt2x00_get_field16(eeprom,
  2071. EEPROM_LED_POLARITY_GPIO_0));
  2072. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
  2073. rt2x00_get_field16(eeprom,
  2074. EEPROM_LED_POLARITY_GPIO_1));
  2075. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
  2076. rt2x00_get_field16(eeprom,
  2077. EEPROM_LED_POLARITY_GPIO_2));
  2078. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
  2079. rt2x00_get_field16(eeprom,
  2080. EEPROM_LED_POLARITY_GPIO_3));
  2081. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
  2082. rt2x00_get_field16(eeprom,
  2083. EEPROM_LED_POLARITY_GPIO_4));
  2084. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
  2085. rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
  2086. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
  2087. rt2x00_get_field16(eeprom,
  2088. EEPROM_LED_POLARITY_RDY_G));
  2089. rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
  2090. rt2x00_get_field16(eeprom,
  2091. EEPROM_LED_POLARITY_RDY_A));
  2092. #endif /* CONFIG_RT2X00_LIB_LEDS */
  2093. return 0;
  2094. }
  2095. /*
  2096. * RF value list for RF5225 & RF5325
  2097. * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
  2098. */
  2099. static const struct rf_channel rf_vals_noseq[] = {
  2100. { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
  2101. { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
  2102. { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
  2103. { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
  2104. { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
  2105. { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
  2106. { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
  2107. { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
  2108. { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
  2109. { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
  2110. { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
  2111. { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
  2112. { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
  2113. { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
  2114. /* 802.11 UNI / HyperLan 2 */
  2115. { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
  2116. { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
  2117. { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
  2118. { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
  2119. { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
  2120. { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
  2121. { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
  2122. { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
  2123. /* 802.11 HyperLan 2 */
  2124. { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
  2125. { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
  2126. { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
  2127. { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
  2128. { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
  2129. { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
  2130. { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
  2131. { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
  2132. { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
  2133. { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
  2134. /* 802.11 UNII */
  2135. { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
  2136. { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
  2137. { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
  2138. { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
  2139. { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
  2140. { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
  2141. /* MMAC(Japan)J52 ch 34,38,42,46 */
  2142. { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
  2143. { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
  2144. { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
  2145. { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
  2146. };
  2147. /*
  2148. * RF value list for RF5225 & RF5325
  2149. * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
  2150. */
  2151. static const struct rf_channel rf_vals_seq[] = {
  2152. { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
  2153. { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
  2154. { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
  2155. { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
  2156. { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
  2157. { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
  2158. { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
  2159. { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
  2160. { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
  2161. { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
  2162. { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
  2163. { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
  2164. { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
  2165. { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
  2166. /* 802.11 UNI / HyperLan 2 */
  2167. { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
  2168. { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
  2169. { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
  2170. { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
  2171. { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
  2172. { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
  2173. { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
  2174. { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
  2175. /* 802.11 HyperLan 2 */
  2176. { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
  2177. { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
  2178. { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
  2179. { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
  2180. { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
  2181. { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
  2182. { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
  2183. { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
  2184. { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
  2185. { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
  2186. /* 802.11 UNII */
  2187. { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
  2188. { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
  2189. { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
  2190. { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
  2191. { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
  2192. { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
  2193. /* MMAC(Japan)J52 ch 34,38,42,46 */
  2194. { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
  2195. { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
  2196. { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
  2197. { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
  2198. };
  2199. static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  2200. {
  2201. struct hw_mode_spec *spec = &rt2x00dev->spec;
  2202. struct channel_info *info;
  2203. char *tx_power;
  2204. unsigned int i;
  2205. /*
  2206. * Disable powersaving as default.
  2207. */
  2208. rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2209. /*
  2210. * Initialize all hw fields.
  2211. */
  2212. rt2x00dev->hw->flags =
  2213. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  2214. IEEE80211_HW_SIGNAL_DBM |
  2215. IEEE80211_HW_SUPPORTS_PS |
  2216. IEEE80211_HW_PS_NULLFUNC_STACK;
  2217. SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
  2218. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  2219. rt2x00_eeprom_addr(rt2x00dev,
  2220. EEPROM_MAC_ADDR_0));
  2221. /*
  2222. * As rt61 has a global fallback table we cannot specify
  2223. * more then one tx rate per frame but since the hw will
  2224. * try several rates (based on the fallback table) we should
  2225. * still initialize max_rates to the maximum number of rates
  2226. * we are going to try. Otherwise mac80211 will truncate our
  2227. * reported tx rates and the rc algortihm will end up with
  2228. * incorrect data.
  2229. */
  2230. rt2x00dev->hw->max_rates = 7;
  2231. rt2x00dev->hw->max_rate_tries = 1;
  2232. /*
  2233. * Initialize hw_mode information.
  2234. */
  2235. spec->supported_bands = SUPPORT_BAND_2GHZ;
  2236. spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
  2237. if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
  2238. spec->num_channels = 14;
  2239. spec->channels = rf_vals_noseq;
  2240. } else {
  2241. spec->num_channels = 14;
  2242. spec->channels = rf_vals_seq;
  2243. }
  2244. if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
  2245. spec->supported_bands |= SUPPORT_BAND_5GHZ;
  2246. spec->num_channels = ARRAY_SIZE(rf_vals_seq);
  2247. }
  2248. /*
  2249. * Create channel information array
  2250. */
  2251. info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
  2252. if (!info)
  2253. return -ENOMEM;
  2254. spec->channels_info = info;
  2255. tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
  2256. for (i = 0; i < 14; i++)
  2257. info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
  2258. if (spec->num_channels > 14) {
  2259. tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
  2260. for (i = 14; i < spec->num_channels; i++)
  2261. info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
  2262. }
  2263. return 0;
  2264. }
  2265. static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
  2266. {
  2267. int retval;
  2268. /*
  2269. * Disable power saving.
  2270. */
  2271. rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
  2272. /*
  2273. * Allocate eeprom data.
  2274. */
  2275. retval = rt61pci_validate_eeprom(rt2x00dev);
  2276. if (retval)
  2277. return retval;
  2278. retval = rt61pci_init_eeprom(rt2x00dev);
  2279. if (retval)
  2280. return retval;
  2281. /*
  2282. * Initialize hw specifications.
  2283. */
  2284. retval = rt61pci_probe_hw_mode(rt2x00dev);
  2285. if (retval)
  2286. return retval;
  2287. /*
  2288. * This device has multiple filters for control frames,
  2289. * but has no a separate filter for PS Poll frames.
  2290. */
  2291. __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
  2292. /*
  2293. * This device requires firmware and DMA mapped skbs.
  2294. */
  2295. __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
  2296. __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
  2297. if (!modparam_nohwcrypt)
  2298. __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
  2299. /*
  2300. * Set the rssi offset.
  2301. */
  2302. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  2303. return 0;
  2304. }
  2305. /*
  2306. * IEEE80211 stack callback functions.
  2307. */
  2308. static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
  2309. const struct ieee80211_tx_queue_params *params)
  2310. {
  2311. struct rt2x00_dev *rt2x00dev = hw->priv;
  2312. struct data_queue *queue;
  2313. struct rt2x00_field32 field;
  2314. int retval;
  2315. u32 reg;
  2316. u32 offset;
  2317. /*
  2318. * First pass the configuration through rt2x00lib, that will
  2319. * update the queue settings and validate the input. After that
  2320. * we are free to update the registers based on the value
  2321. * in the queue parameter.
  2322. */
  2323. retval = rt2x00mac_conf_tx(hw, queue_idx, params);
  2324. if (retval)
  2325. return retval;
  2326. /*
  2327. * We only need to perform additional register initialization
  2328. * for WMM queues.
  2329. */
  2330. if (queue_idx >= 4)
  2331. return 0;
  2332. queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
  2333. /* Update WMM TXOP register */
  2334. offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
  2335. field.bit_offset = (queue_idx & 1) * 16;
  2336. field.bit_mask = 0xffff << field.bit_offset;
  2337. rt2x00pci_register_read(rt2x00dev, offset, &reg);
  2338. rt2x00_set_field32(&reg, field, queue->txop);
  2339. rt2x00pci_register_write(rt2x00dev, offset, reg);
  2340. /* Update WMM registers */
  2341. field.bit_offset = queue_idx * 4;
  2342. field.bit_mask = 0xf << field.bit_offset;
  2343. rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
  2344. rt2x00_set_field32(&reg, field, queue->aifs);
  2345. rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
  2346. rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
  2347. rt2x00_set_field32(&reg, field, queue->cw_min);
  2348. rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
  2349. rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
  2350. rt2x00_set_field32(&reg, field, queue->cw_max);
  2351. rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
  2352. return 0;
  2353. }
  2354. static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
  2355. {
  2356. struct rt2x00_dev *rt2x00dev = hw->priv;
  2357. u64 tsf;
  2358. u32 reg;
  2359. rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
  2360. tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
  2361. rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
  2362. tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
  2363. return tsf;
  2364. }
  2365. static const struct ieee80211_ops rt61pci_mac80211_ops = {
  2366. .tx = rt2x00mac_tx,
  2367. .start = rt2x00mac_start,
  2368. .stop = rt2x00mac_stop,
  2369. .add_interface = rt2x00mac_add_interface,
  2370. .remove_interface = rt2x00mac_remove_interface,
  2371. .config = rt2x00mac_config,
  2372. .configure_filter = rt2x00mac_configure_filter,
  2373. .set_tim = rt2x00mac_set_tim,
  2374. .set_key = rt2x00mac_set_key,
  2375. .get_stats = rt2x00mac_get_stats,
  2376. .bss_info_changed = rt2x00mac_bss_info_changed,
  2377. .conf_tx = rt61pci_conf_tx,
  2378. .get_tsf = rt61pci_get_tsf,
  2379. .rfkill_poll = rt2x00mac_rfkill_poll,
  2380. };
  2381. static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
  2382. .irq_handler = rt61pci_interrupt,
  2383. .probe_hw = rt61pci_probe_hw,
  2384. .get_firmware_name = rt61pci_get_firmware_name,
  2385. .check_firmware = rt61pci_check_firmware,
  2386. .load_firmware = rt61pci_load_firmware,
  2387. .initialize = rt2x00pci_initialize,
  2388. .uninitialize = rt2x00pci_uninitialize,
  2389. .get_entry_state = rt61pci_get_entry_state,
  2390. .clear_entry = rt61pci_clear_entry,
  2391. .set_device_state = rt61pci_set_device_state,
  2392. .rfkill_poll = rt61pci_rfkill_poll,
  2393. .link_stats = rt61pci_link_stats,
  2394. .reset_tuner = rt61pci_reset_tuner,
  2395. .link_tuner = rt61pci_link_tuner,
  2396. .write_tx_desc = rt61pci_write_tx_desc,
  2397. .write_beacon = rt61pci_write_beacon,
  2398. .kick_tx_queue = rt61pci_kick_tx_queue,
  2399. .kill_tx_queue = rt61pci_kill_tx_queue,
  2400. .fill_rxdone = rt61pci_fill_rxdone,
  2401. .config_shared_key = rt61pci_config_shared_key,
  2402. .config_pairwise_key = rt61pci_config_pairwise_key,
  2403. .config_filter = rt61pci_config_filter,
  2404. .config_intf = rt61pci_config_intf,
  2405. .config_erp = rt61pci_config_erp,
  2406. .config_ant = rt61pci_config_ant,
  2407. .config = rt61pci_config,
  2408. };
  2409. static const struct data_queue_desc rt61pci_queue_rx = {
  2410. .entry_num = RX_ENTRIES,
  2411. .data_size = DATA_FRAME_SIZE,
  2412. .desc_size = RXD_DESC_SIZE,
  2413. .priv_size = sizeof(struct queue_entry_priv_pci),
  2414. };
  2415. static const struct data_queue_desc rt61pci_queue_tx = {
  2416. .entry_num = TX_ENTRIES,
  2417. .data_size = DATA_FRAME_SIZE,
  2418. .desc_size = TXD_DESC_SIZE,
  2419. .priv_size = sizeof(struct queue_entry_priv_pci),
  2420. };
  2421. static const struct data_queue_desc rt61pci_queue_bcn = {
  2422. .entry_num = 4 * BEACON_ENTRIES,
  2423. .data_size = 0, /* No DMA required for beacons */
  2424. .desc_size = TXINFO_SIZE,
  2425. .priv_size = sizeof(struct queue_entry_priv_pci),
  2426. };
  2427. static const struct rt2x00_ops rt61pci_ops = {
  2428. .name = KBUILD_MODNAME,
  2429. .max_sta_intf = 1,
  2430. .max_ap_intf = 4,
  2431. .eeprom_size = EEPROM_SIZE,
  2432. .rf_size = RF_SIZE,
  2433. .tx_queues = NUM_TX_QUEUES,
  2434. .extra_tx_headroom = 0,
  2435. .rx = &rt61pci_queue_rx,
  2436. .tx = &rt61pci_queue_tx,
  2437. .bcn = &rt61pci_queue_bcn,
  2438. .lib = &rt61pci_rt2x00_ops,
  2439. .hw = &rt61pci_mac80211_ops,
  2440. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  2441. .debugfs = &rt61pci_rt2x00debug,
  2442. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  2443. };
  2444. /*
  2445. * RT61pci module information.
  2446. */
  2447. static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
  2448. /* RT2561s */
  2449. { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
  2450. /* RT2561 v2 */
  2451. { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
  2452. /* RT2661 */
  2453. { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
  2454. { 0, }
  2455. };
  2456. MODULE_AUTHOR(DRV_PROJECT);
  2457. MODULE_VERSION(DRV_VERSION);
  2458. MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
  2459. MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
  2460. "PCI & PCMCIA chipset based cards");
  2461. MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
  2462. MODULE_FIRMWARE(FIRMWARE_RT2561);
  2463. MODULE_FIRMWARE(FIRMWARE_RT2561s);
  2464. MODULE_FIRMWARE(FIRMWARE_RT2661);
  2465. MODULE_LICENSE("GPL");
  2466. static struct pci_driver rt61pci_driver = {
  2467. .name = KBUILD_MODNAME,
  2468. .id_table = rt61pci_device_table,
  2469. .probe = rt2x00pci_probe,
  2470. .remove = __devexit_p(rt2x00pci_remove),
  2471. .suspend = rt2x00pci_suspend,
  2472. .resume = rt2x00pci_resume,
  2473. };
  2474. static int __init rt61pci_init(void)
  2475. {
  2476. return pci_register_driver(&rt61pci_driver);
  2477. }
  2478. static void __exit rt61pci_exit(void)
  2479. {
  2480. pci_unregister_driver(&rt61pci_driver);
  2481. }
  2482. module_init(rt61pci_init);
  2483. module_exit(rt61pci_exit);