rt2x00pci.c 8.3 KB

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  1. /*
  2. Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2x00pci
  19. Abstract: rt2x00 generic pci device routines.
  20. */
  21. #include <linux/dma-mapping.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/pci.h>
  25. #include <linux/slab.h>
  26. #include "rt2x00.h"
  27. #include "rt2x00pci.h"
  28. /*
  29. * Register access.
  30. */
  31. int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,
  32. const unsigned int offset,
  33. const struct rt2x00_field32 field,
  34. u32 *reg)
  35. {
  36. unsigned int i;
  37. if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
  38. return 0;
  39. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  40. rt2x00pci_register_read(rt2x00dev, offset, reg);
  41. if (!rt2x00_get_field32(*reg, field))
  42. return 1;
  43. udelay(REGISTER_BUSY_DELAY);
  44. }
  45. ERROR(rt2x00dev, "Indirect register access failed: "
  46. "offset=0x%.08x, value=0x%.08x\n", offset, *reg);
  47. *reg = ~0;
  48. return 0;
  49. }
  50. EXPORT_SYMBOL_GPL(rt2x00pci_regbusy_read);
  51. void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
  52. {
  53. struct data_queue *queue = rt2x00dev->rx;
  54. struct queue_entry *entry;
  55. struct queue_entry_priv_pci *entry_priv;
  56. struct skb_frame_desc *skbdesc;
  57. while (1) {
  58. entry = rt2x00queue_get_entry(queue, Q_INDEX);
  59. entry_priv = entry->priv_data;
  60. if (rt2x00dev->ops->lib->get_entry_state(entry))
  61. break;
  62. /*
  63. * Fill in desc fields of the skb descriptor
  64. */
  65. skbdesc = get_skb_frame_desc(entry->skb);
  66. skbdesc->desc = entry_priv->desc;
  67. skbdesc->desc_len = entry->queue->desc_size;
  68. /*
  69. * Send the frame to rt2x00lib for further processing.
  70. */
  71. rt2x00lib_rxdone(rt2x00dev, entry);
  72. }
  73. }
  74. EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
  75. /*
  76. * Device initialization handlers.
  77. */
  78. static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
  79. struct data_queue *queue)
  80. {
  81. struct queue_entry_priv_pci *entry_priv;
  82. void *addr;
  83. dma_addr_t dma;
  84. unsigned int i;
  85. /*
  86. * Allocate DMA memory for descriptor and buffer.
  87. */
  88. addr = dma_alloc_coherent(rt2x00dev->dev,
  89. queue->limit * queue->desc_size,
  90. &dma, GFP_KERNEL | GFP_DMA);
  91. if (!addr)
  92. return -ENOMEM;
  93. memset(addr, 0, queue->limit * queue->desc_size);
  94. /*
  95. * Initialize all queue entries to contain valid addresses.
  96. */
  97. for (i = 0; i < queue->limit; i++) {
  98. entry_priv = queue->entries[i].priv_data;
  99. entry_priv->desc = addr + i * queue->desc_size;
  100. entry_priv->desc_dma = dma + i * queue->desc_size;
  101. }
  102. return 0;
  103. }
  104. static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
  105. struct data_queue *queue)
  106. {
  107. struct queue_entry_priv_pci *entry_priv =
  108. queue->entries[0].priv_data;
  109. if (entry_priv->desc)
  110. dma_free_coherent(rt2x00dev->dev,
  111. queue->limit * queue->desc_size,
  112. entry_priv->desc, entry_priv->desc_dma);
  113. entry_priv->desc = NULL;
  114. }
  115. int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
  116. {
  117. struct data_queue *queue;
  118. int status;
  119. /*
  120. * Allocate DMA
  121. */
  122. queue_for_each(rt2x00dev, queue) {
  123. status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);
  124. if (status)
  125. goto exit;
  126. }
  127. /*
  128. * Register interrupt handler.
  129. */
  130. status = request_irq(rt2x00dev->irq, rt2x00dev->ops->lib->irq_handler,
  131. IRQF_SHARED, rt2x00dev->name, rt2x00dev);
  132. if (status) {
  133. ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
  134. rt2x00dev->irq, status);
  135. goto exit;
  136. }
  137. return 0;
  138. exit:
  139. queue_for_each(rt2x00dev, queue)
  140. rt2x00pci_free_queue_dma(rt2x00dev, queue);
  141. return status;
  142. }
  143. EXPORT_SYMBOL_GPL(rt2x00pci_initialize);
  144. void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
  145. {
  146. struct data_queue *queue;
  147. /*
  148. * Free irq line.
  149. */
  150. free_irq(rt2x00dev->irq, rt2x00dev);
  151. /*
  152. * Free DMA
  153. */
  154. queue_for_each(rt2x00dev, queue)
  155. rt2x00pci_free_queue_dma(rt2x00dev, queue);
  156. }
  157. EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
  158. /*
  159. * PCI driver handlers.
  160. */
  161. static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
  162. {
  163. kfree(rt2x00dev->rf);
  164. rt2x00dev->rf = NULL;
  165. kfree(rt2x00dev->eeprom);
  166. rt2x00dev->eeprom = NULL;
  167. if (rt2x00dev->csr.base) {
  168. iounmap(rt2x00dev->csr.base);
  169. rt2x00dev->csr.base = NULL;
  170. }
  171. }
  172. static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
  173. {
  174. struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);
  175. rt2x00dev->csr.base = pci_ioremap_bar(pci_dev, 0);
  176. if (!rt2x00dev->csr.base)
  177. goto exit;
  178. rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
  179. if (!rt2x00dev->eeprom)
  180. goto exit;
  181. rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
  182. if (!rt2x00dev->rf)
  183. goto exit;
  184. return 0;
  185. exit:
  186. ERROR_PROBE("Failed to allocate registers.\n");
  187. rt2x00pci_free_reg(rt2x00dev);
  188. return -ENOMEM;
  189. }
  190. int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  191. {
  192. struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_data;
  193. struct ieee80211_hw *hw;
  194. struct rt2x00_dev *rt2x00dev;
  195. int retval;
  196. retval = pci_request_regions(pci_dev, pci_name(pci_dev));
  197. if (retval) {
  198. ERROR_PROBE("PCI request regions failed.\n");
  199. return retval;
  200. }
  201. retval = pci_enable_device(pci_dev);
  202. if (retval) {
  203. ERROR_PROBE("Enable device failed.\n");
  204. goto exit_release_regions;
  205. }
  206. pci_set_master(pci_dev);
  207. if (pci_set_mwi(pci_dev))
  208. ERROR_PROBE("MWI not available.\n");
  209. if (dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) {
  210. ERROR_PROBE("PCI DMA not supported.\n");
  211. retval = -EIO;
  212. goto exit_disable_device;
  213. }
  214. hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
  215. if (!hw) {
  216. ERROR_PROBE("Failed to allocate hardware.\n");
  217. retval = -ENOMEM;
  218. goto exit_disable_device;
  219. }
  220. pci_set_drvdata(pci_dev, hw);
  221. rt2x00dev = hw->priv;
  222. rt2x00dev->dev = &pci_dev->dev;
  223. rt2x00dev->ops = ops;
  224. rt2x00dev->hw = hw;
  225. rt2x00dev->irq = pci_dev->irq;
  226. rt2x00dev->name = pci_name(pci_dev);
  227. if (pci_dev->is_pcie)
  228. rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE);
  229. else
  230. rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
  231. retval = rt2x00pci_alloc_reg(rt2x00dev);
  232. if (retval)
  233. goto exit_free_device;
  234. retval = rt2x00lib_probe_dev(rt2x00dev);
  235. if (retval)
  236. goto exit_free_reg;
  237. return 0;
  238. exit_free_reg:
  239. rt2x00pci_free_reg(rt2x00dev);
  240. exit_free_device:
  241. ieee80211_free_hw(hw);
  242. exit_disable_device:
  243. if (retval != -EBUSY)
  244. pci_disable_device(pci_dev);
  245. exit_release_regions:
  246. pci_release_regions(pci_dev);
  247. pci_set_drvdata(pci_dev, NULL);
  248. return retval;
  249. }
  250. EXPORT_SYMBOL_GPL(rt2x00pci_probe);
  251. void rt2x00pci_remove(struct pci_dev *pci_dev)
  252. {
  253. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  254. struct rt2x00_dev *rt2x00dev = hw->priv;
  255. /*
  256. * Free all allocated data.
  257. */
  258. rt2x00lib_remove_dev(rt2x00dev);
  259. rt2x00pci_free_reg(rt2x00dev);
  260. ieee80211_free_hw(hw);
  261. /*
  262. * Free the PCI device data.
  263. */
  264. pci_set_drvdata(pci_dev, NULL);
  265. pci_disable_device(pci_dev);
  266. pci_release_regions(pci_dev);
  267. }
  268. EXPORT_SYMBOL_GPL(rt2x00pci_remove);
  269. #ifdef CONFIG_PM
  270. int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
  271. {
  272. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  273. struct rt2x00_dev *rt2x00dev = hw->priv;
  274. int retval;
  275. retval = rt2x00lib_suspend(rt2x00dev, state);
  276. if (retval)
  277. return retval;
  278. pci_save_state(pci_dev);
  279. pci_disable_device(pci_dev);
  280. return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
  281. }
  282. EXPORT_SYMBOL_GPL(rt2x00pci_suspend);
  283. int rt2x00pci_resume(struct pci_dev *pci_dev)
  284. {
  285. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  286. struct rt2x00_dev *rt2x00dev = hw->priv;
  287. if (pci_set_power_state(pci_dev, PCI_D0) ||
  288. pci_enable_device(pci_dev) ||
  289. pci_restore_state(pci_dev)) {
  290. ERROR(rt2x00dev, "Failed to resume device.\n");
  291. return -EIO;
  292. }
  293. return rt2x00lib_resume(rt2x00dev);
  294. }
  295. EXPORT_SYMBOL_GPL(rt2x00pci_resume);
  296. #endif /* CONFIG_PM */
  297. /*
  298. * rt2x00pci module information.
  299. */
  300. MODULE_AUTHOR(DRV_PROJECT);
  301. MODULE_VERSION(DRV_VERSION);
  302. MODULE_DESCRIPTION("rt2x00 pci library");
  303. MODULE_LICENSE("GPL");