rt2800lib.c 92 KB

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  1. /*
  2. Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
  3. Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
  4. Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
  5. Based on the original rt2800pci.c and rt2800usb.c.
  6. Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
  7. Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  8. Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  9. Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  10. Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  11. Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  12. <http://rt2x00.serialmonkey.com>
  13. This program is free software; you can redistribute it and/or modify
  14. it under the terms of the GNU General Public License as published by
  15. the Free Software Foundation; either version 2 of the License, or
  16. (at your option) any later version.
  17. This program is distributed in the hope that it will be useful,
  18. but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. GNU General Public License for more details.
  21. You should have received a copy of the GNU General Public License
  22. along with this program; if not, write to the
  23. Free Software Foundation, Inc.,
  24. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  25. */
  26. /*
  27. Module: rt2800lib
  28. Abstract: rt2800 generic device routines.
  29. */
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/slab.h>
  33. #include "rt2x00.h"
  34. #include "rt2800lib.h"
  35. #include "rt2800.h"
  36. /*
  37. * Register access.
  38. * All access to the CSR registers will go through the methods
  39. * rt2800_register_read and rt2800_register_write.
  40. * BBP and RF register require indirect register access,
  41. * and use the CSR registers BBPCSR and RFCSR to achieve this.
  42. * These indirect registers work with busy bits,
  43. * and we will try maximal REGISTER_BUSY_COUNT times to access
  44. * the register while taking a REGISTER_BUSY_DELAY us delay
  45. * between each attampt. When the busy bit is still set at that time,
  46. * the access attempt is considered to have failed,
  47. * and we will print an error.
  48. * The _lock versions must be used if you already hold the csr_mutex
  49. */
  50. #define WAIT_FOR_BBP(__dev, __reg) \
  51. rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  52. #define WAIT_FOR_RFCSR(__dev, __reg) \
  53. rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  54. #define WAIT_FOR_RF(__dev, __reg) \
  55. rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  56. #define WAIT_FOR_MCU(__dev, __reg) \
  57. rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  58. H2M_MAILBOX_CSR_OWNER, (__reg))
  59. static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  60. {
  61. /* check for rt2872 on SoC */
  62. if (!rt2x00_is_soc(rt2x00dev) ||
  63. !rt2x00_rt(rt2x00dev, RT2872))
  64. return false;
  65. /* we know for sure that these rf chipsets are used on rt305x boards */
  66. if (rt2x00_rf(rt2x00dev, RF3020) ||
  67. rt2x00_rf(rt2x00dev, RF3021) ||
  68. rt2x00_rf(rt2x00dev, RF3022))
  69. return true;
  70. NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  71. return false;
  72. }
  73. static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  74. const unsigned int word, const u8 value)
  75. {
  76. u32 reg;
  77. mutex_lock(&rt2x00dev->csr_mutex);
  78. /*
  79. * Wait until the BBP becomes available, afterwards we
  80. * can safely write the new data into the register.
  81. */
  82. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  83. reg = 0;
  84. rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  85. rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  86. rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  87. rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  88. if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  89. rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  90. rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  91. }
  92. mutex_unlock(&rt2x00dev->csr_mutex);
  93. }
  94. static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
  95. const unsigned int word, u8 *value)
  96. {
  97. u32 reg;
  98. mutex_lock(&rt2x00dev->csr_mutex);
  99. /*
  100. * Wait until the BBP becomes available, afterwards we
  101. * can safely write the read request into the register.
  102. * After the data has been written, we wait until hardware
  103. * returns the correct value, if at any time the register
  104. * doesn't become available in time, reg will be 0xffffffff
  105. * which means we return 0xff to the caller.
  106. */
  107. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  108. reg = 0;
  109. rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  110. rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  111. rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
  112. if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  113. rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  114. rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  115. WAIT_FOR_BBP(rt2x00dev, &reg);
  116. }
  117. *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
  118. mutex_unlock(&rt2x00dev->csr_mutex);
  119. }
  120. static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
  121. const unsigned int word, const u8 value)
  122. {
  123. u32 reg;
  124. mutex_lock(&rt2x00dev->csr_mutex);
  125. /*
  126. * Wait until the RFCSR becomes available, afterwards we
  127. * can safely write the new data into the register.
  128. */
  129. if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  130. reg = 0;
  131. rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
  132. rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  133. rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
  134. rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  135. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  136. }
  137. mutex_unlock(&rt2x00dev->csr_mutex);
  138. }
  139. static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
  140. const unsigned int word, u8 *value)
  141. {
  142. u32 reg;
  143. mutex_lock(&rt2x00dev->csr_mutex);
  144. /*
  145. * Wait until the RFCSR becomes available, afterwards we
  146. * can safely write the read request into the register.
  147. * After the data has been written, we wait until hardware
  148. * returns the correct value, if at any time the register
  149. * doesn't become available in time, reg will be 0xffffffff
  150. * which means we return 0xff to the caller.
  151. */
  152. if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  153. reg = 0;
  154. rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  155. rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
  156. rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  157. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  158. WAIT_FOR_RFCSR(rt2x00dev, &reg);
  159. }
  160. *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
  161. mutex_unlock(&rt2x00dev->csr_mutex);
  162. }
  163. static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
  164. const unsigned int word, const u32 value)
  165. {
  166. u32 reg;
  167. mutex_lock(&rt2x00dev->csr_mutex);
  168. /*
  169. * Wait until the RF becomes available, afterwards we
  170. * can safely write the new data into the register.
  171. */
  172. if (WAIT_FOR_RF(rt2x00dev, &reg)) {
  173. reg = 0;
  174. rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
  175. rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
  176. rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
  177. rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
  178. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
  179. rt2x00_rf_write(rt2x00dev, word, value);
  180. }
  181. mutex_unlock(&rt2x00dev->csr_mutex);
  182. }
  183. void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
  184. const u8 command, const u8 token,
  185. const u8 arg0, const u8 arg1)
  186. {
  187. u32 reg;
  188. /*
  189. * SOC devices don't support MCU requests.
  190. */
  191. if (rt2x00_is_soc(rt2x00dev))
  192. return;
  193. mutex_lock(&rt2x00dev->csr_mutex);
  194. /*
  195. * Wait until the MCU becomes available, afterwards we
  196. * can safely write the new data into the register.
  197. */
  198. if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
  199. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
  200. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
  201. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
  202. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
  203. rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
  204. reg = 0;
  205. rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
  206. rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
  207. }
  208. mutex_unlock(&rt2x00dev->csr_mutex);
  209. }
  210. EXPORT_SYMBOL_GPL(rt2800_mcu_request);
  211. int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
  212. {
  213. unsigned int i;
  214. u32 reg;
  215. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  216. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  217. if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
  218. !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
  219. return 0;
  220. msleep(1);
  221. }
  222. ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
  223. return -EACCES;
  224. }
  225. EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
  226. void rt2800_write_txwi(__le32 *txwi, struct txentry_desc *txdesc)
  227. {
  228. u32 word;
  229. /*
  230. * Initialize TX Info descriptor
  231. */
  232. rt2x00_desc_read(txwi, 0, &word);
  233. rt2x00_set_field32(&word, TXWI_W0_FRAG,
  234. test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  235. rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
  236. rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
  237. rt2x00_set_field32(&word, TXWI_W0_TS,
  238. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
  239. rt2x00_set_field32(&word, TXWI_W0_AMPDU,
  240. test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
  241. rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
  242. rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
  243. rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
  244. rt2x00_set_field32(&word, TXWI_W0_BW,
  245. test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
  246. rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
  247. test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
  248. rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
  249. rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
  250. rt2x00_desc_write(txwi, 0, word);
  251. rt2x00_desc_read(txwi, 1, &word);
  252. rt2x00_set_field32(&word, TXWI_W1_ACK,
  253. test_bit(ENTRY_TXD_ACK, &txdesc->flags));
  254. rt2x00_set_field32(&word, TXWI_W1_NSEQ,
  255. test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
  256. rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
  257. rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
  258. test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
  259. txdesc->key_idx : 0xff);
  260. rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
  261. txdesc->length);
  262. rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
  263. rt2x00_desc_write(txwi, 1, word);
  264. /*
  265. * Always write 0 to IV/EIV fields, hardware will insert the IV
  266. * from the IVEIV register when TXD_W3_WIV is set to 0.
  267. * When TXD_W3_WIV is set to 1 it will use the IV data
  268. * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
  269. * crypto entry in the registers should be used to encrypt the frame.
  270. */
  271. _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
  272. _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
  273. }
  274. EXPORT_SYMBOL_GPL(rt2800_write_txwi);
  275. void rt2800_process_rxwi(struct sk_buff *skb, struct rxdone_entry_desc *rxdesc)
  276. {
  277. __le32 *rxwi = (__le32 *) skb->data;
  278. u32 word;
  279. rt2x00_desc_read(rxwi, 0, &word);
  280. rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
  281. rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
  282. rt2x00_desc_read(rxwi, 1, &word);
  283. if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
  284. rxdesc->flags |= RX_FLAG_SHORT_GI;
  285. if (rt2x00_get_field32(word, RXWI_W1_BW))
  286. rxdesc->flags |= RX_FLAG_40MHZ;
  287. /*
  288. * Detect RX rate, always use MCS as signal type.
  289. */
  290. rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
  291. rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
  292. rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
  293. /*
  294. * Mask of 0x8 bit to remove the short preamble flag.
  295. */
  296. if (rxdesc->rate_mode == RATE_MODE_CCK)
  297. rxdesc->signal &= ~0x8;
  298. rt2x00_desc_read(rxwi, 2, &word);
  299. rxdesc->rssi =
  300. (rt2x00_get_field32(word, RXWI_W2_RSSI0) +
  301. rt2x00_get_field32(word, RXWI_W2_RSSI1)) / 2;
  302. /*
  303. * Remove RXWI descriptor from start of buffer.
  304. */
  305. skb_pull(skb, RXWI_DESC_SIZE);
  306. }
  307. EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
  308. void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
  309. {
  310. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  311. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  312. unsigned int beacon_base;
  313. u32 reg;
  314. /*
  315. * Disable beaconing while we are reloading the beacon data,
  316. * otherwise we might be sending out invalid data.
  317. */
  318. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  319. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
  320. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  321. /*
  322. * Add space for the TXWI in front of the skb.
  323. */
  324. skb_push(entry->skb, TXWI_DESC_SIZE);
  325. memset(entry->skb, 0, TXWI_DESC_SIZE);
  326. /*
  327. * Register descriptor details in skb frame descriptor.
  328. */
  329. skbdesc->flags |= SKBDESC_DESC_IN_SKB;
  330. skbdesc->desc = entry->skb->data;
  331. skbdesc->desc_len = TXWI_DESC_SIZE;
  332. /*
  333. * Add the TXWI for the beacon to the skb.
  334. */
  335. rt2800_write_txwi((__le32 *)entry->skb->data, txdesc);
  336. /*
  337. * Dump beacon to userspace through debugfs.
  338. */
  339. rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
  340. /*
  341. * Write entire beacon with TXWI to register.
  342. */
  343. beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
  344. rt2800_register_multiwrite(rt2x00dev, beacon_base,
  345. entry->skb->data, entry->skb->len);
  346. /*
  347. * Enable beaconing again.
  348. */
  349. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
  350. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
  351. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
  352. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  353. /*
  354. * Clean up beacon skb.
  355. */
  356. dev_kfree_skb_any(entry->skb);
  357. entry->skb = NULL;
  358. }
  359. EXPORT_SYMBOL(rt2800_write_beacon);
  360. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  361. const struct rt2x00debug rt2800_rt2x00debug = {
  362. .owner = THIS_MODULE,
  363. .csr = {
  364. .read = rt2800_register_read,
  365. .write = rt2800_register_write,
  366. .flags = RT2X00DEBUGFS_OFFSET,
  367. .word_base = CSR_REG_BASE,
  368. .word_size = sizeof(u32),
  369. .word_count = CSR_REG_SIZE / sizeof(u32),
  370. },
  371. .eeprom = {
  372. .read = rt2x00_eeprom_read,
  373. .write = rt2x00_eeprom_write,
  374. .word_base = EEPROM_BASE,
  375. .word_size = sizeof(u16),
  376. .word_count = EEPROM_SIZE / sizeof(u16),
  377. },
  378. .bbp = {
  379. .read = rt2800_bbp_read,
  380. .write = rt2800_bbp_write,
  381. .word_base = BBP_BASE,
  382. .word_size = sizeof(u8),
  383. .word_count = BBP_SIZE / sizeof(u8),
  384. },
  385. .rf = {
  386. .read = rt2x00_rf_read,
  387. .write = rt2800_rf_write,
  388. .word_base = RF_BASE,
  389. .word_size = sizeof(u32),
  390. .word_count = RF_SIZE / sizeof(u32),
  391. },
  392. };
  393. EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
  394. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  395. int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  396. {
  397. u32 reg;
  398. rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
  399. return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
  400. }
  401. EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
  402. #ifdef CONFIG_RT2X00_LIB_LEDS
  403. static void rt2800_brightness_set(struct led_classdev *led_cdev,
  404. enum led_brightness brightness)
  405. {
  406. struct rt2x00_led *led =
  407. container_of(led_cdev, struct rt2x00_led, led_dev);
  408. unsigned int enabled = brightness != LED_OFF;
  409. unsigned int bg_mode =
  410. (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
  411. unsigned int polarity =
  412. rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
  413. EEPROM_FREQ_LED_POLARITY);
  414. unsigned int ledmode =
  415. rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
  416. EEPROM_FREQ_LED_MODE);
  417. if (led->type == LED_TYPE_RADIO) {
  418. rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
  419. enabled ? 0x20 : 0);
  420. } else if (led->type == LED_TYPE_ASSOC) {
  421. rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
  422. enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
  423. } else if (led->type == LED_TYPE_QUALITY) {
  424. /*
  425. * The brightness is divided into 6 levels (0 - 5),
  426. * The specs tell us the following levels:
  427. * 0, 1 ,3, 7, 15, 31
  428. * to determine the level in a simple way we can simply
  429. * work with bitshifting:
  430. * (1 << level) - 1
  431. */
  432. rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
  433. (1 << brightness / (LED_FULL / 6)) - 1,
  434. polarity);
  435. }
  436. }
  437. static int rt2800_blink_set(struct led_classdev *led_cdev,
  438. unsigned long *delay_on, unsigned long *delay_off)
  439. {
  440. struct rt2x00_led *led =
  441. container_of(led_cdev, struct rt2x00_led, led_dev);
  442. u32 reg;
  443. rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
  444. rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
  445. rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
  446. rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
  447. return 0;
  448. }
  449. static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
  450. struct rt2x00_led *led, enum led_type type)
  451. {
  452. led->rt2x00dev = rt2x00dev;
  453. led->type = type;
  454. led->led_dev.brightness_set = rt2800_brightness_set;
  455. led->led_dev.blink_set = rt2800_blink_set;
  456. led->flags = LED_INITIALIZED;
  457. }
  458. #endif /* CONFIG_RT2X00_LIB_LEDS */
  459. /*
  460. * Configuration handlers.
  461. */
  462. static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
  463. struct rt2x00lib_crypto *crypto,
  464. struct ieee80211_key_conf *key)
  465. {
  466. struct mac_wcid_entry wcid_entry;
  467. struct mac_iveiv_entry iveiv_entry;
  468. u32 offset;
  469. u32 reg;
  470. offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
  471. if (crypto->cmd == SET_KEY) {
  472. rt2800_register_read(rt2x00dev, offset, &reg);
  473. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
  474. !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
  475. /*
  476. * Both the cipher as the BSS Idx numbers are split in a main
  477. * value of 3 bits, and a extended field for adding one additional
  478. * bit to the value.
  479. */
  480. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
  481. (crypto->cipher & 0x7));
  482. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
  483. (crypto->cipher & 0x8) >> 3);
  484. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
  485. (crypto->bssidx & 0x7));
  486. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
  487. (crypto->bssidx & 0x8) >> 3);
  488. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
  489. rt2800_register_write(rt2x00dev, offset, reg);
  490. } else {
  491. rt2800_register_write(rt2x00dev, offset, 0);
  492. }
  493. offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
  494. memset(&iveiv_entry, 0, sizeof(iveiv_entry));
  495. if ((crypto->cipher == CIPHER_TKIP) ||
  496. (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
  497. (crypto->cipher == CIPHER_AES))
  498. iveiv_entry.iv[3] |= 0x20;
  499. iveiv_entry.iv[3] |= key->keyidx << 6;
  500. rt2800_register_multiwrite(rt2x00dev, offset,
  501. &iveiv_entry, sizeof(iveiv_entry));
  502. offset = MAC_WCID_ENTRY(key->hw_key_idx);
  503. memset(&wcid_entry, 0, sizeof(wcid_entry));
  504. if (crypto->cmd == SET_KEY)
  505. memcpy(&wcid_entry, crypto->address, ETH_ALEN);
  506. rt2800_register_multiwrite(rt2x00dev, offset,
  507. &wcid_entry, sizeof(wcid_entry));
  508. }
  509. int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
  510. struct rt2x00lib_crypto *crypto,
  511. struct ieee80211_key_conf *key)
  512. {
  513. struct hw_key_entry key_entry;
  514. struct rt2x00_field32 field;
  515. u32 offset;
  516. u32 reg;
  517. if (crypto->cmd == SET_KEY) {
  518. key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
  519. memcpy(key_entry.key, crypto->key,
  520. sizeof(key_entry.key));
  521. memcpy(key_entry.tx_mic, crypto->tx_mic,
  522. sizeof(key_entry.tx_mic));
  523. memcpy(key_entry.rx_mic, crypto->rx_mic,
  524. sizeof(key_entry.rx_mic));
  525. offset = SHARED_KEY_ENTRY(key->hw_key_idx);
  526. rt2800_register_multiwrite(rt2x00dev, offset,
  527. &key_entry, sizeof(key_entry));
  528. }
  529. /*
  530. * The cipher types are stored over multiple registers
  531. * starting with SHARED_KEY_MODE_BASE each word will have
  532. * 32 bits and contains the cipher types for 2 bssidx each.
  533. * Using the correct defines correctly will cause overhead,
  534. * so just calculate the correct offset.
  535. */
  536. field.bit_offset = 4 * (key->hw_key_idx % 8);
  537. field.bit_mask = 0x7 << field.bit_offset;
  538. offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
  539. rt2800_register_read(rt2x00dev, offset, &reg);
  540. rt2x00_set_field32(&reg, field,
  541. (crypto->cmd == SET_KEY) * crypto->cipher);
  542. rt2800_register_write(rt2x00dev, offset, reg);
  543. /*
  544. * Update WCID information
  545. */
  546. rt2800_config_wcid_attr(rt2x00dev, crypto, key);
  547. return 0;
  548. }
  549. EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
  550. int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
  551. struct rt2x00lib_crypto *crypto,
  552. struct ieee80211_key_conf *key)
  553. {
  554. struct hw_key_entry key_entry;
  555. u32 offset;
  556. if (crypto->cmd == SET_KEY) {
  557. /*
  558. * 1 pairwise key is possible per AID, this means that the AID
  559. * equals our hw_key_idx. Make sure the WCID starts _after_ the
  560. * last possible shared key entry.
  561. */
  562. if (crypto->aid > (256 - 32))
  563. return -ENOSPC;
  564. key->hw_key_idx = 32 + crypto->aid;
  565. memcpy(key_entry.key, crypto->key,
  566. sizeof(key_entry.key));
  567. memcpy(key_entry.tx_mic, crypto->tx_mic,
  568. sizeof(key_entry.tx_mic));
  569. memcpy(key_entry.rx_mic, crypto->rx_mic,
  570. sizeof(key_entry.rx_mic));
  571. offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
  572. rt2800_register_multiwrite(rt2x00dev, offset,
  573. &key_entry, sizeof(key_entry));
  574. }
  575. /*
  576. * Update WCID information
  577. */
  578. rt2800_config_wcid_attr(rt2x00dev, crypto, key);
  579. return 0;
  580. }
  581. EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
  582. void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
  583. const unsigned int filter_flags)
  584. {
  585. u32 reg;
  586. /*
  587. * Start configuration steps.
  588. * Note that the version error will always be dropped
  589. * and broadcast frames will always be accepted since
  590. * there is no filter for it at this time.
  591. */
  592. rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
  593. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
  594. !(filter_flags & FIF_FCSFAIL));
  595. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
  596. !(filter_flags & FIF_PLCPFAIL));
  597. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
  598. !(filter_flags & FIF_PROMISC_IN_BSS));
  599. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
  600. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
  601. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
  602. !(filter_flags & FIF_ALLMULTI));
  603. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
  604. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
  605. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
  606. !(filter_flags & FIF_CONTROL));
  607. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
  608. !(filter_flags & FIF_CONTROL));
  609. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
  610. !(filter_flags & FIF_CONTROL));
  611. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
  612. !(filter_flags & FIF_CONTROL));
  613. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
  614. !(filter_flags & FIF_CONTROL));
  615. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
  616. !(filter_flags & FIF_PSPOLL));
  617. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
  618. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
  619. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
  620. !(filter_flags & FIF_CONTROL));
  621. rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
  622. }
  623. EXPORT_SYMBOL_GPL(rt2800_config_filter);
  624. void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
  625. struct rt2x00intf_conf *conf, const unsigned int flags)
  626. {
  627. unsigned int beacon_base;
  628. u32 reg;
  629. if (flags & CONFIG_UPDATE_TYPE) {
  630. /*
  631. * Clear current synchronisation setup.
  632. * For the Beacon base registers we only need to clear
  633. * the first byte since that byte contains the VALID and OWNER
  634. * bits which (when set to 0) will invalidate the entire beacon.
  635. */
  636. beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
  637. rt2800_register_write(rt2x00dev, beacon_base, 0);
  638. /*
  639. * Enable synchronisation.
  640. */
  641. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  642. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
  643. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
  644. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
  645. (conf->sync == TSF_SYNC_BEACON));
  646. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  647. }
  648. if (flags & CONFIG_UPDATE_MAC) {
  649. reg = le32_to_cpu(conf->mac[1]);
  650. rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
  651. conf->mac[1] = cpu_to_le32(reg);
  652. rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
  653. conf->mac, sizeof(conf->mac));
  654. }
  655. if (flags & CONFIG_UPDATE_BSSID) {
  656. reg = le32_to_cpu(conf->bssid[1]);
  657. rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
  658. rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
  659. conf->bssid[1] = cpu_to_le32(reg);
  660. rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
  661. conf->bssid, sizeof(conf->bssid));
  662. }
  663. }
  664. EXPORT_SYMBOL_GPL(rt2800_config_intf);
  665. void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
  666. {
  667. u32 reg;
  668. rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
  669. rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
  670. !!erp->short_preamble);
  671. rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
  672. !!erp->short_preamble);
  673. rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
  674. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  675. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
  676. erp->cts_protection ? 2 : 0);
  677. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  678. rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
  679. erp->basic_rates);
  680. rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
  681. rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
  682. rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
  683. rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
  684. rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
  685. rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
  686. rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
  687. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  688. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
  689. erp->beacon_int * 16);
  690. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  691. }
  692. EXPORT_SYMBOL_GPL(rt2800_config_erp);
  693. void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
  694. {
  695. u8 r1;
  696. u8 r3;
  697. rt2800_bbp_read(rt2x00dev, 1, &r1);
  698. rt2800_bbp_read(rt2x00dev, 3, &r3);
  699. /*
  700. * Configure the TX antenna.
  701. */
  702. switch ((int)ant->tx) {
  703. case 1:
  704. rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
  705. if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  706. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
  707. break;
  708. case 2:
  709. rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
  710. break;
  711. case 3:
  712. /* Do nothing */
  713. break;
  714. }
  715. /*
  716. * Configure the RX antenna.
  717. */
  718. switch ((int)ant->rx) {
  719. case 1:
  720. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
  721. break;
  722. case 2:
  723. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
  724. break;
  725. case 3:
  726. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
  727. break;
  728. }
  729. rt2800_bbp_write(rt2x00dev, 3, r3);
  730. rt2800_bbp_write(rt2x00dev, 1, r1);
  731. }
  732. EXPORT_SYMBOL_GPL(rt2800_config_ant);
  733. static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
  734. struct rt2x00lib_conf *libconf)
  735. {
  736. u16 eeprom;
  737. short lna_gain;
  738. if (libconf->rf.channel <= 14) {
  739. rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
  740. lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
  741. } else if (libconf->rf.channel <= 64) {
  742. rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
  743. lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
  744. } else if (libconf->rf.channel <= 128) {
  745. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
  746. lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
  747. } else {
  748. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
  749. lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
  750. }
  751. rt2x00dev->lna_gain = lna_gain;
  752. }
  753. static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
  754. struct ieee80211_conf *conf,
  755. struct rf_channel *rf,
  756. struct channel_info *info)
  757. {
  758. rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
  759. if (rt2x00dev->default_ant.tx == 1)
  760. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
  761. if (rt2x00dev->default_ant.rx == 1) {
  762. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
  763. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
  764. } else if (rt2x00dev->default_ant.rx == 2)
  765. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
  766. if (rf->channel > 14) {
  767. /*
  768. * When TX power is below 0, we should increase it by 7 to
  769. * make it a positive value (Minumum value is -7).
  770. * However this means that values between 0 and 7 have
  771. * double meaning, and we should set a 7DBm boost flag.
  772. */
  773. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
  774. (info->tx_power1 >= 0));
  775. if (info->tx_power1 < 0)
  776. info->tx_power1 += 7;
  777. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
  778. TXPOWER_A_TO_DEV(info->tx_power1));
  779. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
  780. (info->tx_power2 >= 0));
  781. if (info->tx_power2 < 0)
  782. info->tx_power2 += 7;
  783. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
  784. TXPOWER_A_TO_DEV(info->tx_power2));
  785. } else {
  786. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
  787. TXPOWER_G_TO_DEV(info->tx_power1));
  788. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
  789. TXPOWER_G_TO_DEV(info->tx_power2));
  790. }
  791. rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
  792. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  793. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  794. rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  795. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  796. udelay(200);
  797. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  798. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  799. rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
  800. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  801. udelay(200);
  802. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  803. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  804. rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  805. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  806. }
  807. static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
  808. struct ieee80211_conf *conf,
  809. struct rf_channel *rf,
  810. struct channel_info *info)
  811. {
  812. u8 rfcsr;
  813. rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
  814. rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
  815. rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
  816. rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
  817. rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
  818. rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
  819. rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
  820. TXPOWER_G_TO_DEV(info->tx_power1));
  821. rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
  822. rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
  823. rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
  824. TXPOWER_G_TO_DEV(info->tx_power2));
  825. rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
  826. rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
  827. rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
  828. rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
  829. rt2800_rfcsr_write(rt2x00dev, 24,
  830. rt2x00dev->calibration[conf_is_ht40(conf)]);
  831. rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
  832. rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
  833. rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
  834. }
  835. static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  836. struct ieee80211_conf *conf,
  837. struct rf_channel *rf,
  838. struct channel_info *info)
  839. {
  840. u32 reg;
  841. unsigned int tx_pin;
  842. u8 bbp;
  843. if (rt2x00_rf(rt2x00dev, RF2020) ||
  844. rt2x00_rf(rt2x00dev, RF3020) ||
  845. rt2x00_rf(rt2x00dev, RF3021) ||
  846. rt2x00_rf(rt2x00dev, RF3022))
  847. rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
  848. else
  849. rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
  850. /*
  851. * Change BBP settings
  852. */
  853. rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
  854. rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
  855. rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
  856. rt2800_bbp_write(rt2x00dev, 86, 0);
  857. if (rf->channel <= 14) {
  858. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
  859. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  860. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  861. } else {
  862. rt2800_bbp_write(rt2x00dev, 82, 0x84);
  863. rt2800_bbp_write(rt2x00dev, 75, 0x50);
  864. }
  865. } else {
  866. rt2800_bbp_write(rt2x00dev, 82, 0xf2);
  867. if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
  868. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  869. else
  870. rt2800_bbp_write(rt2x00dev, 75, 0x50);
  871. }
  872. rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
  873. rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
  874. rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
  875. rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
  876. rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
  877. tx_pin = 0;
  878. /* Turn on unused PA or LNA when not using 1T or 1R */
  879. if (rt2x00dev->default_ant.tx != 1) {
  880. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
  881. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
  882. }
  883. /* Turn on unused PA or LNA when not using 1T or 1R */
  884. if (rt2x00dev->default_ant.rx != 1) {
  885. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
  886. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
  887. }
  888. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
  889. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
  890. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
  891. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
  892. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
  893. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
  894. rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
  895. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  896. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
  897. rt2800_bbp_write(rt2x00dev, 4, bbp);
  898. rt2800_bbp_read(rt2x00dev, 3, &bbp);
  899. rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
  900. rt2800_bbp_write(rt2x00dev, 3, bbp);
  901. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
  902. if (conf_is_ht40(conf)) {
  903. rt2800_bbp_write(rt2x00dev, 69, 0x1a);
  904. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  905. rt2800_bbp_write(rt2x00dev, 73, 0x16);
  906. } else {
  907. rt2800_bbp_write(rt2x00dev, 69, 0x16);
  908. rt2800_bbp_write(rt2x00dev, 70, 0x08);
  909. rt2800_bbp_write(rt2x00dev, 73, 0x11);
  910. }
  911. }
  912. msleep(1);
  913. }
  914. static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
  915. const int txpower)
  916. {
  917. u32 reg;
  918. u32 value = TXPOWER_G_TO_DEV(txpower);
  919. u8 r1;
  920. rt2800_bbp_read(rt2x00dev, 1, &r1);
  921. rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
  922. rt2800_bbp_write(rt2x00dev, 1, r1);
  923. rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
  924. rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
  925. rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
  926. rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
  927. rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
  928. rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
  929. rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
  930. rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
  931. rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
  932. rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
  933. rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
  934. rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
  935. rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
  936. rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
  937. rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
  938. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
  939. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
  940. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
  941. rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
  942. rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
  943. rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
  944. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
  945. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
  946. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
  947. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
  948. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
  949. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
  950. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
  951. rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
  952. rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
  953. rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
  954. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
  955. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
  956. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
  957. rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
  958. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
  959. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
  960. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
  961. rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
  962. rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
  963. rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
  964. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
  965. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
  966. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
  967. rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
  968. rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
  969. }
  970. static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
  971. struct rt2x00lib_conf *libconf)
  972. {
  973. u32 reg;
  974. rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
  975. rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
  976. libconf->conf->short_frame_max_tx_count);
  977. rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
  978. libconf->conf->long_frame_max_tx_count);
  979. rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
  980. }
  981. static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
  982. struct rt2x00lib_conf *libconf)
  983. {
  984. enum dev_state state =
  985. (libconf->conf->flags & IEEE80211_CONF_PS) ?
  986. STATE_SLEEP : STATE_AWAKE;
  987. u32 reg;
  988. if (state == STATE_SLEEP) {
  989. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
  990. rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
  991. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
  992. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
  993. libconf->conf->listen_interval - 1);
  994. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
  995. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
  996. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  997. } else {
  998. rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
  999. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
  1000. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
  1001. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
  1002. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
  1003. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  1004. }
  1005. }
  1006. void rt2800_config(struct rt2x00_dev *rt2x00dev,
  1007. struct rt2x00lib_conf *libconf,
  1008. const unsigned int flags)
  1009. {
  1010. /* Always recalculate LNA gain before changing configuration */
  1011. rt2800_config_lna_gain(rt2x00dev, libconf);
  1012. if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
  1013. rt2800_config_channel(rt2x00dev, libconf->conf,
  1014. &libconf->rf, &libconf->channel);
  1015. if (flags & IEEE80211_CONF_CHANGE_POWER)
  1016. rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
  1017. if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
  1018. rt2800_config_retry_limit(rt2x00dev, libconf);
  1019. if (flags & IEEE80211_CONF_CHANGE_PS)
  1020. rt2800_config_ps(rt2x00dev, libconf);
  1021. }
  1022. EXPORT_SYMBOL_GPL(rt2800_config);
  1023. /*
  1024. * Link tuning
  1025. */
  1026. void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
  1027. {
  1028. u32 reg;
  1029. /*
  1030. * Update FCS error count from register.
  1031. */
  1032. rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
  1033. qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
  1034. }
  1035. EXPORT_SYMBOL_GPL(rt2800_link_stats);
  1036. static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
  1037. {
  1038. if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
  1039. if (rt2x00_rt(rt2x00dev, RT3070) ||
  1040. rt2x00_rt(rt2x00dev, RT3071) ||
  1041. rt2x00_rt(rt2x00dev, RT3090) ||
  1042. rt2x00_rt(rt2x00dev, RT3390))
  1043. return 0x1c + (2 * rt2x00dev->lna_gain);
  1044. else
  1045. return 0x2e + rt2x00dev->lna_gain;
  1046. }
  1047. if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
  1048. return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
  1049. else
  1050. return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
  1051. }
  1052. static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
  1053. struct link_qual *qual, u8 vgc_level)
  1054. {
  1055. if (qual->vgc_level != vgc_level) {
  1056. rt2800_bbp_write(rt2x00dev, 66, vgc_level);
  1057. qual->vgc_level = vgc_level;
  1058. qual->vgc_level_reg = vgc_level;
  1059. }
  1060. }
  1061. void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
  1062. {
  1063. rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
  1064. }
  1065. EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
  1066. void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
  1067. const u32 count)
  1068. {
  1069. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
  1070. return;
  1071. /*
  1072. * When RSSI is better then -80 increase VGC level with 0x10
  1073. */
  1074. rt2800_set_vgc(rt2x00dev, qual,
  1075. rt2800_get_default_vgc(rt2x00dev) +
  1076. ((qual->rssi > -80) * 0x10));
  1077. }
  1078. EXPORT_SYMBOL_GPL(rt2800_link_tuner);
  1079. /*
  1080. * Initialization functions.
  1081. */
  1082. int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
  1083. {
  1084. u32 reg;
  1085. u16 eeprom;
  1086. unsigned int i;
  1087. int ret;
  1088. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  1089. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
  1090. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
  1091. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
  1092. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
  1093. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
  1094. rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
  1095. ret = rt2800_drv_init_registers(rt2x00dev);
  1096. if (ret)
  1097. return ret;
  1098. rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
  1099. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
  1100. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
  1101. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
  1102. rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
  1103. rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
  1104. rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
  1105. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
  1106. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
  1107. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
  1108. rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
  1109. rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
  1110. rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
  1111. rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
  1112. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
  1113. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  1114. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
  1115. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
  1116. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
  1117. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
  1118. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
  1119. rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
  1120. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  1121. rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
  1122. rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
  1123. rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
  1124. rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
  1125. rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
  1126. if (rt2x00_rt(rt2x00dev, RT3071) ||
  1127. rt2x00_rt(rt2x00dev, RT3090) ||
  1128. rt2x00_rt(rt2x00dev, RT3390)) {
  1129. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
  1130. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
  1131. if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  1132. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
  1133. rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
  1134. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1135. if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
  1136. rt2800_register_write(rt2x00dev, TX_SW_CFG2,
  1137. 0x0000002c);
  1138. else
  1139. rt2800_register_write(rt2x00dev, TX_SW_CFG2,
  1140. 0x0000000f);
  1141. } else {
  1142. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  1143. }
  1144. } else if (rt2x00_rt(rt2x00dev, RT3070)) {
  1145. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
  1146. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
  1147. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
  1148. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
  1149. } else {
  1150. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  1151. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  1152. }
  1153. } else if (rt2800_is_305x_soc(rt2x00dev)) {
  1154. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
  1155. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
  1156. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
  1157. } else {
  1158. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
  1159. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  1160. }
  1161. rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
  1162. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
  1163. rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
  1164. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
  1165. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
  1166. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
  1167. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
  1168. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
  1169. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
  1170. rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
  1171. rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
  1172. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
  1173. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
  1174. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
  1175. rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
  1176. rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
  1177. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
  1178. if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
  1179. rt2x00_rt(rt2x00dev, RT2883) ||
  1180. rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
  1181. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
  1182. else
  1183. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
  1184. rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
  1185. rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
  1186. rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
  1187. rt2800_register_read(rt2x00dev, LED_CFG, &reg);
  1188. rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
  1189. rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
  1190. rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
  1191. rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
  1192. rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
  1193. rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
  1194. rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
  1195. rt2800_register_write(rt2x00dev, LED_CFG, reg);
  1196. rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
  1197. rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
  1198. rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
  1199. rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
  1200. rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
  1201. rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
  1202. rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
  1203. rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
  1204. rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
  1205. rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
  1206. rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
  1207. rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
  1208. rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
  1209. rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
  1210. rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
  1211. rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
  1212. rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
  1213. rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
  1214. rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
  1215. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
  1216. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
  1217. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
  1218. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1219. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1220. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1221. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  1222. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1223. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  1224. rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
  1225. rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
  1226. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  1227. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
  1228. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
  1229. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
  1230. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1231. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1232. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1233. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  1234. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1235. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  1236. rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
  1237. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  1238. rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
  1239. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
  1240. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
  1241. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
  1242. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1243. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1244. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1245. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  1246. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1247. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  1248. rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
  1249. rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
  1250. rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
  1251. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
  1252. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
  1253. !rt2x00_is_usb(rt2x00dev));
  1254. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
  1255. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1256. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1257. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1258. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
  1259. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1260. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
  1261. rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
  1262. rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
  1263. rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
  1264. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
  1265. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
  1266. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
  1267. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1268. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1269. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1270. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  1271. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1272. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  1273. rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
  1274. rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
  1275. rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
  1276. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
  1277. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
  1278. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
  1279. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  1280. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  1281. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  1282. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
  1283. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  1284. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
  1285. rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
  1286. rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
  1287. if (rt2x00_is_usb(rt2x00dev)) {
  1288. rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
  1289. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  1290. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
  1291. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
  1292. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
  1293. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
  1294. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
  1295. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
  1296. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
  1297. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
  1298. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
  1299. rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
  1300. }
  1301. rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
  1302. rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
  1303. rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
  1304. rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
  1305. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
  1306. IEEE80211_MAX_RTS_THRESHOLD);
  1307. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
  1308. rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
  1309. rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
  1310. /*
  1311. * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
  1312. * time should be set to 16. However, the original Ralink driver uses
  1313. * 16 for both and indeed using a value of 10 for CCK SIFS results in
  1314. * connection problems with 11g + CTS protection. Hence, use the same
  1315. * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
  1316. */
  1317. rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
  1318. rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
  1319. rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
  1320. rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
  1321. rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
  1322. rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
  1323. rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
  1324. rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
  1325. /*
  1326. * ASIC will keep garbage value after boot, clear encryption keys.
  1327. */
  1328. for (i = 0; i < 4; i++)
  1329. rt2800_register_write(rt2x00dev,
  1330. SHARED_KEY_MODE_ENTRY(i), 0);
  1331. for (i = 0; i < 256; i++) {
  1332. u32 wcid[2] = { 0xffffffff, 0x00ffffff };
  1333. rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
  1334. wcid, sizeof(wcid));
  1335. rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
  1336. rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
  1337. }
  1338. /*
  1339. * Clear all beacons
  1340. * For the Beacon base registers we only need to clear
  1341. * the first byte since that byte contains the VALID and OWNER
  1342. * bits which (when set to 0) will invalidate the entire beacon.
  1343. */
  1344. rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
  1345. rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
  1346. rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
  1347. rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
  1348. rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
  1349. rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
  1350. rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
  1351. rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
  1352. if (rt2x00_is_usb(rt2x00dev)) {
  1353. rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
  1354. rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
  1355. rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
  1356. }
  1357. rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
  1358. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
  1359. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
  1360. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
  1361. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
  1362. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
  1363. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
  1364. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
  1365. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
  1366. rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
  1367. rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
  1368. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
  1369. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
  1370. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
  1371. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
  1372. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
  1373. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
  1374. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
  1375. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
  1376. rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
  1377. rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
  1378. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
  1379. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
  1380. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
  1381. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
  1382. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
  1383. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
  1384. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
  1385. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
  1386. rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
  1387. rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
  1388. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
  1389. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
  1390. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
  1391. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
  1392. rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
  1393. /*
  1394. * We must clear the error counters.
  1395. * These registers are cleared on read,
  1396. * so we may pass a useless variable to store the value.
  1397. */
  1398. rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
  1399. rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
  1400. rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
  1401. rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
  1402. rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
  1403. rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
  1404. return 0;
  1405. }
  1406. EXPORT_SYMBOL_GPL(rt2800_init_registers);
  1407. static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
  1408. {
  1409. unsigned int i;
  1410. u32 reg;
  1411. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1412. rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
  1413. if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
  1414. return 0;
  1415. udelay(REGISTER_BUSY_DELAY);
  1416. }
  1417. ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
  1418. return -EACCES;
  1419. }
  1420. static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
  1421. {
  1422. unsigned int i;
  1423. u8 value;
  1424. /*
  1425. * BBP was enabled after firmware was loaded,
  1426. * but we need to reactivate it now.
  1427. */
  1428. rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
  1429. rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  1430. msleep(1);
  1431. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  1432. rt2800_bbp_read(rt2x00dev, 0, &value);
  1433. if ((value != 0xff) && (value != 0x00))
  1434. return 0;
  1435. udelay(REGISTER_BUSY_DELAY);
  1436. }
  1437. ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
  1438. return -EACCES;
  1439. }
  1440. int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
  1441. {
  1442. unsigned int i;
  1443. u16 eeprom;
  1444. u8 reg_id;
  1445. u8 value;
  1446. if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
  1447. rt2800_wait_bbp_ready(rt2x00dev)))
  1448. return -EACCES;
  1449. if (rt2800_is_305x_soc(rt2x00dev))
  1450. rt2800_bbp_write(rt2x00dev, 31, 0x08);
  1451. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  1452. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  1453. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
  1454. rt2800_bbp_write(rt2x00dev, 69, 0x16);
  1455. rt2800_bbp_write(rt2x00dev, 73, 0x12);
  1456. } else {
  1457. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  1458. rt2800_bbp_write(rt2x00dev, 73, 0x10);
  1459. }
  1460. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  1461. if (rt2x00_rt(rt2x00dev, RT3070) ||
  1462. rt2x00_rt(rt2x00dev, RT3071) ||
  1463. rt2x00_rt(rt2x00dev, RT3090) ||
  1464. rt2x00_rt(rt2x00dev, RT3390)) {
  1465. rt2800_bbp_write(rt2x00dev, 79, 0x13);
  1466. rt2800_bbp_write(rt2x00dev, 80, 0x05);
  1467. rt2800_bbp_write(rt2x00dev, 81, 0x33);
  1468. } else if (rt2800_is_305x_soc(rt2x00dev)) {
  1469. rt2800_bbp_write(rt2x00dev, 78, 0x0e);
  1470. rt2800_bbp_write(rt2x00dev, 80, 0x08);
  1471. } else {
  1472. rt2800_bbp_write(rt2x00dev, 81, 0x37);
  1473. }
  1474. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  1475. rt2800_bbp_write(rt2x00dev, 83, 0x6a);
  1476. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
  1477. rt2800_bbp_write(rt2x00dev, 84, 0x19);
  1478. else
  1479. rt2800_bbp_write(rt2x00dev, 84, 0x99);
  1480. rt2800_bbp_write(rt2x00dev, 86, 0x00);
  1481. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  1482. rt2800_bbp_write(rt2x00dev, 92, 0x00);
  1483. if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
  1484. rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
  1485. rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
  1486. rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
  1487. rt2800_is_305x_soc(rt2x00dev))
  1488. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  1489. else
  1490. rt2800_bbp_write(rt2x00dev, 103, 0x00);
  1491. if (rt2800_is_305x_soc(rt2x00dev))
  1492. rt2800_bbp_write(rt2x00dev, 105, 0x01);
  1493. else
  1494. rt2800_bbp_write(rt2x00dev, 105, 0x05);
  1495. rt2800_bbp_write(rt2x00dev, 106, 0x35);
  1496. if (rt2x00_rt(rt2x00dev, RT3071) ||
  1497. rt2x00_rt(rt2x00dev, RT3090) ||
  1498. rt2x00_rt(rt2x00dev, RT3390)) {
  1499. rt2800_bbp_read(rt2x00dev, 138, &value);
  1500. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1501. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
  1502. value |= 0x20;
  1503. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
  1504. value &= ~0x02;
  1505. rt2800_bbp_write(rt2x00dev, 138, value);
  1506. }
  1507. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  1508. rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
  1509. if (eeprom != 0xffff && eeprom != 0x0000) {
  1510. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  1511. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  1512. rt2800_bbp_write(rt2x00dev, reg_id, value);
  1513. }
  1514. }
  1515. return 0;
  1516. }
  1517. EXPORT_SYMBOL_GPL(rt2800_init_bbp);
  1518. static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
  1519. bool bw40, u8 rfcsr24, u8 filter_target)
  1520. {
  1521. unsigned int i;
  1522. u8 bbp;
  1523. u8 rfcsr;
  1524. u8 passband;
  1525. u8 stopband;
  1526. u8 overtuned = 0;
  1527. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  1528. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  1529. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
  1530. rt2800_bbp_write(rt2x00dev, 4, bbp);
  1531. rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
  1532. rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
  1533. rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
  1534. /*
  1535. * Set power & frequency of passband test tone
  1536. */
  1537. rt2800_bbp_write(rt2x00dev, 24, 0);
  1538. for (i = 0; i < 100; i++) {
  1539. rt2800_bbp_write(rt2x00dev, 25, 0x90);
  1540. msleep(1);
  1541. rt2800_bbp_read(rt2x00dev, 55, &passband);
  1542. if (passband)
  1543. break;
  1544. }
  1545. /*
  1546. * Set power & frequency of stopband test tone
  1547. */
  1548. rt2800_bbp_write(rt2x00dev, 24, 0x06);
  1549. for (i = 0; i < 100; i++) {
  1550. rt2800_bbp_write(rt2x00dev, 25, 0x90);
  1551. msleep(1);
  1552. rt2800_bbp_read(rt2x00dev, 55, &stopband);
  1553. if ((passband - stopband) <= filter_target) {
  1554. rfcsr24++;
  1555. overtuned += ((passband - stopband) == filter_target);
  1556. } else
  1557. break;
  1558. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  1559. }
  1560. rfcsr24 -= !!overtuned;
  1561. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  1562. return rfcsr24;
  1563. }
  1564. int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
  1565. {
  1566. u8 rfcsr;
  1567. u8 bbp;
  1568. u32 reg;
  1569. u16 eeprom;
  1570. if (!rt2x00_rt(rt2x00dev, RT3070) &&
  1571. !rt2x00_rt(rt2x00dev, RT3071) &&
  1572. !rt2x00_rt(rt2x00dev, RT3090) &&
  1573. !rt2x00_rt(rt2x00dev, RT3390) &&
  1574. !rt2800_is_305x_soc(rt2x00dev))
  1575. return 0;
  1576. /*
  1577. * Init RF calibration.
  1578. */
  1579. rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
  1580. rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
  1581. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  1582. msleep(1);
  1583. rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
  1584. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  1585. if (rt2x00_rt(rt2x00dev, RT3070) ||
  1586. rt2x00_rt(rt2x00dev, RT3071) ||
  1587. rt2x00_rt(rt2x00dev, RT3090)) {
  1588. rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
  1589. rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
  1590. rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
  1591. rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
  1592. rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
  1593. rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
  1594. rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  1595. rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
  1596. rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
  1597. rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
  1598. rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
  1599. rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
  1600. rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
  1601. rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
  1602. rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
  1603. rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
  1604. rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
  1605. rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
  1606. rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
  1607. } else if (rt2x00_rt(rt2x00dev, RT3390)) {
  1608. rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
  1609. rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
  1610. rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
  1611. rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
  1612. rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
  1613. rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
  1614. rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
  1615. rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
  1616. rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
  1617. rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
  1618. rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
  1619. rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  1620. rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
  1621. rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
  1622. rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
  1623. rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
  1624. rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
  1625. rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
  1626. rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
  1627. rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
  1628. rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
  1629. rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
  1630. rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  1631. rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
  1632. rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
  1633. rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
  1634. rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
  1635. rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
  1636. rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
  1637. rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
  1638. rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
  1639. rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
  1640. } else if (rt2800_is_305x_soc(rt2x00dev)) {
  1641. rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
  1642. rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
  1643. rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
  1644. rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
  1645. rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
  1646. rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
  1647. rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
  1648. rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
  1649. rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
  1650. rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
  1651. rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
  1652. rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  1653. rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
  1654. rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
  1655. rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
  1656. rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
  1657. rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
  1658. rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
  1659. rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
  1660. rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
  1661. rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
  1662. rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
  1663. rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  1664. rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
  1665. rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
  1666. rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
  1667. rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
  1668. rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
  1669. rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
  1670. rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
  1671. rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
  1672. rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
  1673. return 0;
  1674. }
  1675. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
  1676. rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
  1677. rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
  1678. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
  1679. rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
  1680. } else if (rt2x00_rt(rt2x00dev, RT3071) ||
  1681. rt2x00_rt(rt2x00dev, RT3090)) {
  1682. rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
  1683. rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
  1684. rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
  1685. rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
  1686. rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
  1687. rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
  1688. if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  1689. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
  1690. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1691. if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
  1692. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
  1693. else
  1694. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
  1695. }
  1696. rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
  1697. } else if (rt2x00_rt(rt2x00dev, RT3390)) {
  1698. rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
  1699. rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
  1700. rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
  1701. }
  1702. /*
  1703. * Set RX Filter calibration for 20MHz and 40MHz
  1704. */
  1705. if (rt2x00_rt(rt2x00dev, RT3070)) {
  1706. rt2x00dev->calibration[0] =
  1707. rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
  1708. rt2x00dev->calibration[1] =
  1709. rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
  1710. } else if (rt2x00_rt(rt2x00dev, RT3071) ||
  1711. rt2x00_rt(rt2x00dev, RT3090) ||
  1712. rt2x00_rt(rt2x00dev, RT3390)) {
  1713. rt2x00dev->calibration[0] =
  1714. rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
  1715. rt2x00dev->calibration[1] =
  1716. rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
  1717. }
  1718. /*
  1719. * Set back to initial state
  1720. */
  1721. rt2800_bbp_write(rt2x00dev, 24, 0);
  1722. rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
  1723. rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
  1724. rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
  1725. /*
  1726. * set BBP back to BW20
  1727. */
  1728. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  1729. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
  1730. rt2800_bbp_write(rt2x00dev, 4, bbp);
  1731. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
  1732. rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  1733. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
  1734. rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
  1735. rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
  1736. rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
  1737. rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
  1738. rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
  1739. rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
  1740. rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
  1741. if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  1742. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
  1743. rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
  1744. if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
  1745. rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
  1746. }
  1747. rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
  1748. if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
  1749. rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
  1750. rt2x00_get_field16(eeprom,
  1751. EEPROM_TXMIXER_GAIN_BG_VAL));
  1752. rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
  1753. if (rt2x00_rt(rt2x00dev, RT3090)) {
  1754. rt2800_bbp_read(rt2x00dev, 138, &bbp);
  1755. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1756. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
  1757. rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
  1758. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
  1759. rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
  1760. rt2800_bbp_write(rt2x00dev, 138, bbp);
  1761. }
  1762. if (rt2x00_rt(rt2x00dev, RT3071) ||
  1763. rt2x00_rt(rt2x00dev, RT3090) ||
  1764. rt2x00_rt(rt2x00dev, RT3390)) {
  1765. rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  1766. rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
  1767. rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
  1768. rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
  1769. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
  1770. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
  1771. rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  1772. rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
  1773. rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
  1774. rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
  1775. rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
  1776. rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
  1777. rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
  1778. rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
  1779. rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
  1780. rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
  1781. }
  1782. if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
  1783. rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
  1784. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
  1785. rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
  1786. rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
  1787. else
  1788. rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
  1789. rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
  1790. rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
  1791. rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
  1792. rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
  1793. }
  1794. return 0;
  1795. }
  1796. EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
  1797. int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
  1798. {
  1799. u32 reg;
  1800. rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
  1801. return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
  1802. }
  1803. EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
  1804. static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
  1805. {
  1806. u32 reg;
  1807. mutex_lock(&rt2x00dev->csr_mutex);
  1808. rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
  1809. rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
  1810. rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
  1811. rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
  1812. rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
  1813. /* Wait until the EEPROM has been loaded */
  1814. rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
  1815. /* Apparently the data is read from end to start */
  1816. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
  1817. (u32 *)&rt2x00dev->eeprom[i]);
  1818. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
  1819. (u32 *)&rt2x00dev->eeprom[i + 2]);
  1820. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
  1821. (u32 *)&rt2x00dev->eeprom[i + 4]);
  1822. rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
  1823. (u32 *)&rt2x00dev->eeprom[i + 6]);
  1824. mutex_unlock(&rt2x00dev->csr_mutex);
  1825. }
  1826. void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
  1827. {
  1828. unsigned int i;
  1829. for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
  1830. rt2800_efuse_read(rt2x00dev, i);
  1831. }
  1832. EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
  1833. int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1834. {
  1835. u16 word;
  1836. u8 *mac;
  1837. u8 default_lna_gain;
  1838. /*
  1839. * Start validation of the data that has been read.
  1840. */
  1841. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1842. if (!is_valid_ether_addr(mac)) {
  1843. random_ether_addr(mac);
  1844. EEPROM(rt2x00dev, "MAC: %pM\n", mac);
  1845. }
  1846. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
  1847. if (word == 0xffff) {
  1848. rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
  1849. rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
  1850. rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
  1851. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1852. EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
  1853. } else if (rt2x00_rt(rt2x00dev, RT2860) ||
  1854. rt2x00_rt(rt2x00dev, RT2872)) {
  1855. /*
  1856. * There is a max of 2 RX streams for RT28x0 series
  1857. */
  1858. if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
  1859. rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
  1860. rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
  1861. }
  1862. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
  1863. if (word == 0xffff) {
  1864. rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
  1865. rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
  1866. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
  1867. rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
  1868. rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
  1869. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
  1870. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
  1871. rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
  1872. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
  1873. rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
  1874. rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
  1875. EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
  1876. }
  1877. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
  1878. if ((word & 0x00ff) == 0x00ff) {
  1879. rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
  1880. rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
  1881. LED_MODE_TXRX_ACTIVITY);
  1882. rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
  1883. rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
  1884. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
  1885. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
  1886. rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
  1887. EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
  1888. }
  1889. /*
  1890. * During the LNA validation we are going to use
  1891. * lna0 as correct value. Note that EEPROM_LNA
  1892. * is never validated.
  1893. */
  1894. rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
  1895. default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
  1896. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
  1897. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
  1898. rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
  1899. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
  1900. rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
  1901. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
  1902. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
  1903. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
  1904. rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
  1905. if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
  1906. rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
  1907. rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
  1908. default_lna_gain);
  1909. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
  1910. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
  1911. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
  1912. rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
  1913. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
  1914. rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
  1915. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
  1916. rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
  1917. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
  1918. rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
  1919. if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
  1920. rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
  1921. rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
  1922. default_lna_gain);
  1923. rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
  1924. return 0;
  1925. }
  1926. EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
  1927. int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1928. {
  1929. u32 reg;
  1930. u16 value;
  1931. u16 eeprom;
  1932. /*
  1933. * Read EEPROM word for configuration.
  1934. */
  1935. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1936. /*
  1937. * Identify RF chipset.
  1938. */
  1939. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1940. rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
  1941. rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
  1942. value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
  1943. if (!rt2x00_rt(rt2x00dev, RT2860) &&
  1944. !rt2x00_rt(rt2x00dev, RT2872) &&
  1945. !rt2x00_rt(rt2x00dev, RT2883) &&
  1946. !rt2x00_rt(rt2x00dev, RT3070) &&
  1947. !rt2x00_rt(rt2x00dev, RT3071) &&
  1948. !rt2x00_rt(rt2x00dev, RT3090) &&
  1949. !rt2x00_rt(rt2x00dev, RT3390) &&
  1950. !rt2x00_rt(rt2x00dev, RT3572)) {
  1951. ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
  1952. return -ENODEV;
  1953. }
  1954. if (!rt2x00_rf(rt2x00dev, RF2820) &&
  1955. !rt2x00_rf(rt2x00dev, RF2850) &&
  1956. !rt2x00_rf(rt2x00dev, RF2720) &&
  1957. !rt2x00_rf(rt2x00dev, RF2750) &&
  1958. !rt2x00_rf(rt2x00dev, RF3020) &&
  1959. !rt2x00_rf(rt2x00dev, RF2020) &&
  1960. !rt2x00_rf(rt2x00dev, RF3021) &&
  1961. !rt2x00_rf(rt2x00dev, RF3022) &&
  1962. !rt2x00_rf(rt2x00dev, RF3052)) {
  1963. ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
  1964. return -ENODEV;
  1965. }
  1966. /*
  1967. * Identify default antenna configuration.
  1968. */
  1969. rt2x00dev->default_ant.tx =
  1970. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
  1971. rt2x00dev->default_ant.rx =
  1972. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
  1973. /*
  1974. * Read frequency offset and RF programming sequence.
  1975. */
  1976. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
  1977. rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
  1978. /*
  1979. * Read external LNA informations.
  1980. */
  1981. rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
  1982. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
  1983. __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
  1984. if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
  1985. __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
  1986. /*
  1987. * Detect if this device has an hardware controlled radio.
  1988. */
  1989. if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
  1990. __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
  1991. /*
  1992. * Store led settings, for correct led behaviour.
  1993. */
  1994. #ifdef CONFIG_RT2X00_LIB_LEDS
  1995. rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
  1996. rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
  1997. rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
  1998. rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
  1999. #endif /* CONFIG_RT2X00_LIB_LEDS */
  2000. return 0;
  2001. }
  2002. EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
  2003. /*
  2004. * RF value list for rt28xx
  2005. * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
  2006. */
  2007. static const struct rf_channel rf_vals[] = {
  2008. { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
  2009. { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
  2010. { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
  2011. { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
  2012. { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
  2013. { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
  2014. { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
  2015. { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
  2016. { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
  2017. { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
  2018. { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
  2019. { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
  2020. { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
  2021. { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
  2022. /* 802.11 UNI / HyperLan 2 */
  2023. { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
  2024. { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
  2025. { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
  2026. { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
  2027. { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
  2028. { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
  2029. { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
  2030. { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
  2031. { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
  2032. { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
  2033. { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
  2034. { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
  2035. /* 802.11 HyperLan 2 */
  2036. { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
  2037. { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
  2038. { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
  2039. { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
  2040. { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
  2041. { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
  2042. { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
  2043. { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
  2044. { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
  2045. { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
  2046. { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
  2047. { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
  2048. { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
  2049. { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
  2050. { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
  2051. { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
  2052. /* 802.11 UNII */
  2053. { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
  2054. { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
  2055. { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
  2056. { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
  2057. { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
  2058. { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
  2059. { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
  2060. { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
  2061. { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
  2062. { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
  2063. { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
  2064. /* 802.11 Japan */
  2065. { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
  2066. { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
  2067. { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
  2068. { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
  2069. { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
  2070. { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
  2071. { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
  2072. };
  2073. /*
  2074. * RF value list for rt3xxx
  2075. * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
  2076. */
  2077. static const struct rf_channel rf_vals_3x[] = {
  2078. {1, 241, 2, 2 },
  2079. {2, 241, 2, 7 },
  2080. {3, 242, 2, 2 },
  2081. {4, 242, 2, 7 },
  2082. {5, 243, 2, 2 },
  2083. {6, 243, 2, 7 },
  2084. {7, 244, 2, 2 },
  2085. {8, 244, 2, 7 },
  2086. {9, 245, 2, 2 },
  2087. {10, 245, 2, 7 },
  2088. {11, 246, 2, 2 },
  2089. {12, 246, 2, 7 },
  2090. {13, 247, 2, 2 },
  2091. {14, 248, 2, 4 },
  2092. /* 802.11 UNI / HyperLan 2 */
  2093. {36, 0x56, 0, 4},
  2094. {38, 0x56, 0, 6},
  2095. {40, 0x56, 0, 8},
  2096. {44, 0x57, 0, 0},
  2097. {46, 0x57, 0, 2},
  2098. {48, 0x57, 0, 4},
  2099. {52, 0x57, 0, 8},
  2100. {54, 0x57, 0, 10},
  2101. {56, 0x58, 0, 0},
  2102. {60, 0x58, 0, 4},
  2103. {62, 0x58, 0, 6},
  2104. {64, 0x58, 0, 8},
  2105. /* 802.11 HyperLan 2 */
  2106. {100, 0x5b, 0, 8},
  2107. {102, 0x5b, 0, 10},
  2108. {104, 0x5c, 0, 0},
  2109. {108, 0x5c, 0, 4},
  2110. {110, 0x5c, 0, 6},
  2111. {112, 0x5c, 0, 8},
  2112. {116, 0x5d, 0, 0},
  2113. {118, 0x5d, 0, 2},
  2114. {120, 0x5d, 0, 4},
  2115. {124, 0x5d, 0, 8},
  2116. {126, 0x5d, 0, 10},
  2117. {128, 0x5e, 0, 0},
  2118. {132, 0x5e, 0, 4},
  2119. {134, 0x5e, 0, 6},
  2120. {136, 0x5e, 0, 8},
  2121. {140, 0x5f, 0, 0},
  2122. /* 802.11 UNII */
  2123. {149, 0x5f, 0, 9},
  2124. {151, 0x5f, 0, 11},
  2125. {153, 0x60, 0, 1},
  2126. {157, 0x60, 0, 5},
  2127. {159, 0x60, 0, 7},
  2128. {161, 0x60, 0, 9},
  2129. {165, 0x61, 0, 1},
  2130. {167, 0x61, 0, 3},
  2131. {169, 0x61, 0, 5},
  2132. {171, 0x61, 0, 7},
  2133. {173, 0x61, 0, 9},
  2134. };
  2135. int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  2136. {
  2137. struct hw_mode_spec *spec = &rt2x00dev->spec;
  2138. struct channel_info *info;
  2139. char *tx_power1;
  2140. char *tx_power2;
  2141. unsigned int i;
  2142. u16 eeprom;
  2143. /*
  2144. * Disable powersaving as default on PCI devices.
  2145. */
  2146. if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
  2147. rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2148. /*
  2149. * Initialize all hw fields.
  2150. */
  2151. rt2x00dev->hw->flags =
  2152. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  2153. IEEE80211_HW_SIGNAL_DBM |
  2154. IEEE80211_HW_SUPPORTS_PS |
  2155. IEEE80211_HW_PS_NULLFUNC_STACK |
  2156. IEEE80211_HW_AMPDU_AGGREGATION;
  2157. SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
  2158. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  2159. rt2x00_eeprom_addr(rt2x00dev,
  2160. EEPROM_MAC_ADDR_0));
  2161. /*
  2162. * As rt2800 has a global fallback table we cannot specify
  2163. * more then one tx rate per frame but since the hw will
  2164. * try several rates (based on the fallback table) we should
  2165. * still initialize max_rates to the maximum number of rates
  2166. * we are going to try. Otherwise mac80211 will truncate our
  2167. * reported tx rates and the rc algortihm will end up with
  2168. * incorrect data.
  2169. */
  2170. rt2x00dev->hw->max_rates = 7;
  2171. rt2x00dev->hw->max_rate_tries = 1;
  2172. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  2173. /*
  2174. * Initialize hw_mode information.
  2175. */
  2176. spec->supported_bands = SUPPORT_BAND_2GHZ;
  2177. spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
  2178. if (rt2x00_rf(rt2x00dev, RF2820) ||
  2179. rt2x00_rf(rt2x00dev, RF2720)) {
  2180. spec->num_channels = 14;
  2181. spec->channels = rf_vals;
  2182. } else if (rt2x00_rf(rt2x00dev, RF2850) ||
  2183. rt2x00_rf(rt2x00dev, RF2750)) {
  2184. spec->supported_bands |= SUPPORT_BAND_5GHZ;
  2185. spec->num_channels = ARRAY_SIZE(rf_vals);
  2186. spec->channels = rf_vals;
  2187. } else if (rt2x00_rf(rt2x00dev, RF3020) ||
  2188. rt2x00_rf(rt2x00dev, RF2020) ||
  2189. rt2x00_rf(rt2x00dev, RF3021) ||
  2190. rt2x00_rf(rt2x00dev, RF3022)) {
  2191. spec->num_channels = 14;
  2192. spec->channels = rf_vals_3x;
  2193. } else if (rt2x00_rf(rt2x00dev, RF3052)) {
  2194. spec->supported_bands |= SUPPORT_BAND_5GHZ;
  2195. spec->num_channels = ARRAY_SIZE(rf_vals_3x);
  2196. spec->channels = rf_vals_3x;
  2197. }
  2198. /*
  2199. * Initialize HT information.
  2200. */
  2201. if (!rt2x00_rf(rt2x00dev, RF2020))
  2202. spec->ht.ht_supported = true;
  2203. else
  2204. spec->ht.ht_supported = false;
  2205. spec->ht.cap =
  2206. IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  2207. IEEE80211_HT_CAP_GRN_FLD |
  2208. IEEE80211_HT_CAP_SGI_20 |
  2209. IEEE80211_HT_CAP_SGI_40 |
  2210. IEEE80211_HT_CAP_RX_STBC;
  2211. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
  2212. spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
  2213. spec->ht.ampdu_factor = 3;
  2214. spec->ht.ampdu_density = 4;
  2215. spec->ht.mcs.tx_params =
  2216. IEEE80211_HT_MCS_TX_DEFINED |
  2217. IEEE80211_HT_MCS_TX_RX_DIFF |
  2218. ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
  2219. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  2220. switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
  2221. case 3:
  2222. spec->ht.mcs.rx_mask[2] = 0xff;
  2223. case 2:
  2224. spec->ht.mcs.rx_mask[1] = 0xff;
  2225. case 1:
  2226. spec->ht.mcs.rx_mask[0] = 0xff;
  2227. spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
  2228. break;
  2229. }
  2230. /*
  2231. * Create channel information array
  2232. */
  2233. info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
  2234. if (!info)
  2235. return -ENOMEM;
  2236. spec->channels_info = info;
  2237. tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
  2238. tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
  2239. for (i = 0; i < 14; i++) {
  2240. info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
  2241. info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
  2242. }
  2243. if (spec->num_channels > 14) {
  2244. tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
  2245. tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
  2246. for (i = 14; i < spec->num_channels; i++) {
  2247. info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
  2248. info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
  2249. }
  2250. }
  2251. return 0;
  2252. }
  2253. EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
  2254. /*
  2255. * IEEE80211 stack callback functions.
  2256. */
  2257. static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
  2258. u32 *iv32, u16 *iv16)
  2259. {
  2260. struct rt2x00_dev *rt2x00dev = hw->priv;
  2261. struct mac_iveiv_entry iveiv_entry;
  2262. u32 offset;
  2263. offset = MAC_IVEIV_ENTRY(hw_key_idx);
  2264. rt2800_register_multiread(rt2x00dev, offset,
  2265. &iveiv_entry, sizeof(iveiv_entry));
  2266. memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
  2267. memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
  2268. }
  2269. static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
  2270. {
  2271. struct rt2x00_dev *rt2x00dev = hw->priv;
  2272. u32 reg;
  2273. bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
  2274. rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
  2275. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
  2276. rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
  2277. rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
  2278. rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
  2279. rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
  2280. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  2281. rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
  2282. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  2283. rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
  2284. rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
  2285. rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
  2286. rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
  2287. rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
  2288. rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
  2289. rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
  2290. rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
  2291. rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
  2292. rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
  2293. rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
  2294. rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
  2295. return 0;
  2296. }
  2297. static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
  2298. const struct ieee80211_tx_queue_params *params)
  2299. {
  2300. struct rt2x00_dev *rt2x00dev = hw->priv;
  2301. struct data_queue *queue;
  2302. struct rt2x00_field32 field;
  2303. int retval;
  2304. u32 reg;
  2305. u32 offset;
  2306. /*
  2307. * First pass the configuration through rt2x00lib, that will
  2308. * update the queue settings and validate the input. After that
  2309. * we are free to update the registers based on the value
  2310. * in the queue parameter.
  2311. */
  2312. retval = rt2x00mac_conf_tx(hw, queue_idx, params);
  2313. if (retval)
  2314. return retval;
  2315. /*
  2316. * We only need to perform additional register initialization
  2317. * for WMM queues/
  2318. */
  2319. if (queue_idx >= 4)
  2320. return 0;
  2321. queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
  2322. /* Update WMM TXOP register */
  2323. offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
  2324. field.bit_offset = (queue_idx & 1) * 16;
  2325. field.bit_mask = 0xffff << field.bit_offset;
  2326. rt2800_register_read(rt2x00dev, offset, &reg);
  2327. rt2x00_set_field32(&reg, field, queue->txop);
  2328. rt2800_register_write(rt2x00dev, offset, reg);
  2329. /* Update WMM registers */
  2330. field.bit_offset = queue_idx * 4;
  2331. field.bit_mask = 0xf << field.bit_offset;
  2332. rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
  2333. rt2x00_set_field32(&reg, field, queue->aifs);
  2334. rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
  2335. rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
  2336. rt2x00_set_field32(&reg, field, queue->cw_min);
  2337. rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
  2338. rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
  2339. rt2x00_set_field32(&reg, field, queue->cw_max);
  2340. rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
  2341. /* Update EDCA registers */
  2342. offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
  2343. rt2800_register_read(rt2x00dev, offset, &reg);
  2344. rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
  2345. rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
  2346. rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
  2347. rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
  2348. rt2800_register_write(rt2x00dev, offset, reg);
  2349. return 0;
  2350. }
  2351. static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
  2352. {
  2353. struct rt2x00_dev *rt2x00dev = hw->priv;
  2354. u64 tsf;
  2355. u32 reg;
  2356. rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
  2357. tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
  2358. rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
  2359. tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
  2360. return tsf;
  2361. }
  2362. static int rt2800_ampdu_action(struct ieee80211_hw *hw,
  2363. struct ieee80211_vif *vif,
  2364. enum ieee80211_ampdu_mlme_action action,
  2365. struct ieee80211_sta *sta,
  2366. u16 tid, u16 *ssn)
  2367. {
  2368. struct rt2x00_dev *rt2x00dev = hw->priv;
  2369. int ret = 0;
  2370. switch (action) {
  2371. case IEEE80211_AMPDU_RX_START:
  2372. case IEEE80211_AMPDU_RX_STOP:
  2373. /* we don't support RX aggregation yet */
  2374. ret = -ENOTSUPP;
  2375. break;
  2376. case IEEE80211_AMPDU_TX_START:
  2377. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  2378. break;
  2379. case IEEE80211_AMPDU_TX_STOP:
  2380. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  2381. break;
  2382. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2383. break;
  2384. default:
  2385. WARNING(rt2x00dev, "Unknown AMPDU action\n");
  2386. }
  2387. return ret;
  2388. }
  2389. const struct ieee80211_ops rt2800_mac80211_ops = {
  2390. .tx = rt2x00mac_tx,
  2391. .start = rt2x00mac_start,
  2392. .stop = rt2x00mac_stop,
  2393. .add_interface = rt2x00mac_add_interface,
  2394. .remove_interface = rt2x00mac_remove_interface,
  2395. .config = rt2x00mac_config,
  2396. .configure_filter = rt2x00mac_configure_filter,
  2397. .set_tim = rt2x00mac_set_tim,
  2398. .set_key = rt2x00mac_set_key,
  2399. .get_stats = rt2x00mac_get_stats,
  2400. .get_tkip_seq = rt2800_get_tkip_seq,
  2401. .set_rts_threshold = rt2800_set_rts_threshold,
  2402. .bss_info_changed = rt2x00mac_bss_info_changed,
  2403. .conf_tx = rt2800_conf_tx,
  2404. .get_tsf = rt2800_get_tsf,
  2405. .rfkill_poll = rt2x00mac_rfkill_poll,
  2406. .ampdu_action = rt2800_ampdu_action,
  2407. };
  2408. EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
  2409. MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
  2410. MODULE_VERSION(DRV_VERSION);
  2411. MODULE_DESCRIPTION("Ralink RT2800 library");
  2412. MODULE_LICENSE("GPL");