rt2400pci.c 48 KB

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  1. /*
  2. Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2400pci
  19. Abstract: rt2400pci device specific routines.
  20. Supported chipsets: RT2460.
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/init.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/eeprom_93cx6.h>
  29. #include <linux/slab.h>
  30. #include "rt2x00.h"
  31. #include "rt2x00pci.h"
  32. #include "rt2400pci.h"
  33. /*
  34. * Register access.
  35. * All access to the CSR registers will go through the methods
  36. * rt2x00pci_register_read and rt2x00pci_register_write.
  37. * BBP and RF register require indirect register access,
  38. * and use the CSR registers BBPCSR and RFCSR to achieve this.
  39. * These indirect registers work with busy bits,
  40. * and we will try maximal REGISTER_BUSY_COUNT times to access
  41. * the register while taking a REGISTER_BUSY_DELAY us delay
  42. * between each attampt. When the busy bit is still set at that time,
  43. * the access attempt is considered to have failed,
  44. * and we will print an error.
  45. */
  46. #define WAIT_FOR_BBP(__dev, __reg) \
  47. rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
  48. #define WAIT_FOR_RF(__dev, __reg) \
  49. rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
  50. static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  51. const unsigned int word, const u8 value)
  52. {
  53. u32 reg;
  54. mutex_lock(&rt2x00dev->csr_mutex);
  55. /*
  56. * Wait until the BBP becomes available, afterwards we
  57. * can safely write the new data into the register.
  58. */
  59. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  60. reg = 0;
  61. rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  62. rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  63. rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  64. rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  65. rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  66. }
  67. mutex_unlock(&rt2x00dev->csr_mutex);
  68. }
  69. static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  70. const unsigned int word, u8 *value)
  71. {
  72. u32 reg;
  73. mutex_lock(&rt2x00dev->csr_mutex);
  74. /*
  75. * Wait until the BBP becomes available, afterwards we
  76. * can safely write the read request into the register.
  77. * After the data has been written, we wait until hardware
  78. * returns the correct value, if at any time the register
  79. * doesn't become available in time, reg will be 0xffffffff
  80. * which means we return 0xff to the caller.
  81. */
  82. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  83. reg = 0;
  84. rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  85. rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  86. rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
  87. rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  88. WAIT_FOR_BBP(rt2x00dev, &reg);
  89. }
  90. *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
  91. mutex_unlock(&rt2x00dev->csr_mutex);
  92. }
  93. static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
  94. const unsigned int word, const u32 value)
  95. {
  96. u32 reg;
  97. mutex_lock(&rt2x00dev->csr_mutex);
  98. /*
  99. * Wait until the RF becomes available, afterwards we
  100. * can safely write the new data into the register.
  101. */
  102. if (WAIT_FOR_RF(rt2x00dev, &reg)) {
  103. reg = 0;
  104. rt2x00_set_field32(&reg, RFCSR_VALUE, value);
  105. rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
  106. rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
  107. rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
  108. rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
  109. rt2x00_rf_write(rt2x00dev, word, value);
  110. }
  111. mutex_unlock(&rt2x00dev->csr_mutex);
  112. }
  113. static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  114. {
  115. struct rt2x00_dev *rt2x00dev = eeprom->data;
  116. u32 reg;
  117. rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
  118. eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
  119. eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
  120. eeprom->reg_data_clock =
  121. !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
  122. eeprom->reg_chip_select =
  123. !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
  124. }
  125. static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
  126. {
  127. struct rt2x00_dev *rt2x00dev = eeprom->data;
  128. u32 reg = 0;
  129. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
  130. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
  131. rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
  132. !!eeprom->reg_data_clock);
  133. rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
  134. !!eeprom->reg_chip_select);
  135. rt2x00pci_register_write(rt2x00dev, CSR21, reg);
  136. }
  137. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  138. static const struct rt2x00debug rt2400pci_rt2x00debug = {
  139. .owner = THIS_MODULE,
  140. .csr = {
  141. .read = rt2x00pci_register_read,
  142. .write = rt2x00pci_register_write,
  143. .flags = RT2X00DEBUGFS_OFFSET,
  144. .word_base = CSR_REG_BASE,
  145. .word_size = sizeof(u32),
  146. .word_count = CSR_REG_SIZE / sizeof(u32),
  147. },
  148. .eeprom = {
  149. .read = rt2x00_eeprom_read,
  150. .write = rt2x00_eeprom_write,
  151. .word_base = EEPROM_BASE,
  152. .word_size = sizeof(u16),
  153. .word_count = EEPROM_SIZE / sizeof(u16),
  154. },
  155. .bbp = {
  156. .read = rt2400pci_bbp_read,
  157. .write = rt2400pci_bbp_write,
  158. .word_base = BBP_BASE,
  159. .word_size = sizeof(u8),
  160. .word_count = BBP_SIZE / sizeof(u8),
  161. },
  162. .rf = {
  163. .read = rt2x00_rf_read,
  164. .write = rt2400pci_rf_write,
  165. .word_base = RF_BASE,
  166. .word_size = sizeof(u32),
  167. .word_count = RF_SIZE / sizeof(u32),
  168. },
  169. };
  170. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  171. static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  172. {
  173. u32 reg;
  174. rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
  175. return rt2x00_get_field32(reg, GPIOCSR_BIT0);
  176. }
  177. #ifdef CONFIG_RT2X00_LIB_LEDS
  178. static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
  179. enum led_brightness brightness)
  180. {
  181. struct rt2x00_led *led =
  182. container_of(led_cdev, struct rt2x00_led, led_dev);
  183. unsigned int enabled = brightness != LED_OFF;
  184. u32 reg;
  185. rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
  186. if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
  187. rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
  188. else if (led->type == LED_TYPE_ACTIVITY)
  189. rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
  190. rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
  191. }
  192. static int rt2400pci_blink_set(struct led_classdev *led_cdev,
  193. unsigned long *delay_on,
  194. unsigned long *delay_off)
  195. {
  196. struct rt2x00_led *led =
  197. container_of(led_cdev, struct rt2x00_led, led_dev);
  198. u32 reg;
  199. rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
  200. rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
  201. rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
  202. rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
  203. return 0;
  204. }
  205. static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
  206. struct rt2x00_led *led,
  207. enum led_type type)
  208. {
  209. led->rt2x00dev = rt2x00dev;
  210. led->type = type;
  211. led->led_dev.brightness_set = rt2400pci_brightness_set;
  212. led->led_dev.blink_set = rt2400pci_blink_set;
  213. led->flags = LED_INITIALIZED;
  214. }
  215. #endif /* CONFIG_RT2X00_LIB_LEDS */
  216. /*
  217. * Configuration handlers.
  218. */
  219. static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
  220. const unsigned int filter_flags)
  221. {
  222. u32 reg;
  223. /*
  224. * Start configuration steps.
  225. * Note that the version error will always be dropped
  226. * since there is no filter for it at this time.
  227. */
  228. rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
  229. rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
  230. !(filter_flags & FIF_FCSFAIL));
  231. rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
  232. !(filter_flags & FIF_PLCPFAIL));
  233. rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
  234. !(filter_flags & FIF_CONTROL));
  235. rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
  236. !(filter_flags & FIF_PROMISC_IN_BSS));
  237. rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
  238. !(filter_flags & FIF_PROMISC_IN_BSS) &&
  239. !rt2x00dev->intf_ap_count);
  240. rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
  241. rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
  242. }
  243. static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
  244. struct rt2x00_intf *intf,
  245. struct rt2x00intf_conf *conf,
  246. const unsigned int flags)
  247. {
  248. unsigned int bcn_preload;
  249. u32 reg;
  250. if (flags & CONFIG_UPDATE_TYPE) {
  251. /*
  252. * Enable beacon config
  253. */
  254. bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
  255. rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
  256. rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
  257. rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
  258. /*
  259. * Enable synchronisation.
  260. */
  261. rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
  262. rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
  263. rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
  264. rt2x00_set_field32(&reg, CSR14_TBCN, 1);
  265. rt2x00pci_register_write(rt2x00dev, CSR14, reg);
  266. }
  267. if (flags & CONFIG_UPDATE_MAC)
  268. rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
  269. conf->mac, sizeof(conf->mac));
  270. if (flags & CONFIG_UPDATE_BSSID)
  271. rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
  272. conf->bssid, sizeof(conf->bssid));
  273. }
  274. static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
  275. struct rt2x00lib_erp *erp)
  276. {
  277. int preamble_mask;
  278. u32 reg;
  279. /*
  280. * When short preamble is enabled, we should set bit 0x08
  281. */
  282. preamble_mask = erp->short_preamble << 3;
  283. rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
  284. rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
  285. rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
  286. rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
  287. rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
  288. rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
  289. rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
  290. rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
  291. rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
  292. rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
  293. rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
  294. rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
  295. rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
  296. rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
  297. rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
  298. rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
  299. rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
  300. rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
  301. rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
  302. rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
  303. rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
  304. rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
  305. rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
  306. rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
  307. rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
  308. rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
  309. rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
  310. rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
  311. rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
  312. rt2x00pci_register_write(rt2x00dev, CSR11, reg);
  313. rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
  314. rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
  315. rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
  316. rt2x00pci_register_write(rt2x00dev, CSR12, reg);
  317. rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
  318. rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
  319. rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
  320. rt2x00pci_register_write(rt2x00dev, CSR18, reg);
  321. rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
  322. rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
  323. rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
  324. rt2x00pci_register_write(rt2x00dev, CSR19, reg);
  325. }
  326. static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
  327. struct antenna_setup *ant)
  328. {
  329. u8 r1;
  330. u8 r4;
  331. /*
  332. * We should never come here because rt2x00lib is supposed
  333. * to catch this and send us the correct antenna explicitely.
  334. */
  335. BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
  336. ant->tx == ANTENNA_SW_DIVERSITY);
  337. rt2400pci_bbp_read(rt2x00dev, 4, &r4);
  338. rt2400pci_bbp_read(rt2x00dev, 1, &r1);
  339. /*
  340. * Configure the TX antenna.
  341. */
  342. switch (ant->tx) {
  343. case ANTENNA_HW_DIVERSITY:
  344. rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
  345. break;
  346. case ANTENNA_A:
  347. rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
  348. break;
  349. case ANTENNA_B:
  350. default:
  351. rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
  352. break;
  353. }
  354. /*
  355. * Configure the RX antenna.
  356. */
  357. switch (ant->rx) {
  358. case ANTENNA_HW_DIVERSITY:
  359. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
  360. break;
  361. case ANTENNA_A:
  362. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
  363. break;
  364. case ANTENNA_B:
  365. default:
  366. rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
  367. break;
  368. }
  369. rt2400pci_bbp_write(rt2x00dev, 4, r4);
  370. rt2400pci_bbp_write(rt2x00dev, 1, r1);
  371. }
  372. static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
  373. struct rf_channel *rf)
  374. {
  375. /*
  376. * Switch on tuning bits.
  377. */
  378. rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
  379. rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
  380. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  381. rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
  382. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  383. /*
  384. * RF2420 chipset don't need any additional actions.
  385. */
  386. if (rt2x00_rf(rt2x00dev, RF2420))
  387. return;
  388. /*
  389. * For the RT2421 chipsets we need to write an invalid
  390. * reference clock rate to activate auto_tune.
  391. * After that we set the value back to the correct channel.
  392. */
  393. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  394. rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
  395. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  396. msleep(1);
  397. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  398. rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
  399. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  400. msleep(1);
  401. /*
  402. * Switch off tuning bits.
  403. */
  404. rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
  405. rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
  406. rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
  407. rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
  408. /*
  409. * Clear false CRC during channel switch.
  410. */
  411. rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
  412. }
  413. static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
  414. {
  415. rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
  416. }
  417. static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
  418. struct rt2x00lib_conf *libconf)
  419. {
  420. u32 reg;
  421. rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
  422. rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
  423. libconf->conf->long_frame_max_tx_count);
  424. rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
  425. libconf->conf->short_frame_max_tx_count);
  426. rt2x00pci_register_write(rt2x00dev, CSR11, reg);
  427. }
  428. static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
  429. struct rt2x00lib_conf *libconf)
  430. {
  431. enum dev_state state =
  432. (libconf->conf->flags & IEEE80211_CONF_PS) ?
  433. STATE_SLEEP : STATE_AWAKE;
  434. u32 reg;
  435. if (state == STATE_SLEEP) {
  436. rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
  437. rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
  438. (rt2x00dev->beacon_int - 20) * 16);
  439. rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
  440. libconf->conf->listen_interval - 1);
  441. /* We must first disable autowake before it can be enabled */
  442. rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
  443. rt2x00pci_register_write(rt2x00dev, CSR20, reg);
  444. rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
  445. rt2x00pci_register_write(rt2x00dev, CSR20, reg);
  446. } else {
  447. rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
  448. rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
  449. rt2x00pci_register_write(rt2x00dev, CSR20, reg);
  450. }
  451. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  452. }
  453. static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
  454. struct rt2x00lib_conf *libconf,
  455. const unsigned int flags)
  456. {
  457. if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
  458. rt2400pci_config_channel(rt2x00dev, &libconf->rf);
  459. if (flags & IEEE80211_CONF_CHANGE_POWER)
  460. rt2400pci_config_txpower(rt2x00dev,
  461. libconf->conf->power_level);
  462. if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
  463. rt2400pci_config_retry_limit(rt2x00dev, libconf);
  464. if (flags & IEEE80211_CONF_CHANGE_PS)
  465. rt2400pci_config_ps(rt2x00dev, libconf);
  466. }
  467. static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
  468. const int cw_min, const int cw_max)
  469. {
  470. u32 reg;
  471. rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
  472. rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
  473. rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
  474. rt2x00pci_register_write(rt2x00dev, CSR11, reg);
  475. }
  476. /*
  477. * Link tuning
  478. */
  479. static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
  480. struct link_qual *qual)
  481. {
  482. u32 reg;
  483. u8 bbp;
  484. /*
  485. * Update FCS error count from register.
  486. */
  487. rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
  488. qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
  489. /*
  490. * Update False CCA count from register.
  491. */
  492. rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
  493. qual->false_cca = bbp;
  494. }
  495. static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
  496. struct link_qual *qual, u8 vgc_level)
  497. {
  498. rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
  499. qual->vgc_level = vgc_level;
  500. qual->vgc_level_reg = vgc_level;
  501. }
  502. static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
  503. struct link_qual *qual)
  504. {
  505. rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
  506. }
  507. static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
  508. struct link_qual *qual, const u32 count)
  509. {
  510. /*
  511. * The link tuner should not run longer then 60 seconds,
  512. * and should run once every 2 seconds.
  513. */
  514. if (count > 60 || !(count & 1))
  515. return;
  516. /*
  517. * Base r13 link tuning on the false cca count.
  518. */
  519. if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
  520. rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
  521. else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
  522. rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
  523. }
  524. /*
  525. * Initialization functions.
  526. */
  527. static bool rt2400pci_get_entry_state(struct queue_entry *entry)
  528. {
  529. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  530. u32 word;
  531. if (entry->queue->qid == QID_RX) {
  532. rt2x00_desc_read(entry_priv->desc, 0, &word);
  533. return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
  534. } else {
  535. rt2x00_desc_read(entry_priv->desc, 0, &word);
  536. return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  537. rt2x00_get_field32(word, TXD_W0_VALID));
  538. }
  539. }
  540. static void rt2400pci_clear_entry(struct queue_entry *entry)
  541. {
  542. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  543. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  544. u32 word;
  545. if (entry->queue->qid == QID_RX) {
  546. rt2x00_desc_read(entry_priv->desc, 2, &word);
  547. rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
  548. rt2x00_desc_write(entry_priv->desc, 2, word);
  549. rt2x00_desc_read(entry_priv->desc, 1, &word);
  550. rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
  551. rt2x00_desc_write(entry_priv->desc, 1, word);
  552. rt2x00_desc_read(entry_priv->desc, 0, &word);
  553. rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
  554. rt2x00_desc_write(entry_priv->desc, 0, word);
  555. } else {
  556. rt2x00_desc_read(entry_priv->desc, 0, &word);
  557. rt2x00_set_field32(&word, TXD_W0_VALID, 0);
  558. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
  559. rt2x00_desc_write(entry_priv->desc, 0, word);
  560. }
  561. }
  562. static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
  563. {
  564. struct queue_entry_priv_pci *entry_priv;
  565. u32 reg;
  566. /*
  567. * Initialize registers.
  568. */
  569. rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
  570. rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
  571. rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
  572. rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
  573. rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
  574. rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
  575. entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
  576. rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
  577. rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
  578. entry_priv->desc_dma);
  579. rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
  580. entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
  581. rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
  582. rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
  583. entry_priv->desc_dma);
  584. rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
  585. entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
  586. rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
  587. rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
  588. entry_priv->desc_dma);
  589. rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
  590. entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
  591. rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
  592. rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
  593. entry_priv->desc_dma);
  594. rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
  595. rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
  596. rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
  597. rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
  598. rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
  599. entry_priv = rt2x00dev->rx->entries[0].priv_data;
  600. rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
  601. rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
  602. entry_priv->desc_dma);
  603. rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
  604. return 0;
  605. }
  606. static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
  607. {
  608. u32 reg;
  609. rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
  610. rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
  611. rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
  612. rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
  613. rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
  614. rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
  615. rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
  616. rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
  617. rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
  618. rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
  619. rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
  620. (rt2x00dev->rx->data_size / 128));
  621. rt2x00pci_register_write(rt2x00dev, CSR9, reg);
  622. rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
  623. rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
  624. rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
  625. rt2x00_set_field32(&reg, CSR14_TBCN, 0);
  626. rt2x00_set_field32(&reg, CSR14_TCFP, 0);
  627. rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
  628. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
  629. rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
  630. rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
  631. rt2x00pci_register_write(rt2x00dev, CSR14, reg);
  632. rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
  633. rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
  634. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
  635. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
  636. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
  637. rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
  638. rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
  639. rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
  640. rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
  641. rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
  642. rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
  643. rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
  644. rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
  645. rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
  646. rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
  647. rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
  648. if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
  649. return -EBUSY;
  650. rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
  651. rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
  652. rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
  653. rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
  654. rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
  655. rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
  656. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
  657. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
  658. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
  659. rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
  660. rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
  661. rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
  662. rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
  663. rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
  664. rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
  665. rt2x00pci_register_write(rt2x00dev, CSR1, reg);
  666. rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
  667. rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
  668. rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
  669. rt2x00pci_register_write(rt2x00dev, CSR1, reg);
  670. /*
  671. * We must clear the FCS and FIFO error count.
  672. * These registers are cleared on read,
  673. * so we may pass a useless variable to store the value.
  674. */
  675. rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
  676. rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
  677. return 0;
  678. }
  679. static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
  680. {
  681. unsigned int i;
  682. u8 value;
  683. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  684. rt2400pci_bbp_read(rt2x00dev, 0, &value);
  685. if ((value != 0xff) && (value != 0x00))
  686. return 0;
  687. udelay(REGISTER_BUSY_DELAY);
  688. }
  689. ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
  690. return -EACCES;
  691. }
  692. static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
  693. {
  694. unsigned int i;
  695. u16 eeprom;
  696. u8 reg_id;
  697. u8 value;
  698. if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
  699. return -EACCES;
  700. rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
  701. rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
  702. rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
  703. rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
  704. rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
  705. rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
  706. rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
  707. rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
  708. rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
  709. rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
  710. rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
  711. rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
  712. rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
  713. rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
  714. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  715. rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
  716. if (eeprom != 0xffff && eeprom != 0x0000) {
  717. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  718. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  719. rt2400pci_bbp_write(rt2x00dev, reg_id, value);
  720. }
  721. }
  722. return 0;
  723. }
  724. /*
  725. * Device state switch handlers.
  726. */
  727. static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
  728. enum dev_state state)
  729. {
  730. u32 reg;
  731. rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
  732. rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
  733. (state == STATE_RADIO_RX_OFF) ||
  734. (state == STATE_RADIO_RX_OFF_LINK));
  735. rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
  736. }
  737. static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
  738. enum dev_state state)
  739. {
  740. int mask = (state == STATE_RADIO_IRQ_OFF);
  741. u32 reg;
  742. /*
  743. * When interrupts are being enabled, the interrupt registers
  744. * should clear the register to assure a clean state.
  745. */
  746. if (state == STATE_RADIO_IRQ_ON) {
  747. rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
  748. rt2x00pci_register_write(rt2x00dev, CSR7, reg);
  749. }
  750. /*
  751. * Only toggle the interrupts bits we are going to use.
  752. * Non-checked interrupt bits are disabled by default.
  753. */
  754. rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
  755. rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
  756. rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
  757. rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
  758. rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
  759. rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
  760. rt2x00pci_register_write(rt2x00dev, CSR8, reg);
  761. }
  762. static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
  763. {
  764. /*
  765. * Initialize all registers.
  766. */
  767. if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
  768. rt2400pci_init_registers(rt2x00dev) ||
  769. rt2400pci_init_bbp(rt2x00dev)))
  770. return -EIO;
  771. return 0;
  772. }
  773. static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
  774. {
  775. /*
  776. * Disable power
  777. */
  778. rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
  779. }
  780. static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
  781. enum dev_state state)
  782. {
  783. u32 reg, reg2;
  784. unsigned int i;
  785. char put_to_sleep;
  786. char bbp_state;
  787. char rf_state;
  788. put_to_sleep = (state != STATE_AWAKE);
  789. rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
  790. rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
  791. rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
  792. rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
  793. rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
  794. rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
  795. /*
  796. * Device is not guaranteed to be in the requested state yet.
  797. * We must wait until the register indicates that the
  798. * device has entered the correct state.
  799. */
  800. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  801. rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
  802. bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
  803. rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
  804. if (bbp_state == state && rf_state == state)
  805. return 0;
  806. rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
  807. msleep(10);
  808. }
  809. return -EBUSY;
  810. }
  811. static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
  812. enum dev_state state)
  813. {
  814. int retval = 0;
  815. switch (state) {
  816. case STATE_RADIO_ON:
  817. retval = rt2400pci_enable_radio(rt2x00dev);
  818. break;
  819. case STATE_RADIO_OFF:
  820. rt2400pci_disable_radio(rt2x00dev);
  821. break;
  822. case STATE_RADIO_RX_ON:
  823. case STATE_RADIO_RX_ON_LINK:
  824. case STATE_RADIO_RX_OFF:
  825. case STATE_RADIO_RX_OFF_LINK:
  826. rt2400pci_toggle_rx(rt2x00dev, state);
  827. break;
  828. case STATE_RADIO_IRQ_ON:
  829. case STATE_RADIO_IRQ_OFF:
  830. rt2400pci_toggle_irq(rt2x00dev, state);
  831. break;
  832. case STATE_DEEP_SLEEP:
  833. case STATE_SLEEP:
  834. case STATE_STANDBY:
  835. case STATE_AWAKE:
  836. retval = rt2400pci_set_state(rt2x00dev, state);
  837. break;
  838. default:
  839. retval = -ENOTSUPP;
  840. break;
  841. }
  842. if (unlikely(retval))
  843. ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
  844. state, retval);
  845. return retval;
  846. }
  847. /*
  848. * TX descriptor initialization
  849. */
  850. static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
  851. struct sk_buff *skb,
  852. struct txentry_desc *txdesc)
  853. {
  854. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  855. struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
  856. __le32 *txd = entry_priv->desc;
  857. u32 word;
  858. /*
  859. * Start writing the descriptor words.
  860. */
  861. rt2x00_desc_read(txd, 1, &word);
  862. rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
  863. rt2x00_desc_write(txd, 1, word);
  864. rt2x00_desc_read(txd, 2, &word);
  865. rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
  866. rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
  867. rt2x00_desc_write(txd, 2, word);
  868. rt2x00_desc_read(txd, 3, &word);
  869. rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
  870. rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
  871. rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
  872. rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
  873. rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
  874. rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
  875. rt2x00_desc_write(txd, 3, word);
  876. rt2x00_desc_read(txd, 4, &word);
  877. rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
  878. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
  879. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
  880. rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
  881. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
  882. rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
  883. rt2x00_desc_write(txd, 4, word);
  884. /*
  885. * Writing TXD word 0 must the last to prevent a race condition with
  886. * the device, whereby the device may take hold of the TXD before we
  887. * finished updating it.
  888. */
  889. rt2x00_desc_read(txd, 0, &word);
  890. rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
  891. rt2x00_set_field32(&word, TXD_W0_VALID, 1);
  892. rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
  893. test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  894. rt2x00_set_field32(&word, TXD_W0_ACK,
  895. test_bit(ENTRY_TXD_ACK, &txdesc->flags));
  896. rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
  897. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
  898. rt2x00_set_field32(&word, TXD_W0_RTS,
  899. test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
  900. rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
  901. rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
  902. test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
  903. rt2x00_desc_write(txd, 0, word);
  904. /*
  905. * Register descriptor details in skb frame descriptor.
  906. */
  907. skbdesc->desc = txd;
  908. skbdesc->desc_len = TXD_DESC_SIZE;
  909. }
  910. /*
  911. * TX data initialization
  912. */
  913. static void rt2400pci_write_beacon(struct queue_entry *entry,
  914. struct txentry_desc *txdesc)
  915. {
  916. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  917. u32 reg;
  918. /*
  919. * Disable beaconing while we are reloading the beacon data,
  920. * otherwise we might be sending out invalid data.
  921. */
  922. rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
  923. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
  924. rt2x00pci_register_write(rt2x00dev, CSR14, reg);
  925. rt2x00queue_map_txskb(rt2x00dev, entry->skb);
  926. /*
  927. * Write the TX descriptor for the beacon.
  928. */
  929. rt2400pci_write_tx_desc(rt2x00dev, entry->skb, txdesc);
  930. /*
  931. * Dump beacon to userspace through debugfs.
  932. */
  933. rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
  934. /*
  935. * Enable beaconing again.
  936. */
  937. rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
  938. rt2x00_set_field32(&reg, CSR14_TBCN, 1);
  939. rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
  940. rt2x00pci_register_write(rt2x00dev, CSR14, reg);
  941. }
  942. static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
  943. const enum data_queue_qid queue)
  944. {
  945. u32 reg;
  946. rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
  947. rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
  948. rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
  949. rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
  950. rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
  951. }
  952. static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
  953. const enum data_queue_qid qid)
  954. {
  955. u32 reg;
  956. if (qid == QID_BEACON) {
  957. rt2x00pci_register_write(rt2x00dev, CSR14, 0);
  958. } else {
  959. rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
  960. rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
  961. rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
  962. }
  963. }
  964. /*
  965. * RX control handlers
  966. */
  967. static void rt2400pci_fill_rxdone(struct queue_entry *entry,
  968. struct rxdone_entry_desc *rxdesc)
  969. {
  970. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  971. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  972. u32 word0;
  973. u32 word2;
  974. u32 word3;
  975. u32 word4;
  976. u64 tsf;
  977. u32 rx_low;
  978. u32 rx_high;
  979. rt2x00_desc_read(entry_priv->desc, 0, &word0);
  980. rt2x00_desc_read(entry_priv->desc, 2, &word2);
  981. rt2x00_desc_read(entry_priv->desc, 3, &word3);
  982. rt2x00_desc_read(entry_priv->desc, 4, &word4);
  983. if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
  984. rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
  985. if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
  986. rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
  987. /*
  988. * We only get the lower 32bits from the timestamp,
  989. * to get the full 64bits we must complement it with
  990. * the timestamp from get_tsf().
  991. * Note that when a wraparound of the lower 32bits
  992. * has occurred between the frame arrival and the get_tsf()
  993. * call, we must decrease the higher 32bits with 1 to get
  994. * to correct value.
  995. */
  996. tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
  997. rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
  998. rx_high = upper_32_bits(tsf);
  999. if ((u32)tsf <= rx_low)
  1000. rx_high--;
  1001. /*
  1002. * Obtain the status about this packet.
  1003. * The signal is the PLCP value, and needs to be stripped
  1004. * of the preamble bit (0x08).
  1005. */
  1006. rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
  1007. rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
  1008. rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
  1009. entry->queue->rt2x00dev->rssi_offset;
  1010. rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
  1011. rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
  1012. if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
  1013. rxdesc->dev_flags |= RXDONE_MY_BSS;
  1014. }
  1015. /*
  1016. * Interrupt functions.
  1017. */
  1018. static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
  1019. const enum data_queue_qid queue_idx)
  1020. {
  1021. struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
  1022. struct queue_entry_priv_pci *entry_priv;
  1023. struct queue_entry *entry;
  1024. struct txdone_entry_desc txdesc;
  1025. u32 word;
  1026. while (!rt2x00queue_empty(queue)) {
  1027. entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
  1028. entry_priv = entry->priv_data;
  1029. rt2x00_desc_read(entry_priv->desc, 0, &word);
  1030. if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
  1031. !rt2x00_get_field32(word, TXD_W0_VALID))
  1032. break;
  1033. /*
  1034. * Obtain the status about this packet.
  1035. */
  1036. txdesc.flags = 0;
  1037. switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
  1038. case 0: /* Success */
  1039. case 1: /* Success with retry */
  1040. __set_bit(TXDONE_SUCCESS, &txdesc.flags);
  1041. break;
  1042. case 2: /* Failure, excessive retries */
  1043. __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
  1044. /* Don't break, this is a failed frame! */
  1045. default: /* Failure */
  1046. __set_bit(TXDONE_FAILURE, &txdesc.flags);
  1047. }
  1048. txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
  1049. rt2x00lib_txdone(entry, &txdesc);
  1050. }
  1051. }
  1052. static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
  1053. {
  1054. struct rt2x00_dev *rt2x00dev = dev_instance;
  1055. u32 reg;
  1056. /*
  1057. * Get the interrupt sources & saved to local variable.
  1058. * Write register value back to clear pending interrupts.
  1059. */
  1060. rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
  1061. rt2x00pci_register_write(rt2x00dev, CSR7, reg);
  1062. if (!reg)
  1063. return IRQ_NONE;
  1064. if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  1065. return IRQ_HANDLED;
  1066. /*
  1067. * Handle interrupts, walk through all bits
  1068. * and run the tasks, the bits are checked in order of
  1069. * priority.
  1070. */
  1071. /*
  1072. * 1 - Beacon timer expired interrupt.
  1073. */
  1074. if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
  1075. rt2x00lib_beacondone(rt2x00dev);
  1076. /*
  1077. * 2 - Rx ring done interrupt.
  1078. */
  1079. if (rt2x00_get_field32(reg, CSR7_RXDONE))
  1080. rt2x00pci_rxdone(rt2x00dev);
  1081. /*
  1082. * 3 - Atim ring transmit done interrupt.
  1083. */
  1084. if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
  1085. rt2400pci_txdone(rt2x00dev, QID_ATIM);
  1086. /*
  1087. * 4 - Priority ring transmit done interrupt.
  1088. */
  1089. if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
  1090. rt2400pci_txdone(rt2x00dev, QID_AC_BE);
  1091. /*
  1092. * 5 - Tx ring transmit done interrupt.
  1093. */
  1094. if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
  1095. rt2400pci_txdone(rt2x00dev, QID_AC_BK);
  1096. return IRQ_HANDLED;
  1097. }
  1098. /*
  1099. * Device probe functions.
  1100. */
  1101. static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  1102. {
  1103. struct eeprom_93cx6 eeprom;
  1104. u32 reg;
  1105. u16 word;
  1106. u8 *mac;
  1107. rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
  1108. eeprom.data = rt2x00dev;
  1109. eeprom.register_read = rt2400pci_eepromregister_read;
  1110. eeprom.register_write = rt2400pci_eepromregister_write;
  1111. eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
  1112. PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
  1113. eeprom.reg_data_in = 0;
  1114. eeprom.reg_data_out = 0;
  1115. eeprom.reg_data_clock = 0;
  1116. eeprom.reg_chip_select = 0;
  1117. eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
  1118. EEPROM_SIZE / sizeof(u16));
  1119. /*
  1120. * Start validation of the data that has been read.
  1121. */
  1122. mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  1123. if (!is_valid_ether_addr(mac)) {
  1124. random_ether_addr(mac);
  1125. EEPROM(rt2x00dev, "MAC: %pM\n", mac);
  1126. }
  1127. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
  1128. if (word == 0xffff) {
  1129. ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
  1130. return -EINVAL;
  1131. }
  1132. return 0;
  1133. }
  1134. static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
  1135. {
  1136. u32 reg;
  1137. u16 value;
  1138. u16 eeprom;
  1139. /*
  1140. * Read EEPROM word for configuration.
  1141. */
  1142. rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
  1143. /*
  1144. * Identify RF chipset.
  1145. */
  1146. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
  1147. rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
  1148. rt2x00_set_chip(rt2x00dev, RT2460, value,
  1149. rt2x00_get_field32(reg, CSR0_REVISION));
  1150. if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
  1151. ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
  1152. return -ENODEV;
  1153. }
  1154. /*
  1155. * Identify default antenna configuration.
  1156. */
  1157. rt2x00dev->default_ant.tx =
  1158. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
  1159. rt2x00dev->default_ant.rx =
  1160. rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
  1161. /*
  1162. * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
  1163. * I am not 100% sure about this, but the legacy drivers do not
  1164. * indicate antenna swapping in software is required when
  1165. * diversity is enabled.
  1166. */
  1167. if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
  1168. rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
  1169. if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
  1170. rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
  1171. /*
  1172. * Store led mode, for correct led behaviour.
  1173. */
  1174. #ifdef CONFIG_RT2X00_LIB_LEDS
  1175. value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
  1176. rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
  1177. if (value == LED_MODE_TXRX_ACTIVITY ||
  1178. value == LED_MODE_DEFAULT ||
  1179. value == LED_MODE_ASUS)
  1180. rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
  1181. LED_TYPE_ACTIVITY);
  1182. #endif /* CONFIG_RT2X00_LIB_LEDS */
  1183. /*
  1184. * Detect if this device has an hardware controlled radio.
  1185. */
  1186. if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
  1187. __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
  1188. /*
  1189. * Check if the BBP tuning should be enabled.
  1190. */
  1191. if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
  1192. __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
  1193. return 0;
  1194. }
  1195. /*
  1196. * RF value list for RF2420 & RF2421
  1197. * Supports: 2.4 GHz
  1198. */
  1199. static const struct rf_channel rf_vals_b[] = {
  1200. { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
  1201. { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
  1202. { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
  1203. { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
  1204. { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
  1205. { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
  1206. { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
  1207. { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
  1208. { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
  1209. { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
  1210. { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
  1211. { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
  1212. { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
  1213. { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
  1214. };
  1215. static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  1216. {
  1217. struct hw_mode_spec *spec = &rt2x00dev->spec;
  1218. struct channel_info *info;
  1219. char *tx_power;
  1220. unsigned int i;
  1221. /*
  1222. * Initialize all hw fields.
  1223. */
  1224. rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  1225. IEEE80211_HW_SIGNAL_DBM |
  1226. IEEE80211_HW_SUPPORTS_PS |
  1227. IEEE80211_HW_PS_NULLFUNC_STACK;
  1228. SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
  1229. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  1230. rt2x00_eeprom_addr(rt2x00dev,
  1231. EEPROM_MAC_ADDR_0));
  1232. /*
  1233. * Initialize hw_mode information.
  1234. */
  1235. spec->supported_bands = SUPPORT_BAND_2GHZ;
  1236. spec->supported_rates = SUPPORT_RATE_CCK;
  1237. spec->num_channels = ARRAY_SIZE(rf_vals_b);
  1238. spec->channels = rf_vals_b;
  1239. /*
  1240. * Create channel information array
  1241. */
  1242. info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
  1243. if (!info)
  1244. return -ENOMEM;
  1245. spec->channels_info = info;
  1246. tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
  1247. for (i = 0; i < 14; i++)
  1248. info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
  1249. return 0;
  1250. }
  1251. static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
  1252. {
  1253. int retval;
  1254. /*
  1255. * Allocate eeprom data.
  1256. */
  1257. retval = rt2400pci_validate_eeprom(rt2x00dev);
  1258. if (retval)
  1259. return retval;
  1260. retval = rt2400pci_init_eeprom(rt2x00dev);
  1261. if (retval)
  1262. return retval;
  1263. /*
  1264. * Initialize hw specifications.
  1265. */
  1266. retval = rt2400pci_probe_hw_mode(rt2x00dev);
  1267. if (retval)
  1268. return retval;
  1269. /*
  1270. * This device requires the atim queue and DMA-mapped skbs.
  1271. */
  1272. __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
  1273. __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
  1274. /*
  1275. * Set the rssi offset.
  1276. */
  1277. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  1278. return 0;
  1279. }
  1280. /*
  1281. * IEEE80211 stack callback functions.
  1282. */
  1283. static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1284. const struct ieee80211_tx_queue_params *params)
  1285. {
  1286. struct rt2x00_dev *rt2x00dev = hw->priv;
  1287. /*
  1288. * We don't support variating cw_min and cw_max variables
  1289. * per queue. So by default we only configure the TX queue,
  1290. * and ignore all other configurations.
  1291. */
  1292. if (queue != 0)
  1293. return -EINVAL;
  1294. if (rt2x00mac_conf_tx(hw, queue, params))
  1295. return -EINVAL;
  1296. /*
  1297. * Write configuration to register.
  1298. */
  1299. rt2400pci_config_cw(rt2x00dev,
  1300. rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
  1301. return 0;
  1302. }
  1303. static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
  1304. {
  1305. struct rt2x00_dev *rt2x00dev = hw->priv;
  1306. u64 tsf;
  1307. u32 reg;
  1308. rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
  1309. tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
  1310. rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
  1311. tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
  1312. return tsf;
  1313. }
  1314. static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
  1315. {
  1316. struct rt2x00_dev *rt2x00dev = hw->priv;
  1317. u32 reg;
  1318. rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
  1319. return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
  1320. }
  1321. static const struct ieee80211_ops rt2400pci_mac80211_ops = {
  1322. .tx = rt2x00mac_tx,
  1323. .start = rt2x00mac_start,
  1324. .stop = rt2x00mac_stop,
  1325. .add_interface = rt2x00mac_add_interface,
  1326. .remove_interface = rt2x00mac_remove_interface,
  1327. .config = rt2x00mac_config,
  1328. .configure_filter = rt2x00mac_configure_filter,
  1329. .set_tim = rt2x00mac_set_tim,
  1330. .get_stats = rt2x00mac_get_stats,
  1331. .bss_info_changed = rt2x00mac_bss_info_changed,
  1332. .conf_tx = rt2400pci_conf_tx,
  1333. .get_tsf = rt2400pci_get_tsf,
  1334. .tx_last_beacon = rt2400pci_tx_last_beacon,
  1335. .rfkill_poll = rt2x00mac_rfkill_poll,
  1336. };
  1337. static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
  1338. .irq_handler = rt2400pci_interrupt,
  1339. .probe_hw = rt2400pci_probe_hw,
  1340. .initialize = rt2x00pci_initialize,
  1341. .uninitialize = rt2x00pci_uninitialize,
  1342. .get_entry_state = rt2400pci_get_entry_state,
  1343. .clear_entry = rt2400pci_clear_entry,
  1344. .set_device_state = rt2400pci_set_device_state,
  1345. .rfkill_poll = rt2400pci_rfkill_poll,
  1346. .link_stats = rt2400pci_link_stats,
  1347. .reset_tuner = rt2400pci_reset_tuner,
  1348. .link_tuner = rt2400pci_link_tuner,
  1349. .write_tx_desc = rt2400pci_write_tx_desc,
  1350. .write_beacon = rt2400pci_write_beacon,
  1351. .kick_tx_queue = rt2400pci_kick_tx_queue,
  1352. .kill_tx_queue = rt2400pci_kill_tx_queue,
  1353. .fill_rxdone = rt2400pci_fill_rxdone,
  1354. .config_filter = rt2400pci_config_filter,
  1355. .config_intf = rt2400pci_config_intf,
  1356. .config_erp = rt2400pci_config_erp,
  1357. .config_ant = rt2400pci_config_ant,
  1358. .config = rt2400pci_config,
  1359. };
  1360. static const struct data_queue_desc rt2400pci_queue_rx = {
  1361. .entry_num = RX_ENTRIES,
  1362. .data_size = DATA_FRAME_SIZE,
  1363. .desc_size = RXD_DESC_SIZE,
  1364. .priv_size = sizeof(struct queue_entry_priv_pci),
  1365. };
  1366. static const struct data_queue_desc rt2400pci_queue_tx = {
  1367. .entry_num = TX_ENTRIES,
  1368. .data_size = DATA_FRAME_SIZE,
  1369. .desc_size = TXD_DESC_SIZE,
  1370. .priv_size = sizeof(struct queue_entry_priv_pci),
  1371. };
  1372. static const struct data_queue_desc rt2400pci_queue_bcn = {
  1373. .entry_num = BEACON_ENTRIES,
  1374. .data_size = MGMT_FRAME_SIZE,
  1375. .desc_size = TXD_DESC_SIZE,
  1376. .priv_size = sizeof(struct queue_entry_priv_pci),
  1377. };
  1378. static const struct data_queue_desc rt2400pci_queue_atim = {
  1379. .entry_num = ATIM_ENTRIES,
  1380. .data_size = DATA_FRAME_SIZE,
  1381. .desc_size = TXD_DESC_SIZE,
  1382. .priv_size = sizeof(struct queue_entry_priv_pci),
  1383. };
  1384. static const struct rt2x00_ops rt2400pci_ops = {
  1385. .name = KBUILD_MODNAME,
  1386. .max_sta_intf = 1,
  1387. .max_ap_intf = 1,
  1388. .eeprom_size = EEPROM_SIZE,
  1389. .rf_size = RF_SIZE,
  1390. .tx_queues = NUM_TX_QUEUES,
  1391. .extra_tx_headroom = 0,
  1392. .rx = &rt2400pci_queue_rx,
  1393. .tx = &rt2400pci_queue_tx,
  1394. .bcn = &rt2400pci_queue_bcn,
  1395. .atim = &rt2400pci_queue_atim,
  1396. .lib = &rt2400pci_rt2x00_ops,
  1397. .hw = &rt2400pci_mac80211_ops,
  1398. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  1399. .debugfs = &rt2400pci_rt2x00debug,
  1400. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  1401. };
  1402. /*
  1403. * RT2400pci module information.
  1404. */
  1405. static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
  1406. { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
  1407. { 0, }
  1408. };
  1409. MODULE_AUTHOR(DRV_PROJECT);
  1410. MODULE_VERSION(DRV_VERSION);
  1411. MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
  1412. MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
  1413. MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
  1414. MODULE_LICENSE("GPL");
  1415. static struct pci_driver rt2400pci_driver = {
  1416. .name = KBUILD_MODNAME,
  1417. .id_table = rt2400pci_device_table,
  1418. .probe = rt2x00pci_probe,
  1419. .remove = __devexit_p(rt2x00pci_remove),
  1420. .suspend = rt2x00pci_suspend,
  1421. .resume = rt2x00pci_resume,
  1422. };
  1423. static int __init rt2400pci_init(void)
  1424. {
  1425. return pci_register_driver(&rt2400pci_driver);
  1426. }
  1427. static void __exit rt2400pci_exit(void)
  1428. {
  1429. pci_unregister_driver(&rt2400pci_driver);
  1430. }
  1431. module_init(rt2400pci_init);
  1432. module_exit(rt2400pci_exit);