main.c 50 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. #include "btcoex.h"
  19. static void ath_cache_conf_rate(struct ath_softc *sc,
  20. struct ieee80211_conf *conf)
  21. {
  22. switch (conf->channel->band) {
  23. case IEEE80211_BAND_2GHZ:
  24. if (conf_is_ht20(conf))
  25. sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
  26. else if (conf_is_ht40_minus(conf))
  27. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
  28. else if (conf_is_ht40_plus(conf))
  29. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
  30. else
  31. sc->cur_rate_mode = ATH9K_MODE_11G;
  32. break;
  33. case IEEE80211_BAND_5GHZ:
  34. if (conf_is_ht20(conf))
  35. sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
  36. else if (conf_is_ht40_minus(conf))
  37. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
  38. else if (conf_is_ht40_plus(conf))
  39. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
  40. else
  41. sc->cur_rate_mode = ATH9K_MODE_11A;
  42. break;
  43. default:
  44. BUG_ON(1);
  45. break;
  46. }
  47. }
  48. static void ath_update_txpow(struct ath_softc *sc)
  49. {
  50. struct ath_hw *ah = sc->sc_ah;
  51. if (sc->curtxpow != sc->config.txpowlimit) {
  52. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
  53. /* read back in case value is clamped */
  54. sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
  55. }
  56. }
  57. static u8 parse_mpdudensity(u8 mpdudensity)
  58. {
  59. /*
  60. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  61. * 0 for no restriction
  62. * 1 for 1/4 us
  63. * 2 for 1/2 us
  64. * 3 for 1 us
  65. * 4 for 2 us
  66. * 5 for 4 us
  67. * 6 for 8 us
  68. * 7 for 16 us
  69. */
  70. switch (mpdudensity) {
  71. case 0:
  72. return 0;
  73. case 1:
  74. case 2:
  75. case 3:
  76. /* Our lower layer calculations limit our precision to
  77. 1 microsecond */
  78. return 1;
  79. case 4:
  80. return 2;
  81. case 5:
  82. return 4;
  83. case 6:
  84. return 8;
  85. case 7:
  86. return 16;
  87. default:
  88. return 0;
  89. }
  90. }
  91. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  92. struct ieee80211_hw *hw)
  93. {
  94. struct ieee80211_channel *curchan = hw->conf.channel;
  95. struct ath9k_channel *channel;
  96. u8 chan_idx;
  97. chan_idx = curchan->hw_value;
  98. channel = &sc->sc_ah->channels[chan_idx];
  99. ath9k_update_ichannel(sc, hw, channel);
  100. return channel;
  101. }
  102. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  103. {
  104. unsigned long flags;
  105. bool ret;
  106. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  107. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  108. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  109. return ret;
  110. }
  111. void ath9k_ps_wakeup(struct ath_softc *sc)
  112. {
  113. unsigned long flags;
  114. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  115. if (++sc->ps_usecount != 1)
  116. goto unlock;
  117. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  118. unlock:
  119. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  120. }
  121. void ath9k_ps_restore(struct ath_softc *sc)
  122. {
  123. unsigned long flags;
  124. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  125. if (--sc->ps_usecount != 0)
  126. goto unlock;
  127. if (sc->ps_idle)
  128. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  129. else if (sc->ps_enabled &&
  130. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  131. PS_WAIT_FOR_CAB |
  132. PS_WAIT_FOR_PSPOLL_DATA |
  133. PS_WAIT_FOR_TX_ACK)))
  134. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  135. unlock:
  136. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  137. }
  138. /*
  139. * Set/change channels. If the channel is really being changed, it's done
  140. * by reseting the chip. To accomplish this we must first cleanup any pending
  141. * DMA, then restart stuff.
  142. */
  143. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  144. struct ath9k_channel *hchan)
  145. {
  146. struct ath_hw *ah = sc->sc_ah;
  147. struct ath_common *common = ath9k_hw_common(ah);
  148. struct ieee80211_conf *conf = &common->hw->conf;
  149. bool fastcc = true, stopped;
  150. struct ieee80211_channel *channel = hw->conf.channel;
  151. int r;
  152. if (sc->sc_flags & SC_OP_INVALID)
  153. return -EIO;
  154. ath9k_ps_wakeup(sc);
  155. /*
  156. * This is only performed if the channel settings have
  157. * actually changed.
  158. *
  159. * To switch channels clear any pending DMA operations;
  160. * wait long enough for the RX fifo to drain, reset the
  161. * hardware at the new frequency, and then re-enable
  162. * the relevant bits of the h/w.
  163. */
  164. ath9k_hw_set_interrupts(ah, 0);
  165. ath_drain_all_txq(sc, false);
  166. stopped = ath_stoprecv(sc);
  167. /* XXX: do not flush receive queue here. We don't want
  168. * to flush data frames already in queue because of
  169. * changing channel. */
  170. if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
  171. fastcc = false;
  172. ath_print(common, ATH_DBG_CONFIG,
  173. "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
  174. sc->sc_ah->curchan->channel,
  175. channel->center_freq, conf_is_ht40(conf));
  176. spin_lock_bh(&sc->sc_resetlock);
  177. r = ath9k_hw_reset(ah, hchan, fastcc);
  178. if (r) {
  179. ath_print(common, ATH_DBG_FATAL,
  180. "Unable to reset channel (%u MHz), "
  181. "reset status %d\n",
  182. channel->center_freq, r);
  183. spin_unlock_bh(&sc->sc_resetlock);
  184. goto ps_restore;
  185. }
  186. spin_unlock_bh(&sc->sc_resetlock);
  187. sc->sc_flags &= ~SC_OP_FULL_RESET;
  188. if (ath_startrecv(sc) != 0) {
  189. ath_print(common, ATH_DBG_FATAL,
  190. "Unable to restart recv logic\n");
  191. r = -EIO;
  192. goto ps_restore;
  193. }
  194. ath_cache_conf_rate(sc, &hw->conf);
  195. ath_update_txpow(sc);
  196. ath9k_hw_set_interrupts(ah, ah->imask);
  197. ps_restore:
  198. ath9k_ps_restore(sc);
  199. return r;
  200. }
  201. static void ath_paprd_activate(struct ath_softc *sc)
  202. {
  203. struct ath_hw *ah = sc->sc_ah;
  204. int chain;
  205. if (!ah->curchan->paprd_done)
  206. return;
  207. ath9k_ps_wakeup(sc);
  208. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  209. if (!(ah->caps.tx_chainmask & BIT(chain)))
  210. continue;
  211. ar9003_paprd_populate_single_table(ah, ah->curchan, chain);
  212. }
  213. ar9003_paprd_enable(ah, true);
  214. ath9k_ps_restore(sc);
  215. }
  216. void ath_paprd_calibrate(struct work_struct *work)
  217. {
  218. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  219. struct ieee80211_hw *hw = sc->hw;
  220. struct ath_hw *ah = sc->sc_ah;
  221. struct ieee80211_hdr *hdr;
  222. struct sk_buff *skb = NULL;
  223. struct ieee80211_tx_info *tx_info;
  224. int band = hw->conf.channel->band;
  225. struct ieee80211_supported_band *sband = &sc->sbands[band];
  226. struct ath_tx_control txctl;
  227. int qnum, ftype;
  228. int chain_ok = 0;
  229. int chain;
  230. int len = 1800;
  231. int time_left;
  232. int i;
  233. skb = alloc_skb(len, GFP_KERNEL);
  234. if (!skb)
  235. return;
  236. tx_info = IEEE80211_SKB_CB(skb);
  237. skb_put(skb, len);
  238. memset(skb->data, 0, len);
  239. hdr = (struct ieee80211_hdr *)skb->data;
  240. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  241. hdr->frame_control = cpu_to_le16(ftype);
  242. hdr->duration_id = 10;
  243. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  244. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  245. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  246. memset(&txctl, 0, sizeof(txctl));
  247. qnum = sc->tx.hwq_map[WME_AC_BE];
  248. txctl.txq = &sc->tx.txq[qnum];
  249. ath9k_ps_wakeup(sc);
  250. ar9003_paprd_init_table(ah);
  251. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  252. if (!(ah->caps.tx_chainmask & BIT(chain)))
  253. continue;
  254. chain_ok = 0;
  255. memset(tx_info, 0, sizeof(*tx_info));
  256. tx_info->band = band;
  257. for (i = 0; i < 4; i++) {
  258. tx_info->control.rates[i].idx = sband->n_bitrates - 1;
  259. tx_info->control.rates[i].count = 6;
  260. }
  261. init_completion(&sc->paprd_complete);
  262. ar9003_paprd_setup_gain_table(ah, chain);
  263. txctl.paprd = BIT(chain);
  264. if (ath_tx_start(hw, skb, &txctl) != 0)
  265. break;
  266. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  267. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  268. if (!time_left) {
  269. ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
  270. "Timeout waiting for paprd training on "
  271. "TX chain %d\n",
  272. chain);
  273. goto fail_paprd;
  274. }
  275. if (!ar9003_paprd_is_done(ah))
  276. break;
  277. if (ar9003_paprd_create_curve(ah, ah->curchan, chain) != 0)
  278. break;
  279. chain_ok = 1;
  280. }
  281. kfree_skb(skb);
  282. if (chain_ok) {
  283. ah->curchan->paprd_done = true;
  284. ath_paprd_activate(sc);
  285. }
  286. fail_paprd:
  287. ath9k_ps_restore(sc);
  288. }
  289. /*
  290. * This routine performs the periodic noise floor calibration function
  291. * that is used to adjust and optimize the chip performance. This
  292. * takes environmental changes (location, temperature) into account.
  293. * When the task is complete, it reschedules itself depending on the
  294. * appropriate interval that was calculated.
  295. */
  296. void ath_ani_calibrate(unsigned long data)
  297. {
  298. struct ath_softc *sc = (struct ath_softc *)data;
  299. struct ath_hw *ah = sc->sc_ah;
  300. struct ath_common *common = ath9k_hw_common(ah);
  301. bool longcal = false;
  302. bool shortcal = false;
  303. bool aniflag = false;
  304. unsigned int timestamp = jiffies_to_msecs(jiffies);
  305. u32 cal_interval, short_cal_interval;
  306. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  307. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  308. /* Only calibrate if awake */
  309. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  310. goto set_timer;
  311. ath9k_ps_wakeup(sc);
  312. /* Long calibration runs independently of short calibration. */
  313. if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
  314. longcal = true;
  315. ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  316. common->ani.longcal_timer = timestamp;
  317. }
  318. /* Short calibration applies only while caldone is false */
  319. if (!common->ani.caldone) {
  320. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  321. shortcal = true;
  322. ath_print(common, ATH_DBG_ANI,
  323. "shortcal @%lu\n", jiffies);
  324. common->ani.shortcal_timer = timestamp;
  325. common->ani.resetcal_timer = timestamp;
  326. }
  327. } else {
  328. if ((timestamp - common->ani.resetcal_timer) >=
  329. ATH_RESTART_CALINTERVAL) {
  330. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  331. if (common->ani.caldone)
  332. common->ani.resetcal_timer = timestamp;
  333. }
  334. }
  335. /* Verify whether we must check ANI */
  336. if ((timestamp - common->ani.checkani_timer) >=
  337. ah->config.ani_poll_interval) {
  338. aniflag = true;
  339. common->ani.checkani_timer = timestamp;
  340. }
  341. /* Skip all processing if there's nothing to do. */
  342. if (longcal || shortcal || aniflag) {
  343. /* Call ANI routine if necessary */
  344. if (aniflag)
  345. ath9k_hw_ani_monitor(ah, ah->curchan);
  346. /* Perform calibration if necessary */
  347. if (longcal || shortcal) {
  348. common->ani.caldone =
  349. ath9k_hw_calibrate(ah,
  350. ah->curchan,
  351. common->rx_chainmask,
  352. longcal);
  353. if (longcal)
  354. common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
  355. ah->curchan);
  356. ath_print(common, ATH_DBG_ANI,
  357. " calibrate chan %u/%x nf: %d\n",
  358. ah->curchan->channel,
  359. ah->curchan->channelFlags,
  360. common->ani.noise_floor);
  361. }
  362. }
  363. ath9k_ps_restore(sc);
  364. set_timer:
  365. /*
  366. * Set timer interval based on previous results.
  367. * The interval must be the shortest necessary to satisfy ANI,
  368. * short calibration and long calibration.
  369. */
  370. cal_interval = ATH_LONG_CALINTERVAL;
  371. if (sc->sc_ah->config.enable_ani)
  372. cal_interval = min(cal_interval,
  373. (u32)ah->config.ani_poll_interval);
  374. if (!common->ani.caldone)
  375. cal_interval = min(cal_interval, (u32)short_cal_interval);
  376. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  377. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) &&
  378. !(sc->sc_flags & SC_OP_SCANNING)) {
  379. if (!sc->sc_ah->curchan->paprd_done)
  380. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  381. else
  382. ath_paprd_activate(sc);
  383. }
  384. }
  385. static void ath_start_ani(struct ath_common *common)
  386. {
  387. struct ath_hw *ah = common->ah;
  388. unsigned long timestamp = jiffies_to_msecs(jiffies);
  389. struct ath_softc *sc = (struct ath_softc *) common->priv;
  390. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  391. return;
  392. common->ani.longcal_timer = timestamp;
  393. common->ani.shortcal_timer = timestamp;
  394. common->ani.checkani_timer = timestamp;
  395. mod_timer(&common->ani.timer,
  396. jiffies +
  397. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  398. }
  399. /*
  400. * Update tx/rx chainmask. For legacy association,
  401. * hard code chainmask to 1x1, for 11n association, use
  402. * the chainmask configuration, for bt coexistence, use
  403. * the chainmask configuration even in legacy mode.
  404. */
  405. void ath_update_chainmask(struct ath_softc *sc, int is_ht)
  406. {
  407. struct ath_hw *ah = sc->sc_ah;
  408. struct ath_common *common = ath9k_hw_common(ah);
  409. if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
  410. (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
  411. common->tx_chainmask = ah->caps.tx_chainmask;
  412. common->rx_chainmask = ah->caps.rx_chainmask;
  413. } else {
  414. common->tx_chainmask = 1;
  415. common->rx_chainmask = 1;
  416. }
  417. ath_print(common, ATH_DBG_CONFIG,
  418. "tx chmask: %d, rx chmask: %d\n",
  419. common->tx_chainmask,
  420. common->rx_chainmask);
  421. }
  422. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  423. {
  424. struct ath_node *an;
  425. an = (struct ath_node *)sta->drv_priv;
  426. if (sc->sc_flags & SC_OP_TXAGGR) {
  427. ath_tx_node_init(sc, an);
  428. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  429. sta->ht_cap.ampdu_factor);
  430. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  431. an->last_rssi = ATH_RSSI_DUMMY_MARKER;
  432. }
  433. }
  434. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  435. {
  436. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  437. if (sc->sc_flags & SC_OP_TXAGGR)
  438. ath_tx_node_cleanup(sc, an);
  439. }
  440. void ath9k_tasklet(unsigned long data)
  441. {
  442. struct ath_softc *sc = (struct ath_softc *)data;
  443. struct ath_hw *ah = sc->sc_ah;
  444. struct ath_common *common = ath9k_hw_common(ah);
  445. u32 status = sc->intrstatus;
  446. u32 rxmask;
  447. ath9k_ps_wakeup(sc);
  448. if ((status & ATH9K_INT_FATAL) ||
  449. !ath9k_hw_check_alive(ah)) {
  450. ath_reset(sc, false);
  451. ath9k_ps_restore(sc);
  452. return;
  453. }
  454. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  455. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  456. ATH9K_INT_RXORN);
  457. else
  458. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  459. if (status & rxmask) {
  460. spin_lock_bh(&sc->rx.rxflushlock);
  461. /* Check for high priority Rx first */
  462. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  463. (status & ATH9K_INT_RXHP))
  464. ath_rx_tasklet(sc, 0, true);
  465. ath_rx_tasklet(sc, 0, false);
  466. spin_unlock_bh(&sc->rx.rxflushlock);
  467. }
  468. if (status & ATH9K_INT_TX) {
  469. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  470. ath_tx_edma_tasklet(sc);
  471. else
  472. ath_tx_tasklet(sc);
  473. }
  474. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  475. /*
  476. * TSF sync does not look correct; remain awake to sync with
  477. * the next Beacon.
  478. */
  479. ath_print(common, ATH_DBG_PS,
  480. "TSFOOR - Sync with next Beacon\n");
  481. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  482. }
  483. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  484. if (status & ATH9K_INT_GENTIMER)
  485. ath_gen_timer_isr(sc->sc_ah);
  486. /* re-enable hardware interrupt */
  487. ath9k_hw_set_interrupts(ah, ah->imask);
  488. ath9k_ps_restore(sc);
  489. }
  490. irqreturn_t ath_isr(int irq, void *dev)
  491. {
  492. #define SCHED_INTR ( \
  493. ATH9K_INT_FATAL | \
  494. ATH9K_INT_RXORN | \
  495. ATH9K_INT_RXEOL | \
  496. ATH9K_INT_RX | \
  497. ATH9K_INT_RXLP | \
  498. ATH9K_INT_RXHP | \
  499. ATH9K_INT_TX | \
  500. ATH9K_INT_BMISS | \
  501. ATH9K_INT_CST | \
  502. ATH9K_INT_TSFOOR | \
  503. ATH9K_INT_GENTIMER)
  504. struct ath_softc *sc = dev;
  505. struct ath_hw *ah = sc->sc_ah;
  506. enum ath9k_int status;
  507. bool sched = false;
  508. /*
  509. * The hardware is not ready/present, don't
  510. * touch anything. Note this can happen early
  511. * on if the IRQ is shared.
  512. */
  513. if (sc->sc_flags & SC_OP_INVALID)
  514. return IRQ_NONE;
  515. /* shared irq, not for us */
  516. if (!ath9k_hw_intrpend(ah))
  517. return IRQ_NONE;
  518. /*
  519. * Figure out the reason(s) for the interrupt. Note
  520. * that the hal returns a pseudo-ISR that may include
  521. * bits we haven't explicitly enabled so we mask the
  522. * value to insure we only process bits we requested.
  523. */
  524. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  525. status &= ah->imask; /* discard unasked-for bits */
  526. /*
  527. * If there are no status bits set, then this interrupt was not
  528. * for me (should have been caught above).
  529. */
  530. if (!status)
  531. return IRQ_NONE;
  532. /* Cache the status */
  533. sc->intrstatus = status;
  534. if (status & SCHED_INTR)
  535. sched = true;
  536. /*
  537. * If a FATAL or RXORN interrupt is received, we have to reset the
  538. * chip immediately.
  539. */
  540. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  541. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  542. goto chip_reset;
  543. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  544. (status & ATH9K_INT_BB_WATCHDOG)) {
  545. ar9003_hw_bb_watchdog_dbg_info(ah);
  546. goto chip_reset;
  547. }
  548. if (status & ATH9K_INT_SWBA)
  549. tasklet_schedule(&sc->bcon_tasklet);
  550. if (status & ATH9K_INT_TXURN)
  551. ath9k_hw_updatetxtriglevel(ah, true);
  552. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  553. if (status & ATH9K_INT_RXEOL) {
  554. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  555. ath9k_hw_set_interrupts(ah, ah->imask);
  556. }
  557. }
  558. if (status & ATH9K_INT_MIB) {
  559. /*
  560. * Disable interrupts until we service the MIB
  561. * interrupt; otherwise it will continue to
  562. * fire.
  563. */
  564. ath9k_hw_set_interrupts(ah, 0);
  565. /*
  566. * Let the hal handle the event. We assume
  567. * it will clear whatever condition caused
  568. * the interrupt.
  569. */
  570. ath9k_hw_procmibevent(ah);
  571. ath9k_hw_set_interrupts(ah, ah->imask);
  572. }
  573. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  574. if (status & ATH9K_INT_TIM_TIMER) {
  575. /* Clear RxAbort bit so that we can
  576. * receive frames */
  577. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  578. ath9k_hw_setrxabort(sc->sc_ah, 0);
  579. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  580. }
  581. chip_reset:
  582. ath_debug_stat_interrupt(sc, status);
  583. if (sched) {
  584. /* turn off every interrupt except SWBA */
  585. ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
  586. tasklet_schedule(&sc->intr_tq);
  587. }
  588. return IRQ_HANDLED;
  589. #undef SCHED_INTR
  590. }
  591. static u32 ath_get_extchanmode(struct ath_softc *sc,
  592. struct ieee80211_channel *chan,
  593. enum nl80211_channel_type channel_type)
  594. {
  595. u32 chanmode = 0;
  596. switch (chan->band) {
  597. case IEEE80211_BAND_2GHZ:
  598. switch(channel_type) {
  599. case NL80211_CHAN_NO_HT:
  600. case NL80211_CHAN_HT20:
  601. chanmode = CHANNEL_G_HT20;
  602. break;
  603. case NL80211_CHAN_HT40PLUS:
  604. chanmode = CHANNEL_G_HT40PLUS;
  605. break;
  606. case NL80211_CHAN_HT40MINUS:
  607. chanmode = CHANNEL_G_HT40MINUS;
  608. break;
  609. }
  610. break;
  611. case IEEE80211_BAND_5GHZ:
  612. switch(channel_type) {
  613. case NL80211_CHAN_NO_HT:
  614. case NL80211_CHAN_HT20:
  615. chanmode = CHANNEL_A_HT20;
  616. break;
  617. case NL80211_CHAN_HT40PLUS:
  618. chanmode = CHANNEL_A_HT40PLUS;
  619. break;
  620. case NL80211_CHAN_HT40MINUS:
  621. chanmode = CHANNEL_A_HT40MINUS;
  622. break;
  623. }
  624. break;
  625. default:
  626. break;
  627. }
  628. return chanmode;
  629. }
  630. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  631. struct ieee80211_vif *vif,
  632. struct ieee80211_bss_conf *bss_conf)
  633. {
  634. struct ath_hw *ah = sc->sc_ah;
  635. struct ath_common *common = ath9k_hw_common(ah);
  636. if (bss_conf->assoc) {
  637. ath_print(common, ATH_DBG_CONFIG,
  638. "Bss Info ASSOC %d, bssid: %pM\n",
  639. bss_conf->aid, common->curbssid);
  640. /* New association, store aid */
  641. common->curaid = bss_conf->aid;
  642. ath9k_hw_write_associd(ah);
  643. /*
  644. * Request a re-configuration of Beacon related timers
  645. * on the receipt of the first Beacon frame (i.e.,
  646. * after time sync with the AP).
  647. */
  648. sc->ps_flags |= PS_BEACON_SYNC;
  649. /* Configure the beacon */
  650. ath_beacon_config(sc, vif);
  651. /* Reset rssi stats */
  652. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  653. sc->sc_flags |= SC_OP_ANI_RUN;
  654. ath_start_ani(common);
  655. } else {
  656. ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  657. common->curaid = 0;
  658. /* Stop ANI */
  659. sc->sc_flags &= ~SC_OP_ANI_RUN;
  660. del_timer_sync(&common->ani.timer);
  661. }
  662. }
  663. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  664. {
  665. struct ath_hw *ah = sc->sc_ah;
  666. struct ath_common *common = ath9k_hw_common(ah);
  667. struct ieee80211_channel *channel = hw->conf.channel;
  668. int r;
  669. ath9k_ps_wakeup(sc);
  670. ath9k_hw_configpcipowersave(ah, 0, 0);
  671. if (!ah->curchan)
  672. ah->curchan = ath_get_curchannel(sc, sc->hw);
  673. spin_lock_bh(&sc->sc_resetlock);
  674. r = ath9k_hw_reset(ah, ah->curchan, false);
  675. if (r) {
  676. ath_print(common, ATH_DBG_FATAL,
  677. "Unable to reset channel (%u MHz), "
  678. "reset status %d\n",
  679. channel->center_freq, r);
  680. }
  681. spin_unlock_bh(&sc->sc_resetlock);
  682. ath_update_txpow(sc);
  683. if (ath_startrecv(sc) != 0) {
  684. ath_print(common, ATH_DBG_FATAL,
  685. "Unable to restart recv logic\n");
  686. return;
  687. }
  688. if (sc->sc_flags & SC_OP_BEACONS)
  689. ath_beacon_config(sc, NULL); /* restart beacons */
  690. /* Re-Enable interrupts */
  691. ath9k_hw_set_interrupts(ah, ah->imask);
  692. /* Enable LED */
  693. ath9k_hw_cfg_output(ah, ah->led_pin,
  694. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  695. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  696. ieee80211_wake_queues(hw);
  697. ath9k_ps_restore(sc);
  698. }
  699. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  700. {
  701. struct ath_hw *ah = sc->sc_ah;
  702. struct ieee80211_channel *channel = hw->conf.channel;
  703. int r;
  704. ath9k_ps_wakeup(sc);
  705. ieee80211_stop_queues(hw);
  706. /* Disable LED */
  707. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  708. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  709. /* Disable interrupts */
  710. ath9k_hw_set_interrupts(ah, 0);
  711. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  712. ath_stoprecv(sc); /* turn off frame recv */
  713. ath_flushrecv(sc); /* flush recv queue */
  714. if (!ah->curchan)
  715. ah->curchan = ath_get_curchannel(sc, hw);
  716. spin_lock_bh(&sc->sc_resetlock);
  717. r = ath9k_hw_reset(ah, ah->curchan, false);
  718. if (r) {
  719. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  720. "Unable to reset channel (%u MHz), "
  721. "reset status %d\n",
  722. channel->center_freq, r);
  723. }
  724. spin_unlock_bh(&sc->sc_resetlock);
  725. ath9k_hw_phy_disable(ah);
  726. ath9k_hw_configpcipowersave(ah, 1, 1);
  727. ath9k_ps_restore(sc);
  728. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  729. }
  730. int ath_reset(struct ath_softc *sc, bool retry_tx)
  731. {
  732. struct ath_hw *ah = sc->sc_ah;
  733. struct ath_common *common = ath9k_hw_common(ah);
  734. struct ieee80211_hw *hw = sc->hw;
  735. int r;
  736. /* Stop ANI */
  737. del_timer_sync(&common->ani.timer);
  738. ieee80211_stop_queues(hw);
  739. ath9k_hw_set_interrupts(ah, 0);
  740. ath_drain_all_txq(sc, retry_tx);
  741. ath_stoprecv(sc);
  742. ath_flushrecv(sc);
  743. spin_lock_bh(&sc->sc_resetlock);
  744. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
  745. if (r)
  746. ath_print(common, ATH_DBG_FATAL,
  747. "Unable to reset hardware; reset status %d\n", r);
  748. spin_unlock_bh(&sc->sc_resetlock);
  749. if (ath_startrecv(sc) != 0)
  750. ath_print(common, ATH_DBG_FATAL,
  751. "Unable to start recv logic\n");
  752. /*
  753. * We may be doing a reset in response to a request
  754. * that changes the channel so update any state that
  755. * might change as a result.
  756. */
  757. ath_cache_conf_rate(sc, &hw->conf);
  758. ath_update_txpow(sc);
  759. if (sc->sc_flags & SC_OP_BEACONS)
  760. ath_beacon_config(sc, NULL); /* restart beacons */
  761. ath9k_hw_set_interrupts(ah, ah->imask);
  762. if (retry_tx) {
  763. int i;
  764. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  765. if (ATH_TXQ_SETUP(sc, i)) {
  766. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  767. ath_txq_schedule(sc, &sc->tx.txq[i]);
  768. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  769. }
  770. }
  771. }
  772. ieee80211_wake_queues(hw);
  773. /* Start ANI */
  774. ath_start_ani(common);
  775. return r;
  776. }
  777. static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
  778. {
  779. int qnum;
  780. switch (queue) {
  781. case 0:
  782. qnum = sc->tx.hwq_map[WME_AC_VO];
  783. break;
  784. case 1:
  785. qnum = sc->tx.hwq_map[WME_AC_VI];
  786. break;
  787. case 2:
  788. qnum = sc->tx.hwq_map[WME_AC_BE];
  789. break;
  790. case 3:
  791. qnum = sc->tx.hwq_map[WME_AC_BK];
  792. break;
  793. default:
  794. qnum = sc->tx.hwq_map[WME_AC_BE];
  795. break;
  796. }
  797. return qnum;
  798. }
  799. int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
  800. {
  801. int qnum;
  802. switch (queue) {
  803. case WME_AC_VO:
  804. qnum = 0;
  805. break;
  806. case WME_AC_VI:
  807. qnum = 1;
  808. break;
  809. case WME_AC_BE:
  810. qnum = 2;
  811. break;
  812. case WME_AC_BK:
  813. qnum = 3;
  814. break;
  815. default:
  816. qnum = -1;
  817. break;
  818. }
  819. return qnum;
  820. }
  821. /* XXX: Remove me once we don't depend on ath9k_channel for all
  822. * this redundant data */
  823. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  824. struct ath9k_channel *ichan)
  825. {
  826. struct ieee80211_channel *chan = hw->conf.channel;
  827. struct ieee80211_conf *conf = &hw->conf;
  828. ichan->channel = chan->center_freq;
  829. ichan->chan = chan;
  830. if (chan->band == IEEE80211_BAND_2GHZ) {
  831. ichan->chanmode = CHANNEL_G;
  832. ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
  833. } else {
  834. ichan->chanmode = CHANNEL_A;
  835. ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
  836. }
  837. if (conf_is_ht(conf))
  838. ichan->chanmode = ath_get_extchanmode(sc, chan,
  839. conf->channel_type);
  840. }
  841. /**********************/
  842. /* mac80211 callbacks */
  843. /**********************/
  844. static int ath9k_start(struct ieee80211_hw *hw)
  845. {
  846. struct ath_wiphy *aphy = hw->priv;
  847. struct ath_softc *sc = aphy->sc;
  848. struct ath_hw *ah = sc->sc_ah;
  849. struct ath_common *common = ath9k_hw_common(ah);
  850. struct ieee80211_channel *curchan = hw->conf.channel;
  851. struct ath9k_channel *init_channel;
  852. int r;
  853. ath_print(common, ATH_DBG_CONFIG,
  854. "Starting driver with initial channel: %d MHz\n",
  855. curchan->center_freq);
  856. mutex_lock(&sc->mutex);
  857. if (ath9k_wiphy_started(sc)) {
  858. if (sc->chan_idx == curchan->hw_value) {
  859. /*
  860. * Already on the operational channel, the new wiphy
  861. * can be marked active.
  862. */
  863. aphy->state = ATH_WIPHY_ACTIVE;
  864. ieee80211_wake_queues(hw);
  865. } else {
  866. /*
  867. * Another wiphy is on another channel, start the new
  868. * wiphy in paused state.
  869. */
  870. aphy->state = ATH_WIPHY_PAUSED;
  871. ieee80211_stop_queues(hw);
  872. }
  873. mutex_unlock(&sc->mutex);
  874. return 0;
  875. }
  876. aphy->state = ATH_WIPHY_ACTIVE;
  877. /* setup initial channel */
  878. sc->chan_idx = curchan->hw_value;
  879. init_channel = ath_get_curchannel(sc, hw);
  880. /* Reset SERDES registers */
  881. ath9k_hw_configpcipowersave(ah, 0, 0);
  882. /*
  883. * The basic interface to setting the hardware in a good
  884. * state is ``reset''. On return the hardware is known to
  885. * be powered up and with interrupts disabled. This must
  886. * be followed by initialization of the appropriate bits
  887. * and then setup of the interrupt mask.
  888. */
  889. spin_lock_bh(&sc->sc_resetlock);
  890. r = ath9k_hw_reset(ah, init_channel, false);
  891. if (r) {
  892. ath_print(common, ATH_DBG_FATAL,
  893. "Unable to reset hardware; reset status %d "
  894. "(freq %u MHz)\n", r,
  895. curchan->center_freq);
  896. spin_unlock_bh(&sc->sc_resetlock);
  897. goto mutex_unlock;
  898. }
  899. spin_unlock_bh(&sc->sc_resetlock);
  900. /*
  901. * This is needed only to setup initial state
  902. * but it's best done after a reset.
  903. */
  904. ath_update_txpow(sc);
  905. /*
  906. * Setup the hardware after reset:
  907. * The receive engine is set going.
  908. * Frame transmit is handled entirely
  909. * in the frame output path; there's nothing to do
  910. * here except setup the interrupt mask.
  911. */
  912. if (ath_startrecv(sc) != 0) {
  913. ath_print(common, ATH_DBG_FATAL,
  914. "Unable to start recv logic\n");
  915. r = -EIO;
  916. goto mutex_unlock;
  917. }
  918. /* Setup our intr mask. */
  919. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  920. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  921. ATH9K_INT_GLOBAL;
  922. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  923. ah->imask |= ATH9K_INT_RXHP |
  924. ATH9K_INT_RXLP |
  925. ATH9K_INT_BB_WATCHDOG;
  926. else
  927. ah->imask |= ATH9K_INT_RX;
  928. if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
  929. ah->imask |= ATH9K_INT_GTT;
  930. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  931. ah->imask |= ATH9K_INT_CST;
  932. ath_cache_conf_rate(sc, &hw->conf);
  933. sc->sc_flags &= ~SC_OP_INVALID;
  934. /* Disable BMISS interrupt when we're not associated */
  935. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  936. ath9k_hw_set_interrupts(ah, ah->imask);
  937. ieee80211_wake_queues(hw);
  938. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  939. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  940. !ah->btcoex_hw.enabled) {
  941. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  942. AR_STOMP_LOW_WLAN_WGHT);
  943. ath9k_hw_btcoex_enable(ah);
  944. if (common->bus_ops->bt_coex_prep)
  945. common->bus_ops->bt_coex_prep(common);
  946. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  947. ath9k_btcoex_timer_resume(sc);
  948. }
  949. mutex_unlock:
  950. mutex_unlock(&sc->mutex);
  951. return r;
  952. }
  953. static int ath9k_tx(struct ieee80211_hw *hw,
  954. struct sk_buff *skb)
  955. {
  956. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  957. struct ath_wiphy *aphy = hw->priv;
  958. struct ath_softc *sc = aphy->sc;
  959. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  960. struct ath_tx_control txctl;
  961. int padpos, padsize;
  962. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  963. int qnum;
  964. if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
  965. ath_print(common, ATH_DBG_XMIT,
  966. "ath9k: %s: TX in unexpected wiphy state "
  967. "%d\n", wiphy_name(hw->wiphy), aphy->state);
  968. goto exit;
  969. }
  970. if (sc->ps_enabled) {
  971. /*
  972. * mac80211 does not set PM field for normal data frames, so we
  973. * need to update that based on the current PS mode.
  974. */
  975. if (ieee80211_is_data(hdr->frame_control) &&
  976. !ieee80211_is_nullfunc(hdr->frame_control) &&
  977. !ieee80211_has_pm(hdr->frame_control)) {
  978. ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
  979. "while in PS mode\n");
  980. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  981. }
  982. }
  983. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  984. /*
  985. * We are using PS-Poll and mac80211 can request TX while in
  986. * power save mode. Need to wake up hardware for the TX to be
  987. * completed and if needed, also for RX of buffered frames.
  988. */
  989. ath9k_ps_wakeup(sc);
  990. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  991. ath9k_hw_setrxabort(sc->sc_ah, 0);
  992. if (ieee80211_is_pspoll(hdr->frame_control)) {
  993. ath_print(common, ATH_DBG_PS,
  994. "Sending PS-Poll to pick a buffered frame\n");
  995. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  996. } else {
  997. ath_print(common, ATH_DBG_PS,
  998. "Wake up to complete TX\n");
  999. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  1000. }
  1001. /*
  1002. * The actual restore operation will happen only after
  1003. * the sc_flags bit is cleared. We are just dropping
  1004. * the ps_usecount here.
  1005. */
  1006. ath9k_ps_restore(sc);
  1007. }
  1008. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1009. /*
  1010. * As a temporary workaround, assign seq# here; this will likely need
  1011. * to be cleaned up to work better with Beacon transmission and virtual
  1012. * BSSes.
  1013. */
  1014. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1015. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1016. sc->tx.seq_no += 0x10;
  1017. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1018. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1019. }
  1020. /* Add the padding after the header if this is not already done */
  1021. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1022. padsize = padpos & 3;
  1023. if (padsize && skb->len>padpos) {
  1024. if (skb_headroom(skb) < padsize)
  1025. return -1;
  1026. skb_push(skb, padsize);
  1027. memmove(skb->data, skb->data + padsize, padpos);
  1028. }
  1029. qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
  1030. txctl.txq = &sc->tx.txq[qnum];
  1031. ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  1032. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1033. ath_print(common, ATH_DBG_XMIT, "TX failed\n");
  1034. goto exit;
  1035. }
  1036. return 0;
  1037. exit:
  1038. dev_kfree_skb_any(skb);
  1039. return 0;
  1040. }
  1041. static void ath9k_stop(struct ieee80211_hw *hw)
  1042. {
  1043. struct ath_wiphy *aphy = hw->priv;
  1044. struct ath_softc *sc = aphy->sc;
  1045. struct ath_hw *ah = sc->sc_ah;
  1046. struct ath_common *common = ath9k_hw_common(ah);
  1047. mutex_lock(&sc->mutex);
  1048. aphy->state = ATH_WIPHY_INACTIVE;
  1049. if (led_blink)
  1050. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  1051. cancel_delayed_work_sync(&sc->tx_complete_work);
  1052. cancel_work_sync(&sc->paprd_work);
  1053. if (!sc->num_sec_wiphy) {
  1054. cancel_delayed_work_sync(&sc->wiphy_work);
  1055. cancel_work_sync(&sc->chan_work);
  1056. }
  1057. if (sc->sc_flags & SC_OP_INVALID) {
  1058. ath_print(common, ATH_DBG_ANY, "Device not present\n");
  1059. mutex_unlock(&sc->mutex);
  1060. return;
  1061. }
  1062. if (ath9k_wiphy_started(sc)) {
  1063. mutex_unlock(&sc->mutex);
  1064. return; /* another wiphy still in use */
  1065. }
  1066. /* Ensure HW is awake when we try to shut it down. */
  1067. ath9k_ps_wakeup(sc);
  1068. if (ah->btcoex_hw.enabled) {
  1069. ath9k_hw_btcoex_disable(ah);
  1070. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1071. ath9k_btcoex_timer_pause(sc);
  1072. }
  1073. /* make sure h/w will not generate any interrupt
  1074. * before setting the invalid flag. */
  1075. ath9k_hw_set_interrupts(ah, 0);
  1076. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1077. ath_drain_all_txq(sc, false);
  1078. ath_stoprecv(sc);
  1079. ath9k_hw_phy_disable(ah);
  1080. } else
  1081. sc->rx.rxlink = NULL;
  1082. /* disable HAL and put h/w to sleep */
  1083. ath9k_hw_disable(ah);
  1084. ath9k_hw_configpcipowersave(ah, 1, 1);
  1085. ath9k_ps_restore(sc);
  1086. /* Finally, put the chip in FULL SLEEP mode */
  1087. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  1088. sc->sc_flags |= SC_OP_INVALID;
  1089. mutex_unlock(&sc->mutex);
  1090. ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
  1091. }
  1092. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1093. struct ieee80211_vif *vif)
  1094. {
  1095. struct ath_wiphy *aphy = hw->priv;
  1096. struct ath_softc *sc = aphy->sc;
  1097. struct ath_hw *ah = sc->sc_ah;
  1098. struct ath_common *common = ath9k_hw_common(ah);
  1099. struct ath_vif *avp = (void *)vif->drv_priv;
  1100. enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
  1101. int ret = 0;
  1102. mutex_lock(&sc->mutex);
  1103. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
  1104. sc->nvifs > 0) {
  1105. ret = -ENOBUFS;
  1106. goto out;
  1107. }
  1108. switch (vif->type) {
  1109. case NL80211_IFTYPE_STATION:
  1110. ic_opmode = NL80211_IFTYPE_STATION;
  1111. break;
  1112. case NL80211_IFTYPE_ADHOC:
  1113. case NL80211_IFTYPE_AP:
  1114. case NL80211_IFTYPE_MESH_POINT:
  1115. if (sc->nbcnvifs >= ATH_BCBUF) {
  1116. ret = -ENOBUFS;
  1117. goto out;
  1118. }
  1119. ic_opmode = vif->type;
  1120. break;
  1121. default:
  1122. ath_print(common, ATH_DBG_FATAL,
  1123. "Interface type %d not yet supported\n", vif->type);
  1124. ret = -EOPNOTSUPP;
  1125. goto out;
  1126. }
  1127. ath_print(common, ATH_DBG_CONFIG,
  1128. "Attach a VIF of type: %d\n", ic_opmode);
  1129. /* Set the VIF opmode */
  1130. avp->av_opmode = ic_opmode;
  1131. avp->av_bslot = -1;
  1132. sc->nvifs++;
  1133. if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  1134. ath9k_set_bssid_mask(hw);
  1135. if (sc->nvifs > 1)
  1136. goto out; /* skip global settings for secondary vif */
  1137. if (ic_opmode == NL80211_IFTYPE_AP) {
  1138. ath9k_hw_set_tsfadjust(ah, 1);
  1139. sc->sc_flags |= SC_OP_TSF_RESET;
  1140. }
  1141. /* Set the device opmode */
  1142. ah->opmode = ic_opmode;
  1143. /*
  1144. * Enable MIB interrupts when there are hardware phy counters.
  1145. * Note we only do this (at the moment) for station mode.
  1146. */
  1147. if ((vif->type == NL80211_IFTYPE_STATION) ||
  1148. (vif->type == NL80211_IFTYPE_ADHOC) ||
  1149. (vif->type == NL80211_IFTYPE_MESH_POINT)) {
  1150. if (ah->config.enable_ani)
  1151. ah->imask |= ATH9K_INT_MIB;
  1152. ah->imask |= ATH9K_INT_TSFOOR;
  1153. }
  1154. ath9k_hw_set_interrupts(ah, ah->imask);
  1155. if (vif->type == NL80211_IFTYPE_AP ||
  1156. vif->type == NL80211_IFTYPE_ADHOC ||
  1157. vif->type == NL80211_IFTYPE_MONITOR) {
  1158. sc->sc_flags |= SC_OP_ANI_RUN;
  1159. ath_start_ani(common);
  1160. }
  1161. out:
  1162. mutex_unlock(&sc->mutex);
  1163. return ret;
  1164. }
  1165. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1166. struct ieee80211_vif *vif)
  1167. {
  1168. struct ath_wiphy *aphy = hw->priv;
  1169. struct ath_softc *sc = aphy->sc;
  1170. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1171. struct ath_vif *avp = (void *)vif->drv_priv;
  1172. int i;
  1173. ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1174. mutex_lock(&sc->mutex);
  1175. /* Stop ANI */
  1176. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1177. del_timer_sync(&common->ani.timer);
  1178. /* Reclaim beacon resources */
  1179. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  1180. (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1181. (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
  1182. ath9k_ps_wakeup(sc);
  1183. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1184. ath9k_ps_restore(sc);
  1185. }
  1186. ath_beacon_return(sc, avp);
  1187. sc->sc_flags &= ~SC_OP_BEACONS;
  1188. for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
  1189. if (sc->beacon.bslot[i] == vif) {
  1190. printk(KERN_DEBUG "%s: vif had allocated beacon "
  1191. "slot\n", __func__);
  1192. sc->beacon.bslot[i] = NULL;
  1193. sc->beacon.bslot_aphy[i] = NULL;
  1194. }
  1195. }
  1196. sc->nvifs--;
  1197. mutex_unlock(&sc->mutex);
  1198. }
  1199. void ath9k_enable_ps(struct ath_softc *sc)
  1200. {
  1201. struct ath_hw *ah = sc->sc_ah;
  1202. sc->ps_enabled = true;
  1203. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1204. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1205. ah->imask |= ATH9K_INT_TIM_TIMER;
  1206. ath9k_hw_set_interrupts(ah, ah->imask);
  1207. }
  1208. ath9k_hw_setrxabort(ah, 1);
  1209. }
  1210. }
  1211. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1212. {
  1213. struct ath_wiphy *aphy = hw->priv;
  1214. struct ath_softc *sc = aphy->sc;
  1215. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1216. struct ieee80211_conf *conf = &hw->conf;
  1217. struct ath_hw *ah = sc->sc_ah;
  1218. bool disable_radio;
  1219. mutex_lock(&sc->mutex);
  1220. /*
  1221. * Leave this as the first check because we need to turn on the
  1222. * radio if it was disabled before prior to processing the rest
  1223. * of the changes. Likewise we must only disable the radio towards
  1224. * the end.
  1225. */
  1226. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1227. bool enable_radio;
  1228. bool all_wiphys_idle;
  1229. bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1230. spin_lock_bh(&sc->wiphy_lock);
  1231. all_wiphys_idle = ath9k_all_wiphys_idle(sc);
  1232. ath9k_set_wiphy_idle(aphy, idle);
  1233. enable_radio = (!idle && all_wiphys_idle);
  1234. /*
  1235. * After we unlock here its possible another wiphy
  1236. * can be re-renabled so to account for that we will
  1237. * only disable the radio toward the end of this routine
  1238. * if by then all wiphys are still idle.
  1239. */
  1240. spin_unlock_bh(&sc->wiphy_lock);
  1241. if (enable_radio) {
  1242. sc->ps_idle = false;
  1243. ath_radio_enable(sc, hw);
  1244. ath_print(common, ATH_DBG_CONFIG,
  1245. "not-idle: enabling radio\n");
  1246. }
  1247. }
  1248. /*
  1249. * We just prepare to enable PS. We have to wait until our AP has
  1250. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1251. * those ACKs and end up retransmitting the same null data frames.
  1252. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1253. */
  1254. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1255. if (conf->flags & IEEE80211_CONF_PS) {
  1256. sc->ps_flags |= PS_ENABLED;
  1257. /*
  1258. * At this point we know hardware has received an ACK
  1259. * of a previously sent null data frame.
  1260. */
  1261. if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
  1262. sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
  1263. ath9k_enable_ps(sc);
  1264. }
  1265. } else {
  1266. sc->ps_enabled = false;
  1267. sc->ps_flags &= ~(PS_ENABLED |
  1268. PS_NULLFUNC_COMPLETED);
  1269. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  1270. if (!(ah->caps.hw_caps &
  1271. ATH9K_HW_CAP_AUTOSLEEP)) {
  1272. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1273. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1274. PS_WAIT_FOR_CAB |
  1275. PS_WAIT_FOR_PSPOLL_DATA |
  1276. PS_WAIT_FOR_TX_ACK);
  1277. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1278. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1279. ath9k_hw_set_interrupts(sc->sc_ah,
  1280. ah->imask);
  1281. }
  1282. }
  1283. }
  1284. }
  1285. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1286. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1287. ath_print(common, ATH_DBG_CONFIG,
  1288. "HW opmode set to Monitor mode\n");
  1289. sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
  1290. }
  1291. }
  1292. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1293. struct ieee80211_channel *curchan = hw->conf.channel;
  1294. int pos = curchan->hw_value;
  1295. aphy->chan_idx = pos;
  1296. aphy->chan_is_ht = conf_is_ht(conf);
  1297. if (aphy->state == ATH_WIPHY_SCAN ||
  1298. aphy->state == ATH_WIPHY_ACTIVE)
  1299. ath9k_wiphy_pause_all_forced(sc, aphy);
  1300. else {
  1301. /*
  1302. * Do not change operational channel based on a paused
  1303. * wiphy changes.
  1304. */
  1305. goto skip_chan_change;
  1306. }
  1307. ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1308. curchan->center_freq);
  1309. /* XXX: remove me eventualy */
  1310. ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
  1311. ath_update_chainmask(sc, conf_is_ht(conf));
  1312. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1313. ath_print(common, ATH_DBG_FATAL,
  1314. "Unable to set channel\n");
  1315. mutex_unlock(&sc->mutex);
  1316. return -EINVAL;
  1317. }
  1318. }
  1319. skip_chan_change:
  1320. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1321. sc->config.txpowlimit = 2 * conf->power_level;
  1322. ath_update_txpow(sc);
  1323. }
  1324. spin_lock_bh(&sc->wiphy_lock);
  1325. disable_radio = ath9k_all_wiphys_idle(sc);
  1326. spin_unlock_bh(&sc->wiphy_lock);
  1327. if (disable_radio) {
  1328. ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1329. sc->ps_idle = true;
  1330. ath_radio_disable(sc, hw);
  1331. }
  1332. mutex_unlock(&sc->mutex);
  1333. return 0;
  1334. }
  1335. #define SUPPORTED_FILTERS \
  1336. (FIF_PROMISC_IN_BSS | \
  1337. FIF_ALLMULTI | \
  1338. FIF_CONTROL | \
  1339. FIF_PSPOLL | \
  1340. FIF_OTHER_BSS | \
  1341. FIF_BCN_PRBRESP_PROMISC | \
  1342. FIF_FCSFAIL)
  1343. /* FIXME: sc->sc_full_reset ? */
  1344. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1345. unsigned int changed_flags,
  1346. unsigned int *total_flags,
  1347. u64 multicast)
  1348. {
  1349. struct ath_wiphy *aphy = hw->priv;
  1350. struct ath_softc *sc = aphy->sc;
  1351. u32 rfilt;
  1352. changed_flags &= SUPPORTED_FILTERS;
  1353. *total_flags &= SUPPORTED_FILTERS;
  1354. sc->rx.rxfilter = *total_flags;
  1355. ath9k_ps_wakeup(sc);
  1356. rfilt = ath_calcrxfilter(sc);
  1357. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1358. ath9k_ps_restore(sc);
  1359. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1360. "Set HW RX filter: 0x%x\n", rfilt);
  1361. }
  1362. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1363. struct ieee80211_vif *vif,
  1364. struct ieee80211_sta *sta)
  1365. {
  1366. struct ath_wiphy *aphy = hw->priv;
  1367. struct ath_softc *sc = aphy->sc;
  1368. ath_node_attach(sc, sta);
  1369. return 0;
  1370. }
  1371. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1372. struct ieee80211_vif *vif,
  1373. struct ieee80211_sta *sta)
  1374. {
  1375. struct ath_wiphy *aphy = hw->priv;
  1376. struct ath_softc *sc = aphy->sc;
  1377. ath_node_detach(sc, sta);
  1378. return 0;
  1379. }
  1380. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1381. const struct ieee80211_tx_queue_params *params)
  1382. {
  1383. struct ath_wiphy *aphy = hw->priv;
  1384. struct ath_softc *sc = aphy->sc;
  1385. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1386. struct ath9k_tx_queue_info qi;
  1387. int ret = 0, qnum;
  1388. if (queue >= WME_NUM_AC)
  1389. return 0;
  1390. mutex_lock(&sc->mutex);
  1391. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1392. qi.tqi_aifs = params->aifs;
  1393. qi.tqi_cwmin = params->cw_min;
  1394. qi.tqi_cwmax = params->cw_max;
  1395. qi.tqi_burstTime = params->txop;
  1396. qnum = ath_get_hal_qnum(queue, sc);
  1397. ath_print(common, ATH_DBG_CONFIG,
  1398. "Configure tx [queue/halq] [%d/%d], "
  1399. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1400. queue, qnum, params->aifs, params->cw_min,
  1401. params->cw_max, params->txop);
  1402. ret = ath_txq_update(sc, qnum, &qi);
  1403. if (ret)
  1404. ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
  1405. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1406. if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
  1407. ath_beaconq_config(sc);
  1408. mutex_unlock(&sc->mutex);
  1409. return ret;
  1410. }
  1411. static int ath9k_set_key(struct ieee80211_hw *hw,
  1412. enum set_key_cmd cmd,
  1413. struct ieee80211_vif *vif,
  1414. struct ieee80211_sta *sta,
  1415. struct ieee80211_key_conf *key)
  1416. {
  1417. struct ath_wiphy *aphy = hw->priv;
  1418. struct ath_softc *sc = aphy->sc;
  1419. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1420. int ret = 0;
  1421. if (modparam_nohwcrypt)
  1422. return -ENOSPC;
  1423. mutex_lock(&sc->mutex);
  1424. ath9k_ps_wakeup(sc);
  1425. ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1426. switch (cmd) {
  1427. case SET_KEY:
  1428. ret = ath9k_cmn_key_config(common, vif, sta, key);
  1429. if (ret >= 0) {
  1430. key->hw_key_idx = ret;
  1431. /* push IV and Michael MIC generation to stack */
  1432. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1433. if (key->alg == ALG_TKIP)
  1434. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1435. if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
  1436. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1437. ret = 0;
  1438. }
  1439. break;
  1440. case DISABLE_KEY:
  1441. ath9k_cmn_key_delete(common, key);
  1442. break;
  1443. default:
  1444. ret = -EINVAL;
  1445. }
  1446. ath9k_ps_restore(sc);
  1447. mutex_unlock(&sc->mutex);
  1448. return ret;
  1449. }
  1450. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1451. struct ieee80211_vif *vif,
  1452. struct ieee80211_bss_conf *bss_conf,
  1453. u32 changed)
  1454. {
  1455. struct ath_wiphy *aphy = hw->priv;
  1456. struct ath_softc *sc = aphy->sc;
  1457. struct ath_hw *ah = sc->sc_ah;
  1458. struct ath_common *common = ath9k_hw_common(ah);
  1459. struct ath_vif *avp = (void *)vif->drv_priv;
  1460. int slottime;
  1461. int error;
  1462. mutex_lock(&sc->mutex);
  1463. if (changed & BSS_CHANGED_BSSID) {
  1464. /* Set BSSID */
  1465. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1466. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1467. common->curaid = 0;
  1468. ath9k_hw_write_associd(ah);
  1469. /* Set aggregation protection mode parameters */
  1470. sc->config.ath_aggr_prot = 0;
  1471. /* Only legacy IBSS for now */
  1472. if (vif->type == NL80211_IFTYPE_ADHOC)
  1473. ath_update_chainmask(sc, 0);
  1474. ath_print(common, ATH_DBG_CONFIG,
  1475. "BSSID: %pM aid: 0x%x\n",
  1476. common->curbssid, common->curaid);
  1477. /* need to reconfigure the beacon */
  1478. sc->sc_flags &= ~SC_OP_BEACONS ;
  1479. }
  1480. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1481. if ((changed & BSS_CHANGED_BEACON) ||
  1482. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1483. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1484. error = ath_beacon_alloc(aphy, vif);
  1485. if (!error)
  1486. ath_beacon_config(sc, vif);
  1487. }
  1488. if (changed & BSS_CHANGED_ERP_SLOT) {
  1489. if (bss_conf->use_short_slot)
  1490. slottime = 9;
  1491. else
  1492. slottime = 20;
  1493. if (vif->type == NL80211_IFTYPE_AP) {
  1494. /*
  1495. * Defer update, so that connected stations can adjust
  1496. * their settings at the same time.
  1497. * See beacon.c for more details
  1498. */
  1499. sc->beacon.slottime = slottime;
  1500. sc->beacon.updateslot = UPDATE;
  1501. } else {
  1502. ah->slottime = slottime;
  1503. ath9k_hw_init_global_settings(ah);
  1504. }
  1505. }
  1506. /* Disable transmission of beacons */
  1507. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1508. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1509. if (changed & BSS_CHANGED_BEACON_INT) {
  1510. sc->beacon_interval = bss_conf->beacon_int;
  1511. /*
  1512. * In case of AP mode, the HW TSF has to be reset
  1513. * when the beacon interval changes.
  1514. */
  1515. if (vif->type == NL80211_IFTYPE_AP) {
  1516. sc->sc_flags |= SC_OP_TSF_RESET;
  1517. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1518. error = ath_beacon_alloc(aphy, vif);
  1519. if (!error)
  1520. ath_beacon_config(sc, vif);
  1521. } else {
  1522. ath_beacon_config(sc, vif);
  1523. }
  1524. }
  1525. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1526. ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1527. bss_conf->use_short_preamble);
  1528. if (bss_conf->use_short_preamble)
  1529. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1530. else
  1531. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1532. }
  1533. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1534. ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1535. bss_conf->use_cts_prot);
  1536. if (bss_conf->use_cts_prot &&
  1537. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1538. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1539. else
  1540. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1541. }
  1542. if (changed & BSS_CHANGED_ASSOC) {
  1543. ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1544. bss_conf->assoc);
  1545. ath9k_bss_assoc_info(sc, vif, bss_conf);
  1546. }
  1547. mutex_unlock(&sc->mutex);
  1548. }
  1549. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1550. {
  1551. u64 tsf;
  1552. struct ath_wiphy *aphy = hw->priv;
  1553. struct ath_softc *sc = aphy->sc;
  1554. mutex_lock(&sc->mutex);
  1555. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1556. mutex_unlock(&sc->mutex);
  1557. return tsf;
  1558. }
  1559. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1560. {
  1561. struct ath_wiphy *aphy = hw->priv;
  1562. struct ath_softc *sc = aphy->sc;
  1563. mutex_lock(&sc->mutex);
  1564. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1565. mutex_unlock(&sc->mutex);
  1566. }
  1567. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1568. {
  1569. struct ath_wiphy *aphy = hw->priv;
  1570. struct ath_softc *sc = aphy->sc;
  1571. mutex_lock(&sc->mutex);
  1572. ath9k_ps_wakeup(sc);
  1573. ath9k_hw_reset_tsf(sc->sc_ah);
  1574. ath9k_ps_restore(sc);
  1575. mutex_unlock(&sc->mutex);
  1576. }
  1577. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1578. struct ieee80211_vif *vif,
  1579. enum ieee80211_ampdu_mlme_action action,
  1580. struct ieee80211_sta *sta,
  1581. u16 tid, u16 *ssn)
  1582. {
  1583. struct ath_wiphy *aphy = hw->priv;
  1584. struct ath_softc *sc = aphy->sc;
  1585. int ret = 0;
  1586. local_bh_disable();
  1587. switch (action) {
  1588. case IEEE80211_AMPDU_RX_START:
  1589. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1590. ret = -ENOTSUPP;
  1591. break;
  1592. case IEEE80211_AMPDU_RX_STOP:
  1593. break;
  1594. case IEEE80211_AMPDU_TX_START:
  1595. ath9k_ps_wakeup(sc);
  1596. ath_tx_aggr_start(sc, sta, tid, ssn);
  1597. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1598. ath9k_ps_restore(sc);
  1599. break;
  1600. case IEEE80211_AMPDU_TX_STOP:
  1601. ath9k_ps_wakeup(sc);
  1602. ath_tx_aggr_stop(sc, sta, tid);
  1603. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1604. ath9k_ps_restore(sc);
  1605. break;
  1606. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1607. ath9k_ps_wakeup(sc);
  1608. ath_tx_aggr_resume(sc, sta, tid);
  1609. ath9k_ps_restore(sc);
  1610. break;
  1611. default:
  1612. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  1613. "Unknown AMPDU action\n");
  1614. }
  1615. local_bh_enable();
  1616. return ret;
  1617. }
  1618. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1619. struct survey_info *survey)
  1620. {
  1621. struct ath_wiphy *aphy = hw->priv;
  1622. struct ath_softc *sc = aphy->sc;
  1623. struct ath_hw *ah = sc->sc_ah;
  1624. struct ath_common *common = ath9k_hw_common(ah);
  1625. struct ieee80211_conf *conf = &hw->conf;
  1626. if (idx != 0)
  1627. return -ENOENT;
  1628. survey->channel = conf->channel;
  1629. survey->filled = SURVEY_INFO_NOISE_DBM;
  1630. survey->noise = common->ani.noise_floor;
  1631. return 0;
  1632. }
  1633. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1634. {
  1635. struct ath_wiphy *aphy = hw->priv;
  1636. struct ath_softc *sc = aphy->sc;
  1637. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1638. mutex_lock(&sc->mutex);
  1639. if (ath9k_wiphy_scanning(sc)) {
  1640. printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
  1641. "same time\n");
  1642. /*
  1643. * Do not allow the concurrent scanning state for now. This
  1644. * could be improved with scanning control moved into ath9k.
  1645. */
  1646. mutex_unlock(&sc->mutex);
  1647. return;
  1648. }
  1649. aphy->state = ATH_WIPHY_SCAN;
  1650. ath9k_wiphy_pause_all_forced(sc, aphy);
  1651. sc->sc_flags |= SC_OP_SCANNING;
  1652. del_timer_sync(&common->ani.timer);
  1653. cancel_work_sync(&sc->paprd_work);
  1654. cancel_delayed_work_sync(&sc->tx_complete_work);
  1655. mutex_unlock(&sc->mutex);
  1656. }
  1657. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1658. {
  1659. struct ath_wiphy *aphy = hw->priv;
  1660. struct ath_softc *sc = aphy->sc;
  1661. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1662. mutex_lock(&sc->mutex);
  1663. aphy->state = ATH_WIPHY_ACTIVE;
  1664. sc->sc_flags &= ~SC_OP_SCANNING;
  1665. sc->sc_flags |= SC_OP_FULL_RESET;
  1666. ath_start_ani(common);
  1667. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  1668. ath_beacon_config(sc, NULL);
  1669. mutex_unlock(&sc->mutex);
  1670. }
  1671. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1672. {
  1673. struct ath_wiphy *aphy = hw->priv;
  1674. struct ath_softc *sc = aphy->sc;
  1675. struct ath_hw *ah = sc->sc_ah;
  1676. mutex_lock(&sc->mutex);
  1677. ah->coverage_class = coverage_class;
  1678. ath9k_hw_init_global_settings(ah);
  1679. mutex_unlock(&sc->mutex);
  1680. }
  1681. struct ieee80211_ops ath9k_ops = {
  1682. .tx = ath9k_tx,
  1683. .start = ath9k_start,
  1684. .stop = ath9k_stop,
  1685. .add_interface = ath9k_add_interface,
  1686. .remove_interface = ath9k_remove_interface,
  1687. .config = ath9k_config,
  1688. .configure_filter = ath9k_configure_filter,
  1689. .sta_add = ath9k_sta_add,
  1690. .sta_remove = ath9k_sta_remove,
  1691. .conf_tx = ath9k_conf_tx,
  1692. .bss_info_changed = ath9k_bss_info_changed,
  1693. .set_key = ath9k_set_key,
  1694. .get_tsf = ath9k_get_tsf,
  1695. .set_tsf = ath9k_set_tsf,
  1696. .reset_tsf = ath9k_reset_tsf,
  1697. .ampdu_action = ath9k_ampdu_action,
  1698. .get_survey = ath9k_get_survey,
  1699. .sw_scan_start = ath9k_sw_scan_start,
  1700. .sw_scan_complete = ath9k_sw_scan_complete,
  1701. .rfkill_poll = ath9k_rfkill_poll_state,
  1702. .set_coverage_class = ath9k_set_coverage_class,
  1703. };