ar9003_mac.h 3.5 KB

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  1. /*
  2. * Copyright (c) 2010 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef AR9003_MAC_H
  17. #define AR9003_MAC_H
  18. #define AR_DescId 0xffff0000
  19. #define AR_DescId_S 16
  20. #define AR_CtrlStat 0x00004000
  21. #define AR_CtrlStat_S 14
  22. #define AR_TxRxDesc 0x00008000
  23. #define AR_TxRxDesc_S 15
  24. #define AR_TxQcuNum 0x00000f00
  25. #define AR_TxQcuNum_S 8
  26. #define AR_BufLen 0x0fff0000
  27. #define AR_BufLen_S 16
  28. #define AR_TxDescId 0xffff0000
  29. #define AR_TxDescId_S 16
  30. #define AR_TxPtrChkSum 0x0000ffff
  31. #define AR_TxTid 0xf0000000
  32. #define AR_TxTid_S 28
  33. #define AR_LowRxChain 0x00004000
  34. #define AR_Not_Sounding 0x20000000
  35. /* ctl 12 */
  36. #define AR_PAPRDChainMask 0x00000e00
  37. #define AR_PAPRDChainMask_S 9
  38. #define MAP_ISR_S2_CST 6
  39. #define MAP_ISR_S2_GTT 6
  40. #define MAP_ISR_S2_TIM 3
  41. #define MAP_ISR_S2_CABEND 0
  42. #define MAP_ISR_S2_DTIMSYNC 7
  43. #define MAP_ISR_S2_DTIM 7
  44. #define MAP_ISR_S2_TSFOOR 4
  45. #define MAP_ISR_S2_BB_WATCHDOG 6
  46. #define AR9003TXC_CONST(_ds) ((const struct ar9003_txc *) _ds)
  47. struct ar9003_rxs {
  48. u32 ds_info;
  49. u32 status1;
  50. u32 status2;
  51. u32 status3;
  52. u32 status4;
  53. u32 status5;
  54. u32 status6;
  55. u32 status7;
  56. u32 status8;
  57. u32 status9;
  58. u32 status10;
  59. u32 status11;
  60. } __packed;
  61. /* Transmit Control Descriptor */
  62. struct ar9003_txc {
  63. u32 info; /* descriptor information */
  64. u32 link; /* link pointer */
  65. u32 data0; /* data pointer to 1st buffer */
  66. u32 ctl3; /* DMA control 3 */
  67. u32 data1; /* data pointer to 2nd buffer */
  68. u32 ctl5; /* DMA control 5 */
  69. u32 data2; /* data pointer to 3rd buffer */
  70. u32 ctl7; /* DMA control 7 */
  71. u32 data3; /* data pointer to 4th buffer */
  72. u32 ctl9; /* DMA control 9 */
  73. u32 ctl10; /* DMA control 10 */
  74. u32 ctl11; /* DMA control 11 */
  75. u32 ctl12; /* DMA control 12 */
  76. u32 ctl13; /* DMA control 13 */
  77. u32 ctl14; /* DMA control 14 */
  78. u32 ctl15; /* DMA control 15 */
  79. u32 ctl16; /* DMA control 16 */
  80. u32 ctl17; /* DMA control 17 */
  81. u32 ctl18; /* DMA control 18 */
  82. u32 ctl19; /* DMA control 19 */
  83. u32 ctl20; /* DMA control 20 */
  84. u32 ctl21; /* DMA control 21 */
  85. u32 ctl22; /* DMA control 22 */
  86. u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
  87. } __packed;
  88. struct ar9003_txs {
  89. u32 ds_info;
  90. u32 status1;
  91. u32 status2;
  92. u32 status3;
  93. u32 status4;
  94. u32 status5;
  95. u32 status6;
  96. u32 status7;
  97. u32 status8;
  98. } __packed;
  99. void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
  100. void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
  101. void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
  102. enum ath9k_rx_qtype qtype);
  103. int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah,
  104. struct ath_rx_status *rxs,
  105. void *buf_addr);
  106. void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah);
  107. void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
  108. u32 ts_paddr_start,
  109. u8 size);
  110. #endif