common.c 151 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/sched.h>
  32. #include <linux/slab.h>
  33. #include <linux/types.h>
  34. #include <linux/lockdep.h>
  35. #include <linux/init.h>
  36. #include <linux/pci.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/delay.h>
  39. #include <linux/skbuff.h>
  40. #include <net/mac80211.h>
  41. #include "common.h"
  42. int
  43. _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
  44. {
  45. const int interval = 10; /* microseconds */
  46. int t = 0;
  47. do {
  48. if ((_il_rd(il, addr) & mask) == (bits & mask))
  49. return t;
  50. udelay(interval);
  51. t += interval;
  52. } while (t < timeout);
  53. return -ETIMEDOUT;
  54. }
  55. EXPORT_SYMBOL(_il_poll_bit);
  56. void
  57. il_set_bit(struct il_priv *p, u32 r, u32 m)
  58. {
  59. unsigned long reg_flags;
  60. spin_lock_irqsave(&p->reg_lock, reg_flags);
  61. _il_set_bit(p, r, m);
  62. spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  63. }
  64. EXPORT_SYMBOL(il_set_bit);
  65. void
  66. il_clear_bit(struct il_priv *p, u32 r, u32 m)
  67. {
  68. unsigned long reg_flags;
  69. spin_lock_irqsave(&p->reg_lock, reg_flags);
  70. _il_clear_bit(p, r, m);
  71. spin_unlock_irqrestore(&p->reg_lock, reg_flags);
  72. }
  73. EXPORT_SYMBOL(il_clear_bit);
  74. int
  75. _il_grab_nic_access(struct il_priv *il)
  76. {
  77. int ret;
  78. u32 val;
  79. /* this bit wakes up the NIC */
  80. _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  81. /*
  82. * These bits say the device is running, and should keep running for
  83. * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
  84. * but they do not indicate that embedded SRAM is restored yet;
  85. * 3945 and 4965 have volatile SRAM, and must save/restore contents
  86. * to/from host DRAM when sleeping/waking for power-saving.
  87. * Each direction takes approximately 1/4 millisecond; with this
  88. * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
  89. * series of register accesses are expected (e.g. reading Event Log),
  90. * to keep device from sleeping.
  91. *
  92. * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
  93. * SRAM is okay/restored. We don't check that here because this call
  94. * is just for hardware register access; but GP1 MAC_SLEEP check is a
  95. * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
  96. *
  97. */
  98. ret =
  99. _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
  100. (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
  101. CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
  102. if (ret < 0) {
  103. val = _il_rd(il, CSR_GP_CNTRL);
  104. IL_ERR("MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
  105. _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
  106. return -EIO;
  107. }
  108. return 0;
  109. }
  110. EXPORT_SYMBOL_GPL(_il_grab_nic_access);
  111. int
  112. il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
  113. {
  114. const int interval = 10; /* microseconds */
  115. int t = 0;
  116. do {
  117. if ((il_rd(il, addr) & mask) == mask)
  118. return t;
  119. udelay(interval);
  120. t += interval;
  121. } while (t < timeout);
  122. return -ETIMEDOUT;
  123. }
  124. EXPORT_SYMBOL(il_poll_bit);
  125. u32
  126. il_rd_prph(struct il_priv *il, u32 reg)
  127. {
  128. unsigned long reg_flags;
  129. u32 val;
  130. spin_lock_irqsave(&il->reg_lock, reg_flags);
  131. _il_grab_nic_access(il);
  132. val = _il_rd_prph(il, reg);
  133. _il_release_nic_access(il);
  134. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  135. return val;
  136. }
  137. EXPORT_SYMBOL(il_rd_prph);
  138. void
  139. il_wr_prph(struct il_priv *il, u32 addr, u32 val)
  140. {
  141. unsigned long reg_flags;
  142. spin_lock_irqsave(&il->reg_lock, reg_flags);
  143. if (!_il_grab_nic_access(il)) {
  144. _il_wr_prph(il, addr, val);
  145. _il_release_nic_access(il);
  146. }
  147. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  148. }
  149. EXPORT_SYMBOL(il_wr_prph);
  150. u32
  151. il_read_targ_mem(struct il_priv *il, u32 addr)
  152. {
  153. unsigned long reg_flags;
  154. u32 value;
  155. spin_lock_irqsave(&il->reg_lock, reg_flags);
  156. _il_grab_nic_access(il);
  157. _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
  158. rmb();
  159. value = _il_rd(il, HBUS_TARG_MEM_RDAT);
  160. _il_release_nic_access(il);
  161. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  162. return value;
  163. }
  164. EXPORT_SYMBOL(il_read_targ_mem);
  165. void
  166. il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
  167. {
  168. unsigned long reg_flags;
  169. spin_lock_irqsave(&il->reg_lock, reg_flags);
  170. if (!_il_grab_nic_access(il)) {
  171. _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
  172. wmb();
  173. _il_wr(il, HBUS_TARG_MEM_WDAT, val);
  174. _il_release_nic_access(il);
  175. }
  176. spin_unlock_irqrestore(&il->reg_lock, reg_flags);
  177. }
  178. EXPORT_SYMBOL(il_write_targ_mem);
  179. const char *
  180. il_get_cmd_string(u8 cmd)
  181. {
  182. switch (cmd) {
  183. IL_CMD(N_ALIVE);
  184. IL_CMD(N_ERROR);
  185. IL_CMD(C_RXON);
  186. IL_CMD(C_RXON_ASSOC);
  187. IL_CMD(C_QOS_PARAM);
  188. IL_CMD(C_RXON_TIMING);
  189. IL_CMD(C_ADD_STA);
  190. IL_CMD(C_REM_STA);
  191. IL_CMD(C_WEPKEY);
  192. IL_CMD(N_3945_RX);
  193. IL_CMD(C_TX);
  194. IL_CMD(C_RATE_SCALE);
  195. IL_CMD(C_LEDS);
  196. IL_CMD(C_TX_LINK_QUALITY_CMD);
  197. IL_CMD(C_CHANNEL_SWITCH);
  198. IL_CMD(N_CHANNEL_SWITCH);
  199. IL_CMD(C_SPECTRUM_MEASUREMENT);
  200. IL_CMD(N_SPECTRUM_MEASUREMENT);
  201. IL_CMD(C_POWER_TBL);
  202. IL_CMD(N_PM_SLEEP);
  203. IL_CMD(N_PM_DEBUG_STATS);
  204. IL_CMD(C_SCAN);
  205. IL_CMD(C_SCAN_ABORT);
  206. IL_CMD(N_SCAN_START);
  207. IL_CMD(N_SCAN_RESULTS);
  208. IL_CMD(N_SCAN_COMPLETE);
  209. IL_CMD(N_BEACON);
  210. IL_CMD(C_TX_BEACON);
  211. IL_CMD(C_TX_PWR_TBL);
  212. IL_CMD(C_BT_CONFIG);
  213. IL_CMD(C_STATS);
  214. IL_CMD(N_STATS);
  215. IL_CMD(N_CARD_STATE);
  216. IL_CMD(N_MISSED_BEACONS);
  217. IL_CMD(C_CT_KILL_CONFIG);
  218. IL_CMD(C_SENSITIVITY);
  219. IL_CMD(C_PHY_CALIBRATION);
  220. IL_CMD(N_RX_PHY);
  221. IL_CMD(N_RX_MPDU);
  222. IL_CMD(N_RX);
  223. IL_CMD(N_COMPRESSED_BA);
  224. default:
  225. return "UNKNOWN";
  226. }
  227. }
  228. EXPORT_SYMBOL(il_get_cmd_string);
  229. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  230. static void
  231. il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
  232. struct il_rx_pkt *pkt)
  233. {
  234. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  235. IL_ERR("Bad return from %s (0x%08X)\n",
  236. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  237. return;
  238. }
  239. #ifdef CONFIG_IWLEGACY_DEBUG
  240. switch (cmd->hdr.cmd) {
  241. case C_TX_LINK_QUALITY_CMD:
  242. case C_SENSITIVITY:
  243. D_HC_DUMP("back from %s (0x%08X)\n",
  244. il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
  245. break;
  246. default:
  247. D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
  248. pkt->hdr.flags);
  249. }
  250. #endif
  251. }
  252. static int
  253. il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
  254. {
  255. int ret;
  256. BUG_ON(!(cmd->flags & CMD_ASYNC));
  257. /* An asynchronous command can not expect an SKB to be set. */
  258. BUG_ON(cmd->flags & CMD_WANT_SKB);
  259. /* Assign a generic callback if one is not provided */
  260. if (!cmd->callback)
  261. cmd->callback = il_generic_cmd_callback;
  262. if (test_bit(S_EXIT_PENDING, &il->status))
  263. return -EBUSY;
  264. ret = il_enqueue_hcmd(il, cmd);
  265. if (ret < 0) {
  266. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  267. il_get_cmd_string(cmd->id), ret);
  268. return ret;
  269. }
  270. return 0;
  271. }
  272. int
  273. il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
  274. {
  275. int cmd_idx;
  276. int ret;
  277. lockdep_assert_held(&il->mutex);
  278. BUG_ON(cmd->flags & CMD_ASYNC);
  279. /* A synchronous command can not have a callback set. */
  280. BUG_ON(cmd->callback);
  281. D_INFO("Attempting to send sync command %s\n",
  282. il_get_cmd_string(cmd->id));
  283. set_bit(S_HCMD_ACTIVE, &il->status);
  284. D_INFO("Setting HCMD_ACTIVE for command %s\n",
  285. il_get_cmd_string(cmd->id));
  286. cmd_idx = il_enqueue_hcmd(il, cmd);
  287. if (cmd_idx < 0) {
  288. ret = cmd_idx;
  289. IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
  290. il_get_cmd_string(cmd->id), ret);
  291. goto out;
  292. }
  293. ret = wait_event_timeout(il->wait_command_queue,
  294. !test_bit(S_HCMD_ACTIVE, &il->status),
  295. HOST_COMPLETE_TIMEOUT);
  296. if (!ret) {
  297. if (test_bit(S_HCMD_ACTIVE, &il->status)) {
  298. IL_ERR("Error sending %s: time out after %dms.\n",
  299. il_get_cmd_string(cmd->id),
  300. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  301. clear_bit(S_HCMD_ACTIVE, &il->status);
  302. D_INFO("Clearing HCMD_ACTIVE for command %s\n",
  303. il_get_cmd_string(cmd->id));
  304. ret = -ETIMEDOUT;
  305. goto cancel;
  306. }
  307. }
  308. if (test_bit(S_RF_KILL_HW, &il->status)) {
  309. IL_ERR("Command %s aborted: RF KILL Switch\n",
  310. il_get_cmd_string(cmd->id));
  311. ret = -ECANCELED;
  312. goto fail;
  313. }
  314. if (test_bit(S_FW_ERROR, &il->status)) {
  315. IL_ERR("Command %s failed: FW Error\n",
  316. il_get_cmd_string(cmd->id));
  317. ret = -EIO;
  318. goto fail;
  319. }
  320. if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
  321. IL_ERR("Error: Response NULL in '%s'\n",
  322. il_get_cmd_string(cmd->id));
  323. ret = -EIO;
  324. goto cancel;
  325. }
  326. ret = 0;
  327. goto out;
  328. cancel:
  329. if (cmd->flags & CMD_WANT_SKB) {
  330. /*
  331. * Cancel the CMD_WANT_SKB flag for the cmd in the
  332. * TX cmd queue. Otherwise in case the cmd comes
  333. * in later, it will possibly set an invalid
  334. * address (cmd->meta.source).
  335. */
  336. il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
  337. }
  338. fail:
  339. if (cmd->reply_page) {
  340. il_free_pages(il, cmd->reply_page);
  341. cmd->reply_page = 0;
  342. }
  343. out:
  344. return ret;
  345. }
  346. EXPORT_SYMBOL(il_send_cmd_sync);
  347. int
  348. il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
  349. {
  350. if (cmd->flags & CMD_ASYNC)
  351. return il_send_cmd_async(il, cmd);
  352. return il_send_cmd_sync(il, cmd);
  353. }
  354. EXPORT_SYMBOL(il_send_cmd);
  355. int
  356. il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
  357. {
  358. struct il_host_cmd cmd = {
  359. .id = id,
  360. .len = len,
  361. .data = data,
  362. };
  363. return il_send_cmd_sync(il, &cmd);
  364. }
  365. EXPORT_SYMBOL(il_send_cmd_pdu);
  366. int
  367. il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
  368. void (*callback) (struct il_priv *il,
  369. struct il_device_cmd *cmd,
  370. struct il_rx_pkt *pkt))
  371. {
  372. struct il_host_cmd cmd = {
  373. .id = id,
  374. .len = len,
  375. .data = data,
  376. };
  377. cmd.flags |= CMD_ASYNC;
  378. cmd.callback = callback;
  379. return il_send_cmd_async(il, &cmd);
  380. }
  381. EXPORT_SYMBOL(il_send_cmd_pdu_async);
  382. /* default: IL_LED_BLINK(0) using blinking idx table */
  383. static int led_mode;
  384. module_param(led_mode, int, S_IRUGO);
  385. MODULE_PARM_DESC(led_mode,
  386. "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
  387. /* Throughput OFF time(ms) ON time (ms)
  388. * >300 25 25
  389. * >200 to 300 40 40
  390. * >100 to 200 55 55
  391. * >70 to 100 65 65
  392. * >50 to 70 75 75
  393. * >20 to 50 85 85
  394. * >10 to 20 95 95
  395. * >5 to 10 110 110
  396. * >1 to 5 130 130
  397. * >0 to 1 167 167
  398. * <=0 SOLID ON
  399. */
  400. static const struct ieee80211_tpt_blink il_blink[] = {
  401. {.throughput = 0, .blink_time = 334},
  402. {.throughput = 1 * 1024 - 1, .blink_time = 260},
  403. {.throughput = 5 * 1024 - 1, .blink_time = 220},
  404. {.throughput = 10 * 1024 - 1, .blink_time = 190},
  405. {.throughput = 20 * 1024 - 1, .blink_time = 170},
  406. {.throughput = 50 * 1024 - 1, .blink_time = 150},
  407. {.throughput = 70 * 1024 - 1, .blink_time = 130},
  408. {.throughput = 100 * 1024 - 1, .blink_time = 110},
  409. {.throughput = 200 * 1024 - 1, .blink_time = 80},
  410. {.throughput = 300 * 1024 - 1, .blink_time = 50},
  411. };
  412. /*
  413. * Adjust led blink rate to compensate on a MAC Clock difference on every HW
  414. * Led blink rate analysis showed an average deviation of 0% on 3945,
  415. * 5% on 4965 HW.
  416. * Need to compensate on the led on/off time per HW according to the deviation
  417. * to achieve the desired led frequency
  418. * The calculation is: (100-averageDeviation)/100 * blinkTime
  419. * For code efficiency the calculation will be:
  420. * compensation = (100 - averageDeviation) * 64 / 100
  421. * NewBlinkTime = (compensation * BlinkTime) / 64
  422. */
  423. static inline u8
  424. il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
  425. {
  426. if (!compensation) {
  427. IL_ERR("undefined blink compensation: "
  428. "use pre-defined blinking time\n");
  429. return time;
  430. }
  431. return (u8) ((time * compensation) >> 6);
  432. }
  433. /* Set led pattern command */
  434. static int
  435. il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
  436. {
  437. struct il_led_cmd led_cmd = {
  438. .id = IL_LED_LINK,
  439. .interval = IL_DEF_LED_INTRVL
  440. };
  441. int ret;
  442. if (!test_bit(S_READY, &il->status))
  443. return -EBUSY;
  444. if (il->blink_on == on && il->blink_off == off)
  445. return 0;
  446. if (off == 0) {
  447. /* led is SOLID_ON */
  448. on = IL_LED_SOLID;
  449. }
  450. D_LED("Led blink time compensation=%u\n",
  451. il->cfg->base_params->led_compensation);
  452. led_cmd.on =
  453. il_blink_compensation(il, on,
  454. il->cfg->base_params->led_compensation);
  455. led_cmd.off =
  456. il_blink_compensation(il, off,
  457. il->cfg->base_params->led_compensation);
  458. ret = il->cfg->ops->led->cmd(il, &led_cmd);
  459. if (!ret) {
  460. il->blink_on = on;
  461. il->blink_off = off;
  462. }
  463. return ret;
  464. }
  465. static void
  466. il_led_brightness_set(struct led_classdev *led_cdev,
  467. enum led_brightness brightness)
  468. {
  469. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  470. unsigned long on = 0;
  471. if (brightness > 0)
  472. on = IL_LED_SOLID;
  473. il_led_cmd(il, on, 0);
  474. }
  475. static int
  476. il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
  477. unsigned long *delay_off)
  478. {
  479. struct il_priv *il = container_of(led_cdev, struct il_priv, led);
  480. return il_led_cmd(il, *delay_on, *delay_off);
  481. }
  482. void
  483. il_leds_init(struct il_priv *il)
  484. {
  485. int mode = led_mode;
  486. int ret;
  487. if (mode == IL_LED_DEFAULT)
  488. mode = il->cfg->led_mode;
  489. il->led.name =
  490. kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
  491. il->led.brightness_set = il_led_brightness_set;
  492. il->led.blink_set = il_led_blink_set;
  493. il->led.max_brightness = 1;
  494. switch (mode) {
  495. case IL_LED_DEFAULT:
  496. WARN_ON(1);
  497. break;
  498. case IL_LED_BLINK:
  499. il->led.default_trigger =
  500. ieee80211_create_tpt_led_trigger(il->hw,
  501. IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
  502. il_blink,
  503. ARRAY_SIZE(il_blink));
  504. break;
  505. case IL_LED_RF_STATE:
  506. il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
  507. break;
  508. }
  509. ret = led_classdev_register(&il->pci_dev->dev, &il->led);
  510. if (ret) {
  511. kfree(il->led.name);
  512. return;
  513. }
  514. il->led_registered = true;
  515. }
  516. EXPORT_SYMBOL(il_leds_init);
  517. void
  518. il_leds_exit(struct il_priv *il)
  519. {
  520. if (!il->led_registered)
  521. return;
  522. led_classdev_unregister(&il->led);
  523. kfree(il->led.name);
  524. }
  525. EXPORT_SYMBOL(il_leds_exit);
  526. /************************** EEPROM BANDS ****************************
  527. *
  528. * The il_eeprom_band definitions below provide the mapping from the
  529. * EEPROM contents to the specific channel number supported for each
  530. * band.
  531. *
  532. * For example, il_priv->eeprom.band_3_channels[4] from the band_3
  533. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  534. * The specific geography and calibration information for that channel
  535. * is contained in the eeprom map itself.
  536. *
  537. * During init, we copy the eeprom information and channel map
  538. * information into il->channel_info_24/52 and il->channel_map_24/52
  539. *
  540. * channel_map_24/52 provides the idx in the channel_info array for a
  541. * given channel. We have to have two separate maps as there is channel
  542. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  543. * band_2
  544. *
  545. * A value of 0xff stored in the channel_map indicates that the channel
  546. * is not supported by the hardware at all.
  547. *
  548. * A value of 0xfe in the channel_map indicates that the channel is not
  549. * valid for Tx with the current hardware. This means that
  550. * while the system can tune and receive on a given channel, it may not
  551. * be able to associate or transmit any frames on that
  552. * channel. There is no corresponding channel information for that
  553. * entry.
  554. *
  555. *********************************************************************/
  556. /* 2.4 GHz */
  557. const u8 il_eeprom_band_1[14] = {
  558. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  559. };
  560. /* 5.2 GHz bands */
  561. static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
  562. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  563. };
  564. static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
  565. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  566. };
  567. static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
  568. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  569. };
  570. static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
  571. 145, 149, 153, 157, 161, 165
  572. };
  573. static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
  574. 1, 2, 3, 4, 5, 6, 7
  575. };
  576. static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
  577. 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
  578. };
  579. /******************************************************************************
  580. *
  581. * EEPROM related functions
  582. *
  583. ******************************************************************************/
  584. static int
  585. il_eeprom_verify_signature(struct il_priv *il)
  586. {
  587. u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
  588. int ret = 0;
  589. D_EEPROM("EEPROM signature=0x%08x\n", gp);
  590. switch (gp) {
  591. case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
  592. case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
  593. break;
  594. default:
  595. IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
  596. ret = -ENOENT;
  597. break;
  598. }
  599. return ret;
  600. }
  601. const u8 *
  602. il_eeprom_query_addr(const struct il_priv *il, size_t offset)
  603. {
  604. BUG_ON(offset >= il->cfg->base_params->eeprom_size);
  605. return &il->eeprom[offset];
  606. }
  607. EXPORT_SYMBOL(il_eeprom_query_addr);
  608. u16
  609. il_eeprom_query16(const struct il_priv *il, size_t offset)
  610. {
  611. if (!il->eeprom)
  612. return 0;
  613. return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
  614. }
  615. EXPORT_SYMBOL(il_eeprom_query16);
  616. /**
  617. * il_eeprom_init - read EEPROM contents
  618. *
  619. * Load the EEPROM contents from adapter into il->eeprom
  620. *
  621. * NOTE: This routine uses the non-debug IO access functions.
  622. */
  623. int
  624. il_eeprom_init(struct il_priv *il)
  625. {
  626. __le16 *e;
  627. u32 gp = _il_rd(il, CSR_EEPROM_GP);
  628. int sz;
  629. int ret;
  630. u16 addr;
  631. /* allocate eeprom */
  632. sz = il->cfg->base_params->eeprom_size;
  633. D_EEPROM("NVM size = %d\n", sz);
  634. il->eeprom = kzalloc(sz, GFP_KERNEL);
  635. if (!il->eeprom) {
  636. ret = -ENOMEM;
  637. goto alloc_err;
  638. }
  639. e = (__le16 *) il->eeprom;
  640. il->cfg->ops->lib->apm_ops.init(il);
  641. ret = il_eeprom_verify_signature(il);
  642. if (ret < 0) {
  643. IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  644. ret = -ENOENT;
  645. goto err;
  646. }
  647. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  648. ret = il->cfg->ops->lib->eeprom_ops.acquire_semaphore(il);
  649. if (ret < 0) {
  650. IL_ERR("Failed to acquire EEPROM semaphore.\n");
  651. ret = -ENOENT;
  652. goto err;
  653. }
  654. /* eeprom is an array of 16bit values */
  655. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  656. u32 r;
  657. _il_wr(il, CSR_EEPROM_REG,
  658. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  659. ret =
  660. _il_poll_bit(il, CSR_EEPROM_REG,
  661. CSR_EEPROM_REG_READ_VALID_MSK,
  662. CSR_EEPROM_REG_READ_VALID_MSK,
  663. IL_EEPROM_ACCESS_TIMEOUT);
  664. if (ret < 0) {
  665. IL_ERR("Time out reading EEPROM[%d]\n", addr);
  666. goto done;
  667. }
  668. r = _il_rd(il, CSR_EEPROM_REG);
  669. e[addr / 2] = cpu_to_le16(r >> 16);
  670. }
  671. D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
  672. il_eeprom_query16(il, EEPROM_VERSION));
  673. ret = 0;
  674. done:
  675. il->cfg->ops->lib->eeprom_ops.release_semaphore(il);
  676. err:
  677. if (ret)
  678. il_eeprom_free(il);
  679. /* Reset chip to save power until we load uCode during "up". */
  680. il_apm_stop(il);
  681. alloc_err:
  682. return ret;
  683. }
  684. EXPORT_SYMBOL(il_eeprom_init);
  685. void
  686. il_eeprom_free(struct il_priv *il)
  687. {
  688. kfree(il->eeprom);
  689. il->eeprom = NULL;
  690. }
  691. EXPORT_SYMBOL(il_eeprom_free);
  692. static void
  693. il_init_band_reference(const struct il_priv *il, int eep_band,
  694. int *eeprom_ch_count,
  695. const struct il_eeprom_channel **eeprom_ch_info,
  696. const u8 **eeprom_ch_idx)
  697. {
  698. u32 offset =
  699. il->cfg->ops->lib->eeprom_ops.regulatory_bands[eep_band - 1];
  700. switch (eep_band) {
  701. case 1: /* 2.4GHz band */
  702. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
  703. *eeprom_ch_info =
  704. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  705. offset);
  706. *eeprom_ch_idx = il_eeprom_band_1;
  707. break;
  708. case 2: /* 4.9GHz band */
  709. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
  710. *eeprom_ch_info =
  711. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  712. offset);
  713. *eeprom_ch_idx = il_eeprom_band_2;
  714. break;
  715. case 3: /* 5.2GHz band */
  716. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
  717. *eeprom_ch_info =
  718. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  719. offset);
  720. *eeprom_ch_idx = il_eeprom_band_3;
  721. break;
  722. case 4: /* 5.5GHz band */
  723. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
  724. *eeprom_ch_info =
  725. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  726. offset);
  727. *eeprom_ch_idx = il_eeprom_band_4;
  728. break;
  729. case 5: /* 5.7GHz band */
  730. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
  731. *eeprom_ch_info =
  732. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  733. offset);
  734. *eeprom_ch_idx = il_eeprom_band_5;
  735. break;
  736. case 6: /* 2.4GHz ht40 channels */
  737. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
  738. *eeprom_ch_info =
  739. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  740. offset);
  741. *eeprom_ch_idx = il_eeprom_band_6;
  742. break;
  743. case 7: /* 5 GHz ht40 channels */
  744. *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
  745. *eeprom_ch_info =
  746. (struct il_eeprom_channel *)il_eeprom_query_addr(il,
  747. offset);
  748. *eeprom_ch_idx = il_eeprom_band_7;
  749. break;
  750. default:
  751. BUG();
  752. }
  753. }
  754. #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
  755. ? # x " " : "")
  756. /**
  757. * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
  758. *
  759. * Does not set up a command, or touch hardware.
  760. */
  761. static int
  762. il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel,
  763. const struct il_eeprom_channel *eeprom_ch,
  764. u8 clear_ht40_extension_channel)
  765. {
  766. struct il_channel_info *ch_info;
  767. ch_info =
  768. (struct il_channel_info *)il_get_channel_info(il, band, channel);
  769. if (!il_is_channel_valid(ch_info))
  770. return -1;
  771. D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
  772. " Ad-Hoc %ssupported\n", ch_info->channel,
  773. il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
  774. CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
  775. CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
  776. CHECK_AND_PRINT(DFS), eeprom_ch->flags,
  777. eeprom_ch->max_power_avg,
  778. ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
  779. !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
  780. ch_info->ht40_eeprom = *eeprom_ch;
  781. ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
  782. ch_info->ht40_flags = eeprom_ch->flags;
  783. if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
  784. ch_info->ht40_extension_channel &=
  785. ~clear_ht40_extension_channel;
  786. return 0;
  787. }
  788. #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  789. ? # x " " : "")
  790. /**
  791. * il_init_channel_map - Set up driver's info for all possible channels
  792. */
  793. int
  794. il_init_channel_map(struct il_priv *il)
  795. {
  796. int eeprom_ch_count = 0;
  797. const u8 *eeprom_ch_idx = NULL;
  798. const struct il_eeprom_channel *eeprom_ch_info = NULL;
  799. int band, ch;
  800. struct il_channel_info *ch_info;
  801. if (il->channel_count) {
  802. D_EEPROM("Channel map already initialized.\n");
  803. return 0;
  804. }
  805. D_EEPROM("Initializing regulatory info from EEPROM\n");
  806. il->channel_count =
  807. ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
  808. ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
  809. ARRAY_SIZE(il_eeprom_band_5);
  810. D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
  811. il->channel_info =
  812. kzalloc(sizeof(struct il_channel_info) * il->channel_count,
  813. GFP_KERNEL);
  814. if (!il->channel_info) {
  815. IL_ERR("Could not allocate channel_info\n");
  816. il->channel_count = 0;
  817. return -ENOMEM;
  818. }
  819. ch_info = il->channel_info;
  820. /* Loop through the 5 EEPROM bands adding them in order to the
  821. * channel map we maintain (that contains additional information than
  822. * what just in the EEPROM) */
  823. for (band = 1; band <= 5; band++) {
  824. il_init_band_reference(il, band, &eeprom_ch_count,
  825. &eeprom_ch_info, &eeprom_ch_idx);
  826. /* Loop through each band adding each of the channels */
  827. for (ch = 0; ch < eeprom_ch_count; ch++) {
  828. ch_info->channel = eeprom_ch_idx[ch];
  829. ch_info->band =
  830. (band ==
  831. 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  832. /* permanently store EEPROM's channel regulatory flags
  833. * and max power in channel info database. */
  834. ch_info->eeprom = eeprom_ch_info[ch];
  835. /* Copy the run-time flags so they are there even on
  836. * invalid channels */
  837. ch_info->flags = eeprom_ch_info[ch].flags;
  838. /* First write that ht40 is not enabled, and then enable
  839. * one by one */
  840. ch_info->ht40_extension_channel =
  841. IEEE80211_CHAN_NO_HT40;
  842. if (!(il_is_channel_valid(ch_info))) {
  843. D_EEPROM("Ch. %d Flags %x [%sGHz] - "
  844. "No traffic\n", ch_info->channel,
  845. ch_info->flags,
  846. il_is_channel_a_band(ch_info) ? "5.2" :
  847. "2.4");
  848. ch_info++;
  849. continue;
  850. }
  851. /* Initialize regulatory-based run-time data */
  852. ch_info->max_power_avg = ch_info->curr_txpow =
  853. eeprom_ch_info[ch].max_power_avg;
  854. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  855. ch_info->min_power = 0;
  856. D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
  857. " Ad-Hoc %ssupported\n", ch_info->channel,
  858. il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
  859. CHECK_AND_PRINT_I(VALID),
  860. CHECK_AND_PRINT_I(IBSS),
  861. CHECK_AND_PRINT_I(ACTIVE),
  862. CHECK_AND_PRINT_I(RADAR),
  863. CHECK_AND_PRINT_I(WIDE),
  864. CHECK_AND_PRINT_I(DFS),
  865. eeprom_ch_info[ch].flags,
  866. eeprom_ch_info[ch].max_power_avg,
  867. ((eeprom_ch_info[ch].
  868. flags & EEPROM_CHANNEL_IBSS) &&
  869. !(eeprom_ch_info[ch].
  870. flags & EEPROM_CHANNEL_RADAR)) ? "" :
  871. "not ");
  872. ch_info++;
  873. }
  874. }
  875. /* Check if we do have HT40 channels */
  876. if (il->cfg->ops->lib->eeprom_ops.regulatory_bands[5] ==
  877. EEPROM_REGULATORY_BAND_NO_HT40 &&
  878. il->cfg->ops->lib->eeprom_ops.regulatory_bands[6] ==
  879. EEPROM_REGULATORY_BAND_NO_HT40)
  880. return 0;
  881. /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
  882. for (band = 6; band <= 7; band++) {
  883. enum ieee80211_band ieeeband;
  884. il_init_band_reference(il, band, &eeprom_ch_count,
  885. &eeprom_ch_info, &eeprom_ch_idx);
  886. /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
  887. ieeeband =
  888. (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  889. /* Loop through each band adding each of the channels */
  890. for (ch = 0; ch < eeprom_ch_count; ch++) {
  891. /* Set up driver's info for lower half */
  892. il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
  893. &eeprom_ch_info[ch],
  894. IEEE80211_CHAN_NO_HT40PLUS);
  895. /* Set up driver's info for upper half */
  896. il_mod_ht40_chan_info(il, ieeeband,
  897. eeprom_ch_idx[ch] + 4,
  898. &eeprom_ch_info[ch],
  899. IEEE80211_CHAN_NO_HT40MINUS);
  900. }
  901. }
  902. return 0;
  903. }
  904. EXPORT_SYMBOL(il_init_channel_map);
  905. /*
  906. * il_free_channel_map - undo allocations in il_init_channel_map
  907. */
  908. void
  909. il_free_channel_map(struct il_priv *il)
  910. {
  911. kfree(il->channel_info);
  912. il->channel_count = 0;
  913. }
  914. EXPORT_SYMBOL(il_free_channel_map);
  915. /**
  916. * il_get_channel_info - Find driver's ilate channel info
  917. *
  918. * Based on band and channel number.
  919. */
  920. const struct il_channel_info *
  921. il_get_channel_info(const struct il_priv *il, enum ieee80211_band band,
  922. u16 channel)
  923. {
  924. int i;
  925. switch (band) {
  926. case IEEE80211_BAND_5GHZ:
  927. for (i = 14; i < il->channel_count; i++) {
  928. if (il->channel_info[i].channel == channel)
  929. return &il->channel_info[i];
  930. }
  931. break;
  932. case IEEE80211_BAND_2GHZ:
  933. if (channel >= 1 && channel <= 14)
  934. return &il->channel_info[channel - 1];
  935. break;
  936. default:
  937. BUG();
  938. }
  939. return NULL;
  940. }
  941. EXPORT_SYMBOL(il_get_channel_info);
  942. /*
  943. * Setting power level allows the card to go to sleep when not busy.
  944. *
  945. * We calculate a sleep command based on the required latency, which
  946. * we get from mac80211. In order to handle thermal throttling, we can
  947. * also use pre-defined power levels.
  948. */
  949. /*
  950. * This defines the old power levels. They are still used by default
  951. * (level 1) and for thermal throttle (levels 3 through 5)
  952. */
  953. struct il_power_vec_entry {
  954. struct il_powertable_cmd cmd;
  955. u8 no_dtim; /* number of skip dtim */
  956. };
  957. static void
  958. il_power_sleep_cam_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
  959. {
  960. memset(cmd, 0, sizeof(*cmd));
  961. if (il->power_data.pci_pm)
  962. cmd->flags |= IL_POWER_PCI_PM_MSK;
  963. D_POWER("Sleep command for CAM\n");
  964. }
  965. static int
  966. il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
  967. {
  968. D_POWER("Sending power/sleep command\n");
  969. D_POWER("Flags value = 0x%08X\n", cmd->flags);
  970. D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  971. D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  972. D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  973. le32_to_cpu(cmd->sleep_interval[0]),
  974. le32_to_cpu(cmd->sleep_interval[1]),
  975. le32_to_cpu(cmd->sleep_interval[2]),
  976. le32_to_cpu(cmd->sleep_interval[3]),
  977. le32_to_cpu(cmd->sleep_interval[4]));
  978. return il_send_cmd_pdu(il, C_POWER_TBL,
  979. sizeof(struct il_powertable_cmd), cmd);
  980. }
  981. int
  982. il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
  983. {
  984. int ret;
  985. bool update_chains;
  986. lockdep_assert_held(&il->mutex);
  987. /* Don't update the RX chain when chain noise calibration is running */
  988. update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
  989. il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
  990. if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
  991. return 0;
  992. if (!il_is_ready_rf(il))
  993. return -EIO;
  994. /* scan complete use sleep_power_next, need to be updated */
  995. memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
  996. if (test_bit(S_SCANNING, &il->status) && !force) {
  997. D_INFO("Defer power set mode while scanning\n");
  998. return 0;
  999. }
  1000. if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
  1001. set_bit(S_POWER_PMI, &il->status);
  1002. ret = il_set_power(il, cmd);
  1003. if (!ret) {
  1004. if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
  1005. clear_bit(S_POWER_PMI, &il->status);
  1006. if (il->cfg->ops->lib->update_chain_flags && update_chains)
  1007. il->cfg->ops->lib->update_chain_flags(il);
  1008. else if (il->cfg->ops->lib->update_chain_flags)
  1009. D_POWER("Cannot update the power, chain noise "
  1010. "calibration running: %d\n",
  1011. il->chain_noise_data.state);
  1012. memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
  1013. } else
  1014. IL_ERR("set power fail, ret = %d", ret);
  1015. return ret;
  1016. }
  1017. int
  1018. il_power_update_mode(struct il_priv *il, bool force)
  1019. {
  1020. struct il_powertable_cmd cmd;
  1021. il_power_sleep_cam_cmd(il, &cmd);
  1022. return il_power_set_mode(il, &cmd, force);
  1023. }
  1024. EXPORT_SYMBOL(il_power_update_mode);
  1025. /* initialize to default */
  1026. void
  1027. il_power_initialize(struct il_priv *il)
  1028. {
  1029. u16 lctl = il_pcie_link_ctl(il);
  1030. il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
  1031. il->power_data.debug_sleep_level_override = -1;
  1032. memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
  1033. }
  1034. EXPORT_SYMBOL(il_power_initialize);
  1035. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  1036. * sending probe req. This should be set long enough to hear probe responses
  1037. * from more than one AP. */
  1038. #define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  1039. #define IL_ACTIVE_DWELL_TIME_52 (20)
  1040. #define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  1041. #define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  1042. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  1043. * Must be set longer than active dwell time.
  1044. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  1045. #define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  1046. #define IL_PASSIVE_DWELL_TIME_52 (10)
  1047. #define IL_PASSIVE_DWELL_BASE (100)
  1048. #define IL_CHANNEL_TUNE_TIME 5
  1049. static int
  1050. il_send_scan_abort(struct il_priv *il)
  1051. {
  1052. int ret;
  1053. struct il_rx_pkt *pkt;
  1054. struct il_host_cmd cmd = {
  1055. .id = C_SCAN_ABORT,
  1056. .flags = CMD_WANT_SKB,
  1057. };
  1058. /* Exit instantly with error when device is not ready
  1059. * to receive scan abort command or it does not perform
  1060. * hardware scan currently */
  1061. if (!test_bit(S_READY, &il->status) ||
  1062. !test_bit(S_GEO_CONFIGURED, &il->status) ||
  1063. !test_bit(S_SCAN_HW, &il->status) ||
  1064. test_bit(S_FW_ERROR, &il->status) ||
  1065. test_bit(S_EXIT_PENDING, &il->status))
  1066. return -EIO;
  1067. ret = il_send_cmd_sync(il, &cmd);
  1068. if (ret)
  1069. return ret;
  1070. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1071. if (pkt->u.status != CAN_ABORT_STATUS) {
  1072. /* The scan abort will return 1 for success or
  1073. * 2 for "failure". A failure condition can be
  1074. * due to simply not being in an active scan which
  1075. * can occur if we send the scan abort before we
  1076. * the microcode has notified us that a scan is
  1077. * completed. */
  1078. D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
  1079. ret = -EIO;
  1080. }
  1081. il_free_pages(il, cmd.reply_page);
  1082. return ret;
  1083. }
  1084. static void
  1085. il_complete_scan(struct il_priv *il, bool aborted)
  1086. {
  1087. /* check if scan was requested from mac80211 */
  1088. if (il->scan_request) {
  1089. D_SCAN("Complete scan in mac80211\n");
  1090. ieee80211_scan_completed(il->hw, aborted);
  1091. }
  1092. il->scan_vif = NULL;
  1093. il->scan_request = NULL;
  1094. }
  1095. void
  1096. il_force_scan_end(struct il_priv *il)
  1097. {
  1098. lockdep_assert_held(&il->mutex);
  1099. if (!test_bit(S_SCANNING, &il->status)) {
  1100. D_SCAN("Forcing scan end while not scanning\n");
  1101. return;
  1102. }
  1103. D_SCAN("Forcing scan end\n");
  1104. clear_bit(S_SCANNING, &il->status);
  1105. clear_bit(S_SCAN_HW, &il->status);
  1106. clear_bit(S_SCAN_ABORTING, &il->status);
  1107. il_complete_scan(il, true);
  1108. }
  1109. static void
  1110. il_do_scan_abort(struct il_priv *il)
  1111. {
  1112. int ret;
  1113. lockdep_assert_held(&il->mutex);
  1114. if (!test_bit(S_SCANNING, &il->status)) {
  1115. D_SCAN("Not performing scan to abort\n");
  1116. return;
  1117. }
  1118. if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
  1119. D_SCAN("Scan abort in progress\n");
  1120. return;
  1121. }
  1122. ret = il_send_scan_abort(il);
  1123. if (ret) {
  1124. D_SCAN("Send scan abort failed %d\n", ret);
  1125. il_force_scan_end(il);
  1126. } else
  1127. D_SCAN("Successfully send scan abort\n");
  1128. }
  1129. /**
  1130. * il_scan_cancel - Cancel any currently executing HW scan
  1131. */
  1132. int
  1133. il_scan_cancel(struct il_priv *il)
  1134. {
  1135. D_SCAN("Queuing abort scan\n");
  1136. queue_work(il->workqueue, &il->abort_scan);
  1137. return 0;
  1138. }
  1139. EXPORT_SYMBOL(il_scan_cancel);
  1140. /**
  1141. * il_scan_cancel_timeout - Cancel any currently executing HW scan
  1142. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1143. *
  1144. */
  1145. int
  1146. il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
  1147. {
  1148. unsigned long timeout = jiffies + msecs_to_jiffies(ms);
  1149. lockdep_assert_held(&il->mutex);
  1150. D_SCAN("Scan cancel timeout\n");
  1151. il_do_scan_abort(il);
  1152. while (time_before_eq(jiffies, timeout)) {
  1153. if (!test_bit(S_SCAN_HW, &il->status))
  1154. break;
  1155. msleep(20);
  1156. }
  1157. return test_bit(S_SCAN_HW, &il->status);
  1158. }
  1159. EXPORT_SYMBOL(il_scan_cancel_timeout);
  1160. /* Service response to C_SCAN (0x80) */
  1161. static void
  1162. il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
  1163. {
  1164. #ifdef CONFIG_IWLEGACY_DEBUG
  1165. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1166. struct il_scanreq_notification *notif =
  1167. (struct il_scanreq_notification *)pkt->u.raw;
  1168. D_SCAN("Scan request status = 0x%x\n", notif->status);
  1169. #endif
  1170. }
  1171. /* Service N_SCAN_START (0x82) */
  1172. static void
  1173. il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
  1174. {
  1175. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1176. struct il_scanstart_notification *notif =
  1177. (struct il_scanstart_notification *)pkt->u.raw;
  1178. il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  1179. D_SCAN("Scan start: " "%d [802.11%s] "
  1180. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
  1181. notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
  1182. le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
  1183. }
  1184. /* Service N_SCAN_RESULTS (0x83) */
  1185. static void
  1186. il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
  1187. {
  1188. #ifdef CONFIG_IWLEGACY_DEBUG
  1189. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1190. struct il_scanresults_notification *notif =
  1191. (struct il_scanresults_notification *)pkt->u.raw;
  1192. D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
  1193. "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
  1194. le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
  1195. le32_to_cpu(notif->stats[0]),
  1196. le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
  1197. #endif
  1198. }
  1199. /* Service N_SCAN_COMPLETE (0x84) */
  1200. static void
  1201. il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
  1202. {
  1203. #ifdef CONFIG_IWLEGACY_DEBUG
  1204. struct il_rx_pkt *pkt = rxb_addr(rxb);
  1205. struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  1206. #endif
  1207. D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  1208. scan_notif->scanned_channels, scan_notif->tsf_low,
  1209. scan_notif->tsf_high, scan_notif->status);
  1210. /* The HW is no longer scanning */
  1211. clear_bit(S_SCAN_HW, &il->status);
  1212. D_SCAN("Scan on %sGHz took %dms\n",
  1213. (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
  1214. jiffies_to_msecs(jiffies - il->scan_start));
  1215. queue_work(il->workqueue, &il->scan_completed);
  1216. }
  1217. void
  1218. il_setup_rx_scan_handlers(struct il_priv *il)
  1219. {
  1220. /* scan handlers */
  1221. il->handlers[C_SCAN] = il_hdl_scan;
  1222. il->handlers[N_SCAN_START] = il_hdl_scan_start;
  1223. il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
  1224. il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
  1225. }
  1226. EXPORT_SYMBOL(il_setup_rx_scan_handlers);
  1227. inline u16
  1228. il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
  1229. u8 n_probes)
  1230. {
  1231. if (band == IEEE80211_BAND_5GHZ)
  1232. return IL_ACTIVE_DWELL_TIME_52 +
  1233. IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  1234. else
  1235. return IL_ACTIVE_DWELL_TIME_24 +
  1236. IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  1237. }
  1238. EXPORT_SYMBOL(il_get_active_dwell_time);
  1239. u16
  1240. il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
  1241. struct ieee80211_vif *vif)
  1242. {
  1243. struct il_rxon_context *ctx = &il->ctx;
  1244. u16 value;
  1245. u16 passive =
  1246. (band ==
  1247. IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
  1248. IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
  1249. IL_PASSIVE_DWELL_TIME_52;
  1250. if (il_is_any_associated(il)) {
  1251. /*
  1252. * If we're associated, we clamp the maximum passive
  1253. * dwell time to be 98% of the smallest beacon interval
  1254. * (minus 2 * channel tune time)
  1255. */
  1256. value = ctx->vif ? ctx->vif->bss_conf.beacon_int : 0;
  1257. if (value > IL_PASSIVE_DWELL_BASE || !value)
  1258. value = IL_PASSIVE_DWELL_BASE;
  1259. value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
  1260. passive = min(value, passive);
  1261. }
  1262. return passive;
  1263. }
  1264. EXPORT_SYMBOL(il_get_passive_dwell_time);
  1265. void
  1266. il_init_scan_params(struct il_priv *il)
  1267. {
  1268. u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
  1269. if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
  1270. il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
  1271. if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
  1272. il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
  1273. }
  1274. EXPORT_SYMBOL(il_init_scan_params);
  1275. static int
  1276. il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
  1277. {
  1278. int ret;
  1279. lockdep_assert_held(&il->mutex);
  1280. if (WARN_ON(!il->cfg->ops->utils->request_scan))
  1281. return -EOPNOTSUPP;
  1282. cancel_delayed_work(&il->scan_check);
  1283. if (!il_is_ready_rf(il)) {
  1284. IL_WARN("Request scan called when driver not ready.\n");
  1285. return -EIO;
  1286. }
  1287. if (test_bit(S_SCAN_HW, &il->status)) {
  1288. D_SCAN("Multiple concurrent scan requests in parallel.\n");
  1289. return -EBUSY;
  1290. }
  1291. if (test_bit(S_SCAN_ABORTING, &il->status)) {
  1292. D_SCAN("Scan request while abort pending.\n");
  1293. return -EBUSY;
  1294. }
  1295. D_SCAN("Starting scan...\n");
  1296. set_bit(S_SCANNING, &il->status);
  1297. il->scan_start = jiffies;
  1298. ret = il->cfg->ops->utils->request_scan(il, vif);
  1299. if (ret) {
  1300. clear_bit(S_SCANNING, &il->status);
  1301. return ret;
  1302. }
  1303. queue_delayed_work(il->workqueue, &il->scan_check,
  1304. IL_SCAN_CHECK_WATCHDOG);
  1305. return 0;
  1306. }
  1307. int
  1308. il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1309. struct cfg80211_scan_request *req)
  1310. {
  1311. struct il_priv *il = hw->priv;
  1312. int ret;
  1313. D_MAC80211("enter\n");
  1314. if (req->n_channels == 0)
  1315. return -EINVAL;
  1316. mutex_lock(&il->mutex);
  1317. if (test_bit(S_SCANNING, &il->status)) {
  1318. D_SCAN("Scan already in progress.\n");
  1319. ret = -EAGAIN;
  1320. goto out_unlock;
  1321. }
  1322. /* mac80211 will only ask for one band at a time */
  1323. il->scan_request = req;
  1324. il->scan_vif = vif;
  1325. il->scan_band = req->channels[0]->band;
  1326. ret = il_scan_initiate(il, vif);
  1327. D_MAC80211("leave\n");
  1328. out_unlock:
  1329. mutex_unlock(&il->mutex);
  1330. return ret;
  1331. }
  1332. EXPORT_SYMBOL(il_mac_hw_scan);
  1333. static void
  1334. il_bg_scan_check(struct work_struct *data)
  1335. {
  1336. struct il_priv *il =
  1337. container_of(data, struct il_priv, scan_check.work);
  1338. D_SCAN("Scan check work\n");
  1339. /* Since we are here firmware does not finish scan and
  1340. * most likely is in bad shape, so we don't bother to
  1341. * send abort command, just force scan complete to mac80211 */
  1342. mutex_lock(&il->mutex);
  1343. il_force_scan_end(il);
  1344. mutex_unlock(&il->mutex);
  1345. }
  1346. /**
  1347. * il_fill_probe_req - fill in all required fields and IE for probe request
  1348. */
  1349. u16
  1350. il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
  1351. const u8 *ta, const u8 *ies, int ie_len, int left)
  1352. {
  1353. int len = 0;
  1354. u8 *pos = NULL;
  1355. /* Make sure there is enough space for the probe request,
  1356. * two mandatory IEs and the data */
  1357. left -= 24;
  1358. if (left < 0)
  1359. return 0;
  1360. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1361. memcpy(frame->da, il_bcast_addr, ETH_ALEN);
  1362. memcpy(frame->sa, ta, ETH_ALEN);
  1363. memcpy(frame->bssid, il_bcast_addr, ETH_ALEN);
  1364. frame->seq_ctrl = 0;
  1365. len += 24;
  1366. /* ...next IE... */
  1367. pos = &frame->u.probe_req.variable[0];
  1368. /* fill in our indirect SSID IE */
  1369. left -= 2;
  1370. if (left < 0)
  1371. return 0;
  1372. *pos++ = WLAN_EID_SSID;
  1373. *pos++ = 0;
  1374. len += 2;
  1375. if (WARN_ON(left < ie_len))
  1376. return len;
  1377. if (ies && ie_len) {
  1378. memcpy(pos, ies, ie_len);
  1379. len += ie_len;
  1380. }
  1381. return (u16) len;
  1382. }
  1383. EXPORT_SYMBOL(il_fill_probe_req);
  1384. static void
  1385. il_bg_abort_scan(struct work_struct *work)
  1386. {
  1387. struct il_priv *il = container_of(work, struct il_priv, abort_scan);
  1388. D_SCAN("Abort scan work\n");
  1389. /* We keep scan_check work queued in case when firmware will not
  1390. * report back scan completed notification */
  1391. mutex_lock(&il->mutex);
  1392. il_scan_cancel_timeout(il, 200);
  1393. mutex_unlock(&il->mutex);
  1394. }
  1395. static void
  1396. il_bg_scan_completed(struct work_struct *work)
  1397. {
  1398. struct il_priv *il = container_of(work, struct il_priv, scan_completed);
  1399. bool aborted;
  1400. D_SCAN("Completed scan.\n");
  1401. cancel_delayed_work(&il->scan_check);
  1402. mutex_lock(&il->mutex);
  1403. aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
  1404. if (aborted)
  1405. D_SCAN("Aborted scan completed.\n");
  1406. if (!test_and_clear_bit(S_SCANNING, &il->status)) {
  1407. D_SCAN("Scan already completed.\n");
  1408. goto out_settings;
  1409. }
  1410. il_complete_scan(il, aborted);
  1411. out_settings:
  1412. /* Can we still talk to firmware ? */
  1413. if (!il_is_ready_rf(il))
  1414. goto out;
  1415. /*
  1416. * We do not commit power settings while scan is pending,
  1417. * do it now if the settings changed.
  1418. */
  1419. il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
  1420. il_set_tx_power(il, il->tx_power_next, false);
  1421. il->cfg->ops->utils->post_scan(il);
  1422. out:
  1423. mutex_unlock(&il->mutex);
  1424. }
  1425. void
  1426. il_setup_scan_deferred_work(struct il_priv *il)
  1427. {
  1428. INIT_WORK(&il->scan_completed, il_bg_scan_completed);
  1429. INIT_WORK(&il->abort_scan, il_bg_abort_scan);
  1430. INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
  1431. }
  1432. EXPORT_SYMBOL(il_setup_scan_deferred_work);
  1433. void
  1434. il_cancel_scan_deferred_work(struct il_priv *il)
  1435. {
  1436. cancel_work_sync(&il->abort_scan);
  1437. cancel_work_sync(&il->scan_completed);
  1438. if (cancel_delayed_work_sync(&il->scan_check)) {
  1439. mutex_lock(&il->mutex);
  1440. il_force_scan_end(il);
  1441. mutex_unlock(&il->mutex);
  1442. }
  1443. }
  1444. EXPORT_SYMBOL(il_cancel_scan_deferred_work);
  1445. /* il->sta_lock must be held */
  1446. static void
  1447. il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
  1448. {
  1449. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
  1450. IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
  1451. sta_id, il->stations[sta_id].sta.sta.addr);
  1452. if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
  1453. D_ASSOC("STA id %u addr %pM already present"
  1454. " in uCode (according to driver)\n", sta_id,
  1455. il->stations[sta_id].sta.sta.addr);
  1456. } else {
  1457. il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
  1458. D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
  1459. il->stations[sta_id].sta.sta.addr);
  1460. }
  1461. }
  1462. static int
  1463. il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
  1464. struct il_rx_pkt *pkt, bool sync)
  1465. {
  1466. u8 sta_id = addsta->sta.sta_id;
  1467. unsigned long flags;
  1468. int ret = -EIO;
  1469. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1470. IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
  1471. return ret;
  1472. }
  1473. D_INFO("Processing response for adding station %u\n", sta_id);
  1474. spin_lock_irqsave(&il->sta_lock, flags);
  1475. switch (pkt->u.add_sta.status) {
  1476. case ADD_STA_SUCCESS_MSK:
  1477. D_INFO("C_ADD_STA PASSED\n");
  1478. il_sta_ucode_activate(il, sta_id);
  1479. ret = 0;
  1480. break;
  1481. case ADD_STA_NO_ROOM_IN_TBL:
  1482. IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
  1483. break;
  1484. case ADD_STA_NO_BLOCK_ACK_RESOURCE:
  1485. IL_ERR("Adding station %d failed, no block ack resource.\n",
  1486. sta_id);
  1487. break;
  1488. case ADD_STA_MODIFY_NON_EXIST_STA:
  1489. IL_ERR("Attempting to modify non-existing station %d\n",
  1490. sta_id);
  1491. break;
  1492. default:
  1493. D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
  1494. break;
  1495. }
  1496. D_INFO("%s station id %u addr %pM\n",
  1497. il->stations[sta_id].sta.mode ==
  1498. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
  1499. il->stations[sta_id].sta.sta.addr);
  1500. /*
  1501. * XXX: The MAC address in the command buffer is often changed from
  1502. * the original sent to the device. That is, the MAC address
  1503. * written to the command buffer often is not the same MAC address
  1504. * read from the command buffer when the command returns. This
  1505. * issue has not yet been resolved and this debugging is left to
  1506. * observe the problem.
  1507. */
  1508. D_INFO("%s station according to cmd buffer %pM\n",
  1509. il->stations[sta_id].sta.mode ==
  1510. STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
  1511. spin_unlock_irqrestore(&il->sta_lock, flags);
  1512. return ret;
  1513. }
  1514. static void
  1515. il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
  1516. struct il_rx_pkt *pkt)
  1517. {
  1518. struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
  1519. il_process_add_sta_resp(il, addsta, pkt, false);
  1520. }
  1521. int
  1522. il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
  1523. {
  1524. struct il_rx_pkt *pkt = NULL;
  1525. int ret = 0;
  1526. u8 data[sizeof(*sta)];
  1527. struct il_host_cmd cmd = {
  1528. .id = C_ADD_STA,
  1529. .flags = flags,
  1530. .data = data,
  1531. };
  1532. u8 sta_id __maybe_unused = sta->sta.sta_id;
  1533. D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
  1534. flags & CMD_ASYNC ? "a" : "");
  1535. if (flags & CMD_ASYNC)
  1536. cmd.callback = il_add_sta_callback;
  1537. else {
  1538. cmd.flags |= CMD_WANT_SKB;
  1539. might_sleep();
  1540. }
  1541. cmd.len = il->cfg->ops->utils->build_addsta_hcmd(sta, data);
  1542. ret = il_send_cmd(il, &cmd);
  1543. if (ret || (flags & CMD_ASYNC))
  1544. return ret;
  1545. if (ret == 0) {
  1546. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1547. ret = il_process_add_sta_resp(il, sta, pkt, true);
  1548. }
  1549. il_free_pages(il, cmd.reply_page);
  1550. return ret;
  1551. }
  1552. EXPORT_SYMBOL(il_send_add_sta);
  1553. static void
  1554. il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta,
  1555. struct il_rxon_context *ctx)
  1556. {
  1557. struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
  1558. __le32 sta_flags;
  1559. u8 mimo_ps_mode;
  1560. if (!sta || !sta_ht_inf->ht_supported)
  1561. goto done;
  1562. mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2;
  1563. D_ASSOC("spatial multiplexing power save mode: %s\n",
  1564. (mimo_ps_mode == WLAN_HT_CAP_SM_PS_STATIC) ? "static" :
  1565. (mimo_ps_mode == WLAN_HT_CAP_SM_PS_DYNAMIC) ? "dynamic" :
  1566. "disabled");
  1567. sta_flags = il->stations[idx].sta.station_flags;
  1568. sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
  1569. switch (mimo_ps_mode) {
  1570. case WLAN_HT_CAP_SM_PS_STATIC:
  1571. sta_flags |= STA_FLG_MIMO_DIS_MSK;
  1572. break;
  1573. case WLAN_HT_CAP_SM_PS_DYNAMIC:
  1574. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  1575. break;
  1576. case WLAN_HT_CAP_SM_PS_DISABLED:
  1577. break;
  1578. default:
  1579. IL_WARN("Invalid MIMO PS mode %d\n", mimo_ps_mode);
  1580. break;
  1581. }
  1582. sta_flags |=
  1583. cpu_to_le32((u32) sta_ht_inf->
  1584. ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  1585. sta_flags |=
  1586. cpu_to_le32((u32) sta_ht_inf->
  1587. ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  1588. if (il_is_ht40_tx_allowed(il, ctx, &sta->ht_cap))
  1589. sta_flags |= STA_FLG_HT40_EN_MSK;
  1590. else
  1591. sta_flags &= ~STA_FLG_HT40_EN_MSK;
  1592. il->stations[idx].sta.station_flags = sta_flags;
  1593. done:
  1594. return;
  1595. }
  1596. /**
  1597. * il_prep_station - Prepare station information for addition
  1598. *
  1599. * should be called with sta_lock held
  1600. */
  1601. u8
  1602. il_prep_station(struct il_priv *il, struct il_rxon_context *ctx,
  1603. const u8 *addr, bool is_ap, struct ieee80211_sta *sta)
  1604. {
  1605. struct il_station_entry *station;
  1606. int i;
  1607. u8 sta_id = IL_INVALID_STATION;
  1608. u16 rate;
  1609. if (is_ap)
  1610. sta_id = ctx->ap_sta_id;
  1611. else if (is_broadcast_ether_addr(addr))
  1612. sta_id = ctx->bcast_sta_id;
  1613. else
  1614. for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
  1615. if (!compare_ether_addr
  1616. (il->stations[i].sta.sta.addr, addr)) {
  1617. sta_id = i;
  1618. break;
  1619. }
  1620. if (!il->stations[i].used &&
  1621. sta_id == IL_INVALID_STATION)
  1622. sta_id = i;
  1623. }
  1624. /*
  1625. * These two conditions have the same outcome, but keep them
  1626. * separate
  1627. */
  1628. if (unlikely(sta_id == IL_INVALID_STATION))
  1629. return sta_id;
  1630. /*
  1631. * uCode is not able to deal with multiple requests to add a
  1632. * station. Keep track if one is in progress so that we do not send
  1633. * another.
  1634. */
  1635. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1636. D_INFO("STA %d already in process of being added.\n", sta_id);
  1637. return sta_id;
  1638. }
  1639. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1640. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
  1641. !compare_ether_addr(il->stations[sta_id].sta.sta.addr, addr)) {
  1642. D_ASSOC("STA %d (%pM) already added, not adding again.\n",
  1643. sta_id, addr);
  1644. return sta_id;
  1645. }
  1646. station = &il->stations[sta_id];
  1647. station->used = IL_STA_DRIVER_ACTIVE;
  1648. D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
  1649. il->num_stations++;
  1650. /* Set up the C_ADD_STA command to send to device */
  1651. memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
  1652. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  1653. station->sta.mode = 0;
  1654. station->sta.sta.sta_id = sta_id;
  1655. station->sta.station_flags = ctx->station_flags;
  1656. station->ctxid = ctx->ctxid;
  1657. if (sta) {
  1658. struct il_station_priv_common *sta_priv;
  1659. sta_priv = (void *)sta->drv_priv;
  1660. sta_priv->ctx = ctx;
  1661. }
  1662. /*
  1663. * OK to call unconditionally, since local stations (IBSS BSSID
  1664. * STA and broadcast STA) pass in a NULL sta, and mac80211
  1665. * doesn't allow HT IBSS.
  1666. */
  1667. il_set_ht_add_station(il, sta_id, sta, ctx);
  1668. /* 3945 only */
  1669. rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
  1670. /* Turn on both antennas for the station... */
  1671. station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
  1672. return sta_id;
  1673. }
  1674. EXPORT_SYMBOL_GPL(il_prep_station);
  1675. #define STA_WAIT_TIMEOUT (HZ/2)
  1676. /**
  1677. * il_add_station_common -
  1678. */
  1679. int
  1680. il_add_station_common(struct il_priv *il, struct il_rxon_context *ctx,
  1681. const u8 *addr, bool is_ap, struct ieee80211_sta *sta,
  1682. u8 *sta_id_r)
  1683. {
  1684. unsigned long flags_spin;
  1685. int ret = 0;
  1686. u8 sta_id;
  1687. struct il_addsta_cmd sta_cmd;
  1688. *sta_id_r = 0;
  1689. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1690. sta_id = il_prep_station(il, ctx, addr, is_ap, sta);
  1691. if (sta_id == IL_INVALID_STATION) {
  1692. IL_ERR("Unable to prepare station %pM for addition\n", addr);
  1693. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1694. return -EINVAL;
  1695. }
  1696. /*
  1697. * uCode is not able to deal with multiple requests to add a
  1698. * station. Keep track if one is in progress so that we do not send
  1699. * another.
  1700. */
  1701. if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
  1702. D_INFO("STA %d already in process of being added.\n", sta_id);
  1703. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1704. return -EEXIST;
  1705. }
  1706. if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
  1707. (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1708. D_ASSOC("STA %d (%pM) already added, not adding again.\n",
  1709. sta_id, addr);
  1710. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1711. return -EEXIST;
  1712. }
  1713. il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
  1714. memcpy(&sta_cmd, &il->stations[sta_id].sta,
  1715. sizeof(struct il_addsta_cmd));
  1716. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1717. /* Add station to device's station table */
  1718. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1719. if (ret) {
  1720. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1721. IL_ERR("Adding station %pM failed.\n",
  1722. il->stations[sta_id].sta.sta.addr);
  1723. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1724. il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  1725. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1726. }
  1727. *sta_id_r = sta_id;
  1728. return ret;
  1729. }
  1730. EXPORT_SYMBOL(il_add_station_common);
  1731. /**
  1732. * il_sta_ucode_deactivate - deactivate ucode status for a station
  1733. *
  1734. * il->sta_lock must be held
  1735. */
  1736. static void
  1737. il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
  1738. {
  1739. /* Ucode must be active and driver must be non active */
  1740. if ((il->stations[sta_id].
  1741. used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
  1742. IL_STA_UCODE_ACTIVE)
  1743. IL_ERR("removed non active STA %u\n", sta_id);
  1744. il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
  1745. memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
  1746. D_ASSOC("Removed STA %u\n", sta_id);
  1747. }
  1748. static int
  1749. il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
  1750. bool temporary)
  1751. {
  1752. struct il_rx_pkt *pkt;
  1753. int ret;
  1754. unsigned long flags_spin;
  1755. struct il_rem_sta_cmd rm_sta_cmd;
  1756. struct il_host_cmd cmd = {
  1757. .id = C_REM_STA,
  1758. .len = sizeof(struct il_rem_sta_cmd),
  1759. .flags = CMD_SYNC,
  1760. .data = &rm_sta_cmd,
  1761. };
  1762. memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
  1763. rm_sta_cmd.num_sta = 1;
  1764. memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
  1765. cmd.flags |= CMD_WANT_SKB;
  1766. ret = il_send_cmd(il, &cmd);
  1767. if (ret)
  1768. return ret;
  1769. pkt = (struct il_rx_pkt *)cmd.reply_page;
  1770. if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
  1771. IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
  1772. ret = -EIO;
  1773. }
  1774. if (!ret) {
  1775. switch (pkt->u.rem_sta.status) {
  1776. case REM_STA_SUCCESS_MSK:
  1777. if (!temporary) {
  1778. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1779. il_sta_ucode_deactivate(il, sta_id);
  1780. spin_unlock_irqrestore(&il->sta_lock,
  1781. flags_spin);
  1782. }
  1783. D_ASSOC("C_REM_STA PASSED\n");
  1784. break;
  1785. default:
  1786. ret = -EIO;
  1787. IL_ERR("C_REM_STA failed\n");
  1788. break;
  1789. }
  1790. }
  1791. il_free_pages(il, cmd.reply_page);
  1792. return ret;
  1793. }
  1794. /**
  1795. * il_remove_station - Remove driver's knowledge of station.
  1796. */
  1797. int
  1798. il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
  1799. {
  1800. unsigned long flags;
  1801. if (!il_is_ready(il)) {
  1802. D_INFO("Unable to remove station %pM, device not ready.\n",
  1803. addr);
  1804. /*
  1805. * It is typical for stations to be removed when we are
  1806. * going down. Return success since device will be down
  1807. * soon anyway
  1808. */
  1809. return 0;
  1810. }
  1811. D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
  1812. if (WARN_ON(sta_id == IL_INVALID_STATION))
  1813. return -EINVAL;
  1814. spin_lock_irqsave(&il->sta_lock, flags);
  1815. if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  1816. D_INFO("Removing %pM but non DRIVER active\n", addr);
  1817. goto out_err;
  1818. }
  1819. if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
  1820. D_INFO("Removing %pM but non UCODE active\n", addr);
  1821. goto out_err;
  1822. }
  1823. if (il->stations[sta_id].used & IL_STA_LOCAL) {
  1824. kfree(il->stations[sta_id].lq);
  1825. il->stations[sta_id].lq = NULL;
  1826. }
  1827. il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
  1828. il->num_stations--;
  1829. BUG_ON(il->num_stations < 0);
  1830. spin_unlock_irqrestore(&il->sta_lock, flags);
  1831. return il_send_remove_station(il, addr, sta_id, false);
  1832. out_err:
  1833. spin_unlock_irqrestore(&il->sta_lock, flags);
  1834. return -EINVAL;
  1835. }
  1836. EXPORT_SYMBOL_GPL(il_remove_station);
  1837. /**
  1838. * il_clear_ucode_stations - clear ucode station table bits
  1839. *
  1840. * This function clears all the bits in the driver indicating
  1841. * which stations are active in the ucode. Call when something
  1842. * other than explicit station management would cause this in
  1843. * the ucode, e.g. unassociated RXON.
  1844. */
  1845. void
  1846. il_clear_ucode_stations(struct il_priv *il, struct il_rxon_context *ctx)
  1847. {
  1848. int i;
  1849. unsigned long flags_spin;
  1850. bool cleared = false;
  1851. D_INFO("Clearing ucode stations in driver\n");
  1852. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1853. for (i = 0; i < il->hw_params.max_stations; i++) {
  1854. if (ctx && ctx->ctxid != il->stations[i].ctxid)
  1855. continue;
  1856. if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
  1857. D_INFO("Clearing ucode active for station %d\n", i);
  1858. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1859. cleared = true;
  1860. }
  1861. }
  1862. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1863. if (!cleared)
  1864. D_INFO("No active stations found to be cleared\n");
  1865. }
  1866. EXPORT_SYMBOL(il_clear_ucode_stations);
  1867. /**
  1868. * il_restore_stations() - Restore driver known stations to device
  1869. *
  1870. * All stations considered active by driver, but not present in ucode, is
  1871. * restored.
  1872. *
  1873. * Function sleeps.
  1874. */
  1875. void
  1876. il_restore_stations(struct il_priv *il, struct il_rxon_context *ctx)
  1877. {
  1878. struct il_addsta_cmd sta_cmd;
  1879. struct il_link_quality_cmd lq;
  1880. unsigned long flags_spin;
  1881. int i;
  1882. bool found = false;
  1883. int ret;
  1884. bool send_lq;
  1885. if (!il_is_ready(il)) {
  1886. D_INFO("Not ready yet, not restoring any stations.\n");
  1887. return;
  1888. }
  1889. D_ASSOC("Restoring all known stations ... start.\n");
  1890. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1891. for (i = 0; i < il->hw_params.max_stations; i++) {
  1892. if (ctx->ctxid != il->stations[i].ctxid)
  1893. continue;
  1894. if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
  1895. !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
  1896. D_ASSOC("Restoring sta %pM\n",
  1897. il->stations[i].sta.sta.addr);
  1898. il->stations[i].sta.mode = 0;
  1899. il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
  1900. found = true;
  1901. }
  1902. }
  1903. for (i = 0; i < il->hw_params.max_stations; i++) {
  1904. if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
  1905. memcpy(&sta_cmd, &il->stations[i].sta,
  1906. sizeof(struct il_addsta_cmd));
  1907. send_lq = false;
  1908. if (il->stations[i].lq) {
  1909. memcpy(&lq, il->stations[i].lq,
  1910. sizeof(struct il_link_quality_cmd));
  1911. send_lq = true;
  1912. }
  1913. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1914. ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
  1915. if (ret) {
  1916. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1917. IL_ERR("Adding station %pM failed.\n",
  1918. il->stations[i].sta.sta.addr);
  1919. il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
  1920. il->stations[i].used &=
  1921. ~IL_STA_UCODE_INPROGRESS;
  1922. spin_unlock_irqrestore(&il->sta_lock,
  1923. flags_spin);
  1924. }
  1925. /*
  1926. * Rate scaling has already been initialized, send
  1927. * current LQ command
  1928. */
  1929. if (send_lq)
  1930. il_send_lq_cmd(il, ctx, &lq, CMD_SYNC, true);
  1931. spin_lock_irqsave(&il->sta_lock, flags_spin);
  1932. il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
  1933. }
  1934. }
  1935. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  1936. if (!found)
  1937. D_INFO("Restoring all known stations"
  1938. " .... no stations to be restored.\n");
  1939. else
  1940. D_INFO("Restoring all known stations" " .... complete.\n");
  1941. }
  1942. EXPORT_SYMBOL(il_restore_stations);
  1943. int
  1944. il_get_free_ucode_key_idx(struct il_priv *il)
  1945. {
  1946. int i;
  1947. for (i = 0; i < il->sta_key_max_num; i++)
  1948. if (!test_and_set_bit(i, &il->ucode_key_table))
  1949. return i;
  1950. return WEP_INVALID_OFFSET;
  1951. }
  1952. EXPORT_SYMBOL(il_get_free_ucode_key_idx);
  1953. void
  1954. il_dealloc_bcast_stations(struct il_priv *il)
  1955. {
  1956. unsigned long flags;
  1957. int i;
  1958. spin_lock_irqsave(&il->sta_lock, flags);
  1959. for (i = 0; i < il->hw_params.max_stations; i++) {
  1960. if (!(il->stations[i].used & IL_STA_BCAST))
  1961. continue;
  1962. il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
  1963. il->num_stations--;
  1964. BUG_ON(il->num_stations < 0);
  1965. kfree(il->stations[i].lq);
  1966. il->stations[i].lq = NULL;
  1967. }
  1968. spin_unlock_irqrestore(&il->sta_lock, flags);
  1969. }
  1970. EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
  1971. #ifdef CONFIG_IWLEGACY_DEBUG
  1972. static void
  1973. il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
  1974. {
  1975. int i;
  1976. D_RATE("lq station id 0x%x\n", lq->sta_id);
  1977. D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
  1978. lq->general_params.dual_stream_ant_msk);
  1979. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
  1980. D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
  1981. }
  1982. #else
  1983. static inline void
  1984. il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
  1985. {
  1986. }
  1987. #endif
  1988. /**
  1989. * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
  1990. *
  1991. * It sometimes happens when a HT rate has been in use and we
  1992. * loose connectivity with AP then mac80211 will first tell us that the
  1993. * current channel is not HT anymore before removing the station. In such a
  1994. * scenario the RXON flags will be updated to indicate we are not
  1995. * communicating HT anymore, but the LQ command may still contain HT rates.
  1996. * Test for this to prevent driver from sending LQ command between the time
  1997. * RXON flags are updated and when LQ command is updated.
  1998. */
  1999. static bool
  2000. il_is_lq_table_valid(struct il_priv *il, struct il_rxon_context *ctx,
  2001. struct il_link_quality_cmd *lq)
  2002. {
  2003. int i;
  2004. if (ctx->ht.enabled)
  2005. return true;
  2006. D_INFO("Channel %u is not an HT channel\n", ctx->active.channel);
  2007. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  2008. if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
  2009. D_INFO("idx %d of LQ expects HT channel\n", i);
  2010. return false;
  2011. }
  2012. }
  2013. return true;
  2014. }
  2015. /**
  2016. * il_send_lq_cmd() - Send link quality command
  2017. * @init: This command is sent as part of station initialization right
  2018. * after station has been added.
  2019. *
  2020. * The link quality command is sent as the last step of station creation.
  2021. * This is the special case in which init is set and we call a callback in
  2022. * this case to clear the state indicating that station creation is in
  2023. * progress.
  2024. */
  2025. int
  2026. il_send_lq_cmd(struct il_priv *il, struct il_rxon_context *ctx,
  2027. struct il_link_quality_cmd *lq, u8 flags, bool init)
  2028. {
  2029. int ret = 0;
  2030. unsigned long flags_spin;
  2031. struct il_host_cmd cmd = {
  2032. .id = C_TX_LINK_QUALITY_CMD,
  2033. .len = sizeof(struct il_link_quality_cmd),
  2034. .flags = flags,
  2035. .data = lq,
  2036. };
  2037. if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
  2038. return -EINVAL;
  2039. spin_lock_irqsave(&il->sta_lock, flags_spin);
  2040. if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
  2041. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2042. return -EINVAL;
  2043. }
  2044. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2045. il_dump_lq_cmd(il, lq);
  2046. BUG_ON(init && (cmd.flags & CMD_ASYNC));
  2047. if (il_is_lq_table_valid(il, ctx, lq))
  2048. ret = il_send_cmd(il, &cmd);
  2049. else
  2050. ret = -EINVAL;
  2051. if (cmd.flags & CMD_ASYNC)
  2052. return ret;
  2053. if (init) {
  2054. D_INFO("init LQ command complete,"
  2055. " clearing sta addition status for sta %d\n",
  2056. lq->sta_id);
  2057. spin_lock_irqsave(&il->sta_lock, flags_spin);
  2058. il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
  2059. spin_unlock_irqrestore(&il->sta_lock, flags_spin);
  2060. }
  2061. return ret;
  2062. }
  2063. EXPORT_SYMBOL(il_send_lq_cmd);
  2064. int
  2065. il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2066. struct ieee80211_sta *sta)
  2067. {
  2068. struct il_priv *il = hw->priv;
  2069. struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
  2070. int ret;
  2071. D_INFO("received request to remove station %pM\n", sta->addr);
  2072. mutex_lock(&il->mutex);
  2073. D_INFO("proceeding to remove station %pM\n", sta->addr);
  2074. ret = il_remove_station(il, sta_common->sta_id, sta->addr);
  2075. if (ret)
  2076. IL_ERR("Error removing station %pM\n", sta->addr);
  2077. mutex_unlock(&il->mutex);
  2078. return ret;
  2079. }
  2080. EXPORT_SYMBOL(il_mac_sta_remove);
  2081. /************************** RX-FUNCTIONS ****************************/
  2082. /*
  2083. * Rx theory of operation
  2084. *
  2085. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  2086. * each of which point to Receive Buffers to be filled by the NIC. These get
  2087. * used not only for Rx frames, but for any command response or notification
  2088. * from the NIC. The driver and NIC manage the Rx buffers by means
  2089. * of idxes into the circular buffer.
  2090. *
  2091. * Rx Queue Indexes
  2092. * The host/firmware share two idx registers for managing the Rx buffers.
  2093. *
  2094. * The READ idx maps to the first position that the firmware may be writing
  2095. * to -- the driver can read up to (but not including) this position and get
  2096. * good data.
  2097. * The READ idx is managed by the firmware once the card is enabled.
  2098. *
  2099. * The WRITE idx maps to the last position the driver has read from -- the
  2100. * position preceding WRITE is the last slot the firmware can place a packet.
  2101. *
  2102. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2103. * WRITE = READ.
  2104. *
  2105. * During initialization, the host sets up the READ queue position to the first
  2106. * IDX position, and WRITE to the last (READ - 1 wrapped)
  2107. *
  2108. * When the firmware places a packet in a buffer, it will advance the READ idx
  2109. * and fire the RX interrupt. The driver can then query the READ idx and
  2110. * process as many packets as possible, moving the WRITE idx forward as it
  2111. * resets the Rx queue buffers with new memory.
  2112. *
  2113. * The management in the driver is as follows:
  2114. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2115. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2116. * to replenish the iwl->rxq->rx_free.
  2117. * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
  2118. * iwl->rxq is replenished and the READ IDX is updated (updating the
  2119. * 'processed' and 'read' driver idxes as well)
  2120. * + A received packet is processed and handed to the kernel network stack,
  2121. * detached from the iwl->rxq. The driver 'processed' idx is updated.
  2122. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2123. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2124. * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
  2125. * were enough free buffers and RX_STALLED is set it is cleared.
  2126. *
  2127. *
  2128. * Driver sequence:
  2129. *
  2130. * il_rx_queue_alloc() Allocates rx_free
  2131. * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2132. * il_rx_queue_restock
  2133. * il_rx_queue_restock() Moves available buffers from rx_free into Rx
  2134. * queue, updates firmware pointers, and updates
  2135. * the WRITE idx. If insufficient rx_free buffers
  2136. * are available, schedules il_rx_replenish
  2137. *
  2138. * -- enable interrupts --
  2139. * ISR - il_rx() Detach il_rx_bufs from pool up to the
  2140. * READ IDX, detaching the SKB from the pool.
  2141. * Moves the packet buffer from queue to rx_used.
  2142. * Calls il_rx_queue_restock to refill any empty
  2143. * slots.
  2144. * ...
  2145. *
  2146. */
  2147. /**
  2148. * il_rx_queue_space - Return number of free slots available in queue.
  2149. */
  2150. int
  2151. il_rx_queue_space(const struct il_rx_queue *q)
  2152. {
  2153. int s = q->read - q->write;
  2154. if (s <= 0)
  2155. s += RX_QUEUE_SIZE;
  2156. /* keep some buffer to not confuse full and empty queue */
  2157. s -= 2;
  2158. if (s < 0)
  2159. s = 0;
  2160. return s;
  2161. }
  2162. EXPORT_SYMBOL(il_rx_queue_space);
  2163. /**
  2164. * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2165. */
  2166. void
  2167. il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
  2168. {
  2169. unsigned long flags;
  2170. u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
  2171. u32 reg;
  2172. spin_lock_irqsave(&q->lock, flags);
  2173. if (q->need_update == 0)
  2174. goto exit_unlock;
  2175. /* If power-saving is in use, make sure device is awake */
  2176. if (test_bit(S_POWER_PMI, &il->status)) {
  2177. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2178. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2179. D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
  2180. reg);
  2181. il_set_bit(il, CSR_GP_CNTRL,
  2182. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2183. goto exit_unlock;
  2184. }
  2185. q->write_actual = (q->write & ~0x7);
  2186. il_wr(il, rx_wrt_ptr_reg, q->write_actual);
  2187. /* Else device is assumed to be awake */
  2188. } else {
  2189. /* Device expects a multiple of 8 */
  2190. q->write_actual = (q->write & ~0x7);
  2191. il_wr(il, rx_wrt_ptr_reg, q->write_actual);
  2192. }
  2193. q->need_update = 0;
  2194. exit_unlock:
  2195. spin_unlock_irqrestore(&q->lock, flags);
  2196. }
  2197. EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
  2198. int
  2199. il_rx_queue_alloc(struct il_priv *il)
  2200. {
  2201. struct il_rx_queue *rxq = &il->rxq;
  2202. struct device *dev = &il->pci_dev->dev;
  2203. int i;
  2204. spin_lock_init(&rxq->lock);
  2205. INIT_LIST_HEAD(&rxq->rx_free);
  2206. INIT_LIST_HEAD(&rxq->rx_used);
  2207. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  2208. rxq->bd =
  2209. dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
  2210. GFP_KERNEL);
  2211. if (!rxq->bd)
  2212. goto err_bd;
  2213. rxq->rb_stts =
  2214. dma_alloc_coherent(dev, sizeof(struct il_rb_status),
  2215. &rxq->rb_stts_dma, GFP_KERNEL);
  2216. if (!rxq->rb_stts)
  2217. goto err_rb;
  2218. /* Fill the rx_used queue with _all_ of the Rx buffers */
  2219. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  2220. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  2221. /* Set us so that we have processed and used all buffers, but have
  2222. * not restocked the Rx queue with fresh buffers */
  2223. rxq->read = rxq->write = 0;
  2224. rxq->write_actual = 0;
  2225. rxq->free_count = 0;
  2226. rxq->need_update = 0;
  2227. return 0;
  2228. err_rb:
  2229. dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  2230. rxq->bd_dma);
  2231. err_bd:
  2232. return -ENOMEM;
  2233. }
  2234. EXPORT_SYMBOL(il_rx_queue_alloc);
  2235. void
  2236. il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
  2237. {
  2238. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2239. struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2240. if (!report->state) {
  2241. D_11H("Spectrum Measure Notification: Start\n");
  2242. return;
  2243. }
  2244. memcpy(&il->measure_report, report, sizeof(*report));
  2245. il->measurement_status |= MEASUREMENT_READY;
  2246. }
  2247. EXPORT_SYMBOL(il_hdl_spectrum_measurement);
  2248. /*
  2249. * returns non-zero if packet should be dropped
  2250. */
  2251. int
  2252. il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
  2253. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2254. {
  2255. u16 fc = le16_to_cpu(hdr->frame_control);
  2256. /*
  2257. * All contexts have the same setting here due to it being
  2258. * a module parameter, so OK to check any context.
  2259. */
  2260. if (il->ctx.active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2261. return 0;
  2262. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2263. return 0;
  2264. D_RX("decrypt_res:0x%x\n", decrypt_res);
  2265. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2266. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2267. /* The uCode has got a bad phase 1 Key, pushes the packet.
  2268. * Decryption will be done in SW. */
  2269. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2270. RX_RES_STATUS_BAD_KEY_TTAK)
  2271. break;
  2272. case RX_RES_STATUS_SEC_TYPE_WEP:
  2273. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2274. RX_RES_STATUS_BAD_ICV_MIC) {
  2275. /* bad ICV, the packet is destroyed since the
  2276. * decryption is inplace, drop it */
  2277. D_RX("Packet destroyed\n");
  2278. return -1;
  2279. }
  2280. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2281. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2282. RX_RES_STATUS_DECRYPT_OK) {
  2283. D_RX("hw decrypt successfully!!!\n");
  2284. stats->flag |= RX_FLAG_DECRYPTED;
  2285. }
  2286. break;
  2287. default:
  2288. break;
  2289. }
  2290. return 0;
  2291. }
  2292. EXPORT_SYMBOL(il_set_decrypted_flag);
  2293. /**
  2294. * il_txq_update_write_ptr - Send new write idx to hardware
  2295. */
  2296. void
  2297. il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
  2298. {
  2299. u32 reg = 0;
  2300. int txq_id = txq->q.id;
  2301. if (txq->need_update == 0)
  2302. return;
  2303. /* if we're trying to save power */
  2304. if (test_bit(S_POWER_PMI, &il->status)) {
  2305. /* wake up nic if it's powered down ...
  2306. * uCode will wake up, and interrupt us again, so next
  2307. * time we'll skip this part. */
  2308. reg = _il_rd(il, CSR_UCODE_DRV_GP1);
  2309. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2310. D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
  2311. txq_id, reg);
  2312. il_set_bit(il, CSR_GP_CNTRL,
  2313. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2314. return;
  2315. }
  2316. il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
  2317. /*
  2318. * else not in power-save mode,
  2319. * uCode will never sleep when we're
  2320. * trying to tx (during RFKILL, we're not trying to tx).
  2321. */
  2322. } else
  2323. _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
  2324. txq->need_update = 0;
  2325. }
  2326. EXPORT_SYMBOL(il_txq_update_write_ptr);
  2327. /**
  2328. * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
  2329. */
  2330. void
  2331. il_tx_queue_unmap(struct il_priv *il, int txq_id)
  2332. {
  2333. struct il_tx_queue *txq = &il->txq[txq_id];
  2334. struct il_queue *q = &txq->q;
  2335. if (q->n_bd == 0)
  2336. return;
  2337. while (q->write_ptr != q->read_ptr) {
  2338. il->cfg->ops->lib->txq_free_tfd(il, txq);
  2339. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2340. }
  2341. }
  2342. EXPORT_SYMBOL(il_tx_queue_unmap);
  2343. /**
  2344. * il_tx_queue_free - Deallocate DMA queue.
  2345. * @txq: Transmit queue to deallocate.
  2346. *
  2347. * Empty queue by removing and destroying all BD's.
  2348. * Free all buffers.
  2349. * 0-fill, but do not free "txq" descriptor structure.
  2350. */
  2351. void
  2352. il_tx_queue_free(struct il_priv *il, int txq_id)
  2353. {
  2354. struct il_tx_queue *txq = &il->txq[txq_id];
  2355. struct device *dev = &il->pci_dev->dev;
  2356. int i;
  2357. il_tx_queue_unmap(il, txq_id);
  2358. /* De-alloc array of command/tx buffers */
  2359. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  2360. kfree(txq->cmd[i]);
  2361. /* De-alloc circular buffer of TFDs */
  2362. if (txq->q.n_bd)
  2363. dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
  2364. txq->tfds, txq->q.dma_addr);
  2365. /* De-alloc array of per-TFD driver data */
  2366. kfree(txq->txb);
  2367. txq->txb = NULL;
  2368. /* deallocate arrays */
  2369. kfree(txq->cmd);
  2370. kfree(txq->meta);
  2371. txq->cmd = NULL;
  2372. txq->meta = NULL;
  2373. /* 0-fill queue descriptor structure */
  2374. memset(txq, 0, sizeof(*txq));
  2375. }
  2376. EXPORT_SYMBOL(il_tx_queue_free);
  2377. /**
  2378. * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
  2379. */
  2380. void
  2381. il_cmd_queue_unmap(struct il_priv *il)
  2382. {
  2383. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2384. struct il_queue *q = &txq->q;
  2385. int i;
  2386. if (q->n_bd == 0)
  2387. return;
  2388. while (q->read_ptr != q->write_ptr) {
  2389. i = il_get_cmd_idx(q, q->read_ptr, 0);
  2390. if (txq->meta[i].flags & CMD_MAPPED) {
  2391. pci_unmap_single(il->pci_dev,
  2392. dma_unmap_addr(&txq->meta[i], mapping),
  2393. dma_unmap_len(&txq->meta[i], len),
  2394. PCI_DMA_BIDIRECTIONAL);
  2395. txq->meta[i].flags = 0;
  2396. }
  2397. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
  2398. }
  2399. i = q->n_win;
  2400. if (txq->meta[i].flags & CMD_MAPPED) {
  2401. pci_unmap_single(il->pci_dev,
  2402. dma_unmap_addr(&txq->meta[i], mapping),
  2403. dma_unmap_len(&txq->meta[i], len),
  2404. PCI_DMA_BIDIRECTIONAL);
  2405. txq->meta[i].flags = 0;
  2406. }
  2407. }
  2408. EXPORT_SYMBOL(il_cmd_queue_unmap);
  2409. /**
  2410. * il_cmd_queue_free - Deallocate DMA queue.
  2411. * @txq: Transmit queue to deallocate.
  2412. *
  2413. * Empty queue by removing and destroying all BD's.
  2414. * Free all buffers.
  2415. * 0-fill, but do not free "txq" descriptor structure.
  2416. */
  2417. void
  2418. il_cmd_queue_free(struct il_priv *il)
  2419. {
  2420. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2421. struct device *dev = &il->pci_dev->dev;
  2422. int i;
  2423. il_cmd_queue_unmap(il);
  2424. /* De-alloc array of command/tx buffers */
  2425. for (i = 0; i <= TFD_CMD_SLOTS; i++)
  2426. kfree(txq->cmd[i]);
  2427. /* De-alloc circular buffer of TFDs */
  2428. if (txq->q.n_bd)
  2429. dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
  2430. txq->tfds, txq->q.dma_addr);
  2431. /* deallocate arrays */
  2432. kfree(txq->cmd);
  2433. kfree(txq->meta);
  2434. txq->cmd = NULL;
  2435. txq->meta = NULL;
  2436. /* 0-fill queue descriptor structure */
  2437. memset(txq, 0, sizeof(*txq));
  2438. }
  2439. EXPORT_SYMBOL(il_cmd_queue_free);
  2440. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  2441. * DMA services
  2442. *
  2443. * Theory of operation
  2444. *
  2445. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  2446. * of buffer descriptors, each of which points to one or more data buffers for
  2447. * the device to read from or fill. Driver and device exchange status of each
  2448. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  2449. * entries in each circular buffer, to protect against confusing empty and full
  2450. * queue states.
  2451. *
  2452. * The device reads or writes the data in the queues via the device's several
  2453. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  2454. *
  2455. * For Tx queue, there are low mark and high mark limits. If, after queuing
  2456. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  2457. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  2458. * Tx queue resumed.
  2459. *
  2460. * See more detailed info in 4965.h.
  2461. ***************************************************/
  2462. int
  2463. il_queue_space(const struct il_queue *q)
  2464. {
  2465. int s = q->read_ptr - q->write_ptr;
  2466. if (q->read_ptr > q->write_ptr)
  2467. s -= q->n_bd;
  2468. if (s <= 0)
  2469. s += q->n_win;
  2470. /* keep some reserve to not confuse empty and full situations */
  2471. s -= 2;
  2472. if (s < 0)
  2473. s = 0;
  2474. return s;
  2475. }
  2476. EXPORT_SYMBOL(il_queue_space);
  2477. /**
  2478. * il_queue_init - Initialize queue's high/low-water and read/write idxes
  2479. */
  2480. static int
  2481. il_queue_init(struct il_priv *il, struct il_queue *q, int count, int slots_num,
  2482. u32 id)
  2483. {
  2484. q->n_bd = count;
  2485. q->n_win = slots_num;
  2486. q->id = id;
  2487. /* count must be power-of-two size, otherwise il_queue_inc_wrap
  2488. * and il_queue_dec_wrap are broken. */
  2489. BUG_ON(!is_power_of_2(count));
  2490. /* slots_num must be power-of-two size, otherwise
  2491. * il_get_cmd_idx is broken. */
  2492. BUG_ON(!is_power_of_2(slots_num));
  2493. q->low_mark = q->n_win / 4;
  2494. if (q->low_mark < 4)
  2495. q->low_mark = 4;
  2496. q->high_mark = q->n_win / 8;
  2497. if (q->high_mark < 2)
  2498. q->high_mark = 2;
  2499. q->write_ptr = q->read_ptr = 0;
  2500. return 0;
  2501. }
  2502. /**
  2503. * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  2504. */
  2505. static int
  2506. il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
  2507. {
  2508. struct device *dev = &il->pci_dev->dev;
  2509. size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
  2510. /* Driver ilate data, only for Tx (not command) queues,
  2511. * not shared with device. */
  2512. if (id != il->cmd_queue) {
  2513. txq->txb = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->txb[0]),
  2514. GFP_KERNEL);
  2515. if (!txq->txb) {
  2516. IL_ERR("kmalloc for auxiliary BD "
  2517. "structures failed\n");
  2518. goto error;
  2519. }
  2520. } else {
  2521. txq->txb = NULL;
  2522. }
  2523. /* Circular buffer of transmit frame descriptors (TFDs),
  2524. * shared with device */
  2525. txq->tfds =
  2526. dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
  2527. if (!txq->tfds) {
  2528. IL_ERR("pci_alloc_consistent(%zd) failed\n", tfd_sz);
  2529. goto error;
  2530. }
  2531. txq->q.id = id;
  2532. return 0;
  2533. error:
  2534. kfree(txq->txb);
  2535. txq->txb = NULL;
  2536. return -ENOMEM;
  2537. }
  2538. /**
  2539. * il_tx_queue_init - Allocate and initialize one tx/cmd queue
  2540. */
  2541. int
  2542. il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
  2543. u32 txq_id)
  2544. {
  2545. int i, len;
  2546. int ret;
  2547. int actual_slots = slots_num;
  2548. /*
  2549. * Alloc buffer array for commands (Tx or other types of commands).
  2550. * For the command queue (#4/#9), allocate command space + one big
  2551. * command for scan, since scan command is very huge; the system will
  2552. * not have two scans at the same time, so only one is needed.
  2553. * For normal Tx queues (all other queues), no super-size command
  2554. * space is needed.
  2555. */
  2556. if (txq_id == il->cmd_queue)
  2557. actual_slots++;
  2558. txq->meta =
  2559. kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL);
  2560. txq->cmd =
  2561. kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL);
  2562. if (!txq->meta || !txq->cmd)
  2563. goto out_free_arrays;
  2564. len = sizeof(struct il_device_cmd);
  2565. for (i = 0; i < actual_slots; i++) {
  2566. /* only happens for cmd queue */
  2567. if (i == slots_num)
  2568. len = IL_MAX_CMD_SIZE;
  2569. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  2570. if (!txq->cmd[i])
  2571. goto err;
  2572. }
  2573. /* Alloc driver data array and TFD circular buffer */
  2574. ret = il_tx_queue_alloc(il, txq, txq_id);
  2575. if (ret)
  2576. goto err;
  2577. txq->need_update = 0;
  2578. /*
  2579. * For the default queues 0-3, set up the swq_id
  2580. * already -- all others need to get one later
  2581. * (if they need one at all).
  2582. */
  2583. if (txq_id < 4)
  2584. il_set_swq_id(txq, txq_id, txq_id);
  2585. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  2586. * il_queue_inc_wrap and il_queue_dec_wrap are broken. */
  2587. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  2588. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2589. il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  2590. /* Tell device where to find queue */
  2591. il->cfg->ops->lib->txq_init(il, txq);
  2592. return 0;
  2593. err:
  2594. for (i = 0; i < actual_slots; i++)
  2595. kfree(txq->cmd[i]);
  2596. out_free_arrays:
  2597. kfree(txq->meta);
  2598. kfree(txq->cmd);
  2599. return -ENOMEM;
  2600. }
  2601. EXPORT_SYMBOL(il_tx_queue_init);
  2602. void
  2603. il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
  2604. u32 txq_id)
  2605. {
  2606. int actual_slots = slots_num;
  2607. if (txq_id == il->cmd_queue)
  2608. actual_slots++;
  2609. memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
  2610. txq->need_update = 0;
  2611. /* Initialize queue's high/low-water marks, and head/tail idxes */
  2612. il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  2613. /* Tell device where to find queue */
  2614. il->cfg->ops->lib->txq_init(il, txq);
  2615. }
  2616. EXPORT_SYMBOL(il_tx_queue_reset);
  2617. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  2618. /**
  2619. * il_enqueue_hcmd - enqueue a uCode command
  2620. * @il: device ilate data point
  2621. * @cmd: a point to the ucode command structure
  2622. *
  2623. * The function returns < 0 values to indicate the operation is
  2624. * failed. On success, it turns the idx (> 0) of command in the
  2625. * command queue.
  2626. */
  2627. int
  2628. il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
  2629. {
  2630. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2631. struct il_queue *q = &txq->q;
  2632. struct il_device_cmd *out_cmd;
  2633. struct il_cmd_meta *out_meta;
  2634. dma_addr_t phys_addr;
  2635. unsigned long flags;
  2636. int len;
  2637. u32 idx;
  2638. u16 fix_size;
  2639. cmd->len = il->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
  2640. fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
  2641. /* If any of the command structures end up being larger than
  2642. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  2643. * we will need to increase the size of the TFD entries
  2644. * Also, check to see if command buffer should not exceed the size
  2645. * of device_cmd and max_cmd_size. */
  2646. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  2647. !(cmd->flags & CMD_SIZE_HUGE));
  2648. BUG_ON(fix_size > IL_MAX_CMD_SIZE);
  2649. if (il_is_rfkill(il) || il_is_ctkill(il)) {
  2650. IL_WARN("Not sending command - %s KILL\n",
  2651. il_is_rfkill(il) ? "RF" : "CT");
  2652. return -EIO;
  2653. }
  2654. spin_lock_irqsave(&il->hcmd_lock, flags);
  2655. if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
  2656. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2657. IL_ERR("Restarting adapter due to command queue full\n");
  2658. queue_work(il->workqueue, &il->restart);
  2659. return -ENOSPC;
  2660. }
  2661. idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
  2662. out_cmd = txq->cmd[idx];
  2663. out_meta = &txq->meta[idx];
  2664. if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
  2665. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2666. return -ENOSPC;
  2667. }
  2668. memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
  2669. out_meta->flags = cmd->flags | CMD_MAPPED;
  2670. if (cmd->flags & CMD_WANT_SKB)
  2671. out_meta->source = cmd;
  2672. if (cmd->flags & CMD_ASYNC)
  2673. out_meta->callback = cmd->callback;
  2674. out_cmd->hdr.cmd = cmd->id;
  2675. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  2676. /* At this point, the out_cmd now has all of the incoming cmd
  2677. * information */
  2678. out_cmd->hdr.flags = 0;
  2679. out_cmd->hdr.sequence =
  2680. cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
  2681. if (cmd->flags & CMD_SIZE_HUGE)
  2682. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  2683. len = sizeof(struct il_device_cmd);
  2684. if (idx == TFD_CMD_SLOTS)
  2685. len = IL_MAX_CMD_SIZE;
  2686. #ifdef CONFIG_IWLEGACY_DEBUG
  2687. switch (out_cmd->hdr.cmd) {
  2688. case C_TX_LINK_QUALITY_CMD:
  2689. case C_SENSITIVITY:
  2690. D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
  2691. "%d bytes at %d[%d]:%d\n",
  2692. il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
  2693. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  2694. q->write_ptr, idx, il->cmd_queue);
  2695. break;
  2696. default:
  2697. D_HC("Sending command %s (#%x), seq: 0x%04X, "
  2698. "%d bytes at %d[%d]:%d\n",
  2699. il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
  2700. le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
  2701. idx, il->cmd_queue);
  2702. }
  2703. #endif
  2704. txq->need_update = 1;
  2705. if (il->cfg->ops->lib->txq_update_byte_cnt_tbl)
  2706. /* Set up entry in queue's byte count circular buffer */
  2707. il->cfg->ops->lib->txq_update_byte_cnt_tbl(il, txq, 0);
  2708. phys_addr =
  2709. pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size,
  2710. PCI_DMA_BIDIRECTIONAL);
  2711. dma_unmap_addr_set(out_meta, mapping, phys_addr);
  2712. dma_unmap_len_set(out_meta, len, fix_size);
  2713. il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size,
  2714. 1, U32_PAD(cmd->len));
  2715. /* Increment and update queue's write idx */
  2716. q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
  2717. il_txq_update_write_ptr(il, txq);
  2718. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2719. return idx;
  2720. }
  2721. /**
  2722. * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
  2723. *
  2724. * When FW advances 'R' idx, all entries between old and new 'R' idx
  2725. * need to be reclaimed. As result, some free space forms. If there is
  2726. * enough free space (> low mark), wake the stack that feeds us.
  2727. */
  2728. static void
  2729. il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
  2730. {
  2731. struct il_tx_queue *txq = &il->txq[txq_id];
  2732. struct il_queue *q = &txq->q;
  2733. int nfreed = 0;
  2734. if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
  2735. IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
  2736. "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
  2737. q->write_ptr, q->read_ptr);
  2738. return;
  2739. }
  2740. for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
  2741. q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2742. if (nfreed++ > 0) {
  2743. IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
  2744. q->write_ptr, q->read_ptr);
  2745. queue_work(il->workqueue, &il->restart);
  2746. }
  2747. }
  2748. }
  2749. /**
  2750. * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2751. * @rxb: Rx buffer to reclaim
  2752. *
  2753. * If an Rx buffer has an async callback associated with it the callback
  2754. * will be executed. The attached skb (if present) will only be freed
  2755. * if the callback returns 1
  2756. */
  2757. void
  2758. il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
  2759. {
  2760. struct il_rx_pkt *pkt = rxb_addr(rxb);
  2761. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2762. int txq_id = SEQ_TO_QUEUE(sequence);
  2763. int idx = SEQ_TO_IDX(sequence);
  2764. int cmd_idx;
  2765. bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2766. struct il_device_cmd *cmd;
  2767. struct il_cmd_meta *meta;
  2768. struct il_tx_queue *txq = &il->txq[il->cmd_queue];
  2769. unsigned long flags;
  2770. /* If a Tx command is being handled and it isn't in the actual
  2771. * command queue then there a command routing bug has been introduced
  2772. * in the queue management code. */
  2773. if (WARN
  2774. (txq_id != il->cmd_queue,
  2775. "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
  2776. txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
  2777. il->txq[il->cmd_queue].q.write_ptr)) {
  2778. il_print_hex_error(il, pkt, 32);
  2779. return;
  2780. }
  2781. cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
  2782. cmd = txq->cmd[cmd_idx];
  2783. meta = &txq->meta[cmd_idx];
  2784. txq->time_stamp = jiffies;
  2785. pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping),
  2786. dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL);
  2787. /* Input error checking is done when commands are added to queue. */
  2788. if (meta->flags & CMD_WANT_SKB) {
  2789. meta->source->reply_page = (unsigned long)rxb_addr(rxb);
  2790. rxb->page = NULL;
  2791. } else if (meta->callback)
  2792. meta->callback(il, cmd, pkt);
  2793. spin_lock_irqsave(&il->hcmd_lock, flags);
  2794. il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
  2795. if (!(meta->flags & CMD_ASYNC)) {
  2796. clear_bit(S_HCMD_ACTIVE, &il->status);
  2797. D_INFO("Clearing HCMD_ACTIVE for command %s\n",
  2798. il_get_cmd_string(cmd->hdr.cmd));
  2799. wake_up(&il->wait_command_queue);
  2800. }
  2801. /* Mark as unmapped */
  2802. meta->flags = 0;
  2803. spin_unlock_irqrestore(&il->hcmd_lock, flags);
  2804. }
  2805. EXPORT_SYMBOL(il_tx_cmd_complete);
  2806. MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
  2807. MODULE_VERSION(IWLWIFI_VERSION);
  2808. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  2809. MODULE_LICENSE("GPL");
  2810. /*
  2811. * set bt_coex_active to true, uCode will do kill/defer
  2812. * every time the priority line is asserted (BT is sending signals on the
  2813. * priority line in the PCIx).
  2814. * set bt_coex_active to false, uCode will ignore the BT activity and
  2815. * perform the normal operation
  2816. *
  2817. * User might experience transmit issue on some platform due to WiFi/BT
  2818. * co-exist problem. The possible behaviors are:
  2819. * Able to scan and finding all the available AP
  2820. * Not able to associate with any AP
  2821. * On those platforms, WiFi communication can be restored by set
  2822. * "bt_coex_active" module parameter to "false"
  2823. *
  2824. * default: bt_coex_active = true (BT_COEX_ENABLE)
  2825. */
  2826. static bool bt_coex_active = true;
  2827. module_param(bt_coex_active, bool, S_IRUGO);
  2828. MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
  2829. u32 il_debug_level;
  2830. EXPORT_SYMBOL(il_debug_level);
  2831. const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  2832. EXPORT_SYMBOL(il_bcast_addr);
  2833. /* This function both allocates and initializes hw and il. */
  2834. struct ieee80211_hw *
  2835. il_alloc_all(struct il_cfg *cfg)
  2836. {
  2837. struct il_priv *il;
  2838. /* mac80211 allocates memory for this device instance, including
  2839. * space for this driver's ilate structure */
  2840. struct ieee80211_hw *hw;
  2841. hw = ieee80211_alloc_hw(sizeof(struct il_priv),
  2842. cfg->ops->ieee80211_ops);
  2843. if (hw == NULL) {
  2844. pr_err("%s: Can not allocate network device\n", cfg->name);
  2845. goto out;
  2846. }
  2847. il = hw->priv;
  2848. il->hw = hw;
  2849. out:
  2850. return hw;
  2851. }
  2852. EXPORT_SYMBOL(il_alloc_all);
  2853. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  2854. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  2855. static void
  2856. il_init_ht_hw_capab(const struct il_priv *il,
  2857. struct ieee80211_sta_ht_cap *ht_info,
  2858. enum ieee80211_band band)
  2859. {
  2860. u16 max_bit_rate = 0;
  2861. u8 rx_chains_num = il->hw_params.rx_chains_num;
  2862. u8 tx_chains_num = il->hw_params.tx_chains_num;
  2863. ht_info->cap = 0;
  2864. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  2865. ht_info->ht_supported = true;
  2866. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  2867. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  2868. if (il->hw_params.ht40_channel & BIT(band)) {
  2869. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  2870. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  2871. ht_info->mcs.rx_mask[4] = 0x01;
  2872. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  2873. }
  2874. if (il->cfg->mod_params->amsdu_size_8K)
  2875. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  2876. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  2877. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  2878. ht_info->mcs.rx_mask[0] = 0xFF;
  2879. if (rx_chains_num >= 2)
  2880. ht_info->mcs.rx_mask[1] = 0xFF;
  2881. if (rx_chains_num >= 3)
  2882. ht_info->mcs.rx_mask[2] = 0xFF;
  2883. /* Highest supported Rx data rate */
  2884. max_bit_rate *= rx_chains_num;
  2885. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  2886. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  2887. /* Tx MCS capabilities */
  2888. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  2889. if (tx_chains_num != rx_chains_num) {
  2890. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  2891. ht_info->mcs.tx_params |=
  2892. ((tx_chains_num -
  2893. 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  2894. }
  2895. }
  2896. /**
  2897. * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
  2898. */
  2899. int
  2900. il_init_geos(struct il_priv *il)
  2901. {
  2902. struct il_channel_info *ch;
  2903. struct ieee80211_supported_band *sband;
  2904. struct ieee80211_channel *channels;
  2905. struct ieee80211_channel *geo_ch;
  2906. struct ieee80211_rate *rates;
  2907. int i = 0;
  2908. s8 max_tx_power = 0;
  2909. if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  2910. il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  2911. D_INFO("Geography modes already initialized.\n");
  2912. set_bit(S_GEO_CONFIGURED, &il->status);
  2913. return 0;
  2914. }
  2915. channels =
  2916. kzalloc(sizeof(struct ieee80211_channel) * il->channel_count,
  2917. GFP_KERNEL);
  2918. if (!channels)
  2919. return -ENOMEM;
  2920. rates =
  2921. kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
  2922. GFP_KERNEL);
  2923. if (!rates) {
  2924. kfree(channels);
  2925. return -ENOMEM;
  2926. }
  2927. /* 5.2GHz channels start after the 2.4GHz channels */
  2928. sband = &il->bands[IEEE80211_BAND_5GHZ];
  2929. sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
  2930. /* just OFDM */
  2931. sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
  2932. sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
  2933. if (il->cfg->sku & IL_SKU_N)
  2934. il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ);
  2935. sband = &il->bands[IEEE80211_BAND_2GHZ];
  2936. sband->channels = channels;
  2937. /* OFDM & CCK */
  2938. sband->bitrates = rates;
  2939. sband->n_bitrates = RATE_COUNT_LEGACY;
  2940. if (il->cfg->sku & IL_SKU_N)
  2941. il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ);
  2942. il->ieee_channels = channels;
  2943. il->ieee_rates = rates;
  2944. for (i = 0; i < il->channel_count; i++) {
  2945. ch = &il->channel_info[i];
  2946. if (!il_is_channel_valid(ch))
  2947. continue;
  2948. sband = &il->bands[ch->band];
  2949. geo_ch = &sband->channels[sband->n_channels++];
  2950. geo_ch->center_freq =
  2951. ieee80211_channel_to_frequency(ch->channel, ch->band);
  2952. geo_ch->max_power = ch->max_power_avg;
  2953. geo_ch->max_antenna_gain = 0xff;
  2954. geo_ch->hw_value = ch->channel;
  2955. if (il_is_channel_valid(ch)) {
  2956. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  2957. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  2958. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  2959. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  2960. if (ch->flags & EEPROM_CHANNEL_RADAR)
  2961. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  2962. geo_ch->flags |= ch->ht40_extension_channel;
  2963. if (ch->max_power_avg > max_tx_power)
  2964. max_tx_power = ch->max_power_avg;
  2965. } else {
  2966. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  2967. }
  2968. D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
  2969. geo_ch->center_freq,
  2970. il_is_channel_a_band(ch) ? "5.2" : "2.4",
  2971. geo_ch->
  2972. flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
  2973. geo_ch->flags);
  2974. }
  2975. il->tx_power_device_lmt = max_tx_power;
  2976. il->tx_power_user_lmt = max_tx_power;
  2977. il->tx_power_next = max_tx_power;
  2978. if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
  2979. (il->cfg->sku & IL_SKU_A)) {
  2980. IL_INFO("Incorrectly detected BG card as ABG. "
  2981. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  2982. il->pci_dev->device, il->pci_dev->subsystem_device);
  2983. il->cfg->sku &= ~IL_SKU_A;
  2984. }
  2985. IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  2986. il->bands[IEEE80211_BAND_2GHZ].n_channels,
  2987. il->bands[IEEE80211_BAND_5GHZ].n_channels);
  2988. set_bit(S_GEO_CONFIGURED, &il->status);
  2989. return 0;
  2990. }
  2991. EXPORT_SYMBOL(il_init_geos);
  2992. /*
  2993. * il_free_geos - undo allocations in il_init_geos
  2994. */
  2995. void
  2996. il_free_geos(struct il_priv *il)
  2997. {
  2998. kfree(il->ieee_channels);
  2999. kfree(il->ieee_rates);
  3000. clear_bit(S_GEO_CONFIGURED, &il->status);
  3001. }
  3002. EXPORT_SYMBOL(il_free_geos);
  3003. static bool
  3004. il_is_channel_extension(struct il_priv *il, enum ieee80211_band band,
  3005. u16 channel, u8 extension_chan_offset)
  3006. {
  3007. const struct il_channel_info *ch_info;
  3008. ch_info = il_get_channel_info(il, band, channel);
  3009. if (!il_is_channel_valid(ch_info))
  3010. return false;
  3011. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  3012. return !(ch_info->
  3013. ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
  3014. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  3015. return !(ch_info->
  3016. ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
  3017. return false;
  3018. }
  3019. bool
  3020. il_is_ht40_tx_allowed(struct il_priv *il, struct il_rxon_context *ctx,
  3021. struct ieee80211_sta_ht_cap *ht_cap)
  3022. {
  3023. if (!ctx->ht.enabled || !ctx->ht.is_40mhz)
  3024. return false;
  3025. /*
  3026. * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  3027. * the bit will not set if it is pure 40MHz case
  3028. */
  3029. if (ht_cap && !ht_cap->ht_supported)
  3030. return false;
  3031. #ifdef CONFIG_IWLEGACY_DEBUGFS
  3032. if (il->disable_ht40)
  3033. return false;
  3034. #endif
  3035. return il_is_channel_extension(il, il->band,
  3036. le16_to_cpu(ctx->staging.channel),
  3037. ctx->ht.extension_chan_offset);
  3038. }
  3039. EXPORT_SYMBOL(il_is_ht40_tx_allowed);
  3040. static u16
  3041. il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  3042. {
  3043. u16 new_val;
  3044. u16 beacon_factor;
  3045. /*
  3046. * If mac80211 hasn't given us a beacon interval, program
  3047. * the default into the device.
  3048. */
  3049. if (!beacon_val)
  3050. return DEFAULT_BEACON_INTERVAL;
  3051. /*
  3052. * If the beacon interval we obtained from the peer
  3053. * is too large, we'll have to wake up more often
  3054. * (and in IBSS case, we'll beacon too much)
  3055. *
  3056. * For example, if max_beacon_val is 4096, and the
  3057. * requested beacon interval is 7000, we'll have to
  3058. * use 3500 to be able to wake up on the beacons.
  3059. *
  3060. * This could badly influence beacon detection stats.
  3061. */
  3062. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  3063. new_val = beacon_val / beacon_factor;
  3064. if (!new_val)
  3065. new_val = max_beacon_val;
  3066. return new_val;
  3067. }
  3068. int
  3069. il_send_rxon_timing(struct il_priv *il, struct il_rxon_context *ctx)
  3070. {
  3071. u64 tsf;
  3072. s32 interval_tm, rem;
  3073. struct ieee80211_conf *conf = NULL;
  3074. u16 beacon_int;
  3075. struct ieee80211_vif *vif = ctx->vif;
  3076. conf = &il->hw->conf;
  3077. lockdep_assert_held(&il->mutex);
  3078. memset(&ctx->timing, 0, sizeof(struct il_rxon_time_cmd));
  3079. ctx->timing.timestamp = cpu_to_le64(il->timestamp);
  3080. ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval);
  3081. beacon_int = vif ? vif->bss_conf.beacon_int : 0;
  3082. /*
  3083. * TODO: For IBSS we need to get atim_win from mac80211,
  3084. * for now just always use 0
  3085. */
  3086. ctx->timing.atim_win = 0;
  3087. beacon_int =
  3088. il_adjust_beacon_interval(beacon_int,
  3089. il->hw_params.max_beacon_itrvl *
  3090. TIME_UNIT);
  3091. ctx->timing.beacon_interval = cpu_to_le16(beacon_int);
  3092. tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
  3093. interval_tm = beacon_int * TIME_UNIT;
  3094. rem = do_div(tsf, interval_tm);
  3095. ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  3096. ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
  3097. D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
  3098. le16_to_cpu(ctx->timing.beacon_interval),
  3099. le32_to_cpu(ctx->timing.beacon_init_val),
  3100. le16_to_cpu(ctx->timing.atim_win));
  3101. return il_send_cmd_pdu(il, ctx->rxon_timing_cmd, sizeof(ctx->timing),
  3102. &ctx->timing);
  3103. }
  3104. EXPORT_SYMBOL(il_send_rxon_timing);
  3105. void
  3106. il_set_rxon_hwcrypto(struct il_priv *il, struct il_rxon_context *ctx,
  3107. int hw_decrypt)
  3108. {
  3109. struct il_rxon_cmd *rxon = &ctx->staging;
  3110. if (hw_decrypt)
  3111. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  3112. else
  3113. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  3114. }
  3115. EXPORT_SYMBOL(il_set_rxon_hwcrypto);
  3116. /* validate RXON structure is valid */
  3117. int
  3118. il_check_rxon_cmd(struct il_priv *il, struct il_rxon_context *ctx)
  3119. {
  3120. struct il_rxon_cmd *rxon = &ctx->staging;
  3121. bool error = false;
  3122. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  3123. if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
  3124. IL_WARN("check 2.4G: wrong narrow\n");
  3125. error = true;
  3126. }
  3127. if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
  3128. IL_WARN("check 2.4G: wrong radar\n");
  3129. error = true;
  3130. }
  3131. } else {
  3132. if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
  3133. IL_WARN("check 5.2G: not short slot!\n");
  3134. error = true;
  3135. }
  3136. if (rxon->flags & RXON_FLG_CCK_MSK) {
  3137. IL_WARN("check 5.2G: CCK!\n");
  3138. error = true;
  3139. }
  3140. }
  3141. if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
  3142. IL_WARN("mac/bssid mcast!\n");
  3143. error = true;
  3144. }
  3145. /* make sure basic rates 6Mbps and 1Mbps are supported */
  3146. if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
  3147. (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
  3148. IL_WARN("neither 1 nor 6 are basic\n");
  3149. error = true;
  3150. }
  3151. if (le16_to_cpu(rxon->assoc_id) > 2007) {
  3152. IL_WARN("aid > 2007\n");
  3153. error = true;
  3154. }
  3155. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
  3156. (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
  3157. IL_WARN("CCK and short slot\n");
  3158. error = true;
  3159. }
  3160. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
  3161. (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
  3162. IL_WARN("CCK and auto detect");
  3163. error = true;
  3164. }
  3165. if ((rxon->
  3166. flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
  3167. RXON_FLG_TGG_PROTECT_MSK) {
  3168. IL_WARN("TGg but no auto-detect\n");
  3169. error = true;
  3170. }
  3171. if (error)
  3172. IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
  3173. if (error) {
  3174. IL_ERR("Invalid RXON\n");
  3175. return -EINVAL;
  3176. }
  3177. return 0;
  3178. }
  3179. EXPORT_SYMBOL(il_check_rxon_cmd);
  3180. /**
  3181. * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  3182. * @il: staging_rxon is compared to active_rxon
  3183. *
  3184. * If the RXON structure is changing enough to require a new tune,
  3185. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  3186. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  3187. */
  3188. int
  3189. il_full_rxon_required(struct il_priv *il, struct il_rxon_context *ctx)
  3190. {
  3191. const struct il_rxon_cmd *staging = &ctx->staging;
  3192. const struct il_rxon_cmd *active = &ctx->active;
  3193. #define CHK(cond) \
  3194. if ((cond)) { \
  3195. D_INFO("need full RXON - " #cond "\n"); \
  3196. return 1; \
  3197. }
  3198. #define CHK_NEQ(c1, c2) \
  3199. if ((c1) != (c2)) { \
  3200. D_INFO("need full RXON - " \
  3201. #c1 " != " #c2 " - %d != %d\n", \
  3202. (c1), (c2)); \
  3203. return 1; \
  3204. }
  3205. /* These items are only settable from the full RXON command */
  3206. CHK(!il_is_associated_ctx(ctx));
  3207. CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr));
  3208. CHK(compare_ether_addr(staging->node_addr, active->node_addr));
  3209. CHK(compare_ether_addr
  3210. (staging->wlap_bssid_addr, active->wlap_bssid_addr));
  3211. CHK_NEQ(staging->dev_type, active->dev_type);
  3212. CHK_NEQ(staging->channel, active->channel);
  3213. CHK_NEQ(staging->air_propagation, active->air_propagation);
  3214. CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
  3215. active->ofdm_ht_single_stream_basic_rates);
  3216. CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
  3217. active->ofdm_ht_dual_stream_basic_rates);
  3218. CHK_NEQ(staging->assoc_id, active->assoc_id);
  3219. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  3220. * be updated with the RXON_ASSOC command -- however only some
  3221. * flag transitions are allowed using RXON_ASSOC */
  3222. /* Check if we are not switching bands */
  3223. CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
  3224. active->flags & RXON_FLG_BAND_24G_MSK);
  3225. /* Check if we are switching association toggle */
  3226. CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
  3227. active->filter_flags & RXON_FILTER_ASSOC_MSK);
  3228. #undef CHK
  3229. #undef CHK_NEQ
  3230. return 0;
  3231. }
  3232. EXPORT_SYMBOL(il_full_rxon_required);
  3233. u8
  3234. il_get_lowest_plcp(struct il_priv *il, struct il_rxon_context *ctx)
  3235. {
  3236. /*
  3237. * Assign the lowest rate -- should really get this from
  3238. * the beacon skb from mac80211.
  3239. */
  3240. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK)
  3241. return RATE_1M_PLCP;
  3242. else
  3243. return RATE_6M_PLCP;
  3244. }
  3245. EXPORT_SYMBOL(il_get_lowest_plcp);
  3246. static void
  3247. _il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf,
  3248. struct il_rxon_context *ctx)
  3249. {
  3250. struct il_rxon_cmd *rxon = &ctx->staging;
  3251. if (!ctx->ht.enabled) {
  3252. rxon->flags &=
  3253. ~(RXON_FLG_CHANNEL_MODE_MSK |
  3254. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
  3255. | RXON_FLG_HT_PROT_MSK);
  3256. return;
  3257. }
  3258. rxon->flags |=
  3259. cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
  3260. /* Set up channel bandwidth:
  3261. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  3262. /* clear the HT channel mode before set the mode */
  3263. rxon->flags &=
  3264. ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3265. if (il_is_ht40_tx_allowed(il, ctx, NULL)) {
  3266. /* pure ht40 */
  3267. if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  3268. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  3269. /* Note: control channel is opposite of extension channel */
  3270. switch (ctx->ht.extension_chan_offset) {
  3271. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3272. rxon->flags &=
  3273. ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3274. break;
  3275. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3276. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3277. break;
  3278. }
  3279. } else {
  3280. /* Note: control channel is opposite of extension channel */
  3281. switch (ctx->ht.extension_chan_offset) {
  3282. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  3283. rxon->flags &=
  3284. ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3285. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3286. break;
  3287. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  3288. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3289. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  3290. break;
  3291. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  3292. default:
  3293. /* channel location only valid if in Mixed mode */
  3294. IL_ERR("invalid extension channel offset\n");
  3295. break;
  3296. }
  3297. }
  3298. } else {
  3299. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  3300. }
  3301. if (il->cfg->ops->hcmd->set_rxon_chain)
  3302. il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
  3303. D_ASSOC("rxon flags 0x%X operation mode :0x%X "
  3304. "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
  3305. ctx->ht.protection, ctx->ht.extension_chan_offset);
  3306. }
  3307. void
  3308. il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
  3309. {
  3310. _il_set_rxon_ht(il, ht_conf, &il->ctx);
  3311. }
  3312. EXPORT_SYMBOL(il_set_rxon_ht);
  3313. /* Return valid, unused, channel for a passive scan to reset the RF */
  3314. u8
  3315. il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band)
  3316. {
  3317. const struct il_channel_info *ch_info;
  3318. int i;
  3319. u8 channel = 0;
  3320. u8 min, max;
  3321. if (band == IEEE80211_BAND_5GHZ) {
  3322. min = 14;
  3323. max = il->channel_count;
  3324. } else {
  3325. min = 0;
  3326. max = 14;
  3327. }
  3328. for (i = min; i < max; i++) {
  3329. channel = il->channel_info[i].channel;
  3330. if (channel == le16_to_cpu(il->ctx.staging.channel))
  3331. continue;
  3332. ch_info = il_get_channel_info(il, band, channel);
  3333. if (il_is_channel_valid(ch_info))
  3334. break;
  3335. }
  3336. return channel;
  3337. }
  3338. EXPORT_SYMBOL(il_get_single_channel_number);
  3339. /**
  3340. * il_set_rxon_channel - Set the band and channel values in staging RXON
  3341. * @ch: requested channel as a pointer to struct ieee80211_channel
  3342. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  3343. * in the staging RXON flag structure based on the ch->band
  3344. */
  3345. int
  3346. il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch,
  3347. struct il_rxon_context *ctx)
  3348. {
  3349. enum ieee80211_band band = ch->band;
  3350. u16 channel = ch->hw_value;
  3351. if (le16_to_cpu(ctx->staging.channel) == channel && il->band == band)
  3352. return 0;
  3353. ctx->staging.channel = cpu_to_le16(channel);
  3354. if (band == IEEE80211_BAND_5GHZ)
  3355. ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
  3356. else
  3357. ctx->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3358. il->band = band;
  3359. D_INFO("Staging channel set to %d [%d]\n", channel, band);
  3360. return 0;
  3361. }
  3362. EXPORT_SYMBOL(il_set_rxon_channel);
  3363. void
  3364. il_set_flags_for_band(struct il_priv *il, struct il_rxon_context *ctx,
  3365. enum ieee80211_band band, struct ieee80211_vif *vif)
  3366. {
  3367. if (band == IEEE80211_BAND_5GHZ) {
  3368. ctx->staging.flags &=
  3369. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
  3370. RXON_FLG_CCK_MSK);
  3371. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3372. } else {
  3373. /* Copied from il_post_associate() */
  3374. if (vif && vif->bss_conf.use_short_slot)
  3375. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  3376. else
  3377. ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  3378. ctx->staging.flags |= RXON_FLG_BAND_24G_MSK;
  3379. ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
  3380. ctx->staging.flags &= ~RXON_FLG_CCK_MSK;
  3381. }
  3382. }
  3383. EXPORT_SYMBOL(il_set_flags_for_band);
  3384. /*
  3385. * initialize rxon structure with default values from eeprom
  3386. */
  3387. void
  3388. il_connection_init_rx_config(struct il_priv *il, struct il_rxon_context *ctx)
  3389. {
  3390. const struct il_channel_info *ch_info;
  3391. memset(&ctx->staging, 0, sizeof(ctx->staging));
  3392. if (!ctx->vif) {
  3393. ctx->staging.dev_type = ctx->unused_devtype;
  3394. } else
  3395. switch (ctx->vif->type) {
  3396. case NL80211_IFTYPE_STATION:
  3397. ctx->staging.dev_type = ctx->station_devtype;
  3398. ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  3399. break;
  3400. case NL80211_IFTYPE_ADHOC:
  3401. ctx->staging.dev_type = ctx->ibss_devtype;
  3402. ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  3403. ctx->staging.filter_flags =
  3404. RXON_FILTER_BCON_AWARE_MSK |
  3405. RXON_FILTER_ACCEPT_GRP_MSK;
  3406. break;
  3407. default:
  3408. IL_ERR("Unsupported interface type %d\n",
  3409. ctx->vif->type);
  3410. break;
  3411. }
  3412. #if 0
  3413. /* TODO: Figure out when short_preamble would be set and cache from
  3414. * that */
  3415. if (!hw_to_local(il->hw)->short_preamble)
  3416. ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  3417. else
  3418. ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  3419. #endif
  3420. ch_info =
  3421. il_get_channel_info(il, il->band, le16_to_cpu(ctx->active.channel));
  3422. if (!ch_info)
  3423. ch_info = &il->channel_info[0];
  3424. ctx->staging.channel = cpu_to_le16(ch_info->channel);
  3425. il->band = ch_info->band;
  3426. il_set_flags_for_band(il, ctx, il->band, ctx->vif);
  3427. ctx->staging.ofdm_basic_rates =
  3428. (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3429. ctx->staging.cck_basic_rates =
  3430. (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3431. /* clear both MIX and PURE40 mode flag */
  3432. ctx->staging.flags &=
  3433. ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
  3434. if (ctx->vif)
  3435. memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN);
  3436. ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff;
  3437. ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
  3438. }
  3439. EXPORT_SYMBOL(il_connection_init_rx_config);
  3440. void
  3441. il_set_rate(struct il_priv *il)
  3442. {
  3443. const struct ieee80211_supported_band *hw = NULL;
  3444. struct ieee80211_rate *rate;
  3445. int i;
  3446. hw = il_get_hw_mode(il, il->band);
  3447. if (!hw) {
  3448. IL_ERR("Failed to set rate: unable to get hw mode\n");
  3449. return;
  3450. }
  3451. il->active_rate = 0;
  3452. for (i = 0; i < hw->n_bitrates; i++) {
  3453. rate = &(hw->bitrates[i]);
  3454. if (rate->hw_value < RATE_COUNT_LEGACY)
  3455. il->active_rate |= (1 << rate->hw_value);
  3456. }
  3457. D_RATE("Set active_rate = %0x\n", il->active_rate);
  3458. il->ctx.staging.cck_basic_rates =
  3459. (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
  3460. il->ctx.staging.ofdm_basic_rates =
  3461. (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
  3462. }
  3463. EXPORT_SYMBOL(il_set_rate);
  3464. void
  3465. il_chswitch_done(struct il_priv *il, bool is_success)
  3466. {
  3467. struct il_rxon_context *ctx = &il->ctx;
  3468. if (test_bit(S_EXIT_PENDING, &il->status))
  3469. return;
  3470. if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3471. ieee80211_chswitch_done(ctx->vif, is_success);
  3472. }
  3473. EXPORT_SYMBOL(il_chswitch_done);
  3474. void
  3475. il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
  3476. {
  3477. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3478. struct il_csa_notification *csa = &(pkt->u.csa_notif);
  3479. struct il_rxon_context *ctx = &il->ctx;
  3480. struct il_rxon_cmd *rxon = (void *)&ctx->active;
  3481. if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
  3482. return;
  3483. if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
  3484. rxon->channel = csa->channel;
  3485. ctx->staging.channel = csa->channel;
  3486. D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
  3487. il_chswitch_done(il, true);
  3488. } else {
  3489. IL_ERR("CSA notif (fail) : channel %d\n",
  3490. le16_to_cpu(csa->channel));
  3491. il_chswitch_done(il, false);
  3492. }
  3493. }
  3494. EXPORT_SYMBOL(il_hdl_csa);
  3495. #ifdef CONFIG_IWLEGACY_DEBUG
  3496. void
  3497. il_print_rx_config_cmd(struct il_priv *il, struct il_rxon_context *ctx)
  3498. {
  3499. struct il_rxon_cmd *rxon = &ctx->staging;
  3500. D_RADIO("RX CONFIG:\n");
  3501. il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3502. D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3503. D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3504. D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
  3505. D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3506. D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
  3507. D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3508. D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3509. D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3510. D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3511. }
  3512. EXPORT_SYMBOL(il_print_rx_config_cmd);
  3513. #endif
  3514. /**
  3515. * il_irq_handle_error - called for HW or SW error interrupt from card
  3516. */
  3517. void
  3518. il_irq_handle_error(struct il_priv *il)
  3519. {
  3520. /* Set the FW error flag -- cleared on il_down */
  3521. set_bit(S_FW_ERROR, &il->status);
  3522. /* Cancel currently queued command. */
  3523. clear_bit(S_HCMD_ACTIVE, &il->status);
  3524. IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
  3525. il->cfg->ops->lib->dump_nic_error_log(il);
  3526. if (il->cfg->ops->lib->dump_fh)
  3527. il->cfg->ops->lib->dump_fh(il, NULL, false);
  3528. #ifdef CONFIG_IWLEGACY_DEBUG
  3529. if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
  3530. il_print_rx_config_cmd(il, &il->ctx);
  3531. #endif
  3532. wake_up(&il->wait_command_queue);
  3533. /* Keep the restart process from trying to send host
  3534. * commands by clearing the INIT status bit */
  3535. clear_bit(S_READY, &il->status);
  3536. if (!test_bit(S_EXIT_PENDING, &il->status)) {
  3537. IL_DBG(IL_DL_FW_ERRORS,
  3538. "Restarting adapter due to uCode error.\n");
  3539. if (il->cfg->mod_params->restart_fw)
  3540. queue_work(il->workqueue, &il->restart);
  3541. }
  3542. }
  3543. EXPORT_SYMBOL(il_irq_handle_error);
  3544. static int
  3545. il_apm_stop_master(struct il_priv *il)
  3546. {
  3547. int ret = 0;
  3548. /* stop device's busmaster DMA activity */
  3549. il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  3550. ret =
  3551. _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  3552. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  3553. if (ret)
  3554. IL_WARN("Master Disable Timed Out, 100 usec\n");
  3555. D_INFO("stop master\n");
  3556. return ret;
  3557. }
  3558. void
  3559. il_apm_stop(struct il_priv *il)
  3560. {
  3561. D_INFO("Stop card, put in low power state\n");
  3562. /* Stop device's DMA activity */
  3563. il_apm_stop_master(il);
  3564. /* Reset the entire device */
  3565. il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  3566. udelay(10);
  3567. /*
  3568. * Clear "initialization complete" bit to move adapter from
  3569. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  3570. */
  3571. il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3572. }
  3573. EXPORT_SYMBOL(il_apm_stop);
  3574. /*
  3575. * Start up NIC's basic functionality after it has been reset
  3576. * (e.g. after platform boot, or shutdown via il_apm_stop())
  3577. * NOTE: This does not load uCode nor start the embedded processor
  3578. */
  3579. int
  3580. il_apm_init(struct il_priv *il)
  3581. {
  3582. int ret = 0;
  3583. u16 lctl;
  3584. D_INFO("Init card's basic functions\n");
  3585. /*
  3586. * Use "set_bit" below rather than "write", to preserve any hardware
  3587. * bits already set by default after reset.
  3588. */
  3589. /* Disable L0S exit timer (platform NMI Work/Around) */
  3590. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3591. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  3592. /*
  3593. * Disable L0s without affecting L1;
  3594. * don't wait for ICH L0s (ICH bug W/A)
  3595. */
  3596. il_set_bit(il, CSR_GIO_CHICKEN_BITS,
  3597. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  3598. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  3599. il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  3600. /*
  3601. * Enable HAP INTA (interrupt from management bus) to
  3602. * wake device's PCI Express link L1a -> L0s
  3603. * NOTE: This is no-op for 3945 (non-existent bit)
  3604. */
  3605. il_set_bit(il, CSR_HW_IF_CONFIG_REG,
  3606. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  3607. /*
  3608. * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
  3609. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  3610. * If so (likely), disable L0S, so device moves directly L0->L1;
  3611. * costs negligible amount of power savings.
  3612. * If not (unlikely), enable L0S, so there is at least some
  3613. * power savings, even without L1.
  3614. */
  3615. if (il->cfg->base_params->set_l0s) {
  3616. lctl = il_pcie_link_ctl(il);
  3617. if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
  3618. PCI_CFG_LINK_CTRL_VAL_L1_EN) {
  3619. /* L1-ASPM enabled; disable(!) L0S */
  3620. il_set_bit(il, CSR_GIO_REG,
  3621. CSR_GIO_REG_VAL_L0S_ENABLED);
  3622. D_POWER("L1 Enabled; Disabling L0S\n");
  3623. } else {
  3624. /* L1-ASPM disabled; enable(!) L0S */
  3625. il_clear_bit(il, CSR_GIO_REG,
  3626. CSR_GIO_REG_VAL_L0S_ENABLED);
  3627. D_POWER("L1 Disabled; Enabling L0S\n");
  3628. }
  3629. }
  3630. /* Configure analog phase-lock-loop before activating to D0A */
  3631. if (il->cfg->base_params->pll_cfg_val)
  3632. il_set_bit(il, CSR_ANA_PLL_CFG,
  3633. il->cfg->base_params->pll_cfg_val);
  3634. /*
  3635. * Set "initialization complete" bit to move adapter from
  3636. * D0U* --> D0A* (powered-up active) state.
  3637. */
  3638. il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  3639. /*
  3640. * Wait for clock stabilization; once stabilized, access to
  3641. * device-internal resources is supported, e.g. il_wr_prph()
  3642. * and accesses to uCode SRAM.
  3643. */
  3644. ret =
  3645. _il_poll_bit(il, CSR_GP_CNTRL,
  3646. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  3647. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  3648. if (ret < 0) {
  3649. D_INFO("Failed to init the card\n");
  3650. goto out;
  3651. }
  3652. /*
  3653. * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
  3654. * BSM (Boostrap State Machine) is only in 3945 and 4965.
  3655. *
  3656. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  3657. * do not disable clocks. This preserves any hardware bits already
  3658. * set by default in "CLK_CTRL_REG" after reset.
  3659. */
  3660. if (il->cfg->base_params->use_bsm)
  3661. il_wr_prph(il, APMG_CLK_EN_REG,
  3662. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  3663. else
  3664. il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  3665. udelay(20);
  3666. /* Disable L1-Active */
  3667. il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
  3668. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  3669. out:
  3670. return ret;
  3671. }
  3672. EXPORT_SYMBOL(il_apm_init);
  3673. int
  3674. il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
  3675. {
  3676. int ret;
  3677. s8 prev_tx_power;
  3678. bool defer;
  3679. struct il_rxon_context *ctx = &il->ctx;
  3680. lockdep_assert_held(&il->mutex);
  3681. if (il->tx_power_user_lmt == tx_power && !force)
  3682. return 0;
  3683. if (!il->cfg->ops->lib->send_tx_power)
  3684. return -EOPNOTSUPP;
  3685. /* 0 dBm mean 1 milliwatt */
  3686. if (tx_power < 0) {
  3687. IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
  3688. return -EINVAL;
  3689. }
  3690. if (tx_power > il->tx_power_device_lmt) {
  3691. IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
  3692. tx_power, il->tx_power_device_lmt);
  3693. return -EINVAL;
  3694. }
  3695. if (!il_is_ready_rf(il))
  3696. return -EIO;
  3697. /* scan complete and commit_rxon use tx_power_next value,
  3698. * it always need to be updated for newest request */
  3699. il->tx_power_next = tx_power;
  3700. /* do not set tx power when scanning or channel changing */
  3701. defer = test_bit(S_SCANNING, &il->status) ||
  3702. memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging));
  3703. if (defer && !force) {
  3704. D_INFO("Deferring tx power set\n");
  3705. return 0;
  3706. }
  3707. prev_tx_power = il->tx_power_user_lmt;
  3708. il->tx_power_user_lmt = tx_power;
  3709. ret = il->cfg->ops->lib->send_tx_power(il);
  3710. /* if fail to set tx_power, restore the orig. tx power */
  3711. if (ret) {
  3712. il->tx_power_user_lmt = prev_tx_power;
  3713. il->tx_power_next = prev_tx_power;
  3714. }
  3715. return ret;
  3716. }
  3717. EXPORT_SYMBOL(il_set_tx_power);
  3718. void
  3719. il_send_bt_config(struct il_priv *il)
  3720. {
  3721. struct il_bt_cmd bt_cmd = {
  3722. .lead_time = BT_LEAD_TIME_DEF,
  3723. .max_kill = BT_MAX_KILL_DEF,
  3724. .kill_ack_mask = 0,
  3725. .kill_cts_mask = 0,
  3726. };
  3727. if (!bt_coex_active)
  3728. bt_cmd.flags = BT_COEX_DISABLE;
  3729. else
  3730. bt_cmd.flags = BT_COEX_ENABLE;
  3731. D_INFO("BT coex %s\n",
  3732. (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
  3733. if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
  3734. IL_ERR("failed to send BT Coex Config\n");
  3735. }
  3736. EXPORT_SYMBOL(il_send_bt_config);
  3737. int
  3738. il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
  3739. {
  3740. struct il_stats_cmd stats_cmd = {
  3741. .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
  3742. };
  3743. if (flags & CMD_ASYNC)
  3744. return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
  3745. &stats_cmd, NULL);
  3746. else
  3747. return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
  3748. &stats_cmd);
  3749. }
  3750. EXPORT_SYMBOL(il_send_stats_request);
  3751. void
  3752. il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
  3753. {
  3754. #ifdef CONFIG_IWLEGACY_DEBUG
  3755. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3756. struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
  3757. D_RX("sleep mode: %d, src: %d\n",
  3758. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  3759. #endif
  3760. }
  3761. EXPORT_SYMBOL(il_hdl_pm_sleep);
  3762. void
  3763. il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
  3764. {
  3765. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3766. u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
  3767. D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
  3768. il_get_cmd_string(pkt->hdr.cmd));
  3769. il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
  3770. }
  3771. EXPORT_SYMBOL(il_hdl_pm_debug_stats);
  3772. void
  3773. il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
  3774. {
  3775. struct il_rx_pkt *pkt = rxb_addr(rxb);
  3776. IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
  3777. "seq 0x%04X ser 0x%08X\n",
  3778. le32_to_cpu(pkt->u.err_resp.error_type),
  3779. il_get_cmd_string(pkt->u.err_resp.cmd_id),
  3780. pkt->u.err_resp.cmd_id,
  3781. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  3782. le32_to_cpu(pkt->u.err_resp.error_info));
  3783. }
  3784. EXPORT_SYMBOL(il_hdl_error);
  3785. void
  3786. il_clear_isr_stats(struct il_priv *il)
  3787. {
  3788. memset(&il->isr_stats, 0, sizeof(il->isr_stats));
  3789. }
  3790. int
  3791. il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
  3792. const struct ieee80211_tx_queue_params *params)
  3793. {
  3794. struct il_priv *il = hw->priv;
  3795. unsigned long flags;
  3796. int q;
  3797. D_MAC80211("enter\n");
  3798. if (!il_is_ready_rf(il)) {
  3799. D_MAC80211("leave - RF not ready\n");
  3800. return -EIO;
  3801. }
  3802. if (queue >= AC_NUM) {
  3803. D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  3804. return 0;
  3805. }
  3806. q = AC_NUM - 1 - queue;
  3807. spin_lock_irqsave(&il->lock, flags);
  3808. il->ctx.qos_data.def_qos_parm.ac[q].cw_min =
  3809. cpu_to_le16(params->cw_min);
  3810. il->ctx.qos_data.def_qos_parm.ac[q].cw_max =
  3811. cpu_to_le16(params->cw_max);
  3812. il->ctx.qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  3813. il->ctx.qos_data.def_qos_parm.ac[q].edca_txop =
  3814. cpu_to_le16((params->txop * 32));
  3815. il->ctx.qos_data.def_qos_parm.ac[q].reserved1 = 0;
  3816. spin_unlock_irqrestore(&il->lock, flags);
  3817. D_MAC80211("leave\n");
  3818. return 0;
  3819. }
  3820. EXPORT_SYMBOL(il_mac_conf_tx);
  3821. int
  3822. il_mac_tx_last_beacon(struct ieee80211_hw *hw)
  3823. {
  3824. struct il_priv *il = hw->priv;
  3825. return il->ibss_manager == IL_IBSS_MANAGER;
  3826. }
  3827. EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
  3828. static int
  3829. il_set_mode(struct il_priv *il, struct il_rxon_context *ctx)
  3830. {
  3831. il_connection_init_rx_config(il, ctx);
  3832. if (il->cfg->ops->hcmd->set_rxon_chain)
  3833. il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
  3834. return il_commit_rxon(il, ctx);
  3835. }
  3836. static int
  3837. il_setup_interface(struct il_priv *il, struct il_rxon_context *ctx)
  3838. {
  3839. struct ieee80211_vif *vif = ctx->vif;
  3840. int err;
  3841. lockdep_assert_held(&il->mutex);
  3842. /*
  3843. * This variable will be correct only when there's just
  3844. * a single context, but all code using it is for hardware
  3845. * that supports only one context.
  3846. */
  3847. il->iw_mode = vif->type;
  3848. ctx->is_active = true;
  3849. err = il_set_mode(il, ctx);
  3850. if (err) {
  3851. if (!ctx->always_active)
  3852. ctx->is_active = false;
  3853. return err;
  3854. }
  3855. return 0;
  3856. }
  3857. int
  3858. il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3859. {
  3860. struct il_priv *il = hw->priv;
  3861. struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
  3862. int err;
  3863. u32 modes;
  3864. D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
  3865. mutex_lock(&il->mutex);
  3866. if (!il_is_ready_rf(il)) {
  3867. IL_WARN("Try to add interface when device not ready\n");
  3868. err = -EINVAL;
  3869. goto out;
  3870. }
  3871. /* check if busy context is exclusive */
  3872. if (il->ctx.vif &&
  3873. (il->ctx.exclusive_interface_modes & BIT(il->ctx.vif->type))) {
  3874. err = -EINVAL;
  3875. goto out;
  3876. }
  3877. modes = il->ctx.interface_modes | il->ctx.exclusive_interface_modes;
  3878. if (!(modes & BIT(vif->type))) {
  3879. err = -EOPNOTSUPP;
  3880. goto out;
  3881. }
  3882. vif_priv->ctx = &il->ctx;
  3883. il->ctx.vif = vif;
  3884. err = il_setup_interface(il, &il->ctx);
  3885. if (err) {
  3886. il->ctx.vif = NULL;
  3887. il->iw_mode = NL80211_IFTYPE_STATION;
  3888. }
  3889. out:
  3890. mutex_unlock(&il->mutex);
  3891. D_MAC80211("leave\n");
  3892. return err;
  3893. }
  3894. EXPORT_SYMBOL(il_mac_add_interface);
  3895. static void
  3896. il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif,
  3897. bool mode_change)
  3898. {
  3899. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  3900. lockdep_assert_held(&il->mutex);
  3901. if (il->scan_vif == vif) {
  3902. il_scan_cancel_timeout(il, 200);
  3903. il_force_scan_end(il);
  3904. }
  3905. if (!mode_change) {
  3906. il_set_mode(il, ctx);
  3907. if (!ctx->always_active)
  3908. ctx->is_active = false;
  3909. }
  3910. }
  3911. void
  3912. il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3913. {
  3914. struct il_priv *il = hw->priv;
  3915. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  3916. D_MAC80211("enter\n");
  3917. mutex_lock(&il->mutex);
  3918. WARN_ON(ctx->vif != vif);
  3919. ctx->vif = NULL;
  3920. il_teardown_interface(il, vif, false);
  3921. memset(il->bssid, 0, ETH_ALEN);
  3922. mutex_unlock(&il->mutex);
  3923. D_MAC80211("leave\n");
  3924. }
  3925. EXPORT_SYMBOL(il_mac_remove_interface);
  3926. int
  3927. il_alloc_txq_mem(struct il_priv *il)
  3928. {
  3929. if (!il->txq)
  3930. il->txq =
  3931. kzalloc(sizeof(struct il_tx_queue) *
  3932. il->cfg->base_params->num_of_queues, GFP_KERNEL);
  3933. if (!il->txq) {
  3934. IL_ERR("Not enough memory for txq\n");
  3935. return -ENOMEM;
  3936. }
  3937. return 0;
  3938. }
  3939. EXPORT_SYMBOL(il_alloc_txq_mem);
  3940. void
  3941. il_txq_mem(struct il_priv *il)
  3942. {
  3943. kfree(il->txq);
  3944. il->txq = NULL;
  3945. }
  3946. EXPORT_SYMBOL(il_txq_mem);
  3947. #ifdef CONFIG_IWLEGACY_DEBUGFS
  3948. #define IL_TRAFFIC_DUMP_SIZE (IL_TRAFFIC_ENTRY_SIZE * IL_TRAFFIC_ENTRIES)
  3949. void
  3950. il_reset_traffic_log(struct il_priv *il)
  3951. {
  3952. il->tx_traffic_idx = 0;
  3953. il->rx_traffic_idx = 0;
  3954. if (il->tx_traffic)
  3955. memset(il->tx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
  3956. if (il->rx_traffic)
  3957. memset(il->rx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
  3958. }
  3959. int
  3960. il_alloc_traffic_mem(struct il_priv *il)
  3961. {
  3962. u32 traffic_size = IL_TRAFFIC_DUMP_SIZE;
  3963. if (il_debug_level & IL_DL_TX) {
  3964. if (!il->tx_traffic) {
  3965. il->tx_traffic = kzalloc(traffic_size, GFP_KERNEL);
  3966. if (!il->tx_traffic)
  3967. return -ENOMEM;
  3968. }
  3969. }
  3970. if (il_debug_level & IL_DL_RX) {
  3971. if (!il->rx_traffic) {
  3972. il->rx_traffic = kzalloc(traffic_size, GFP_KERNEL);
  3973. if (!il->rx_traffic)
  3974. return -ENOMEM;
  3975. }
  3976. }
  3977. il_reset_traffic_log(il);
  3978. return 0;
  3979. }
  3980. EXPORT_SYMBOL(il_alloc_traffic_mem);
  3981. void
  3982. il_free_traffic_mem(struct il_priv *il)
  3983. {
  3984. kfree(il->tx_traffic);
  3985. il->tx_traffic = NULL;
  3986. kfree(il->rx_traffic);
  3987. il->rx_traffic = NULL;
  3988. }
  3989. EXPORT_SYMBOL(il_free_traffic_mem);
  3990. void
  3991. il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
  3992. struct ieee80211_hdr *header)
  3993. {
  3994. __le16 fc;
  3995. u16 len;
  3996. if (likely(!(il_debug_level & IL_DL_TX)))
  3997. return;
  3998. if (!il->tx_traffic)
  3999. return;
  4000. fc = header->frame_control;
  4001. if (ieee80211_is_data(fc)) {
  4002. len =
  4003. (length >
  4004. IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length;
  4005. memcpy((il->tx_traffic +
  4006. (il->tx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header,
  4007. len);
  4008. il->tx_traffic_idx =
  4009. (il->tx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
  4010. }
  4011. }
  4012. EXPORT_SYMBOL(il_dbg_log_tx_data_frame);
  4013. void
  4014. il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
  4015. struct ieee80211_hdr *header)
  4016. {
  4017. __le16 fc;
  4018. u16 len;
  4019. if (likely(!(il_debug_level & IL_DL_RX)))
  4020. return;
  4021. if (!il->rx_traffic)
  4022. return;
  4023. fc = header->frame_control;
  4024. if (ieee80211_is_data(fc)) {
  4025. len =
  4026. (length >
  4027. IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length;
  4028. memcpy((il->rx_traffic +
  4029. (il->rx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header,
  4030. len);
  4031. il->rx_traffic_idx =
  4032. (il->rx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
  4033. }
  4034. }
  4035. EXPORT_SYMBOL(il_dbg_log_rx_data_frame);
  4036. const char *
  4037. il_get_mgmt_string(int cmd)
  4038. {
  4039. switch (cmd) {
  4040. IL_CMD(MANAGEMENT_ASSOC_REQ);
  4041. IL_CMD(MANAGEMENT_ASSOC_RESP);
  4042. IL_CMD(MANAGEMENT_REASSOC_REQ);
  4043. IL_CMD(MANAGEMENT_REASSOC_RESP);
  4044. IL_CMD(MANAGEMENT_PROBE_REQ);
  4045. IL_CMD(MANAGEMENT_PROBE_RESP);
  4046. IL_CMD(MANAGEMENT_BEACON);
  4047. IL_CMD(MANAGEMENT_ATIM);
  4048. IL_CMD(MANAGEMENT_DISASSOC);
  4049. IL_CMD(MANAGEMENT_AUTH);
  4050. IL_CMD(MANAGEMENT_DEAUTH);
  4051. IL_CMD(MANAGEMENT_ACTION);
  4052. default:
  4053. return "UNKNOWN";
  4054. }
  4055. }
  4056. const char *
  4057. il_get_ctrl_string(int cmd)
  4058. {
  4059. switch (cmd) {
  4060. IL_CMD(CONTROL_BACK_REQ);
  4061. IL_CMD(CONTROL_BACK);
  4062. IL_CMD(CONTROL_PSPOLL);
  4063. IL_CMD(CONTROL_RTS);
  4064. IL_CMD(CONTROL_CTS);
  4065. IL_CMD(CONTROL_ACK);
  4066. IL_CMD(CONTROL_CFEND);
  4067. IL_CMD(CONTROL_CFENDACK);
  4068. default:
  4069. return "UNKNOWN";
  4070. }
  4071. }
  4072. void
  4073. il_clear_traffic_stats(struct il_priv *il)
  4074. {
  4075. memset(&il->tx_stats, 0, sizeof(struct traffic_stats));
  4076. memset(&il->rx_stats, 0, sizeof(struct traffic_stats));
  4077. }
  4078. /*
  4079. * if CONFIG_IWLEGACY_DEBUGFS defined,
  4080. * il_update_stats function will
  4081. * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass
  4082. * Use debugFs to display the rx/rx_stats
  4083. * if CONFIG_IWLEGACY_DEBUGFS not being defined, then no MGMT and CTRL
  4084. * information will be recorded, but DATA pkt still will be recorded
  4085. * for the reason of il_led.c need to control the led blinking based on
  4086. * number of tx and rx data.
  4087. *
  4088. */
  4089. void
  4090. il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
  4091. {
  4092. struct traffic_stats *stats;
  4093. if (is_tx)
  4094. stats = &il->tx_stats;
  4095. else
  4096. stats = &il->rx_stats;
  4097. if (ieee80211_is_mgmt(fc)) {
  4098. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  4099. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  4100. stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
  4101. break;
  4102. case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
  4103. stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
  4104. break;
  4105. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  4106. stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
  4107. break;
  4108. case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
  4109. stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
  4110. break;
  4111. case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
  4112. stats->mgmt[MANAGEMENT_PROBE_REQ]++;
  4113. break;
  4114. case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
  4115. stats->mgmt[MANAGEMENT_PROBE_RESP]++;
  4116. break;
  4117. case cpu_to_le16(IEEE80211_STYPE_BEACON):
  4118. stats->mgmt[MANAGEMENT_BEACON]++;
  4119. break;
  4120. case cpu_to_le16(IEEE80211_STYPE_ATIM):
  4121. stats->mgmt[MANAGEMENT_ATIM]++;
  4122. break;
  4123. case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
  4124. stats->mgmt[MANAGEMENT_DISASSOC]++;
  4125. break;
  4126. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  4127. stats->mgmt[MANAGEMENT_AUTH]++;
  4128. break;
  4129. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  4130. stats->mgmt[MANAGEMENT_DEAUTH]++;
  4131. break;
  4132. case cpu_to_le16(IEEE80211_STYPE_ACTION):
  4133. stats->mgmt[MANAGEMENT_ACTION]++;
  4134. break;
  4135. }
  4136. } else if (ieee80211_is_ctl(fc)) {
  4137. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  4138. case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
  4139. stats->ctrl[CONTROL_BACK_REQ]++;
  4140. break;
  4141. case cpu_to_le16(IEEE80211_STYPE_BACK):
  4142. stats->ctrl[CONTROL_BACK]++;
  4143. break;
  4144. case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
  4145. stats->ctrl[CONTROL_PSPOLL]++;
  4146. break;
  4147. case cpu_to_le16(IEEE80211_STYPE_RTS):
  4148. stats->ctrl[CONTROL_RTS]++;
  4149. break;
  4150. case cpu_to_le16(IEEE80211_STYPE_CTS):
  4151. stats->ctrl[CONTROL_CTS]++;
  4152. break;
  4153. case cpu_to_le16(IEEE80211_STYPE_ACK):
  4154. stats->ctrl[CONTROL_ACK]++;
  4155. break;
  4156. case cpu_to_le16(IEEE80211_STYPE_CFEND):
  4157. stats->ctrl[CONTROL_CFEND]++;
  4158. break;
  4159. case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
  4160. stats->ctrl[CONTROL_CFENDACK]++;
  4161. break;
  4162. }
  4163. } else {
  4164. /* data */
  4165. stats->data_cnt++;
  4166. stats->data_bytes += len;
  4167. }
  4168. }
  4169. EXPORT_SYMBOL(il_update_stats);
  4170. #endif
  4171. int
  4172. il_force_reset(struct il_priv *il, bool external)
  4173. {
  4174. struct il_force_reset *force_reset;
  4175. if (test_bit(S_EXIT_PENDING, &il->status))
  4176. return -EINVAL;
  4177. force_reset = &il->force_reset;
  4178. force_reset->reset_request_count++;
  4179. if (!external) {
  4180. if (force_reset->last_force_reset_jiffies &&
  4181. time_after(force_reset->last_force_reset_jiffies +
  4182. force_reset->reset_duration, jiffies)) {
  4183. D_INFO("force reset rejected\n");
  4184. force_reset->reset_reject_count++;
  4185. return -EAGAIN;
  4186. }
  4187. }
  4188. force_reset->reset_success_count++;
  4189. force_reset->last_force_reset_jiffies = jiffies;
  4190. /*
  4191. * if the request is from external(ex: debugfs),
  4192. * then always perform the request in regardless the module
  4193. * parameter setting
  4194. * if the request is from internal (uCode error or driver
  4195. * detect failure), then fw_restart module parameter
  4196. * need to be check before performing firmware reload
  4197. */
  4198. if (!external && !il->cfg->mod_params->restart_fw) {
  4199. D_INFO("Cancel firmware reload based on "
  4200. "module parameter setting\n");
  4201. return 0;
  4202. }
  4203. IL_ERR("On demand firmware reload\n");
  4204. /* Set the FW error flag -- cleared on il_down */
  4205. set_bit(S_FW_ERROR, &il->status);
  4206. wake_up(&il->wait_command_queue);
  4207. /*
  4208. * Keep the restart process from trying to send host
  4209. * commands by clearing the INIT status bit
  4210. */
  4211. clear_bit(S_READY, &il->status);
  4212. queue_work(il->workqueue, &il->restart);
  4213. return 0;
  4214. }
  4215. int
  4216. il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  4217. enum nl80211_iftype newtype, bool newp2p)
  4218. {
  4219. struct il_priv *il = hw->priv;
  4220. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  4221. u32 modes;
  4222. int err;
  4223. newtype = ieee80211_iftype_p2p(newtype, newp2p);
  4224. mutex_lock(&il->mutex);
  4225. if (!ctx->vif || !il_is_ready_rf(il)) {
  4226. /*
  4227. * Huh? But wait ... this can maybe happen when
  4228. * we're in the middle of a firmware restart!
  4229. */
  4230. err = -EBUSY;
  4231. goto out;
  4232. }
  4233. modes = ctx->interface_modes | ctx->exclusive_interface_modes;
  4234. if (!(modes & BIT(newtype))) {
  4235. err = -EOPNOTSUPP;
  4236. goto out;
  4237. }
  4238. if ((il->ctx.exclusive_interface_modes & BIT(il->ctx.vif->type)) ||
  4239. (il->ctx.exclusive_interface_modes & BIT(newtype))) {
  4240. err = -EINVAL;
  4241. goto out;
  4242. }
  4243. /* success */
  4244. il_teardown_interface(il, vif, true);
  4245. vif->type = newtype;
  4246. vif->p2p = newp2p;
  4247. err = il_setup_interface(il, ctx);
  4248. WARN_ON(err);
  4249. /*
  4250. * We've switched internally, but submitting to the
  4251. * device may have failed for some reason. Mask this
  4252. * error, because otherwise mac80211 will not switch
  4253. * (and set the interface type back) and we'll be
  4254. * out of sync with it.
  4255. */
  4256. err = 0;
  4257. out:
  4258. mutex_unlock(&il->mutex);
  4259. return err;
  4260. }
  4261. EXPORT_SYMBOL(il_mac_change_interface);
  4262. /*
  4263. * On every watchdog tick we check (latest) time stamp. If it does not
  4264. * change during timeout period and queue is not empty we reset firmware.
  4265. */
  4266. static int
  4267. il_check_stuck_queue(struct il_priv *il, int cnt)
  4268. {
  4269. struct il_tx_queue *txq = &il->txq[cnt];
  4270. struct il_queue *q = &txq->q;
  4271. unsigned long timeout;
  4272. int ret;
  4273. if (q->read_ptr == q->write_ptr) {
  4274. txq->time_stamp = jiffies;
  4275. return 0;
  4276. }
  4277. timeout =
  4278. txq->time_stamp +
  4279. msecs_to_jiffies(il->cfg->base_params->wd_timeout);
  4280. if (time_after(jiffies, timeout)) {
  4281. IL_ERR("Queue %d stuck for %u ms.\n", q->id,
  4282. il->cfg->base_params->wd_timeout);
  4283. ret = il_force_reset(il, false);
  4284. return (ret == -EAGAIN) ? 0 : 1;
  4285. }
  4286. return 0;
  4287. }
  4288. /*
  4289. * Making watchdog tick be a quarter of timeout assure we will
  4290. * discover the queue hung between timeout and 1.25*timeout
  4291. */
  4292. #define IL_WD_TICK(timeout) ((timeout) / 4)
  4293. /*
  4294. * Watchdog timer callback, we check each tx queue for stuck, if if hung
  4295. * we reset the firmware. If everything is fine just rearm the timer.
  4296. */
  4297. void
  4298. il_bg_watchdog(unsigned long data)
  4299. {
  4300. struct il_priv *il = (struct il_priv *)data;
  4301. int cnt;
  4302. unsigned long timeout;
  4303. if (test_bit(S_EXIT_PENDING, &il->status))
  4304. return;
  4305. timeout = il->cfg->base_params->wd_timeout;
  4306. if (timeout == 0)
  4307. return;
  4308. /* monitor and check for stuck cmd queue */
  4309. if (il_check_stuck_queue(il, il->cmd_queue))
  4310. return;
  4311. /* monitor and check for other stuck queues */
  4312. if (il_is_any_associated(il)) {
  4313. for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
  4314. /* skip as we already checked the command queue */
  4315. if (cnt == il->cmd_queue)
  4316. continue;
  4317. if (il_check_stuck_queue(il, cnt))
  4318. return;
  4319. }
  4320. }
  4321. mod_timer(&il->watchdog,
  4322. jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
  4323. }
  4324. EXPORT_SYMBOL(il_bg_watchdog);
  4325. void
  4326. il_setup_watchdog(struct il_priv *il)
  4327. {
  4328. unsigned int timeout = il->cfg->base_params->wd_timeout;
  4329. if (timeout)
  4330. mod_timer(&il->watchdog,
  4331. jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
  4332. else
  4333. del_timer(&il->watchdog);
  4334. }
  4335. EXPORT_SYMBOL(il_setup_watchdog);
  4336. /*
  4337. * extended beacon time format
  4338. * time in usec will be changed into a 32-bit value in extended:internal format
  4339. * the extended part is the beacon counts
  4340. * the internal part is the time in usec within one beacon interval
  4341. */
  4342. u32
  4343. il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
  4344. {
  4345. u32 quot;
  4346. u32 rem;
  4347. u32 interval = beacon_interval * TIME_UNIT;
  4348. if (!interval || !usec)
  4349. return 0;
  4350. quot =
  4351. (usec /
  4352. interval) & (il_beacon_time_mask_high(il,
  4353. il->hw_params.
  4354. beacon_time_tsf_bits) >> il->
  4355. hw_params.beacon_time_tsf_bits);
  4356. rem =
  4357. (usec % interval) & il_beacon_time_mask_low(il,
  4358. il->hw_params.
  4359. beacon_time_tsf_bits);
  4360. return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
  4361. }
  4362. EXPORT_SYMBOL(il_usecs_to_beacons);
  4363. /* base is usually what we get from ucode with each received frame,
  4364. * the same as HW timer counter counting down
  4365. */
  4366. __le32
  4367. il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
  4368. u32 beacon_interval)
  4369. {
  4370. u32 base_low = base & il_beacon_time_mask_low(il,
  4371. il->hw_params.
  4372. beacon_time_tsf_bits);
  4373. u32 addon_low = addon & il_beacon_time_mask_low(il,
  4374. il->hw_params.
  4375. beacon_time_tsf_bits);
  4376. u32 interval = beacon_interval * TIME_UNIT;
  4377. u32 res = (base & il_beacon_time_mask_high(il,
  4378. il->hw_params.
  4379. beacon_time_tsf_bits)) +
  4380. (addon & il_beacon_time_mask_high(il,
  4381. il->hw_params.
  4382. beacon_time_tsf_bits));
  4383. if (base_low > addon_low)
  4384. res += base_low - addon_low;
  4385. else if (base_low < addon_low) {
  4386. res += interval + base_low - addon_low;
  4387. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4388. } else
  4389. res += (1 << il->hw_params.beacon_time_tsf_bits);
  4390. return cpu_to_le32(res);
  4391. }
  4392. EXPORT_SYMBOL(il_add_beacon_time);
  4393. #ifdef CONFIG_PM
  4394. int
  4395. il_pci_suspend(struct device *device)
  4396. {
  4397. struct pci_dev *pdev = to_pci_dev(device);
  4398. struct il_priv *il = pci_get_drvdata(pdev);
  4399. /*
  4400. * This function is called when system goes into suspend state
  4401. * mac80211 will call il_mac_stop() from the mac80211 suspend function
  4402. * first but since il_mac_stop() has no knowledge of who the caller is,
  4403. * it will not call apm_ops.stop() to stop the DMA operation.
  4404. * Calling apm_ops.stop here to make sure we stop the DMA.
  4405. */
  4406. il_apm_stop(il);
  4407. return 0;
  4408. }
  4409. EXPORT_SYMBOL(il_pci_suspend);
  4410. int
  4411. il_pci_resume(struct device *device)
  4412. {
  4413. struct pci_dev *pdev = to_pci_dev(device);
  4414. struct il_priv *il = pci_get_drvdata(pdev);
  4415. bool hw_rfkill = false;
  4416. /*
  4417. * We disable the RETRY_TIMEOUT register (0x41) to keep
  4418. * PCI Tx retries from interfering with C3 CPU state.
  4419. */
  4420. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  4421. il_enable_interrupts(il);
  4422. if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  4423. hw_rfkill = true;
  4424. if (hw_rfkill)
  4425. set_bit(S_RF_KILL_HW, &il->status);
  4426. else
  4427. clear_bit(S_RF_KILL_HW, &il->status);
  4428. wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
  4429. return 0;
  4430. }
  4431. EXPORT_SYMBOL(il_pci_resume);
  4432. const struct dev_pm_ops il_pm_ops = {
  4433. .suspend = il_pci_suspend,
  4434. .resume = il_pci_resume,
  4435. .freeze = il_pci_suspend,
  4436. .thaw = il_pci_resume,
  4437. .poweroff = il_pci_suspend,
  4438. .restore = il_pci_resume,
  4439. };
  4440. EXPORT_SYMBOL(il_pm_ops);
  4441. #endif /* CONFIG_PM */
  4442. static void
  4443. il_update_qos(struct il_priv *il, struct il_rxon_context *ctx)
  4444. {
  4445. if (test_bit(S_EXIT_PENDING, &il->status))
  4446. return;
  4447. if (!ctx->is_active)
  4448. return;
  4449. ctx->qos_data.def_qos_parm.qos_flags = 0;
  4450. if (ctx->qos_data.qos_active)
  4451. ctx->qos_data.def_qos_parm.qos_flags |=
  4452. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  4453. if (ctx->ht.enabled)
  4454. ctx->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  4455. D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  4456. ctx->qos_data.qos_active, ctx->qos_data.def_qos_parm.qos_flags);
  4457. il_send_cmd_pdu_async(il, ctx->qos_cmd, sizeof(struct il_qosparam_cmd),
  4458. &ctx->qos_data.def_qos_parm, NULL);
  4459. }
  4460. /**
  4461. * il_mac_config - mac80211 config callback
  4462. */
  4463. int
  4464. il_mac_config(struct ieee80211_hw *hw, u32 changed)
  4465. {
  4466. struct il_priv *il = hw->priv;
  4467. const struct il_channel_info *ch_info;
  4468. struct ieee80211_conf *conf = &hw->conf;
  4469. struct ieee80211_channel *channel = conf->channel;
  4470. struct il_ht_config *ht_conf = &il->current_ht_config;
  4471. struct il_rxon_context *ctx = &il->ctx;
  4472. unsigned long flags = 0;
  4473. int ret = 0;
  4474. u16 ch;
  4475. int scan_active = 0;
  4476. bool ht_changed = false;
  4477. if (WARN_ON(!il->cfg->ops->legacy))
  4478. return -EOPNOTSUPP;
  4479. mutex_lock(&il->mutex);
  4480. D_MAC80211("enter to channel %d changed 0x%X\n", channel->hw_value,
  4481. changed);
  4482. if (unlikely(test_bit(S_SCANNING, &il->status))) {
  4483. scan_active = 1;
  4484. D_MAC80211("scan active\n");
  4485. }
  4486. if (changed &
  4487. (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
  4488. /* mac80211 uses static for non-HT which is what we want */
  4489. il->current_ht_config.smps = conf->smps_mode;
  4490. /*
  4491. * Recalculate chain counts.
  4492. *
  4493. * If monitor mode is enabled then mac80211 will
  4494. * set up the SM PS mode to OFF if an HT channel is
  4495. * configured.
  4496. */
  4497. if (il->cfg->ops->hcmd->set_rxon_chain)
  4498. il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx);
  4499. }
  4500. /* during scanning mac80211 will delay channel setting until
  4501. * scan finish with changed = 0
  4502. */
  4503. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  4504. if (scan_active)
  4505. goto set_ch_out;
  4506. ch = channel->hw_value;
  4507. ch_info = il_get_channel_info(il, channel->band, ch);
  4508. if (!il_is_channel_valid(ch_info)) {
  4509. D_MAC80211("leave - invalid channel\n");
  4510. ret = -EINVAL;
  4511. goto set_ch_out;
  4512. }
  4513. if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
  4514. !il_is_channel_ibss(ch_info)) {
  4515. D_MAC80211("leave - not IBSS channel\n");
  4516. ret = -EINVAL;
  4517. goto set_ch_out;
  4518. }
  4519. spin_lock_irqsave(&il->lock, flags);
  4520. /* Configure HT40 channels */
  4521. if (ctx->ht.enabled != conf_is_ht(conf)) {
  4522. ctx->ht.enabled = conf_is_ht(conf);
  4523. ht_changed = true;
  4524. }
  4525. if (ctx->ht.enabled) {
  4526. if (conf_is_ht40_minus(conf)) {
  4527. ctx->ht.extension_chan_offset =
  4528. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  4529. ctx->ht.is_40mhz = true;
  4530. } else if (conf_is_ht40_plus(conf)) {
  4531. ctx->ht.extension_chan_offset =
  4532. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  4533. ctx->ht.is_40mhz = true;
  4534. } else {
  4535. ctx->ht.extension_chan_offset =
  4536. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  4537. ctx->ht.is_40mhz = false;
  4538. }
  4539. } else
  4540. ctx->ht.is_40mhz = false;
  4541. /*
  4542. * Default to no protection. Protection mode will
  4543. * later be set from BSS config in il_ht_conf
  4544. */
  4545. ctx->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  4546. /* if we are switching from ht to 2.4 clear flags
  4547. * from any ht related info since 2.4 does not
  4548. * support ht */
  4549. if ((le16_to_cpu(ctx->staging.channel) != ch))
  4550. ctx->staging.flags = 0;
  4551. il_set_rxon_channel(il, channel, ctx);
  4552. il_set_rxon_ht(il, ht_conf);
  4553. il_set_flags_for_band(il, ctx, channel->band, ctx->vif);
  4554. spin_unlock_irqrestore(&il->lock, flags);
  4555. if (il->cfg->ops->legacy->update_bcast_stations)
  4556. ret = il->cfg->ops->legacy->update_bcast_stations(il);
  4557. set_ch_out:
  4558. /* The list of supported rates and rate mask can be different
  4559. * for each band; since the band may have changed, reset
  4560. * the rate mask to what mac80211 lists */
  4561. il_set_rate(il);
  4562. }
  4563. if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
  4564. ret = il_power_update_mode(il, false);
  4565. if (ret)
  4566. D_MAC80211("Error setting sleep level\n");
  4567. }
  4568. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  4569. D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
  4570. conf->power_level);
  4571. il_set_tx_power(il, conf->power_level, false);
  4572. }
  4573. if (!il_is_ready(il)) {
  4574. D_MAC80211("leave - not ready\n");
  4575. goto out;
  4576. }
  4577. if (scan_active)
  4578. goto out;
  4579. if (memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)))
  4580. il_commit_rxon(il, ctx);
  4581. else
  4582. D_INFO("Not re-sending same RXON configuration.\n");
  4583. if (ht_changed)
  4584. il_update_qos(il, ctx);
  4585. out:
  4586. D_MAC80211("leave\n");
  4587. mutex_unlock(&il->mutex);
  4588. return ret;
  4589. }
  4590. EXPORT_SYMBOL(il_mac_config);
  4591. void
  4592. il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  4593. {
  4594. struct il_priv *il = hw->priv;
  4595. unsigned long flags;
  4596. struct il_rxon_context *ctx = &il->ctx;
  4597. if (WARN_ON(!il->cfg->ops->legacy))
  4598. return;
  4599. mutex_lock(&il->mutex);
  4600. D_MAC80211("enter\n");
  4601. spin_lock_irqsave(&il->lock, flags);
  4602. memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
  4603. spin_unlock_irqrestore(&il->lock, flags);
  4604. spin_lock_irqsave(&il->lock, flags);
  4605. /* new association get rid of ibss beacon skb */
  4606. if (il->beacon_skb)
  4607. dev_kfree_skb(il->beacon_skb);
  4608. il->beacon_skb = NULL;
  4609. il->timestamp = 0;
  4610. spin_unlock_irqrestore(&il->lock, flags);
  4611. il_scan_cancel_timeout(il, 100);
  4612. if (!il_is_ready_rf(il)) {
  4613. D_MAC80211("leave - not ready\n");
  4614. mutex_unlock(&il->mutex);
  4615. return;
  4616. }
  4617. /* we are restarting association process
  4618. * clear RXON_FILTER_ASSOC_MSK bit
  4619. */
  4620. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4621. il_commit_rxon(il, ctx);
  4622. il_set_rate(il);
  4623. mutex_unlock(&il->mutex);
  4624. D_MAC80211("leave\n");
  4625. }
  4626. EXPORT_SYMBOL(il_mac_reset_tsf);
  4627. static void
  4628. il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
  4629. {
  4630. struct il_ht_config *ht_conf = &il->current_ht_config;
  4631. struct ieee80211_sta *sta;
  4632. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  4633. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  4634. D_ASSOC("enter:\n");
  4635. if (!ctx->ht.enabled)
  4636. return;
  4637. ctx->ht.protection =
  4638. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  4639. ctx->ht.non_gf_sta_present =
  4640. !!(bss_conf->
  4641. ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  4642. ht_conf->single_chain_sufficient = false;
  4643. switch (vif->type) {
  4644. case NL80211_IFTYPE_STATION:
  4645. rcu_read_lock();
  4646. sta = ieee80211_find_sta(vif, bss_conf->bssid);
  4647. if (sta) {
  4648. struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
  4649. int maxstreams;
  4650. maxstreams =
  4651. (ht_cap->mcs.
  4652. tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
  4653. >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  4654. maxstreams += 1;
  4655. if (ht_cap->mcs.rx_mask[1] == 0 &&
  4656. ht_cap->mcs.rx_mask[2] == 0)
  4657. ht_conf->single_chain_sufficient = true;
  4658. if (maxstreams <= 1)
  4659. ht_conf->single_chain_sufficient = true;
  4660. } else {
  4661. /*
  4662. * If at all, this can only happen through a race
  4663. * when the AP disconnects us while we're still
  4664. * setting up the connection, in that case mac80211
  4665. * will soon tell us about that.
  4666. */
  4667. ht_conf->single_chain_sufficient = true;
  4668. }
  4669. rcu_read_unlock();
  4670. break;
  4671. case NL80211_IFTYPE_ADHOC:
  4672. ht_conf->single_chain_sufficient = true;
  4673. break;
  4674. default:
  4675. break;
  4676. }
  4677. D_ASSOC("leave\n");
  4678. }
  4679. static inline void
  4680. il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
  4681. {
  4682. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  4683. /*
  4684. * inform the ucode that there is no longer an
  4685. * association and that no more packets should be
  4686. * sent
  4687. */
  4688. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4689. ctx->staging.assoc_id = 0;
  4690. il_commit_rxon(il, ctx);
  4691. }
  4692. static void
  4693. il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  4694. {
  4695. struct il_priv *il = hw->priv;
  4696. unsigned long flags;
  4697. __le64 timestamp;
  4698. struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
  4699. if (!skb)
  4700. return;
  4701. D_MAC80211("enter\n");
  4702. lockdep_assert_held(&il->mutex);
  4703. if (!il->beacon_ctx) {
  4704. IL_ERR("update beacon but no beacon context!\n");
  4705. dev_kfree_skb(skb);
  4706. return;
  4707. }
  4708. spin_lock_irqsave(&il->lock, flags);
  4709. if (il->beacon_skb)
  4710. dev_kfree_skb(il->beacon_skb);
  4711. il->beacon_skb = skb;
  4712. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  4713. il->timestamp = le64_to_cpu(timestamp);
  4714. D_MAC80211("leave\n");
  4715. spin_unlock_irqrestore(&il->lock, flags);
  4716. if (!il_is_ready_rf(il)) {
  4717. D_MAC80211("leave - RF not ready\n");
  4718. return;
  4719. }
  4720. il->cfg->ops->legacy->post_associate(il);
  4721. }
  4722. void
  4723. il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  4724. struct ieee80211_bss_conf *bss_conf, u32 changes)
  4725. {
  4726. struct il_priv *il = hw->priv;
  4727. struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
  4728. int ret;
  4729. if (WARN_ON(!il->cfg->ops->legacy))
  4730. return;
  4731. D_MAC80211("changes = 0x%X\n", changes);
  4732. mutex_lock(&il->mutex);
  4733. if (!il_is_alive(il)) {
  4734. mutex_unlock(&il->mutex);
  4735. return;
  4736. }
  4737. if (changes & BSS_CHANGED_QOS) {
  4738. unsigned long flags;
  4739. spin_lock_irqsave(&il->lock, flags);
  4740. ctx->qos_data.qos_active = bss_conf->qos;
  4741. il_update_qos(il, ctx);
  4742. spin_unlock_irqrestore(&il->lock, flags);
  4743. }
  4744. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4745. /*
  4746. * the add_interface code must make sure we only ever
  4747. * have a single interface that could be beaconing at
  4748. * any time.
  4749. */
  4750. if (vif->bss_conf.enable_beacon)
  4751. il->beacon_ctx = ctx;
  4752. else
  4753. il->beacon_ctx = NULL;
  4754. }
  4755. if (changes & BSS_CHANGED_BSSID) {
  4756. D_MAC80211("BSSID %pM\n", bss_conf->bssid);
  4757. /*
  4758. * If there is currently a HW scan going on in the
  4759. * background then we need to cancel it else the RXON
  4760. * below/in post_associate will fail.
  4761. */
  4762. if (il_scan_cancel_timeout(il, 100)) {
  4763. IL_WARN("Aborted scan still in progress after 100ms\n");
  4764. D_MAC80211("leaving - scan abort failed.\n");
  4765. mutex_unlock(&il->mutex);
  4766. return;
  4767. }
  4768. /* mac80211 only sets assoc when in STATION mode */
  4769. if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) {
  4770. memcpy(ctx->staging.bssid_addr, bss_conf->bssid,
  4771. ETH_ALEN);
  4772. /* currently needed in a few places */
  4773. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4774. } else {
  4775. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4776. }
  4777. }
  4778. /*
  4779. * This needs to be after setting the BSSID in case
  4780. * mac80211 decides to do both changes at once because
  4781. * it will invoke post_associate.
  4782. */
  4783. if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
  4784. il_beacon_update(hw, vif);
  4785. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  4786. D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
  4787. if (bss_conf->use_short_preamble)
  4788. ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4789. else
  4790. ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4791. }
  4792. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  4793. D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  4794. if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
  4795. ctx->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
  4796. else
  4797. ctx->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  4798. if (bss_conf->use_cts_prot)
  4799. ctx->staging.flags |= RXON_FLG_SELF_CTS_EN;
  4800. else
  4801. ctx->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
  4802. }
  4803. if (changes & BSS_CHANGED_BASIC_RATES) {
  4804. /* XXX use this information
  4805. *
  4806. * To do that, remove code from il_set_rate() and put something
  4807. * like this here:
  4808. *
  4809. if (A-band)
  4810. ctx->staging.ofdm_basic_rates =
  4811. bss_conf->basic_rates;
  4812. else
  4813. ctx->staging.ofdm_basic_rates =
  4814. bss_conf->basic_rates >> 4;
  4815. ctx->staging.cck_basic_rates =
  4816. bss_conf->basic_rates & 0xF;
  4817. */
  4818. }
  4819. if (changes & BSS_CHANGED_HT) {
  4820. il_ht_conf(il, vif);
  4821. if (il->cfg->ops->hcmd->set_rxon_chain)
  4822. il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
  4823. }
  4824. if (changes & BSS_CHANGED_ASSOC) {
  4825. D_MAC80211("ASSOC %d\n", bss_conf->assoc);
  4826. if (bss_conf->assoc) {
  4827. il->timestamp = bss_conf->timestamp;
  4828. if (!il_is_rfkill(il))
  4829. il->cfg->ops->legacy->post_associate(il);
  4830. } else
  4831. il_set_no_assoc(il, vif);
  4832. }
  4833. if (changes && il_is_associated_ctx(ctx) && bss_conf->aid) {
  4834. D_MAC80211("Changes (%#x) while associated\n", changes);
  4835. ret = il_send_rxon_assoc(il, ctx);
  4836. if (!ret) {
  4837. /* Sync active_rxon with latest change. */
  4838. memcpy((void *)&ctx->active, &ctx->staging,
  4839. sizeof(struct il_rxon_cmd));
  4840. }
  4841. }
  4842. if (changes & BSS_CHANGED_BEACON_ENABLED) {
  4843. if (vif->bss_conf.enable_beacon) {
  4844. memcpy(ctx->staging.bssid_addr, bss_conf->bssid,
  4845. ETH_ALEN);
  4846. memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
  4847. il->cfg->ops->legacy->config_ap(il);
  4848. } else
  4849. il_set_no_assoc(il, vif);
  4850. }
  4851. if (changes & BSS_CHANGED_IBSS) {
  4852. ret =
  4853. il->cfg->ops->legacy->manage_ibss_station(il, vif,
  4854. bss_conf->
  4855. ibss_joined);
  4856. if (ret)
  4857. IL_ERR("failed to %s IBSS station %pM\n",
  4858. bss_conf->ibss_joined ? "add" : "remove",
  4859. bss_conf->bssid);
  4860. }
  4861. mutex_unlock(&il->mutex);
  4862. D_MAC80211("leave\n");
  4863. }
  4864. EXPORT_SYMBOL(il_mac_bss_info_changed);
  4865. irqreturn_t
  4866. il_isr(int irq, void *data)
  4867. {
  4868. struct il_priv *il = data;
  4869. u32 inta, inta_mask;
  4870. u32 inta_fh;
  4871. unsigned long flags;
  4872. if (!il)
  4873. return IRQ_NONE;
  4874. spin_lock_irqsave(&il->lock, flags);
  4875. /* Disable (but don't clear!) interrupts here to avoid
  4876. * back-to-back ISRs and sporadic interrupts from our NIC.
  4877. * If we have something to service, the tasklet will re-enable ints.
  4878. * If we *don't* have something, we'll re-enable before leaving here. */
  4879. inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
  4880. _il_wr(il, CSR_INT_MASK, 0x00000000);
  4881. /* Discover which interrupts are active/pending */
  4882. inta = _il_rd(il, CSR_INT);
  4883. inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
  4884. /* Ignore interrupt if there's nothing in NIC to service.
  4885. * This may be due to IRQ shared with another device,
  4886. * or due to sporadic interrupts thrown from our NIC. */
  4887. if (!inta && !inta_fh) {
  4888. D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  4889. goto none;
  4890. }
  4891. if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
  4892. /* Hardware disappeared. It might have already raised
  4893. * an interrupt */
  4894. IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
  4895. goto unplugged;
  4896. }
  4897. D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
  4898. inta_fh);
  4899. inta &= ~CSR_INT_BIT_SCD;
  4900. /* il_irq_tasklet() will service interrupts and re-enable them */
  4901. if (likely(inta || inta_fh))
  4902. tasklet_schedule(&il->irq_tasklet);
  4903. unplugged:
  4904. spin_unlock_irqrestore(&il->lock, flags);
  4905. return IRQ_HANDLED;
  4906. none:
  4907. /* re-enable interrupts here since we don't have anything to service. */
  4908. /* only Re-enable if disabled by irq */
  4909. if (test_bit(S_INT_ENABLED, &il->status))
  4910. il_enable_interrupts(il);
  4911. spin_unlock_irqrestore(&il->lock, flags);
  4912. return IRQ_NONE;
  4913. }
  4914. EXPORT_SYMBOL(il_isr);
  4915. /*
  4916. * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
  4917. * function.
  4918. */
  4919. void
  4920. il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
  4921. __le16 fc, __le32 *tx_flags)
  4922. {
  4923. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  4924. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  4925. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  4926. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4927. if (!ieee80211_is_mgmt(fc))
  4928. return;
  4929. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  4930. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  4931. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  4932. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  4933. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  4934. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4935. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4936. break;
  4937. }
  4938. } else if (info->control.rates[0].
  4939. flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  4940. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  4941. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  4942. *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  4943. }
  4944. }
  4945. EXPORT_SYMBOL(il_tx_cmd_protection);