netxen_nic_init.c 47 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  19. * MA 02111-1307, USA.
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called "COPYING".
  23. *
  24. */
  25. #include <linux/netdevice.h>
  26. #include <linux/delay.h>
  27. #include <linux/slab.h>
  28. #include <linux/if_vlan.h>
  29. #include "netxen_nic.h"
  30. #include "netxen_nic_hw.h"
  31. struct crb_addr_pair {
  32. u32 addr;
  33. u32 data;
  34. };
  35. #define NETXEN_MAX_CRB_XFORM 60
  36. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  37. #define NETXEN_ADDR_ERROR (0xffffffff)
  38. #define crb_addr_transform(name) \
  39. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  40. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  41. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  42. static void
  43. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  44. struct nx_host_rds_ring *rds_ring);
  45. static int netxen_p3_has_mn(struct netxen_adapter *adapter);
  46. static void crb_addr_transform_setup(void)
  47. {
  48. crb_addr_transform(XDMA);
  49. crb_addr_transform(TIMR);
  50. crb_addr_transform(SRE);
  51. crb_addr_transform(SQN3);
  52. crb_addr_transform(SQN2);
  53. crb_addr_transform(SQN1);
  54. crb_addr_transform(SQN0);
  55. crb_addr_transform(SQS3);
  56. crb_addr_transform(SQS2);
  57. crb_addr_transform(SQS1);
  58. crb_addr_transform(SQS0);
  59. crb_addr_transform(RPMX7);
  60. crb_addr_transform(RPMX6);
  61. crb_addr_transform(RPMX5);
  62. crb_addr_transform(RPMX4);
  63. crb_addr_transform(RPMX3);
  64. crb_addr_transform(RPMX2);
  65. crb_addr_transform(RPMX1);
  66. crb_addr_transform(RPMX0);
  67. crb_addr_transform(ROMUSB);
  68. crb_addr_transform(SN);
  69. crb_addr_transform(QMN);
  70. crb_addr_transform(QMS);
  71. crb_addr_transform(PGNI);
  72. crb_addr_transform(PGND);
  73. crb_addr_transform(PGN3);
  74. crb_addr_transform(PGN2);
  75. crb_addr_transform(PGN1);
  76. crb_addr_transform(PGN0);
  77. crb_addr_transform(PGSI);
  78. crb_addr_transform(PGSD);
  79. crb_addr_transform(PGS3);
  80. crb_addr_transform(PGS2);
  81. crb_addr_transform(PGS1);
  82. crb_addr_transform(PGS0);
  83. crb_addr_transform(PS);
  84. crb_addr_transform(PH);
  85. crb_addr_transform(NIU);
  86. crb_addr_transform(I2Q);
  87. crb_addr_transform(EG);
  88. crb_addr_transform(MN);
  89. crb_addr_transform(MS);
  90. crb_addr_transform(CAS2);
  91. crb_addr_transform(CAS1);
  92. crb_addr_transform(CAS0);
  93. crb_addr_transform(CAM);
  94. crb_addr_transform(C2C1);
  95. crb_addr_transform(C2C0);
  96. crb_addr_transform(SMB);
  97. crb_addr_transform(OCM0);
  98. crb_addr_transform(I2C0);
  99. }
  100. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  101. {
  102. struct netxen_recv_context *recv_ctx;
  103. struct nx_host_rds_ring *rds_ring;
  104. struct netxen_rx_buffer *rx_buf;
  105. int i, ring;
  106. recv_ctx = &adapter->recv_ctx;
  107. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  108. rds_ring = &recv_ctx->rds_rings[ring];
  109. for (i = 0; i < rds_ring->num_desc; ++i) {
  110. rx_buf = &(rds_ring->rx_buf_arr[i]);
  111. if (rx_buf->state == NETXEN_BUFFER_FREE)
  112. continue;
  113. pci_unmap_single(adapter->pdev,
  114. rx_buf->dma,
  115. rds_ring->dma_size,
  116. PCI_DMA_FROMDEVICE);
  117. if (rx_buf->skb != NULL)
  118. dev_kfree_skb_any(rx_buf->skb);
  119. }
  120. }
  121. }
  122. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  123. {
  124. struct netxen_cmd_buffer *cmd_buf;
  125. struct netxen_skb_frag *buffrag;
  126. int i, j;
  127. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  128. cmd_buf = tx_ring->cmd_buf_arr;
  129. for (i = 0; i < tx_ring->num_desc; i++) {
  130. buffrag = cmd_buf->frag_array;
  131. if (buffrag->dma) {
  132. pci_unmap_single(adapter->pdev, buffrag->dma,
  133. buffrag->length, PCI_DMA_TODEVICE);
  134. buffrag->dma = 0ULL;
  135. }
  136. for (j = 0; j < cmd_buf->frag_count; j++) {
  137. buffrag++;
  138. if (buffrag->dma) {
  139. pci_unmap_page(adapter->pdev, buffrag->dma,
  140. buffrag->length,
  141. PCI_DMA_TODEVICE);
  142. buffrag->dma = 0ULL;
  143. }
  144. }
  145. if (cmd_buf->skb) {
  146. dev_kfree_skb_any(cmd_buf->skb);
  147. cmd_buf->skb = NULL;
  148. }
  149. cmd_buf++;
  150. }
  151. }
  152. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  153. {
  154. struct netxen_recv_context *recv_ctx;
  155. struct nx_host_rds_ring *rds_ring;
  156. struct nx_host_tx_ring *tx_ring;
  157. int ring;
  158. recv_ctx = &adapter->recv_ctx;
  159. if (recv_ctx->rds_rings == NULL)
  160. goto skip_rds;
  161. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  162. rds_ring = &recv_ctx->rds_rings[ring];
  163. vfree(rds_ring->rx_buf_arr);
  164. rds_ring->rx_buf_arr = NULL;
  165. }
  166. kfree(recv_ctx->rds_rings);
  167. skip_rds:
  168. if (adapter->tx_ring == NULL)
  169. return;
  170. tx_ring = adapter->tx_ring;
  171. vfree(tx_ring->cmd_buf_arr);
  172. kfree(tx_ring);
  173. adapter->tx_ring = NULL;
  174. }
  175. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  176. {
  177. struct netxen_recv_context *recv_ctx;
  178. struct nx_host_rds_ring *rds_ring;
  179. struct nx_host_sds_ring *sds_ring;
  180. struct nx_host_tx_ring *tx_ring;
  181. struct netxen_rx_buffer *rx_buf;
  182. int ring, i, size;
  183. struct netxen_cmd_buffer *cmd_buf_arr;
  184. struct net_device *netdev = adapter->netdev;
  185. struct pci_dev *pdev = adapter->pdev;
  186. size = sizeof(struct nx_host_tx_ring);
  187. tx_ring = kzalloc(size, GFP_KERNEL);
  188. if (tx_ring == NULL) {
  189. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  190. netdev->name);
  191. return -ENOMEM;
  192. }
  193. adapter->tx_ring = tx_ring;
  194. tx_ring->num_desc = adapter->num_txd;
  195. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  196. cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
  197. if (cmd_buf_arr == NULL) {
  198. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  199. netdev->name);
  200. goto err_out;
  201. }
  202. tx_ring->cmd_buf_arr = cmd_buf_arr;
  203. recv_ctx = &adapter->recv_ctx;
  204. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  205. rds_ring = kzalloc(size, GFP_KERNEL);
  206. if (rds_ring == NULL) {
  207. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  208. netdev->name);
  209. goto err_out;
  210. }
  211. recv_ctx->rds_rings = rds_ring;
  212. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  213. rds_ring = &recv_ctx->rds_rings[ring];
  214. switch (ring) {
  215. case RCV_RING_NORMAL:
  216. rds_ring->num_desc = adapter->num_rxd;
  217. if (adapter->ahw.cut_through) {
  218. rds_ring->dma_size =
  219. NX_CT_DEFAULT_RX_BUF_LEN;
  220. rds_ring->skb_size =
  221. NX_CT_DEFAULT_RX_BUF_LEN;
  222. } else {
  223. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  224. rds_ring->dma_size =
  225. NX_P3_RX_BUF_MAX_LEN;
  226. else
  227. rds_ring->dma_size =
  228. NX_P2_RX_BUF_MAX_LEN;
  229. rds_ring->skb_size =
  230. rds_ring->dma_size + NET_IP_ALIGN;
  231. }
  232. break;
  233. case RCV_RING_JUMBO:
  234. rds_ring->num_desc = adapter->num_jumbo_rxd;
  235. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  236. rds_ring->dma_size =
  237. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  238. else
  239. rds_ring->dma_size =
  240. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  241. if (adapter->capabilities & NX_CAP0_HW_LRO)
  242. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  243. rds_ring->skb_size =
  244. rds_ring->dma_size + NET_IP_ALIGN;
  245. break;
  246. case RCV_RING_LRO:
  247. rds_ring->num_desc = adapter->num_lro_rxd;
  248. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  249. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  250. break;
  251. }
  252. rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
  253. if (rds_ring->rx_buf_arr == NULL) {
  254. printk(KERN_ERR "%s: Failed to allocate "
  255. "rx buffer ring %d\n",
  256. netdev->name, ring);
  257. /* free whatever was already allocated */
  258. goto err_out;
  259. }
  260. INIT_LIST_HEAD(&rds_ring->free_list);
  261. /*
  262. * Now go through all of them, set reference handles
  263. * and put them in the queues.
  264. */
  265. rx_buf = rds_ring->rx_buf_arr;
  266. for (i = 0; i < rds_ring->num_desc; i++) {
  267. list_add_tail(&rx_buf->list,
  268. &rds_ring->free_list);
  269. rx_buf->ref_handle = i;
  270. rx_buf->state = NETXEN_BUFFER_FREE;
  271. rx_buf++;
  272. }
  273. spin_lock_init(&rds_ring->lock);
  274. }
  275. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  276. sds_ring = &recv_ctx->sds_rings[ring];
  277. sds_ring->irq = adapter->msix_entries[ring].vector;
  278. sds_ring->adapter = adapter;
  279. sds_ring->num_desc = adapter->num_rxd;
  280. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  281. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  282. }
  283. return 0;
  284. err_out:
  285. netxen_free_sw_resources(adapter);
  286. return -ENOMEM;
  287. }
  288. /*
  289. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  290. * address to external PCI CRB address.
  291. */
  292. static u32 netxen_decode_crb_addr(u32 addr)
  293. {
  294. int i;
  295. u32 base_addr, offset, pci_base;
  296. crb_addr_transform_setup();
  297. pci_base = NETXEN_ADDR_ERROR;
  298. base_addr = addr & 0xfff00000;
  299. offset = addr & 0x000fffff;
  300. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  301. if (crb_addr_xform[i] == base_addr) {
  302. pci_base = i << 20;
  303. break;
  304. }
  305. }
  306. if (pci_base == NETXEN_ADDR_ERROR)
  307. return pci_base;
  308. else
  309. return pci_base + offset;
  310. }
  311. #define NETXEN_MAX_ROM_WAIT_USEC 100
  312. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  313. {
  314. long timeout = 0;
  315. long done = 0;
  316. cond_resched();
  317. while (done == 0) {
  318. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  319. done &= 2;
  320. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  321. dev_err(&adapter->pdev->dev,
  322. "Timeout reached waiting for rom done");
  323. return -EIO;
  324. }
  325. udelay(1);
  326. }
  327. return 0;
  328. }
  329. static int do_rom_fast_read(struct netxen_adapter *adapter,
  330. int addr, int *valp)
  331. {
  332. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  333. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  334. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  335. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  336. if (netxen_wait_rom_done(adapter)) {
  337. printk("Error waiting for rom done\n");
  338. return -EIO;
  339. }
  340. /* reset abyte_cnt and dummy_byte_cnt */
  341. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  342. udelay(10);
  343. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  344. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  345. return 0;
  346. }
  347. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  348. u8 *bytes, size_t size)
  349. {
  350. int addridx;
  351. int ret = 0;
  352. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  353. int v;
  354. ret = do_rom_fast_read(adapter, addridx, &v);
  355. if (ret != 0)
  356. break;
  357. *(__le32 *)bytes = cpu_to_le32(v);
  358. bytes += 4;
  359. }
  360. return ret;
  361. }
  362. int
  363. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  364. u8 *bytes, size_t size)
  365. {
  366. int ret;
  367. ret = netxen_rom_lock(adapter);
  368. if (ret < 0)
  369. return ret;
  370. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  371. netxen_rom_unlock(adapter);
  372. return ret;
  373. }
  374. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  375. {
  376. int ret;
  377. if (netxen_rom_lock(adapter) != 0)
  378. return -EIO;
  379. ret = do_rom_fast_read(adapter, addr, valp);
  380. netxen_rom_unlock(adapter);
  381. return ret;
  382. }
  383. #define NETXEN_BOARDTYPE 0x4008
  384. #define NETXEN_BOARDNUM 0x400c
  385. #define NETXEN_CHIPNUM 0x4010
  386. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  387. {
  388. int addr, val;
  389. int i, n, init_delay = 0;
  390. struct crb_addr_pair *buf;
  391. unsigned offset;
  392. u32 off;
  393. /* resetall */
  394. netxen_rom_lock(adapter);
  395. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  396. netxen_rom_unlock(adapter);
  397. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  398. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  399. (n != 0xcafecafe) ||
  400. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  401. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  402. "n: %08x\n", netxen_nic_driver_name, n);
  403. return -EIO;
  404. }
  405. offset = n & 0xffffU;
  406. n = (n >> 16) & 0xffffU;
  407. } else {
  408. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  409. !(n & 0x80000000)) {
  410. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  411. "n: %08x\n", netxen_nic_driver_name, n);
  412. return -EIO;
  413. }
  414. offset = 1;
  415. n &= ~0x80000000;
  416. }
  417. if (n >= 1024) {
  418. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  419. " initialized.\n", __func__, n);
  420. return -EIO;
  421. }
  422. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  423. if (buf == NULL) {
  424. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  425. netxen_nic_driver_name);
  426. return -ENOMEM;
  427. }
  428. for (i = 0; i < n; i++) {
  429. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  430. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  431. kfree(buf);
  432. return -EIO;
  433. }
  434. buf[i].addr = addr;
  435. buf[i].data = val;
  436. }
  437. for (i = 0; i < n; i++) {
  438. off = netxen_decode_crb_addr(buf[i].addr);
  439. if (off == NETXEN_ADDR_ERROR) {
  440. printk(KERN_ERR"CRB init value out of range %x\n",
  441. buf[i].addr);
  442. continue;
  443. }
  444. off += NETXEN_PCI_CRBSPACE;
  445. if (off & 1)
  446. continue;
  447. /* skipping cold reboot MAGIC */
  448. if (off == NETXEN_CAM_RAM(0x1fc))
  449. continue;
  450. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  451. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  452. continue;
  453. /* do not reset PCI */
  454. if (off == (ROMUSB_GLB + 0xbc))
  455. continue;
  456. if (off == (ROMUSB_GLB + 0xa8))
  457. continue;
  458. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  459. continue;
  460. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  461. continue;
  462. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  463. continue;
  464. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  465. continue;
  466. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  467. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  468. buf[i].data = 0x1020;
  469. /* skip the function enable register */
  470. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  471. continue;
  472. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  473. continue;
  474. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  475. continue;
  476. }
  477. init_delay = 1;
  478. /* After writing this register, HW needs time for CRB */
  479. /* to quiet down (else crb_window returns 0xffffffff) */
  480. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  481. init_delay = 1000;
  482. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  483. /* hold xdma in reset also */
  484. buf[i].data = NETXEN_NIC_XDMA_RESET;
  485. buf[i].data = 0x8000ff;
  486. }
  487. }
  488. NXWR32(adapter, off, buf[i].data);
  489. msleep(init_delay);
  490. }
  491. kfree(buf);
  492. /* disable_peg_cache_all */
  493. /* unreset_net_cache */
  494. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  495. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  496. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  497. }
  498. /* p2dn replyCount */
  499. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  500. /* disable_peg_cache 0 */
  501. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  502. /* disable_peg_cache 1 */
  503. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  504. /* peg_clr_all */
  505. /* peg_clr 0 */
  506. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  507. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  508. /* peg_clr 1 */
  509. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  510. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  511. /* peg_clr 2 */
  512. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  513. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  514. /* peg_clr 3 */
  515. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  516. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  517. return 0;
  518. }
  519. static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
  520. {
  521. uint32_t i;
  522. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  523. __le32 entries = cpu_to_le32(directory->num_entries);
  524. for (i = 0; i < entries; i++) {
  525. __le32 offs = cpu_to_le32(directory->findex) +
  526. (i * cpu_to_le32(directory->entry_size));
  527. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  528. if (tab_type == section)
  529. return (struct uni_table_desc *) &unirom[offs];
  530. }
  531. return NULL;
  532. }
  533. #define QLCNIC_FILEHEADER_SIZE (14 * 4)
  534. static int
  535. netxen_nic_validate_header(struct netxen_adapter *adapter)
  536. {
  537. const u8 *unirom = adapter->fw->data;
  538. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  539. u32 fw_file_size = adapter->fw->size;
  540. u32 tab_size;
  541. __le32 entries;
  542. __le32 entry_size;
  543. if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
  544. return -EINVAL;
  545. entries = cpu_to_le32(directory->num_entries);
  546. entry_size = cpu_to_le32(directory->entry_size);
  547. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  548. if (fw_file_size < tab_size)
  549. return -EINVAL;
  550. return 0;
  551. }
  552. static int
  553. netxen_nic_validate_bootld(struct netxen_adapter *adapter)
  554. {
  555. struct uni_table_desc *tab_desc;
  556. struct uni_data_desc *descr;
  557. const u8 *unirom = adapter->fw->data;
  558. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  559. NX_UNI_BOOTLD_IDX_OFF));
  560. u32 offs;
  561. u32 tab_size;
  562. u32 data_size;
  563. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
  564. if (!tab_desc)
  565. return -EINVAL;
  566. tab_size = cpu_to_le32(tab_desc->findex) +
  567. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  568. if (adapter->fw->size < tab_size)
  569. return -EINVAL;
  570. offs = cpu_to_le32(tab_desc->findex) +
  571. (cpu_to_le32(tab_desc->entry_size) * (idx));
  572. descr = (struct uni_data_desc *)&unirom[offs];
  573. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  574. if (adapter->fw->size < data_size)
  575. return -EINVAL;
  576. return 0;
  577. }
  578. static int
  579. netxen_nic_validate_fw(struct netxen_adapter *adapter)
  580. {
  581. struct uni_table_desc *tab_desc;
  582. struct uni_data_desc *descr;
  583. const u8 *unirom = adapter->fw->data;
  584. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  585. NX_UNI_FIRMWARE_IDX_OFF));
  586. u32 offs;
  587. u32 tab_size;
  588. u32 data_size;
  589. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
  590. if (!tab_desc)
  591. return -EINVAL;
  592. tab_size = cpu_to_le32(tab_desc->findex) +
  593. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  594. if (adapter->fw->size < tab_size)
  595. return -EINVAL;
  596. offs = cpu_to_le32(tab_desc->findex) +
  597. (cpu_to_le32(tab_desc->entry_size) * (idx));
  598. descr = (struct uni_data_desc *)&unirom[offs];
  599. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  600. if (adapter->fw->size < data_size)
  601. return -EINVAL;
  602. return 0;
  603. }
  604. static int
  605. netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
  606. {
  607. struct uni_table_desc *ptab_descr;
  608. const u8 *unirom = adapter->fw->data;
  609. int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
  610. 1 : netxen_p3_has_mn(adapter);
  611. __le32 entries;
  612. __le32 entry_size;
  613. u32 tab_size;
  614. u32 i;
  615. ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
  616. if (ptab_descr == NULL)
  617. return -EINVAL;
  618. entries = cpu_to_le32(ptab_descr->num_entries);
  619. entry_size = cpu_to_le32(ptab_descr->entry_size);
  620. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  621. if (adapter->fw->size < tab_size)
  622. return -EINVAL;
  623. nomn:
  624. for (i = 0; i < entries; i++) {
  625. __le32 flags, file_chiprev, offs;
  626. u8 chiprev = adapter->ahw.revision_id;
  627. uint32_t flagbit;
  628. offs = cpu_to_le32(ptab_descr->findex) +
  629. (i * cpu_to_le32(ptab_descr->entry_size));
  630. flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
  631. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  632. NX_UNI_CHIP_REV_OFF));
  633. flagbit = mn_present ? 1 : 2;
  634. if ((chiprev == file_chiprev) &&
  635. ((1ULL << flagbit) & flags)) {
  636. adapter->file_prd_off = offs;
  637. return 0;
  638. }
  639. }
  640. if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  641. mn_present = 0;
  642. goto nomn;
  643. }
  644. return -EINVAL;
  645. }
  646. static int
  647. netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
  648. {
  649. if (netxen_nic_validate_header(adapter)) {
  650. dev_err(&adapter->pdev->dev,
  651. "unified image: header validation failed\n");
  652. return -EINVAL;
  653. }
  654. if (netxen_nic_validate_product_offs(adapter)) {
  655. dev_err(&adapter->pdev->dev,
  656. "unified image: product validation failed\n");
  657. return -EINVAL;
  658. }
  659. if (netxen_nic_validate_bootld(adapter)) {
  660. dev_err(&adapter->pdev->dev,
  661. "unified image: bootld validation failed\n");
  662. return -EINVAL;
  663. }
  664. if (netxen_nic_validate_fw(adapter)) {
  665. dev_err(&adapter->pdev->dev,
  666. "unified image: firmware validation failed\n");
  667. return -EINVAL;
  668. }
  669. return 0;
  670. }
  671. static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
  672. u32 section, u32 idx_offset)
  673. {
  674. const u8 *unirom = adapter->fw->data;
  675. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  676. idx_offset));
  677. struct uni_table_desc *tab_desc;
  678. __le32 offs;
  679. tab_desc = nx_get_table_desc(unirom, section);
  680. if (tab_desc == NULL)
  681. return NULL;
  682. offs = cpu_to_le32(tab_desc->findex) +
  683. (cpu_to_le32(tab_desc->entry_size) * idx);
  684. return (struct uni_data_desc *)&unirom[offs];
  685. }
  686. static u8 *
  687. nx_get_bootld_offs(struct netxen_adapter *adapter)
  688. {
  689. u32 offs = NETXEN_BOOTLD_START;
  690. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  691. offs = cpu_to_le32((nx_get_data_desc(adapter,
  692. NX_UNI_DIR_SECT_BOOTLD,
  693. NX_UNI_BOOTLD_IDX_OFF))->findex);
  694. return (u8 *)&adapter->fw->data[offs];
  695. }
  696. static u8 *
  697. nx_get_fw_offs(struct netxen_adapter *adapter)
  698. {
  699. u32 offs = NETXEN_IMAGE_START;
  700. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  701. offs = cpu_to_le32((nx_get_data_desc(adapter,
  702. NX_UNI_DIR_SECT_FW,
  703. NX_UNI_FIRMWARE_IDX_OFF))->findex);
  704. return (u8 *)&adapter->fw->data[offs];
  705. }
  706. static __le32
  707. nx_get_fw_size(struct netxen_adapter *adapter)
  708. {
  709. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  710. return cpu_to_le32((nx_get_data_desc(adapter,
  711. NX_UNI_DIR_SECT_FW,
  712. NX_UNI_FIRMWARE_IDX_OFF))->size);
  713. else
  714. return cpu_to_le32(
  715. *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
  716. }
  717. static __le32
  718. nx_get_fw_version(struct netxen_adapter *adapter)
  719. {
  720. struct uni_data_desc *fw_data_desc;
  721. const struct firmware *fw = adapter->fw;
  722. __le32 major, minor, sub;
  723. const u8 *ver_str;
  724. int i, ret = 0;
  725. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  726. fw_data_desc = nx_get_data_desc(adapter,
  727. NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
  728. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  729. cpu_to_le32(fw_data_desc->size) - 17;
  730. for (i = 0; i < 12; i++) {
  731. if (!strncmp(&ver_str[i], "REV=", 4)) {
  732. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  733. &major, &minor, &sub);
  734. break;
  735. }
  736. }
  737. if (ret != 3)
  738. return 0;
  739. return major + (minor << 8) + (sub << 16);
  740. } else
  741. return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  742. }
  743. static __le32
  744. nx_get_bios_version(struct netxen_adapter *adapter)
  745. {
  746. const struct firmware *fw = adapter->fw;
  747. __le32 bios_ver, prd_off = adapter->file_prd_off;
  748. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  749. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  750. + NX_UNI_BIOS_VERSION_OFF));
  751. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
  752. (bios_ver >> 24);
  753. } else
  754. return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  755. }
  756. int
  757. netxen_need_fw_reset(struct netxen_adapter *adapter)
  758. {
  759. u32 count, old_count;
  760. u32 val, version, major, minor, build;
  761. int i, timeout;
  762. u8 fw_type;
  763. /* NX2031 firmware doesn't support heartbit */
  764. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  765. return 1;
  766. if (adapter->need_fw_reset)
  767. return 1;
  768. /* last attempt had failed */
  769. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  770. return 1;
  771. old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  772. for (i = 0; i < 10; i++) {
  773. timeout = msleep_interruptible(200);
  774. if (timeout) {
  775. NXWR32(adapter, CRB_CMDPEG_STATE,
  776. PHAN_INITIALIZE_FAILED);
  777. return -EINTR;
  778. }
  779. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  780. if (count != old_count)
  781. break;
  782. }
  783. /* firmware is dead */
  784. if (count == old_count)
  785. return 1;
  786. /* check if we have got newer or different file firmware */
  787. if (adapter->fw) {
  788. val = nx_get_fw_version(adapter);
  789. version = NETXEN_DECODE_VERSION(val);
  790. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  791. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  792. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  793. if (version > NETXEN_VERSION_CODE(major, minor, build))
  794. return 1;
  795. if (version == NETXEN_VERSION_CODE(major, minor, build) &&
  796. adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
  797. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  798. fw_type = (val & 0x4) ?
  799. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  800. if (adapter->fw_type != fw_type)
  801. return 1;
  802. }
  803. }
  804. return 0;
  805. }
  806. #define NETXEN_MIN_P3_FW_SUPP NETXEN_VERSION_CODE(4, 0, 505)
  807. int
  808. netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter)
  809. {
  810. u32 flash_fw_ver, min_fw_ver;
  811. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  812. return 0;
  813. if (netxen_rom_fast_read(adapter,
  814. NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
  815. dev_err(&adapter->pdev->dev, "Unable to read flash fw"
  816. "version\n");
  817. return -EIO;
  818. }
  819. flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
  820. min_fw_ver = NETXEN_MIN_P3_FW_SUPP;
  821. if (flash_fw_ver >= min_fw_ver)
  822. return 0;
  823. dev_info(&adapter->pdev->dev, "Flash fw[%d.%d.%d] is < min fw supported"
  824. "[4.0.505]. Please update firmware on flash\n",
  825. _major(flash_fw_ver), _minor(flash_fw_ver),
  826. _build(flash_fw_ver));
  827. return -EINVAL;
  828. }
  829. static char *fw_name[] = {
  830. NX_P2_MN_ROMIMAGE_NAME,
  831. NX_P3_CT_ROMIMAGE_NAME,
  832. NX_P3_MN_ROMIMAGE_NAME,
  833. NX_UNIFIED_ROMIMAGE_NAME,
  834. NX_FLASH_ROMIMAGE_NAME,
  835. };
  836. int
  837. netxen_load_firmware(struct netxen_adapter *adapter)
  838. {
  839. u64 *ptr64;
  840. u32 i, flashaddr, size;
  841. const struct firmware *fw = adapter->fw;
  842. struct pci_dev *pdev = adapter->pdev;
  843. dev_info(&pdev->dev, "loading firmware from %s\n",
  844. fw_name[adapter->fw_type]);
  845. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  846. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  847. if (fw) {
  848. __le64 data;
  849. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  850. ptr64 = (u64 *)nx_get_bootld_offs(adapter);
  851. flashaddr = NETXEN_BOOTLD_START;
  852. for (i = 0; i < size; i++) {
  853. data = cpu_to_le64(ptr64[i]);
  854. if (adapter->pci_mem_write(adapter, flashaddr, data))
  855. return -EIO;
  856. flashaddr += 8;
  857. }
  858. size = (__force u32)nx_get_fw_size(adapter) / 8;
  859. ptr64 = (u64 *)nx_get_fw_offs(adapter);
  860. flashaddr = NETXEN_IMAGE_START;
  861. for (i = 0; i < size; i++) {
  862. data = cpu_to_le64(ptr64[i]);
  863. if (adapter->pci_mem_write(adapter,
  864. flashaddr, data))
  865. return -EIO;
  866. flashaddr += 8;
  867. }
  868. size = (__force u32)nx_get_fw_size(adapter) % 8;
  869. if (size) {
  870. data = cpu_to_le64(ptr64[i]);
  871. if (adapter->pci_mem_write(adapter,
  872. flashaddr, data))
  873. return -EIO;
  874. }
  875. } else {
  876. u64 data;
  877. u32 hi, lo;
  878. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  879. flashaddr = NETXEN_BOOTLD_START;
  880. for (i = 0; i < size; i++) {
  881. if (netxen_rom_fast_read(adapter,
  882. flashaddr, (int *)&lo) != 0)
  883. return -EIO;
  884. if (netxen_rom_fast_read(adapter,
  885. flashaddr + 4, (int *)&hi) != 0)
  886. return -EIO;
  887. /* hi, lo are already in host endian byteorder */
  888. data = (((u64)hi << 32) | lo);
  889. if (adapter->pci_mem_write(adapter,
  890. flashaddr, data))
  891. return -EIO;
  892. flashaddr += 8;
  893. }
  894. }
  895. msleep(1);
  896. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  897. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  898. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  899. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  900. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  901. else {
  902. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  903. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  904. }
  905. return 0;
  906. }
  907. static int
  908. netxen_validate_firmware(struct netxen_adapter *adapter)
  909. {
  910. __le32 val;
  911. __le32 flash_fw_ver;
  912. u32 file_fw_ver, min_ver, bios;
  913. struct pci_dev *pdev = adapter->pdev;
  914. const struct firmware *fw = adapter->fw;
  915. u8 fw_type = adapter->fw_type;
  916. u32 crbinit_fix_fw;
  917. if (fw_type == NX_UNIFIED_ROMIMAGE) {
  918. if (netxen_nic_validate_unified_romimage(adapter))
  919. return -EINVAL;
  920. } else {
  921. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  922. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  923. return -EINVAL;
  924. if (fw->size < NX_FW_MIN_SIZE)
  925. return -EINVAL;
  926. }
  927. val = nx_get_fw_version(adapter);
  928. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  929. min_ver = NETXEN_MIN_P3_FW_SUPP;
  930. else
  931. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  932. file_fw_ver = NETXEN_DECODE_VERSION(val);
  933. if ((_major(file_fw_ver) > _NETXEN_NIC_LINUX_MAJOR) ||
  934. (file_fw_ver < min_ver)) {
  935. dev_err(&pdev->dev,
  936. "%s: firmware version %d.%d.%d unsupported\n",
  937. fw_name[fw_type], _major(file_fw_ver), _minor(file_fw_ver),
  938. _build(file_fw_ver));
  939. return -EINVAL;
  940. }
  941. val = nx_get_bios_version(adapter);
  942. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  943. if ((__force u32)val != bios) {
  944. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  945. fw_name[fw_type]);
  946. return -EINVAL;
  947. }
  948. if (netxen_rom_fast_read(adapter,
  949. NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
  950. dev_err(&pdev->dev, "Unable to read flash fw version\n");
  951. return -EIO;
  952. }
  953. flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
  954. /* New fw from file is not allowed, if fw on flash is < 4.0.554 */
  955. crbinit_fix_fw = NETXEN_VERSION_CODE(4, 0, 554);
  956. if (file_fw_ver >= crbinit_fix_fw && flash_fw_ver < crbinit_fix_fw &&
  957. NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  958. dev_err(&pdev->dev, "Incompatibility detected between driver "
  959. "and firmware version on flash. This configuration "
  960. "is not recommended. Please update the firmware on "
  961. "flash immediately\n");
  962. return -EINVAL;
  963. }
  964. /* check if flashed firmware is newer only for no-mn and P2 case*/
  965. if (!netxen_p3_has_mn(adapter) ||
  966. NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  967. if (flash_fw_ver > file_fw_ver) {
  968. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  969. fw_name[fw_type]);
  970. return -EINVAL;
  971. }
  972. }
  973. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  974. return 0;
  975. }
  976. static void
  977. nx_get_next_fwtype(struct netxen_adapter *adapter)
  978. {
  979. u8 fw_type;
  980. switch (adapter->fw_type) {
  981. case NX_UNKNOWN_ROMIMAGE:
  982. fw_type = NX_UNIFIED_ROMIMAGE;
  983. break;
  984. case NX_UNIFIED_ROMIMAGE:
  985. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  986. fw_type = NX_FLASH_ROMIMAGE;
  987. else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  988. fw_type = NX_P2_MN_ROMIMAGE;
  989. else if (netxen_p3_has_mn(adapter))
  990. fw_type = NX_P3_MN_ROMIMAGE;
  991. else
  992. fw_type = NX_P3_CT_ROMIMAGE;
  993. break;
  994. case NX_P3_MN_ROMIMAGE:
  995. fw_type = NX_P3_CT_ROMIMAGE;
  996. break;
  997. case NX_P2_MN_ROMIMAGE:
  998. case NX_P3_CT_ROMIMAGE:
  999. default:
  1000. fw_type = NX_FLASH_ROMIMAGE;
  1001. break;
  1002. }
  1003. adapter->fw_type = fw_type;
  1004. }
  1005. static int
  1006. netxen_p3_has_mn(struct netxen_adapter *adapter)
  1007. {
  1008. u32 capability, flashed_ver;
  1009. capability = 0;
  1010. /* NX2031 always had MN */
  1011. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1012. return 1;
  1013. netxen_rom_fast_read(adapter,
  1014. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  1015. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  1016. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  1017. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  1018. if (capability & NX_PEG_TUNE_MN_PRESENT)
  1019. return 1;
  1020. }
  1021. return 0;
  1022. }
  1023. void netxen_request_firmware(struct netxen_adapter *adapter)
  1024. {
  1025. struct pci_dev *pdev = adapter->pdev;
  1026. int rc = 0;
  1027. adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
  1028. next:
  1029. nx_get_next_fwtype(adapter);
  1030. if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
  1031. adapter->fw = NULL;
  1032. } else {
  1033. rc = request_firmware(&adapter->fw,
  1034. fw_name[adapter->fw_type], &pdev->dev);
  1035. if (rc != 0)
  1036. goto next;
  1037. rc = netxen_validate_firmware(adapter);
  1038. if (rc != 0) {
  1039. release_firmware(adapter->fw);
  1040. msleep(1);
  1041. goto next;
  1042. }
  1043. }
  1044. }
  1045. void
  1046. netxen_release_firmware(struct netxen_adapter *adapter)
  1047. {
  1048. if (adapter->fw)
  1049. release_firmware(adapter->fw);
  1050. adapter->fw = NULL;
  1051. }
  1052. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  1053. {
  1054. u64 addr;
  1055. u32 hi, lo;
  1056. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1057. return 0;
  1058. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  1059. NETXEN_HOST_DUMMY_DMA_SIZE,
  1060. &adapter->dummy_dma.phys_addr);
  1061. if (adapter->dummy_dma.addr == NULL) {
  1062. dev_err(&adapter->pdev->dev,
  1063. "ERROR: Could not allocate dummy DMA memory\n");
  1064. return -ENOMEM;
  1065. }
  1066. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  1067. hi = (addr >> 32) & 0xffffffff;
  1068. lo = addr & 0xffffffff;
  1069. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  1070. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  1071. return 0;
  1072. }
  1073. /*
  1074. * NetXen DMA watchdog control:
  1075. *
  1076. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1077. * Bit 1 : disable_request => 1 req disable dma watchdog
  1078. * Bit 2 : enable_request => 1 req enable dma watchdog
  1079. * Bit 3-31 : unused
  1080. */
  1081. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  1082. {
  1083. int i = 100;
  1084. u32 ctrl;
  1085. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1086. return;
  1087. if (!adapter->dummy_dma.addr)
  1088. return;
  1089. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1090. if ((ctrl & 0x1) != 0) {
  1091. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  1092. while ((ctrl & 0x1) != 0) {
  1093. msleep(50);
  1094. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1095. if (--i == 0)
  1096. break;
  1097. }
  1098. }
  1099. if (i) {
  1100. pci_free_consistent(adapter->pdev,
  1101. NETXEN_HOST_DUMMY_DMA_SIZE,
  1102. adapter->dummy_dma.addr,
  1103. adapter->dummy_dma.phys_addr);
  1104. adapter->dummy_dma.addr = NULL;
  1105. } else
  1106. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  1107. }
  1108. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  1109. {
  1110. u32 val = 0;
  1111. int retries = 60;
  1112. if (pegtune_val)
  1113. return 0;
  1114. do {
  1115. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  1116. switch (val) {
  1117. case PHAN_INITIALIZE_COMPLETE:
  1118. case PHAN_INITIALIZE_ACK:
  1119. return 0;
  1120. case PHAN_INITIALIZE_FAILED:
  1121. goto out_err;
  1122. default:
  1123. break;
  1124. }
  1125. msleep(500);
  1126. } while (--retries);
  1127. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  1128. out_err:
  1129. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  1130. return -EIO;
  1131. }
  1132. static int
  1133. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  1134. {
  1135. u32 val = 0;
  1136. int retries = 2000;
  1137. do {
  1138. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  1139. if (val == PHAN_PEG_RCV_INITIALIZED)
  1140. return 0;
  1141. msleep(10);
  1142. } while (--retries);
  1143. if (!retries) {
  1144. printk(KERN_ERR "Receive Peg initialization not "
  1145. "complete, state: 0x%x.\n", val);
  1146. return -EIO;
  1147. }
  1148. return 0;
  1149. }
  1150. int netxen_init_firmware(struct netxen_adapter *adapter)
  1151. {
  1152. int err;
  1153. err = netxen_receive_peg_ready(adapter);
  1154. if (err)
  1155. return err;
  1156. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  1157. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  1158. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1159. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1160. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  1161. return err;
  1162. }
  1163. static void
  1164. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  1165. {
  1166. u32 cable_OUI;
  1167. u16 cable_len;
  1168. u16 link_speed;
  1169. u8 link_status, module, duplex, autoneg;
  1170. struct net_device *netdev = adapter->netdev;
  1171. adapter->has_link_events = 1;
  1172. cable_OUI = msg->body[1] & 0xffffffff;
  1173. cable_len = (msg->body[1] >> 32) & 0xffff;
  1174. link_speed = (msg->body[1] >> 48) & 0xffff;
  1175. link_status = msg->body[2] & 0xff;
  1176. duplex = (msg->body[2] >> 16) & 0xff;
  1177. autoneg = (msg->body[2] >> 24) & 0xff;
  1178. module = (msg->body[2] >> 8) & 0xff;
  1179. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  1180. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  1181. netdev->name, cable_OUI, cable_len);
  1182. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  1183. printk(KERN_INFO "%s: unsupported cable length %d\n",
  1184. netdev->name, cable_len);
  1185. }
  1186. netxen_advert_link_change(adapter, link_status);
  1187. /* update link parameters */
  1188. if (duplex == LINKEVENT_FULL_DUPLEX)
  1189. adapter->link_duplex = DUPLEX_FULL;
  1190. else
  1191. adapter->link_duplex = DUPLEX_HALF;
  1192. adapter->module_type = module;
  1193. adapter->link_autoneg = autoneg;
  1194. adapter->link_speed = link_speed;
  1195. }
  1196. static void
  1197. netxen_handle_fw_message(int desc_cnt, int index,
  1198. struct nx_host_sds_ring *sds_ring)
  1199. {
  1200. nx_fw_msg_t msg;
  1201. struct status_desc *desc;
  1202. int i = 0, opcode;
  1203. while (desc_cnt > 0 && i < 8) {
  1204. desc = &sds_ring->desc_head[index];
  1205. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1206. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1207. index = get_next_index(index, sds_ring->num_desc);
  1208. desc_cnt--;
  1209. }
  1210. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  1211. switch (opcode) {
  1212. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1213. netxen_handle_linkevent(sds_ring->adapter, &msg);
  1214. break;
  1215. default:
  1216. break;
  1217. }
  1218. }
  1219. static int
  1220. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  1221. struct nx_host_rds_ring *rds_ring,
  1222. struct netxen_rx_buffer *buffer)
  1223. {
  1224. struct sk_buff *skb;
  1225. dma_addr_t dma;
  1226. struct pci_dev *pdev = adapter->pdev;
  1227. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  1228. if (!buffer->skb)
  1229. return 1;
  1230. skb = buffer->skb;
  1231. if (!adapter->ahw.cut_through)
  1232. skb_reserve(skb, 2);
  1233. dma = pci_map_single(pdev, skb->data,
  1234. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1235. if (pci_dma_mapping_error(pdev, dma)) {
  1236. dev_kfree_skb_any(skb);
  1237. buffer->skb = NULL;
  1238. return 1;
  1239. }
  1240. buffer->skb = skb;
  1241. buffer->dma = dma;
  1242. buffer->state = NETXEN_BUFFER_BUSY;
  1243. return 0;
  1244. }
  1245. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1246. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1247. {
  1248. struct netxen_rx_buffer *buffer;
  1249. struct sk_buff *skb;
  1250. buffer = &rds_ring->rx_buf_arr[index];
  1251. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1252. PCI_DMA_FROMDEVICE);
  1253. skb = buffer->skb;
  1254. if (!skb)
  1255. goto no_skb;
  1256. if (likely((adapter->netdev->features & NETIF_F_RXCSUM)
  1257. && cksum == STATUS_CKSUM_OK)) {
  1258. adapter->stats.csummed++;
  1259. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1260. } else
  1261. skb->ip_summed = CHECKSUM_NONE;
  1262. skb->dev = adapter->netdev;
  1263. buffer->skb = NULL;
  1264. no_skb:
  1265. buffer->state = NETXEN_BUFFER_FREE;
  1266. return skb;
  1267. }
  1268. static struct netxen_rx_buffer *
  1269. netxen_process_rcv(struct netxen_adapter *adapter,
  1270. struct nx_host_sds_ring *sds_ring,
  1271. int ring, u64 sts_data0)
  1272. {
  1273. struct net_device *netdev = adapter->netdev;
  1274. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1275. struct netxen_rx_buffer *buffer;
  1276. struct sk_buff *skb;
  1277. struct nx_host_rds_ring *rds_ring;
  1278. int index, length, cksum, pkt_offset;
  1279. if (unlikely(ring >= adapter->max_rds_rings))
  1280. return NULL;
  1281. rds_ring = &recv_ctx->rds_rings[ring];
  1282. index = netxen_get_sts_refhandle(sts_data0);
  1283. if (unlikely(index >= rds_ring->num_desc))
  1284. return NULL;
  1285. buffer = &rds_ring->rx_buf_arr[index];
  1286. length = netxen_get_sts_totallength(sts_data0);
  1287. cksum = netxen_get_sts_status(sts_data0);
  1288. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1289. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1290. if (!skb)
  1291. return buffer;
  1292. if (length > rds_ring->skb_size)
  1293. skb_put(skb, rds_ring->skb_size);
  1294. else
  1295. skb_put(skb, length);
  1296. if (pkt_offset)
  1297. skb_pull(skb, pkt_offset);
  1298. skb->protocol = eth_type_trans(skb, netdev);
  1299. napi_gro_receive(&sds_ring->napi, skb);
  1300. adapter->stats.rx_pkts++;
  1301. adapter->stats.rxbytes += length;
  1302. return buffer;
  1303. }
  1304. #define TCP_HDR_SIZE 20
  1305. #define TCP_TS_OPTION_SIZE 12
  1306. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1307. static struct netxen_rx_buffer *
  1308. netxen_process_lro(struct netxen_adapter *adapter,
  1309. struct nx_host_sds_ring *sds_ring,
  1310. int ring, u64 sts_data0, u64 sts_data1)
  1311. {
  1312. struct net_device *netdev = adapter->netdev;
  1313. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1314. struct netxen_rx_buffer *buffer;
  1315. struct sk_buff *skb;
  1316. struct nx_host_rds_ring *rds_ring;
  1317. struct iphdr *iph;
  1318. struct tcphdr *th;
  1319. bool push, timestamp;
  1320. int l2_hdr_offset, l4_hdr_offset;
  1321. int index;
  1322. u16 lro_length, length, data_offset;
  1323. u32 seq_number;
  1324. u8 vhdr_len = 0;
  1325. if (unlikely(ring > adapter->max_rds_rings))
  1326. return NULL;
  1327. rds_ring = &recv_ctx->rds_rings[ring];
  1328. index = netxen_get_lro_sts_refhandle(sts_data0);
  1329. if (unlikely(index > rds_ring->num_desc))
  1330. return NULL;
  1331. buffer = &rds_ring->rx_buf_arr[index];
  1332. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1333. lro_length = netxen_get_lro_sts_length(sts_data0);
  1334. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1335. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1336. push = netxen_get_lro_sts_push_flag(sts_data0);
  1337. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1338. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1339. if (!skb)
  1340. return buffer;
  1341. if (timestamp)
  1342. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1343. else
  1344. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1345. skb_put(skb, lro_length + data_offset);
  1346. skb_pull(skb, l2_hdr_offset);
  1347. skb->protocol = eth_type_trans(skb, netdev);
  1348. if (skb->protocol == htons(ETH_P_8021Q))
  1349. vhdr_len = VLAN_HLEN;
  1350. iph = (struct iphdr *)(skb->data + vhdr_len);
  1351. th = (struct tcphdr *)((skb->data + vhdr_len) + (iph->ihl << 2));
  1352. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1353. iph->tot_len = htons(length);
  1354. iph->check = 0;
  1355. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1356. th->psh = push;
  1357. th->seq = htonl(seq_number);
  1358. length = skb->len;
  1359. netif_receive_skb(skb);
  1360. adapter->stats.lro_pkts++;
  1361. adapter->stats.rxbytes += length;
  1362. return buffer;
  1363. }
  1364. #define netxen_merge_rx_buffers(list, head) \
  1365. do { list_splice_tail_init(list, head); } while (0);
  1366. int
  1367. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1368. {
  1369. struct netxen_adapter *adapter = sds_ring->adapter;
  1370. struct list_head *cur;
  1371. struct status_desc *desc;
  1372. struct netxen_rx_buffer *rxbuf;
  1373. u32 consumer = sds_ring->consumer;
  1374. int count = 0;
  1375. u64 sts_data0, sts_data1;
  1376. int opcode, ring = 0, desc_cnt;
  1377. while (count < max) {
  1378. desc = &sds_ring->desc_head[consumer];
  1379. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1380. if (!(sts_data0 & STATUS_OWNER_HOST))
  1381. break;
  1382. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1383. opcode = netxen_get_sts_opcode(sts_data0);
  1384. switch (opcode) {
  1385. case NETXEN_NIC_RXPKT_DESC:
  1386. case NETXEN_OLD_RXPKT_DESC:
  1387. case NETXEN_NIC_SYN_OFFLOAD:
  1388. ring = netxen_get_sts_type(sts_data0);
  1389. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1390. ring, sts_data0);
  1391. break;
  1392. case NETXEN_NIC_LRO_DESC:
  1393. ring = netxen_get_lro_sts_type(sts_data0);
  1394. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1395. rxbuf = netxen_process_lro(adapter, sds_ring,
  1396. ring, sts_data0, sts_data1);
  1397. break;
  1398. case NETXEN_NIC_RESPONSE_DESC:
  1399. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1400. default:
  1401. goto skip;
  1402. }
  1403. WARN_ON(desc_cnt > 1);
  1404. if (rxbuf)
  1405. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1406. skip:
  1407. for (; desc_cnt > 0; desc_cnt--) {
  1408. desc = &sds_ring->desc_head[consumer];
  1409. desc->status_desc_data[0] =
  1410. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1411. consumer = get_next_index(consumer, sds_ring->num_desc);
  1412. }
  1413. count++;
  1414. }
  1415. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1416. struct nx_host_rds_ring *rds_ring =
  1417. &adapter->recv_ctx.rds_rings[ring];
  1418. if (!list_empty(&sds_ring->free_list[ring])) {
  1419. list_for_each(cur, &sds_ring->free_list[ring]) {
  1420. rxbuf = list_entry(cur,
  1421. struct netxen_rx_buffer, list);
  1422. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1423. }
  1424. spin_lock(&rds_ring->lock);
  1425. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1426. &rds_ring->free_list);
  1427. spin_unlock(&rds_ring->lock);
  1428. }
  1429. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1430. }
  1431. if (count) {
  1432. sds_ring->consumer = consumer;
  1433. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1434. }
  1435. return count;
  1436. }
  1437. /* Process Command status ring */
  1438. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1439. {
  1440. u32 sw_consumer, hw_consumer;
  1441. int count = 0, i;
  1442. struct netxen_cmd_buffer *buffer;
  1443. struct pci_dev *pdev = adapter->pdev;
  1444. struct net_device *netdev = adapter->netdev;
  1445. struct netxen_skb_frag *frag;
  1446. int done = 0;
  1447. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1448. if (!spin_trylock(&adapter->tx_clean_lock))
  1449. return 1;
  1450. sw_consumer = tx_ring->sw_consumer;
  1451. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1452. while (sw_consumer != hw_consumer) {
  1453. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1454. if (buffer->skb) {
  1455. frag = &buffer->frag_array[0];
  1456. pci_unmap_single(pdev, frag->dma, frag->length,
  1457. PCI_DMA_TODEVICE);
  1458. frag->dma = 0ULL;
  1459. for (i = 1; i < buffer->frag_count; i++) {
  1460. frag++; /* Get the next frag */
  1461. pci_unmap_page(pdev, frag->dma, frag->length,
  1462. PCI_DMA_TODEVICE);
  1463. frag->dma = 0ULL;
  1464. }
  1465. adapter->stats.xmitfinished++;
  1466. dev_kfree_skb_any(buffer->skb);
  1467. buffer->skb = NULL;
  1468. }
  1469. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1470. if (++count >= MAX_STATUS_HANDLE)
  1471. break;
  1472. }
  1473. if (count && netif_running(netdev)) {
  1474. tx_ring->sw_consumer = sw_consumer;
  1475. smp_mb();
  1476. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev))
  1477. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1478. netif_wake_queue(netdev);
  1479. adapter->tx_timeo_cnt = 0;
  1480. }
  1481. /*
  1482. * If everything is freed up to consumer then check if the ring is full
  1483. * If the ring is full then check if more needs to be freed and
  1484. * schedule the call back again.
  1485. *
  1486. * This happens when there are 2 CPUs. One could be freeing and the
  1487. * other filling it. If the ring is full when we get out of here and
  1488. * the card has already interrupted the host then the host can miss the
  1489. * interrupt.
  1490. *
  1491. * There is still a possible race condition and the host could miss an
  1492. * interrupt. The card has to take care of this.
  1493. */
  1494. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1495. done = (sw_consumer == hw_consumer);
  1496. spin_unlock(&adapter->tx_clean_lock);
  1497. return done;
  1498. }
  1499. void
  1500. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1501. struct nx_host_rds_ring *rds_ring)
  1502. {
  1503. struct rcv_desc *pdesc;
  1504. struct netxen_rx_buffer *buffer;
  1505. int producer, count = 0;
  1506. netxen_ctx_msg msg = 0;
  1507. struct list_head *head;
  1508. producer = rds_ring->producer;
  1509. head = &rds_ring->free_list;
  1510. while (!list_empty(head)) {
  1511. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1512. if (!buffer->skb) {
  1513. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1514. break;
  1515. }
  1516. count++;
  1517. list_del(&buffer->list);
  1518. /* make a rcv descriptor */
  1519. pdesc = &rds_ring->desc_head[producer];
  1520. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1521. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1522. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1523. producer = get_next_index(producer, rds_ring->num_desc);
  1524. }
  1525. if (count) {
  1526. rds_ring->producer = producer;
  1527. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1528. (producer-1) & (rds_ring->num_desc-1));
  1529. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1530. /*
  1531. * Write a doorbell msg to tell phanmon of change in
  1532. * receive ring producer
  1533. * Only for firmware version < 4.0.0
  1534. */
  1535. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1536. netxen_set_msg_privid(msg);
  1537. netxen_set_msg_count(msg,
  1538. ((producer - 1) &
  1539. (rds_ring->num_desc - 1)));
  1540. netxen_set_msg_ctxid(msg, adapter->portnum);
  1541. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1542. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1543. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1544. }
  1545. }
  1546. }
  1547. static void
  1548. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1549. struct nx_host_rds_ring *rds_ring)
  1550. {
  1551. struct rcv_desc *pdesc;
  1552. struct netxen_rx_buffer *buffer;
  1553. int producer, count = 0;
  1554. struct list_head *head;
  1555. if (!spin_trylock(&rds_ring->lock))
  1556. return;
  1557. producer = rds_ring->producer;
  1558. head = &rds_ring->free_list;
  1559. while (!list_empty(head)) {
  1560. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1561. if (!buffer->skb) {
  1562. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1563. break;
  1564. }
  1565. count++;
  1566. list_del(&buffer->list);
  1567. /* make a rcv descriptor */
  1568. pdesc = &rds_ring->desc_head[producer];
  1569. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1570. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1571. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1572. producer = get_next_index(producer, rds_ring->num_desc);
  1573. }
  1574. if (count) {
  1575. rds_ring->producer = producer;
  1576. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1577. (producer - 1) & (rds_ring->num_desc - 1));
  1578. }
  1579. spin_unlock(&rds_ring->lock);
  1580. }
  1581. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1582. {
  1583. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1584. }