gpio.c 23 KB

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  1. /*
  2. * Generic GPIO driver for logic cells found in the Nomadik SoC
  3. *
  4. * Copyright (C) 2008,2009 STMicroelectronics
  5. * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
  6. * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/device.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/io.h>
  18. #include <linux/clk.h>
  19. #include <linux/err.h>
  20. #include <linux/gpio.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/irq.h>
  24. #include <linux/slab.h>
  25. #include <plat/pincfg.h>
  26. #include <mach/hardware.h>
  27. #include <mach/gpio.h>
  28. /*
  29. * The GPIO module in the Nomadik family of Systems-on-Chip is an
  30. * AMBA device, managing 32 pins and alternate functions. The logic block
  31. * is currently used in the Nomadik and ux500.
  32. *
  33. * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
  34. */
  35. static const u32 backup_regs[] = {
  36. NMK_GPIO_PDIS,
  37. NMK_GPIO_DIR,
  38. NMK_GPIO_AFSLA,
  39. NMK_GPIO_AFSLB,
  40. NMK_GPIO_SLPC,
  41. NMK_GPIO_RIMSC,
  42. NMK_GPIO_FIMSC,
  43. NMK_GPIO_RWIMSC,
  44. NMK_GPIO_FWIMSC,
  45. };
  46. struct nmk_gpio_chip {
  47. struct gpio_chip chip;
  48. void __iomem *addr;
  49. struct clk *clk;
  50. unsigned int bank;
  51. unsigned int parent_irq;
  52. unsigned int secondary_parent_irq;
  53. u32 (*get_secondary_status)(unsigned int bank);
  54. spinlock_t lock;
  55. /* Keep track of configured edges */
  56. u32 edge_rising;
  57. u32 edge_falling;
  58. u32 backup[ARRAY_SIZE(backup_regs)];
  59. /* Bitmap, 1 = pull up, 0 = pull down */
  60. u32 pull;
  61. };
  62. static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
  63. unsigned offset, int gpio_mode)
  64. {
  65. u32 bit = 1 << offset;
  66. u32 afunc, bfunc;
  67. afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
  68. bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
  69. if (gpio_mode & NMK_GPIO_ALT_A)
  70. afunc |= bit;
  71. if (gpio_mode & NMK_GPIO_ALT_B)
  72. bfunc |= bit;
  73. writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
  74. writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
  75. }
  76. static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
  77. unsigned offset, enum nmk_gpio_slpm mode)
  78. {
  79. u32 bit = 1 << offset;
  80. u32 slpm;
  81. slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
  82. if (mode == NMK_GPIO_SLPM_NOCHANGE)
  83. slpm |= bit;
  84. else
  85. slpm &= ~bit;
  86. writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
  87. }
  88. static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
  89. unsigned offset, enum nmk_gpio_pull pull)
  90. {
  91. u32 bit = 1 << offset;
  92. u32 pdis;
  93. pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
  94. if (pull == NMK_GPIO_PULL_NONE)
  95. pdis |= bit;
  96. else
  97. pdis &= ~bit;
  98. writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
  99. if (pull == NMK_GPIO_PULL_UP) {
  100. nmk_chip->pull |= bit;
  101. writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
  102. } else if (pull == NMK_GPIO_PULL_DOWN) {
  103. nmk_chip->pull &= ~bit;
  104. writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
  105. }
  106. }
  107. static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
  108. unsigned offset)
  109. {
  110. writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
  111. }
  112. static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
  113. unsigned offset, int val)
  114. {
  115. if (val)
  116. writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
  117. else
  118. writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
  119. }
  120. static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
  121. unsigned offset, int val)
  122. {
  123. writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
  124. __nmk_gpio_set_output(nmk_chip, offset, val);
  125. }
  126. static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
  127. pin_cfg_t cfg, bool sleep)
  128. {
  129. static const char *afnames[] = {
  130. [NMK_GPIO_ALT_GPIO] = "GPIO",
  131. [NMK_GPIO_ALT_A] = "A",
  132. [NMK_GPIO_ALT_B] = "B",
  133. [NMK_GPIO_ALT_C] = "C"
  134. };
  135. static const char *pullnames[] = {
  136. [NMK_GPIO_PULL_NONE] = "none",
  137. [NMK_GPIO_PULL_UP] = "up",
  138. [NMK_GPIO_PULL_DOWN] = "down",
  139. [3] /* illegal */ = "??"
  140. };
  141. static const char *slpmnames[] = {
  142. [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
  143. [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
  144. };
  145. int pin = PIN_NUM(cfg);
  146. int pull = PIN_PULL(cfg);
  147. int af = PIN_ALT(cfg);
  148. int slpm = PIN_SLPM(cfg);
  149. int output = PIN_DIR(cfg);
  150. int val = PIN_VAL(cfg);
  151. dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
  152. pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
  153. output ? "output " : "input",
  154. output ? (val ? "high" : "low") : "");
  155. if (sleep) {
  156. int slpm_pull = PIN_SLPM_PULL(cfg);
  157. int slpm_output = PIN_SLPM_DIR(cfg);
  158. int slpm_val = PIN_SLPM_VAL(cfg);
  159. /*
  160. * The SLPM_* values are normal values + 1 to allow zero to
  161. * mean "same as normal".
  162. */
  163. if (slpm_pull)
  164. pull = slpm_pull - 1;
  165. if (slpm_output)
  166. output = slpm_output - 1;
  167. if (slpm_val)
  168. val = slpm_val - 1;
  169. dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
  170. pin,
  171. slpm_pull ? pullnames[pull] : "same",
  172. slpm_output ? (output ? "output" : "input") : "same",
  173. slpm_val ? (val ? "high" : "low") : "same");
  174. }
  175. if (output)
  176. __nmk_gpio_make_output(nmk_chip, offset, val);
  177. else {
  178. __nmk_gpio_make_input(nmk_chip, offset);
  179. __nmk_gpio_set_pull(nmk_chip, offset, pull);
  180. }
  181. __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
  182. __nmk_gpio_set_mode(nmk_chip, offset, af);
  183. }
  184. /**
  185. * nmk_config_pin - configure a pin's mux attributes
  186. * @cfg: pin confguration
  187. *
  188. * Configures a pin's mode (alternate function or GPIO), its pull up status,
  189. * and its sleep mode based on the specified configuration. The @cfg is
  190. * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
  191. * are constructed using, and can be further enhanced with, the macros in
  192. * plat/pincfg.h.
  193. *
  194. * If a pin's mode is set to GPIO, it is configured as an input to avoid
  195. * side-effects. The gpio can be manipulated later using standard GPIO API
  196. * calls.
  197. */
  198. int nmk_config_pin(pin_cfg_t cfg, bool sleep)
  199. {
  200. struct nmk_gpio_chip *nmk_chip;
  201. int gpio = PIN_NUM(cfg);
  202. unsigned long flags;
  203. nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
  204. if (!nmk_chip)
  205. return -EINVAL;
  206. spin_lock_irqsave(&nmk_chip->lock, flags);
  207. __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg, sleep);
  208. spin_unlock_irqrestore(&nmk_chip->lock, flags);
  209. return 0;
  210. }
  211. EXPORT_SYMBOL(nmk_config_pin);
  212. /**
  213. * nmk_config_pins - configure several pins at once
  214. * @cfgs: array of pin configurations
  215. * @num: number of elments in the array
  216. *
  217. * Configures several pins using nmk_config_pin(). Refer to that function for
  218. * further information.
  219. */
  220. int nmk_config_pins(pin_cfg_t *cfgs, int num)
  221. {
  222. int ret = 0;
  223. int i;
  224. for (i = 0; i < num; i++) {
  225. ret = nmk_config_pin(cfgs[i], false);
  226. if (ret)
  227. break;
  228. }
  229. return ret;
  230. }
  231. EXPORT_SYMBOL(nmk_config_pins);
  232. int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
  233. {
  234. int ret = 0;
  235. int i;
  236. for (i = 0; i < num; i++) {
  237. ret = nmk_config_pin(cfgs[i], true);
  238. if (ret)
  239. break;
  240. }
  241. return ret;
  242. }
  243. EXPORT_SYMBOL(nmk_config_pins_sleep);
  244. /**
  245. * nmk_gpio_set_slpm() - configure the sleep mode of a pin
  246. * @gpio: pin number
  247. * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
  248. *
  249. * Sets the sleep mode of a pin. If @mode is NMK_GPIO_SLPM_INPUT, the pin is
  250. * changed to an input (with pullup/down enabled) in sleep and deep sleep. If
  251. * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
  252. * configured even when in sleep and deep sleep.
  253. *
  254. * On DB8500v2 onwards, this setting loses the previous meaning and instead
  255. * indicates if wakeup detection is enabled on the pin. Note that
  256. * enable_irq_wake() will automatically enable wakeup detection.
  257. */
  258. int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
  259. {
  260. struct nmk_gpio_chip *nmk_chip;
  261. unsigned long flags;
  262. nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
  263. if (!nmk_chip)
  264. return -EINVAL;
  265. spin_lock_irqsave(&nmk_chip->lock, flags);
  266. __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
  267. spin_unlock_irqrestore(&nmk_chip->lock, flags);
  268. return 0;
  269. }
  270. /**
  271. * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
  272. * @gpio: pin number
  273. * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
  274. *
  275. * Enables/disables pull up/down on a specified pin. This only takes effect if
  276. * the pin is configured as an input (either explicitly or by the alternate
  277. * function).
  278. *
  279. * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
  280. * configured as an input. Otherwise, due to the way the controller registers
  281. * work, this function will change the value output on the pin.
  282. */
  283. int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
  284. {
  285. struct nmk_gpio_chip *nmk_chip;
  286. unsigned long flags;
  287. nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
  288. if (!nmk_chip)
  289. return -EINVAL;
  290. spin_lock_irqsave(&nmk_chip->lock, flags);
  291. __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
  292. spin_unlock_irqrestore(&nmk_chip->lock, flags);
  293. return 0;
  294. }
  295. /* Mode functions */
  296. /**
  297. * nmk_gpio_set_mode() - set the mux mode of a gpio pin
  298. * @gpio: pin number
  299. * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
  300. * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
  301. *
  302. * Sets the mode of the specified pin to one of the alternate functions or
  303. * plain GPIO.
  304. */
  305. int nmk_gpio_set_mode(int gpio, int gpio_mode)
  306. {
  307. struct nmk_gpio_chip *nmk_chip;
  308. unsigned long flags;
  309. nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
  310. if (!nmk_chip)
  311. return -EINVAL;
  312. spin_lock_irqsave(&nmk_chip->lock, flags);
  313. __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
  314. spin_unlock_irqrestore(&nmk_chip->lock, flags);
  315. return 0;
  316. }
  317. EXPORT_SYMBOL(nmk_gpio_set_mode);
  318. int nmk_gpio_get_mode(int gpio)
  319. {
  320. struct nmk_gpio_chip *nmk_chip;
  321. u32 afunc, bfunc, bit;
  322. nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
  323. if (!nmk_chip)
  324. return -EINVAL;
  325. bit = 1 << (gpio - nmk_chip->chip.base);
  326. afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
  327. bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
  328. return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
  329. }
  330. EXPORT_SYMBOL(nmk_gpio_get_mode);
  331. /* IRQ functions */
  332. static inline int nmk_gpio_get_bitmask(int gpio)
  333. {
  334. return 1 << (gpio % 32);
  335. }
  336. static void nmk_gpio_irq_ack(struct irq_data *d)
  337. {
  338. int gpio;
  339. struct nmk_gpio_chip *nmk_chip;
  340. gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
  341. nmk_chip = irq_data_get_irq_chip_data(d);
  342. if (!nmk_chip)
  343. return;
  344. writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
  345. }
  346. enum nmk_gpio_irq_type {
  347. NORMAL,
  348. WAKE,
  349. };
  350. static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
  351. int gpio, enum nmk_gpio_irq_type which,
  352. bool enable)
  353. {
  354. u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
  355. u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
  356. u32 bitmask = nmk_gpio_get_bitmask(gpio);
  357. u32 reg;
  358. /* we must individually set/clear the two edges */
  359. if (nmk_chip->edge_rising & bitmask) {
  360. reg = readl(nmk_chip->addr + rimsc);
  361. if (enable)
  362. reg |= bitmask;
  363. else
  364. reg &= ~bitmask;
  365. writel(reg, nmk_chip->addr + rimsc);
  366. }
  367. if (nmk_chip->edge_falling & bitmask) {
  368. reg = readl(nmk_chip->addr + fimsc);
  369. if (enable)
  370. reg |= bitmask;
  371. else
  372. reg &= ~bitmask;
  373. writel(reg, nmk_chip->addr + fimsc);
  374. }
  375. }
  376. static int nmk_gpio_irq_modify(struct irq_data *d, enum nmk_gpio_irq_type which,
  377. bool enable)
  378. {
  379. int gpio;
  380. struct nmk_gpio_chip *nmk_chip;
  381. unsigned long flags;
  382. u32 bitmask;
  383. gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
  384. nmk_chip = irq_data_get_irq_chip_data(d);
  385. bitmask = nmk_gpio_get_bitmask(gpio);
  386. if (!nmk_chip)
  387. return -EINVAL;
  388. spin_lock_irqsave(&nmk_chip->lock, flags);
  389. __nmk_gpio_irq_modify(nmk_chip, gpio, which, enable);
  390. spin_unlock_irqrestore(&nmk_chip->lock, flags);
  391. return 0;
  392. }
  393. static void nmk_gpio_irq_mask(struct irq_data *d)
  394. {
  395. nmk_gpio_irq_modify(d, NORMAL, false);
  396. }
  397. static void nmk_gpio_irq_unmask(struct irq_data *d)
  398. {
  399. nmk_gpio_irq_modify(d, NORMAL, true);
  400. }
  401. static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
  402. {
  403. struct nmk_gpio_chip *nmk_chip;
  404. unsigned long flags;
  405. int gpio;
  406. gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
  407. nmk_chip = irq_data_get_irq_chip_data(d);
  408. if (!nmk_chip)
  409. return -EINVAL;
  410. spin_lock_irqsave(&nmk_chip->lock, flags);
  411. #ifdef CONFIG_ARCH_U8500
  412. if (cpu_is_u8500v2()) {
  413. __nmk_gpio_set_slpm(nmk_chip, gpio,
  414. on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
  415. : NMK_GPIO_SLPM_WAKEUP_DISABLE);
  416. }
  417. #endif
  418. __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
  419. spin_unlock_irqrestore(&nmk_chip->lock, flags);
  420. return 0;
  421. }
  422. static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  423. {
  424. struct irq_desc *desc = irq_to_desc(d->irq);
  425. bool enabled = !(desc->status & IRQ_DISABLED);
  426. bool wake = desc->wake_depth;
  427. int gpio;
  428. struct nmk_gpio_chip *nmk_chip;
  429. unsigned long flags;
  430. u32 bitmask;
  431. gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
  432. nmk_chip = irq_data_get_irq_chip_data(d);
  433. bitmask = nmk_gpio_get_bitmask(gpio);
  434. if (!nmk_chip)
  435. return -EINVAL;
  436. if (type & IRQ_TYPE_LEVEL_HIGH)
  437. return -EINVAL;
  438. if (type & IRQ_TYPE_LEVEL_LOW)
  439. return -EINVAL;
  440. spin_lock_irqsave(&nmk_chip->lock, flags);
  441. if (enabled)
  442. __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
  443. if (wake)
  444. __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
  445. nmk_chip->edge_rising &= ~bitmask;
  446. if (type & IRQ_TYPE_EDGE_RISING)
  447. nmk_chip->edge_rising |= bitmask;
  448. nmk_chip->edge_falling &= ~bitmask;
  449. if (type & IRQ_TYPE_EDGE_FALLING)
  450. nmk_chip->edge_falling |= bitmask;
  451. if (enabled)
  452. __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
  453. if (wake)
  454. __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
  455. spin_unlock_irqrestore(&nmk_chip->lock, flags);
  456. return 0;
  457. }
  458. static struct irq_chip nmk_gpio_irq_chip = {
  459. .name = "Nomadik-GPIO",
  460. .irq_ack = nmk_gpio_irq_ack,
  461. .irq_mask = nmk_gpio_irq_mask,
  462. .irq_unmask = nmk_gpio_irq_unmask,
  463. .irq_set_type = nmk_gpio_irq_set_type,
  464. .irq_set_wake = nmk_gpio_irq_set_wake,
  465. };
  466. static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
  467. u32 status)
  468. {
  469. struct nmk_gpio_chip *nmk_chip;
  470. struct irq_chip *host_chip = get_irq_chip(irq);
  471. unsigned int first_irq;
  472. if (host_chip->irq_mask_ack)
  473. host_chip->irq_mask_ack(&desc->irq_data);
  474. else {
  475. host_chip->irq_mask(&desc->irq_data);
  476. if (host_chip->irq_ack)
  477. host_chip->irq_ack(&desc->irq_data);
  478. }
  479. nmk_chip = get_irq_data(irq);
  480. first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
  481. while (status) {
  482. int bit = __ffs(status);
  483. generic_handle_irq(first_irq + bit);
  484. status &= ~BIT(bit);
  485. }
  486. host_chip->irq_unmask(&desc->irq_data);
  487. }
  488. static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
  489. {
  490. struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
  491. u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
  492. __nmk_gpio_irq_handler(irq, desc, status);
  493. }
  494. static void nmk_gpio_secondary_irq_handler(unsigned int irq,
  495. struct irq_desc *desc)
  496. {
  497. struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
  498. u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
  499. __nmk_gpio_irq_handler(irq, desc, status);
  500. }
  501. static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
  502. {
  503. unsigned int first_irq;
  504. int i;
  505. first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
  506. for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
  507. set_irq_chip(i, &nmk_gpio_irq_chip);
  508. set_irq_handler(i, handle_edge_irq);
  509. set_irq_flags(i, IRQF_VALID);
  510. set_irq_chip_data(i, nmk_chip);
  511. set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
  512. }
  513. set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
  514. set_irq_data(nmk_chip->parent_irq, nmk_chip);
  515. if (nmk_chip->secondary_parent_irq >= 0) {
  516. set_irq_chained_handler(nmk_chip->secondary_parent_irq,
  517. nmk_gpio_secondary_irq_handler);
  518. set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip);
  519. }
  520. return 0;
  521. }
  522. /* I/O Functions */
  523. static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
  524. {
  525. struct nmk_gpio_chip *nmk_chip =
  526. container_of(chip, struct nmk_gpio_chip, chip);
  527. writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
  528. return 0;
  529. }
  530. static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
  531. {
  532. struct nmk_gpio_chip *nmk_chip =
  533. container_of(chip, struct nmk_gpio_chip, chip);
  534. u32 bit = 1 << offset;
  535. return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
  536. }
  537. static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
  538. int val)
  539. {
  540. struct nmk_gpio_chip *nmk_chip =
  541. container_of(chip, struct nmk_gpio_chip, chip);
  542. __nmk_gpio_set_output(nmk_chip, offset, val);
  543. }
  544. static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
  545. int val)
  546. {
  547. struct nmk_gpio_chip *nmk_chip =
  548. container_of(chip, struct nmk_gpio_chip, chip);
  549. __nmk_gpio_make_output(nmk_chip, offset, val);
  550. return 0;
  551. }
  552. static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  553. {
  554. struct nmk_gpio_chip *nmk_chip =
  555. container_of(chip, struct nmk_gpio_chip, chip);
  556. return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
  557. }
  558. #ifdef CONFIG_DEBUG_FS
  559. #include <linux/seq_file.h>
  560. static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  561. {
  562. int mode;
  563. unsigned i;
  564. unsigned gpio = chip->base;
  565. int is_out;
  566. struct nmk_gpio_chip *nmk_chip =
  567. container_of(chip, struct nmk_gpio_chip, chip);
  568. const char *modes[] = {
  569. [NMK_GPIO_ALT_GPIO] = "gpio",
  570. [NMK_GPIO_ALT_A] = "altA",
  571. [NMK_GPIO_ALT_B] = "altB",
  572. [NMK_GPIO_ALT_C] = "altC",
  573. };
  574. for (i = 0; i < chip->ngpio; i++, gpio++) {
  575. const char *label = gpiochip_is_requested(chip, i);
  576. bool pull;
  577. u32 bit = 1 << i;
  578. if (!label)
  579. continue;
  580. is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
  581. pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
  582. mode = nmk_gpio_get_mode(gpio);
  583. seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
  584. gpio, label,
  585. is_out ? "out" : "in ",
  586. chip->get
  587. ? (chip->get(chip, i) ? "hi" : "lo")
  588. : "? ",
  589. (mode < 0) ? "unknown" : modes[mode],
  590. pull ? "pull" : "none");
  591. if (!is_out) {
  592. int irq = gpio_to_irq(gpio);
  593. struct irq_desc *desc = irq_to_desc(irq);
  594. /* This races with request_irq(), set_irq_type(),
  595. * and set_irq_wake() ... but those are "rare".
  596. *
  597. * More significantly, trigger type flags aren't
  598. * currently maintained by genirq.
  599. */
  600. if (irq >= 0 && desc->action) {
  601. char *trigger;
  602. switch (desc->status & IRQ_TYPE_SENSE_MASK) {
  603. case IRQ_TYPE_NONE:
  604. trigger = "(default)";
  605. break;
  606. case IRQ_TYPE_EDGE_FALLING:
  607. trigger = "edge-falling";
  608. break;
  609. case IRQ_TYPE_EDGE_RISING:
  610. trigger = "edge-rising";
  611. break;
  612. case IRQ_TYPE_EDGE_BOTH:
  613. trigger = "edge-both";
  614. break;
  615. case IRQ_TYPE_LEVEL_HIGH:
  616. trigger = "level-high";
  617. break;
  618. case IRQ_TYPE_LEVEL_LOW:
  619. trigger = "level-low";
  620. break;
  621. default:
  622. trigger = "?trigger?";
  623. break;
  624. }
  625. seq_printf(s, " irq-%d %s%s",
  626. irq, trigger,
  627. (desc->status & IRQ_WAKEUP)
  628. ? " wakeup" : "");
  629. }
  630. }
  631. seq_printf(s, "\n");
  632. }
  633. }
  634. #else
  635. #define nmk_gpio_dbg_show NULL
  636. #endif
  637. /* This structure is replicated for each GPIO block allocated at probe time */
  638. static struct gpio_chip nmk_gpio_template = {
  639. .direction_input = nmk_gpio_make_input,
  640. .get = nmk_gpio_get_input,
  641. .direction_output = nmk_gpio_make_output,
  642. .set = nmk_gpio_set_output,
  643. .to_irq = nmk_gpio_to_irq,
  644. .dbg_show = nmk_gpio_dbg_show,
  645. .can_sleep = 0,
  646. };
  647. static int __devinit nmk_gpio_probe(struct platform_device *dev)
  648. {
  649. struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
  650. struct nmk_gpio_chip *nmk_chip;
  651. struct gpio_chip *chip;
  652. struct resource *res;
  653. struct clk *clk;
  654. int secondary_irq;
  655. int irq;
  656. int ret;
  657. if (!pdata)
  658. return -ENODEV;
  659. res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  660. if (!res) {
  661. ret = -ENOENT;
  662. goto out;
  663. }
  664. irq = platform_get_irq(dev, 0);
  665. if (irq < 0) {
  666. ret = irq;
  667. goto out;
  668. }
  669. secondary_irq = platform_get_irq(dev, 1);
  670. if (secondary_irq >= 0 && !pdata->get_secondary_status) {
  671. ret = -EINVAL;
  672. goto out;
  673. }
  674. if (request_mem_region(res->start, resource_size(res),
  675. dev_name(&dev->dev)) == NULL) {
  676. ret = -EBUSY;
  677. goto out;
  678. }
  679. clk = clk_get(&dev->dev, NULL);
  680. if (IS_ERR(clk)) {
  681. ret = PTR_ERR(clk);
  682. goto out_release;
  683. }
  684. clk_enable(clk);
  685. nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
  686. if (!nmk_chip) {
  687. ret = -ENOMEM;
  688. goto out_clk;
  689. }
  690. /*
  691. * The virt address in nmk_chip->addr is in the nomadik register space,
  692. * so we can simply convert the resource address, without remapping
  693. */
  694. nmk_chip->bank = dev->id;
  695. nmk_chip->clk = clk;
  696. nmk_chip->addr = io_p2v(res->start);
  697. nmk_chip->chip = nmk_gpio_template;
  698. nmk_chip->parent_irq = irq;
  699. nmk_chip->secondary_parent_irq = secondary_irq;
  700. nmk_chip->get_secondary_status = pdata->get_secondary_status;
  701. spin_lock_init(&nmk_chip->lock);
  702. chip = &nmk_chip->chip;
  703. chip->base = pdata->first_gpio;
  704. chip->ngpio = pdata->num_gpio;
  705. chip->label = pdata->name ?: dev_name(&dev->dev);
  706. chip->dev = &dev->dev;
  707. chip->owner = THIS_MODULE;
  708. ret = gpiochip_add(&nmk_chip->chip);
  709. if (ret)
  710. goto out_free;
  711. platform_set_drvdata(dev, nmk_chip);
  712. nmk_gpio_init_irq(nmk_chip);
  713. dev_info(&dev->dev, "Bits %i-%i at address %p\n",
  714. nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr);
  715. return 0;
  716. out_free:
  717. kfree(nmk_chip);
  718. out_clk:
  719. clk_disable(clk);
  720. clk_put(clk);
  721. out_release:
  722. release_mem_region(res->start, resource_size(res));
  723. out:
  724. dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
  725. pdata->first_gpio, pdata->first_gpio+31);
  726. return ret;
  727. }
  728. #ifdef CONFIG_NOMADIK_GPIO_PM
  729. static int nmk_gpio_pm(struct platform_device *dev, bool suspend)
  730. {
  731. struct nmk_gpio_chip *nmk_chip = platform_get_drvdata(dev);
  732. int i;
  733. u32 dir;
  734. u32 dat;
  735. for (i = 0; i < ARRAY_SIZE(backup_regs); i++) {
  736. if (suspend)
  737. nmk_chip->backup[i] = readl(nmk_chip->addr +
  738. backup_regs[i]);
  739. else
  740. writel(nmk_chip->backup[i],
  741. nmk_chip->addr + backup_regs[i]);
  742. }
  743. if (!suspend) {
  744. /*
  745. * Restore pull-up and pull-down on inputs and
  746. * outputs.
  747. */
  748. dir = readl(nmk_chip->addr + NMK_GPIO_DIR);
  749. dat = readl(nmk_chip->addr + NMK_GPIO_DAT);
  750. writel((nmk_chip->pull & ~dir) |
  751. (dat & dir),
  752. nmk_chip->addr + NMK_GPIO_DATS);
  753. writel((~nmk_chip->pull & ~dir) |
  754. (~dat & dir),
  755. nmk_chip->addr + NMK_GPIO_DATC);
  756. }
  757. return 0;
  758. }
  759. static int nmk_gpio_suspend(struct platform_device *dev, pm_message_t state)
  760. {
  761. return nmk_gpio_pm(dev, true);
  762. }
  763. static int nmk_gpio_resume(struct platform_device *dev)
  764. {
  765. return nmk_gpio_pm(dev, false);
  766. }
  767. #else
  768. #define nmk_gpio_suspend NULL
  769. #define nmk_gpio_resume NULL
  770. #endif
  771. static struct platform_driver nmk_gpio_driver = {
  772. .driver = {
  773. .owner = THIS_MODULE,
  774. .name = "gpio",
  775. },
  776. .probe = nmk_gpio_probe,
  777. .suspend = nmk_gpio_suspend,
  778. .resume = nmk_gpio_resume,
  779. };
  780. static int __init nmk_gpio_init(void)
  781. {
  782. return platform_driver_register(&nmk_gpio_driver);
  783. }
  784. core_initcall(nmk_gpio_init);
  785. MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
  786. MODULE_DESCRIPTION("Nomadik GPIO Driver");
  787. MODULE_LICENSE("GPL");