twl4030.c 38 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x93, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /*
  117. * read twl4030 register cache
  118. */
  119. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  120. unsigned int reg)
  121. {
  122. u8 *cache = codec->reg_cache;
  123. return cache[reg];
  124. }
  125. /*
  126. * write twl4030 register cache
  127. */
  128. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  129. u8 reg, u8 value)
  130. {
  131. u8 *cache = codec->reg_cache;
  132. if (reg >= TWL4030_CACHEREGNUM)
  133. return;
  134. cache[reg] = value;
  135. }
  136. /*
  137. * write to the twl4030 register space
  138. */
  139. static int twl4030_write(struct snd_soc_codec *codec,
  140. unsigned int reg, unsigned int value)
  141. {
  142. twl4030_write_reg_cache(codec, reg, value);
  143. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  144. }
  145. static void twl4030_clear_codecpdz(struct snd_soc_codec *codec)
  146. {
  147. u8 mode;
  148. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  149. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  150. mode & ~TWL4030_CODECPDZ);
  151. /* REVISIT: this delay is present in TI sample drivers */
  152. /* but there seems to be no TRM requirement for it */
  153. udelay(10);
  154. }
  155. static void twl4030_set_codecpdz(struct snd_soc_codec *codec)
  156. {
  157. u8 mode;
  158. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  159. twl4030_write(codec, TWL4030_REG_CODEC_MODE,
  160. mode | TWL4030_CODECPDZ);
  161. /* REVISIT: this delay is present in TI sample drivers */
  162. /* but there seems to be no TRM requirement for it */
  163. udelay(10);
  164. }
  165. static void twl4030_init_chip(struct snd_soc_codec *codec)
  166. {
  167. int i;
  168. /* clear CODECPDZ prior to setting register defaults */
  169. twl4030_clear_codecpdz(codec);
  170. /* set all audio section registers to reasonable defaults */
  171. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  172. twl4030_write(codec, i, twl4030_reg[i]);
  173. }
  174. /* Earpiece */
  175. static const char *twl4030_earpiece_texts[] =
  176. {"Off", "DACL1", "DACL2", "DACR1"};
  177. static const unsigned int twl4030_earpiece_values[] =
  178. {0x0, 0x1, 0x2, 0x4};
  179. static const struct soc_enum twl4030_earpiece_enum =
  180. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
  181. ARRAY_SIZE(twl4030_earpiece_texts),
  182. twl4030_earpiece_texts,
  183. twl4030_earpiece_values);
  184. static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
  185. SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
  186. /* PreDrive Left */
  187. static const char *twl4030_predrivel_texts[] =
  188. {"Off", "DACL1", "DACL2", "DACR2"};
  189. static const unsigned int twl4030_predrivel_values[] =
  190. {0x0, 0x1, 0x2, 0x4};
  191. static const struct soc_enum twl4030_predrivel_enum =
  192. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
  193. ARRAY_SIZE(twl4030_predrivel_texts),
  194. twl4030_predrivel_texts,
  195. twl4030_predrivel_values);
  196. static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
  197. SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
  198. /* PreDrive Right */
  199. static const char *twl4030_predriver_texts[] =
  200. {"Off", "DACR1", "DACR2", "DACL2"};
  201. static const unsigned int twl4030_predriver_values[] =
  202. {0x0, 0x1, 0x2, 0x4};
  203. static const struct soc_enum twl4030_predriver_enum =
  204. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
  205. ARRAY_SIZE(twl4030_predriver_texts),
  206. twl4030_predriver_texts,
  207. twl4030_predriver_values);
  208. static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
  209. SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
  210. /* Headset Left */
  211. static const char *twl4030_hsol_texts[] =
  212. {"Off", "DACL1", "DACL2"};
  213. static const struct soc_enum twl4030_hsol_enum =
  214. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
  215. ARRAY_SIZE(twl4030_hsol_texts),
  216. twl4030_hsol_texts);
  217. static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
  218. SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
  219. /* Headset Right */
  220. static const char *twl4030_hsor_texts[] =
  221. {"Off", "DACR1", "DACR2"};
  222. static const struct soc_enum twl4030_hsor_enum =
  223. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
  224. ARRAY_SIZE(twl4030_hsor_texts),
  225. twl4030_hsor_texts);
  226. static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
  227. SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
  228. /* Carkit Left */
  229. static const char *twl4030_carkitl_texts[] =
  230. {"Off", "DACL1", "DACL2"};
  231. static const struct soc_enum twl4030_carkitl_enum =
  232. SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
  233. ARRAY_SIZE(twl4030_carkitl_texts),
  234. twl4030_carkitl_texts);
  235. static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
  236. SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
  237. /* Carkit Right */
  238. static const char *twl4030_carkitr_texts[] =
  239. {"Off", "DACR1", "DACR2"};
  240. static const struct soc_enum twl4030_carkitr_enum =
  241. SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
  242. ARRAY_SIZE(twl4030_carkitr_texts),
  243. twl4030_carkitr_texts);
  244. static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
  245. SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
  246. /* Handsfree Left */
  247. static const char *twl4030_handsfreel_texts[] =
  248. {"Voice", "DACL1", "DACL2", "DACR2"};
  249. static const struct soc_enum twl4030_handsfreel_enum =
  250. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  251. ARRAY_SIZE(twl4030_handsfreel_texts),
  252. twl4030_handsfreel_texts);
  253. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  254. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  255. /* Handsfree Right */
  256. static const char *twl4030_handsfreer_texts[] =
  257. {"Voice", "DACR1", "DACR2", "DACL2"};
  258. static const struct soc_enum twl4030_handsfreer_enum =
  259. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  260. ARRAY_SIZE(twl4030_handsfreer_texts),
  261. twl4030_handsfreer_texts);
  262. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  263. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  264. /* Left analog microphone selection */
  265. static const char *twl4030_analoglmic_texts[] =
  266. {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
  267. static const unsigned int twl4030_analoglmic_values[] =
  268. {0x0, 0x1, 0x2, 0x4, 0x8};
  269. static const struct soc_enum twl4030_analoglmic_enum =
  270. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
  271. ARRAY_SIZE(twl4030_analoglmic_texts),
  272. twl4030_analoglmic_texts,
  273. twl4030_analoglmic_values);
  274. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
  275. SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
  276. /* Right analog microphone selection */
  277. static const char *twl4030_analogrmic_texts[] =
  278. {"Off", "Sub mic", "AUXR"};
  279. static const unsigned int twl4030_analogrmic_values[] =
  280. {0x0, 0x1, 0x4};
  281. static const struct soc_enum twl4030_analogrmic_enum =
  282. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
  283. ARRAY_SIZE(twl4030_analogrmic_texts),
  284. twl4030_analogrmic_texts,
  285. twl4030_analogrmic_values);
  286. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
  287. SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
  288. /* TX1 L/R Analog/Digital microphone selection */
  289. static const char *twl4030_micpathtx1_texts[] =
  290. {"Analog", "Digimic0"};
  291. static const struct soc_enum twl4030_micpathtx1_enum =
  292. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  293. ARRAY_SIZE(twl4030_micpathtx1_texts),
  294. twl4030_micpathtx1_texts);
  295. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  296. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  297. /* TX2 L/R Analog/Digital microphone selection */
  298. static const char *twl4030_micpathtx2_texts[] =
  299. {"Analog", "Digimic1"};
  300. static const struct soc_enum twl4030_micpathtx2_enum =
  301. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  302. ARRAY_SIZE(twl4030_micpathtx2_texts),
  303. twl4030_micpathtx2_texts);
  304. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  305. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  306. static int micpath_event(struct snd_soc_dapm_widget *w,
  307. struct snd_kcontrol *kcontrol, int event)
  308. {
  309. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  310. unsigned char adcmicsel, micbias_ctl;
  311. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  312. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  313. /* Prepare the bits for the given TX path:
  314. * shift_l == 0: TX1 microphone path
  315. * shift_l == 2: TX2 microphone path */
  316. if (e->shift_l) {
  317. /* TX2 microphone path */
  318. if (adcmicsel & TWL4030_TX2IN_SEL)
  319. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  320. else
  321. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  322. } else {
  323. /* TX1 microphone path */
  324. if (adcmicsel & TWL4030_TX1IN_SEL)
  325. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  326. else
  327. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  328. }
  329. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  330. return 0;
  331. }
  332. static int handsfree_event(struct snd_soc_dapm_widget *w,
  333. struct snd_kcontrol *kcontrol, int event)
  334. {
  335. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  336. unsigned char hs_ctl;
  337. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  338. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  339. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  340. twl4030_write(w->codec, e->reg, hs_ctl);
  341. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  342. twl4030_write(w->codec, e->reg, hs_ctl);
  343. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  344. twl4030_write(w->codec, e->reg, hs_ctl);
  345. } else {
  346. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  347. | TWL4030_HF_CTL_HB_EN);
  348. twl4030_write(w->codec, e->reg, hs_ctl);
  349. }
  350. return 0;
  351. }
  352. /*
  353. * Some of the gain controls in TWL (mostly those which are associated with
  354. * the outputs) are implemented in an interesting way:
  355. * 0x0 : Power down (mute)
  356. * 0x1 : 6dB
  357. * 0x2 : 0 dB
  358. * 0x3 : -6 dB
  359. * Inverting not going to help with these.
  360. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  361. */
  362. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  363. xinvert, tlv_array) \
  364. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  365. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  366. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  367. .tlv.p = (tlv_array), \
  368. .info = snd_soc_info_volsw, \
  369. .get = snd_soc_get_volsw_twl4030, \
  370. .put = snd_soc_put_volsw_twl4030, \
  371. .private_value = (unsigned long)&(struct soc_mixer_control) \
  372. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  373. .max = xmax, .invert = xinvert} }
  374. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  375. xinvert, tlv_array) \
  376. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  377. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  378. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  379. .tlv.p = (tlv_array), \
  380. .info = snd_soc_info_volsw_2r, \
  381. .get = snd_soc_get_volsw_r2_twl4030,\
  382. .put = snd_soc_put_volsw_r2_twl4030, \
  383. .private_value = (unsigned long)&(struct soc_mixer_control) \
  384. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  385. .rshift = xshift, .max = xmax, .invert = xinvert} }
  386. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  387. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  388. xinvert, tlv_array)
  389. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  390. struct snd_ctl_elem_value *ucontrol)
  391. {
  392. struct soc_mixer_control *mc =
  393. (struct soc_mixer_control *)kcontrol->private_value;
  394. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  395. unsigned int reg = mc->reg;
  396. unsigned int shift = mc->shift;
  397. unsigned int rshift = mc->rshift;
  398. int max = mc->max;
  399. int mask = (1 << fls(max)) - 1;
  400. ucontrol->value.integer.value[0] =
  401. (snd_soc_read(codec, reg) >> shift) & mask;
  402. if (ucontrol->value.integer.value[0])
  403. ucontrol->value.integer.value[0] =
  404. max + 1 - ucontrol->value.integer.value[0];
  405. if (shift != rshift) {
  406. ucontrol->value.integer.value[1] =
  407. (snd_soc_read(codec, reg) >> rshift) & mask;
  408. if (ucontrol->value.integer.value[1])
  409. ucontrol->value.integer.value[1] =
  410. max + 1 - ucontrol->value.integer.value[1];
  411. }
  412. return 0;
  413. }
  414. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  415. struct snd_ctl_elem_value *ucontrol)
  416. {
  417. struct soc_mixer_control *mc =
  418. (struct soc_mixer_control *)kcontrol->private_value;
  419. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  420. unsigned int reg = mc->reg;
  421. unsigned int shift = mc->shift;
  422. unsigned int rshift = mc->rshift;
  423. int max = mc->max;
  424. int mask = (1 << fls(max)) - 1;
  425. unsigned short val, val2, val_mask;
  426. val = (ucontrol->value.integer.value[0] & mask);
  427. val_mask = mask << shift;
  428. if (val)
  429. val = max + 1 - val;
  430. val = val << shift;
  431. if (shift != rshift) {
  432. val2 = (ucontrol->value.integer.value[1] & mask);
  433. val_mask |= mask << rshift;
  434. if (val2)
  435. val2 = max + 1 - val2;
  436. val |= val2 << rshift;
  437. }
  438. return snd_soc_update_bits(codec, reg, val_mask, val);
  439. }
  440. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  441. struct snd_ctl_elem_value *ucontrol)
  442. {
  443. struct soc_mixer_control *mc =
  444. (struct soc_mixer_control *)kcontrol->private_value;
  445. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  446. unsigned int reg = mc->reg;
  447. unsigned int reg2 = mc->rreg;
  448. unsigned int shift = mc->shift;
  449. int max = mc->max;
  450. int mask = (1<<fls(max))-1;
  451. ucontrol->value.integer.value[0] =
  452. (snd_soc_read(codec, reg) >> shift) & mask;
  453. ucontrol->value.integer.value[1] =
  454. (snd_soc_read(codec, reg2) >> shift) & mask;
  455. if (ucontrol->value.integer.value[0])
  456. ucontrol->value.integer.value[0] =
  457. max + 1 - ucontrol->value.integer.value[0];
  458. if (ucontrol->value.integer.value[1])
  459. ucontrol->value.integer.value[1] =
  460. max + 1 - ucontrol->value.integer.value[1];
  461. return 0;
  462. }
  463. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  464. struct snd_ctl_elem_value *ucontrol)
  465. {
  466. struct soc_mixer_control *mc =
  467. (struct soc_mixer_control *)kcontrol->private_value;
  468. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  469. unsigned int reg = mc->reg;
  470. unsigned int reg2 = mc->rreg;
  471. unsigned int shift = mc->shift;
  472. int max = mc->max;
  473. int mask = (1 << fls(max)) - 1;
  474. int err;
  475. unsigned short val, val2, val_mask;
  476. val_mask = mask << shift;
  477. val = (ucontrol->value.integer.value[0] & mask);
  478. val2 = (ucontrol->value.integer.value[1] & mask);
  479. if (val)
  480. val = max + 1 - val;
  481. if (val2)
  482. val2 = max + 1 - val2;
  483. val = val << shift;
  484. val2 = val2 << shift;
  485. err = snd_soc_update_bits(codec, reg, val_mask, val);
  486. if (err < 0)
  487. return err;
  488. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  489. return err;
  490. }
  491. /*
  492. * FGAIN volume control:
  493. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  494. */
  495. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  496. /*
  497. * CGAIN volume control:
  498. * 0 dB to 12 dB in 6 dB steps
  499. * value 2 and 3 means 12 dB
  500. */
  501. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  502. /*
  503. * Analog playback gain
  504. * -24 dB to 12 dB in 2 dB steps
  505. */
  506. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  507. /*
  508. * Gain controls tied to outputs
  509. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  510. */
  511. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  512. /*
  513. * Capture gain after the ADCs
  514. * from 0 dB to 31 dB in 1 dB steps
  515. */
  516. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  517. /*
  518. * Gain control for input amplifiers
  519. * 0 dB to 30 dB in 6 dB steps
  520. */
  521. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  522. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  523. /* Common playback gain controls */
  524. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  525. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  526. 0, 0x3f, 0, digital_fine_tlv),
  527. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  528. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  529. 0, 0x3f, 0, digital_fine_tlv),
  530. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  531. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  532. 6, 0x2, 0, digital_coarse_tlv),
  533. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  534. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  535. 6, 0x2, 0, digital_coarse_tlv),
  536. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  537. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  538. 3, 0x12, 1, analog_tlv),
  539. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  540. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  541. 3, 0x12, 1, analog_tlv),
  542. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  543. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  544. 1, 1, 0),
  545. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  546. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  547. 1, 1, 0),
  548. /* Separate output gain controls */
  549. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  550. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  551. 4, 3, 0, output_tvl),
  552. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  553. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  554. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  555. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  556. 4, 3, 0, output_tvl),
  557. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  558. TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
  559. /* Common capture gain controls */
  560. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  561. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  562. 0, 0x1f, 0, digital_capture_tlv),
  563. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  564. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  565. 0, 0x1f, 0, digital_capture_tlv),
  566. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  567. 0, 3, 5, 0, input_gain_tlv),
  568. };
  569. /* add non dapm controls */
  570. static int twl4030_add_controls(struct snd_soc_codec *codec)
  571. {
  572. int err, i;
  573. for (i = 0; i < ARRAY_SIZE(twl4030_snd_controls); i++) {
  574. err = snd_ctl_add(codec->card,
  575. snd_soc_cnew(&twl4030_snd_controls[i],
  576. codec, NULL));
  577. if (err < 0)
  578. return err;
  579. }
  580. return 0;
  581. }
  582. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  583. /* Left channel inputs */
  584. SND_SOC_DAPM_INPUT("MAINMIC"),
  585. SND_SOC_DAPM_INPUT("HSMIC"),
  586. SND_SOC_DAPM_INPUT("AUXL"),
  587. SND_SOC_DAPM_INPUT("CARKITMIC"),
  588. /* Right channel inputs */
  589. SND_SOC_DAPM_INPUT("SUBMIC"),
  590. SND_SOC_DAPM_INPUT("AUXR"),
  591. /* Digital microphones (Stereo) */
  592. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  593. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  594. /* Outputs */
  595. SND_SOC_DAPM_OUTPUT("OUTL"),
  596. SND_SOC_DAPM_OUTPUT("OUTR"),
  597. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  598. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  599. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  600. SND_SOC_DAPM_OUTPUT("HSOL"),
  601. SND_SOC_DAPM_OUTPUT("HSOR"),
  602. SND_SOC_DAPM_OUTPUT("CARKITL"),
  603. SND_SOC_DAPM_OUTPUT("CARKITR"),
  604. SND_SOC_DAPM_OUTPUT("HFL"),
  605. SND_SOC_DAPM_OUTPUT("HFR"),
  606. /* DACs */
  607. SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
  608. TWL4030_REG_AVDAC_CTL, 0, 0),
  609. SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
  610. TWL4030_REG_AVDAC_CTL, 1, 0),
  611. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
  612. TWL4030_REG_AVDAC_CTL, 2, 0),
  613. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
  614. TWL4030_REG_AVDAC_CTL, 3, 0),
  615. /* Analog PGAs */
  616. SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
  617. 0, 0, NULL, 0),
  618. SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
  619. 0, 0, NULL, 0),
  620. SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
  621. 0, 0, NULL, 0),
  622. SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
  623. 0, 0, NULL, 0),
  624. /* Output MUX controls */
  625. /* Earpiece */
  626. SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
  627. &twl4030_dapm_earpiece_control),
  628. /* PreDrivL/R */
  629. SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
  630. &twl4030_dapm_predrivel_control),
  631. SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
  632. &twl4030_dapm_predriver_control),
  633. /* HeadsetL/R */
  634. SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
  635. &twl4030_dapm_hsol_control),
  636. SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
  637. &twl4030_dapm_hsor_control),
  638. /* CarkitL/R */
  639. SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
  640. &twl4030_dapm_carkitl_control),
  641. SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
  642. &twl4030_dapm_carkitr_control),
  643. /* HandsfreeL/R */
  644. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  645. &twl4030_dapm_handsfreel_control, handsfree_event,
  646. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  647. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  648. &twl4030_dapm_handsfreer_control, handsfree_event,
  649. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  650. /* Introducing four virtual ADC, since TWL4030 have four channel for
  651. capture */
  652. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  653. SND_SOC_NOPM, 0, 0),
  654. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  655. SND_SOC_NOPM, 0, 0),
  656. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  657. SND_SOC_NOPM, 0, 0),
  658. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  659. SND_SOC_NOPM, 0, 0),
  660. /* Analog/Digital mic path selection.
  661. TX1 Left/Right: either analog Left/Right or Digimic0
  662. TX2 Left/Right: either analog Left/Right or Digimic1 */
  663. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  664. &twl4030_dapm_micpathtx1_control, micpath_event,
  665. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  666. SND_SOC_DAPM_POST_REG),
  667. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  668. &twl4030_dapm_micpathtx2_control, micpath_event,
  669. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  670. SND_SOC_DAPM_POST_REG),
  671. /* Analog input muxes with power switch for the physical ADCL/R */
  672. SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
  673. TWL4030_REG_AVADC_CTL, 3, 0, &twl4030_dapm_analoglmic_control),
  674. SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
  675. TWL4030_REG_AVADC_CTL, 1, 0, &twl4030_dapm_analogrmic_control),
  676. SND_SOC_DAPM_PGA("Analog Left Amplifier",
  677. TWL4030_REG_ANAMICL, 4, 0, NULL, 0),
  678. SND_SOC_DAPM_PGA("Analog Right Amplifier",
  679. TWL4030_REG_ANAMICR, 4, 0, NULL, 0),
  680. SND_SOC_DAPM_PGA("Digimic0 Enable",
  681. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  682. SND_SOC_DAPM_PGA("Digimic1 Enable",
  683. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  684. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  685. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  686. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  687. };
  688. static const struct snd_soc_dapm_route intercon[] = {
  689. {"ARXL1_APGA", NULL, "DAC Left1"},
  690. {"ARXR1_APGA", NULL, "DAC Right1"},
  691. {"ARXL2_APGA", NULL, "DAC Left2"},
  692. {"ARXR2_APGA", NULL, "DAC Right2"},
  693. /* Internal playback routings */
  694. /* Earpiece */
  695. {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
  696. {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
  697. {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
  698. /* PreDrivL */
  699. {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
  700. {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
  701. {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
  702. /* PreDrivR */
  703. {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
  704. {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
  705. {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
  706. /* HeadsetL */
  707. {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
  708. {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
  709. /* HeadsetR */
  710. {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
  711. {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
  712. /* CarkitL */
  713. {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
  714. {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
  715. /* CarkitR */
  716. {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
  717. {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
  718. /* HandsfreeL */
  719. {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
  720. {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
  721. {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
  722. /* HandsfreeR */
  723. {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
  724. {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
  725. {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
  726. /* outputs */
  727. {"OUTL", NULL, "ARXL2_APGA"},
  728. {"OUTR", NULL, "ARXR2_APGA"},
  729. {"EARPIECE", NULL, "Earpiece Mux"},
  730. {"PREDRIVEL", NULL, "PredriveL Mux"},
  731. {"PREDRIVER", NULL, "PredriveR Mux"},
  732. {"HSOL", NULL, "HeadsetL Mux"},
  733. {"HSOR", NULL, "HeadsetR Mux"},
  734. {"CARKITL", NULL, "CarkitL Mux"},
  735. {"CARKITR", NULL, "CarkitR Mux"},
  736. {"HFL", NULL, "HandsfreeL Mux"},
  737. {"HFR", NULL, "HandsfreeR Mux"},
  738. /* Capture path */
  739. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  740. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  741. {"Analog Left Capture Route", "AUXL", "AUXL"},
  742. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  743. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  744. {"Analog Right Capture Route", "AUXR", "AUXR"},
  745. {"Analog Left Amplifier", NULL, "Analog Left Capture Route"},
  746. {"Analog Right Amplifier", NULL, "Analog Right Capture Route"},
  747. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  748. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  749. /* TX1 Left capture path */
  750. {"TX1 Capture Route", "Analog", "Analog Left Amplifier"},
  751. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  752. /* TX1 Right capture path */
  753. {"TX1 Capture Route", "Analog", "Analog Right Amplifier"},
  754. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  755. /* TX2 Left capture path */
  756. {"TX2 Capture Route", "Analog", "Analog Left Amplifier"},
  757. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  758. /* TX2 Right capture path */
  759. {"TX2 Capture Route", "Analog", "Analog Right Amplifier"},
  760. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  761. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  762. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  763. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  764. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  765. };
  766. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  767. {
  768. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  769. ARRAY_SIZE(twl4030_dapm_widgets));
  770. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  771. snd_soc_dapm_new_widgets(codec);
  772. return 0;
  773. }
  774. static void twl4030_power_up(struct snd_soc_codec *codec)
  775. {
  776. u8 anamicl, regmisc1, byte, popn;
  777. int i = 0;
  778. /* set CODECPDZ to turn on codec */
  779. twl4030_set_codecpdz(codec);
  780. /* initiate offset cancellation */
  781. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  782. twl4030_write(codec, TWL4030_REG_ANAMICL,
  783. anamicl | TWL4030_CNCL_OFFSET_START);
  784. /* wait for offset cancellation to complete */
  785. do {
  786. /* this takes a little while, so don't slam i2c */
  787. udelay(2000);
  788. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  789. TWL4030_REG_ANAMICL);
  790. } while ((i++ < 100) &&
  791. ((byte & TWL4030_CNCL_OFFSET_START) ==
  792. TWL4030_CNCL_OFFSET_START));
  793. /* anti-pop when changing analog gain */
  794. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  795. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  796. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  797. /* toggle CODECPDZ as per TRM */
  798. twl4030_clear_codecpdz(codec);
  799. twl4030_set_codecpdz(codec);
  800. /* program anti-pop with bias ramp delay */
  801. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  802. popn &= TWL4030_RAMP_DELAY;
  803. popn |= TWL4030_RAMP_DELAY_645MS;
  804. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  805. popn |= TWL4030_VMID_EN;
  806. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  807. /* enable anti-pop ramp */
  808. popn |= TWL4030_RAMP_EN;
  809. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  810. }
  811. static void twl4030_power_down(struct snd_soc_codec *codec)
  812. {
  813. u8 popn;
  814. /* disable anti-pop ramp */
  815. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  816. popn &= ~TWL4030_RAMP_EN;
  817. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  818. /* disable bias out */
  819. popn &= ~TWL4030_VMID_EN;
  820. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  821. /* power down */
  822. twl4030_clear_codecpdz(codec);
  823. }
  824. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  825. enum snd_soc_bias_level level)
  826. {
  827. switch (level) {
  828. case SND_SOC_BIAS_ON:
  829. twl4030_power_up(codec);
  830. break;
  831. case SND_SOC_BIAS_PREPARE:
  832. /* TODO: develop a twl4030_prepare function */
  833. break;
  834. case SND_SOC_BIAS_STANDBY:
  835. /* TODO: develop a twl4030_standby function */
  836. twl4030_power_down(codec);
  837. break;
  838. case SND_SOC_BIAS_OFF:
  839. twl4030_power_down(codec);
  840. break;
  841. }
  842. codec->bias_level = level;
  843. return 0;
  844. }
  845. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  846. struct snd_pcm_hw_params *params,
  847. struct snd_soc_dai *dai)
  848. {
  849. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  850. struct snd_soc_device *socdev = rtd->socdev;
  851. struct snd_soc_codec *codec = socdev->codec;
  852. u8 mode, old_mode, format, old_format;
  853. /* bit rate */
  854. old_mode = twl4030_read_reg_cache(codec,
  855. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  856. mode = old_mode & ~TWL4030_APLL_RATE;
  857. switch (params_rate(params)) {
  858. case 8000:
  859. mode |= TWL4030_APLL_RATE_8000;
  860. break;
  861. case 11025:
  862. mode |= TWL4030_APLL_RATE_11025;
  863. break;
  864. case 12000:
  865. mode |= TWL4030_APLL_RATE_12000;
  866. break;
  867. case 16000:
  868. mode |= TWL4030_APLL_RATE_16000;
  869. break;
  870. case 22050:
  871. mode |= TWL4030_APLL_RATE_22050;
  872. break;
  873. case 24000:
  874. mode |= TWL4030_APLL_RATE_24000;
  875. break;
  876. case 32000:
  877. mode |= TWL4030_APLL_RATE_32000;
  878. break;
  879. case 44100:
  880. mode |= TWL4030_APLL_RATE_44100;
  881. break;
  882. case 48000:
  883. mode |= TWL4030_APLL_RATE_48000;
  884. break;
  885. default:
  886. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  887. params_rate(params));
  888. return -EINVAL;
  889. }
  890. if (mode != old_mode) {
  891. /* change rate and set CODECPDZ */
  892. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  893. twl4030_set_codecpdz(codec);
  894. }
  895. /* sample size */
  896. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  897. format = old_format;
  898. format &= ~TWL4030_DATA_WIDTH;
  899. switch (params_format(params)) {
  900. case SNDRV_PCM_FORMAT_S16_LE:
  901. format |= TWL4030_DATA_WIDTH_16S_16W;
  902. break;
  903. case SNDRV_PCM_FORMAT_S24_LE:
  904. format |= TWL4030_DATA_WIDTH_32S_24W;
  905. break;
  906. default:
  907. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  908. params_format(params));
  909. return -EINVAL;
  910. }
  911. if (format != old_format) {
  912. /* clear CODECPDZ before changing format (codec requirement) */
  913. twl4030_clear_codecpdz(codec);
  914. /* change format */
  915. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  916. /* set CODECPDZ afterwards */
  917. twl4030_set_codecpdz(codec);
  918. }
  919. return 0;
  920. }
  921. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  922. int clk_id, unsigned int freq, int dir)
  923. {
  924. struct snd_soc_codec *codec = codec_dai->codec;
  925. u8 infreq;
  926. switch (freq) {
  927. case 19200000:
  928. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  929. break;
  930. case 26000000:
  931. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  932. break;
  933. case 38400000:
  934. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  935. break;
  936. default:
  937. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  938. freq);
  939. return -EINVAL;
  940. }
  941. infreq |= TWL4030_APLL_EN;
  942. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  943. return 0;
  944. }
  945. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  946. unsigned int fmt)
  947. {
  948. struct snd_soc_codec *codec = codec_dai->codec;
  949. u8 old_format, format;
  950. /* get format */
  951. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  952. format = old_format;
  953. /* set master/slave audio interface */
  954. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  955. case SND_SOC_DAIFMT_CBM_CFM:
  956. format &= ~(TWL4030_AIF_SLAVE_EN);
  957. format &= ~(TWL4030_CLK256FS_EN);
  958. break;
  959. case SND_SOC_DAIFMT_CBS_CFS:
  960. format |= TWL4030_AIF_SLAVE_EN;
  961. format |= TWL4030_CLK256FS_EN;
  962. break;
  963. default:
  964. return -EINVAL;
  965. }
  966. /* interface format */
  967. format &= ~TWL4030_AIF_FORMAT;
  968. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  969. case SND_SOC_DAIFMT_I2S:
  970. format |= TWL4030_AIF_FORMAT_CODEC;
  971. break;
  972. default:
  973. return -EINVAL;
  974. }
  975. if (format != old_format) {
  976. /* clear CODECPDZ before changing format (codec requirement) */
  977. twl4030_clear_codecpdz(codec);
  978. /* change format */
  979. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  980. /* set CODECPDZ afterwards */
  981. twl4030_set_codecpdz(codec);
  982. }
  983. return 0;
  984. }
  985. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  986. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  987. struct snd_soc_dai twl4030_dai = {
  988. .name = "twl4030",
  989. .playback = {
  990. .stream_name = "Playback",
  991. .channels_min = 2,
  992. .channels_max = 2,
  993. .rates = TWL4030_RATES,
  994. .formats = TWL4030_FORMATS,},
  995. .capture = {
  996. .stream_name = "Capture",
  997. .channels_min = 2,
  998. .channels_max = 2,
  999. .rates = TWL4030_RATES,
  1000. .formats = TWL4030_FORMATS,},
  1001. .ops = {
  1002. .hw_params = twl4030_hw_params,
  1003. .set_sysclk = twl4030_set_dai_sysclk,
  1004. .set_fmt = twl4030_set_dai_fmt,
  1005. }
  1006. };
  1007. EXPORT_SYMBOL_GPL(twl4030_dai);
  1008. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1009. {
  1010. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1011. struct snd_soc_codec *codec = socdev->codec;
  1012. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1013. return 0;
  1014. }
  1015. static int twl4030_resume(struct platform_device *pdev)
  1016. {
  1017. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1018. struct snd_soc_codec *codec = socdev->codec;
  1019. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1020. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1021. return 0;
  1022. }
  1023. /*
  1024. * initialize the driver
  1025. * register the mixer and dsp interfaces with the kernel
  1026. */
  1027. static int twl4030_init(struct snd_soc_device *socdev)
  1028. {
  1029. struct snd_soc_codec *codec = socdev->codec;
  1030. int ret = 0;
  1031. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1032. codec->name = "twl4030";
  1033. codec->owner = THIS_MODULE;
  1034. codec->read = twl4030_read_reg_cache;
  1035. codec->write = twl4030_write;
  1036. codec->set_bias_level = twl4030_set_bias_level;
  1037. codec->dai = &twl4030_dai;
  1038. codec->num_dai = 1;
  1039. codec->reg_cache_size = sizeof(twl4030_reg);
  1040. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1041. GFP_KERNEL);
  1042. if (codec->reg_cache == NULL)
  1043. return -ENOMEM;
  1044. /* register pcms */
  1045. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1046. if (ret < 0) {
  1047. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1048. goto pcm_err;
  1049. }
  1050. twl4030_init_chip(codec);
  1051. /* power on device */
  1052. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1053. twl4030_add_controls(codec);
  1054. twl4030_add_widgets(codec);
  1055. ret = snd_soc_init_card(socdev);
  1056. if (ret < 0) {
  1057. printk(KERN_ERR "twl4030: failed to register card\n");
  1058. goto card_err;
  1059. }
  1060. return ret;
  1061. card_err:
  1062. snd_soc_free_pcms(socdev);
  1063. snd_soc_dapm_free(socdev);
  1064. pcm_err:
  1065. kfree(codec->reg_cache);
  1066. return ret;
  1067. }
  1068. static struct snd_soc_device *twl4030_socdev;
  1069. static int twl4030_probe(struct platform_device *pdev)
  1070. {
  1071. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1072. struct snd_soc_codec *codec;
  1073. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1074. if (codec == NULL)
  1075. return -ENOMEM;
  1076. socdev->codec = codec;
  1077. mutex_init(&codec->mutex);
  1078. INIT_LIST_HEAD(&codec->dapm_widgets);
  1079. INIT_LIST_HEAD(&codec->dapm_paths);
  1080. twl4030_socdev = socdev;
  1081. twl4030_init(socdev);
  1082. return 0;
  1083. }
  1084. static int twl4030_remove(struct platform_device *pdev)
  1085. {
  1086. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1087. struct snd_soc_codec *codec = socdev->codec;
  1088. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1089. snd_soc_free_pcms(socdev);
  1090. snd_soc_dapm_free(socdev);
  1091. kfree(codec);
  1092. return 0;
  1093. }
  1094. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1095. .probe = twl4030_probe,
  1096. .remove = twl4030_remove,
  1097. .suspend = twl4030_suspend,
  1098. .resume = twl4030_resume,
  1099. };
  1100. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1101. static int __init twl4030_modinit(void)
  1102. {
  1103. return snd_soc_register_dai(&twl4030_dai);
  1104. }
  1105. module_init(twl4030_modinit);
  1106. static void __exit twl4030_exit(void)
  1107. {
  1108. snd_soc_unregister_dai(&twl4030_dai);
  1109. }
  1110. module_exit(twl4030_exit);
  1111. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1112. MODULE_AUTHOR("Steve Sakoman");
  1113. MODULE_LICENSE("GPL");