dmaengine.c 26 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #include <linux/init.h>
  47. #include <linux/module.h>
  48. #include <linux/mm.h>
  49. #include <linux/device.h>
  50. #include <linux/dmaengine.h>
  51. #include <linux/hardirq.h>
  52. #include <linux/spinlock.h>
  53. #include <linux/percpu.h>
  54. #include <linux/rcupdate.h>
  55. #include <linux/mutex.h>
  56. #include <linux/jiffies.h>
  57. #include <linux/rculist.h>
  58. #include <linux/idr.h>
  59. static DEFINE_MUTEX(dma_list_mutex);
  60. static LIST_HEAD(dma_device_list);
  61. static long dmaengine_ref_count;
  62. static struct idr dma_idr;
  63. /* --- sysfs implementation --- */
  64. /**
  65. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  66. * @dev - device node
  67. *
  68. * Must be called under dma_list_mutex
  69. */
  70. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  71. {
  72. struct dma_chan_dev *chan_dev;
  73. chan_dev = container_of(dev, typeof(*chan_dev), device);
  74. return chan_dev->chan;
  75. }
  76. static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
  77. {
  78. struct dma_chan *chan;
  79. unsigned long count = 0;
  80. int i;
  81. int err;
  82. mutex_lock(&dma_list_mutex);
  83. chan = dev_to_dma_chan(dev);
  84. if (chan) {
  85. for_each_possible_cpu(i)
  86. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  87. err = sprintf(buf, "%lu\n", count);
  88. } else
  89. err = -ENODEV;
  90. mutex_unlock(&dma_list_mutex);
  91. return err;
  92. }
  93. static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
  94. char *buf)
  95. {
  96. struct dma_chan *chan;
  97. unsigned long count = 0;
  98. int i;
  99. int err;
  100. mutex_lock(&dma_list_mutex);
  101. chan = dev_to_dma_chan(dev);
  102. if (chan) {
  103. for_each_possible_cpu(i)
  104. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  105. err = sprintf(buf, "%lu\n", count);
  106. } else
  107. err = -ENODEV;
  108. mutex_unlock(&dma_list_mutex);
  109. return err;
  110. }
  111. static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
  112. {
  113. struct dma_chan *chan;
  114. int err;
  115. mutex_lock(&dma_list_mutex);
  116. chan = dev_to_dma_chan(dev);
  117. if (chan)
  118. err = sprintf(buf, "%d\n", chan->client_count);
  119. else
  120. err = -ENODEV;
  121. mutex_unlock(&dma_list_mutex);
  122. return err;
  123. }
  124. static struct device_attribute dma_attrs[] = {
  125. __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
  126. __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
  127. __ATTR(in_use, S_IRUGO, show_in_use, NULL),
  128. __ATTR_NULL
  129. };
  130. static void chan_dev_release(struct device *dev)
  131. {
  132. struct dma_chan_dev *chan_dev;
  133. chan_dev = container_of(dev, typeof(*chan_dev), device);
  134. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  135. mutex_lock(&dma_list_mutex);
  136. idr_remove(&dma_idr, chan_dev->dev_id);
  137. mutex_unlock(&dma_list_mutex);
  138. kfree(chan_dev->idr_ref);
  139. }
  140. kfree(chan_dev);
  141. }
  142. static struct class dma_devclass = {
  143. .name = "dma",
  144. .dev_attrs = dma_attrs,
  145. .dev_release = chan_dev_release,
  146. };
  147. /* --- client and device registration --- */
  148. #define dma_device_satisfies_mask(device, mask) \
  149. __dma_device_satisfies_mask((device), &(mask))
  150. static int
  151. __dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
  152. {
  153. dma_cap_mask_t has;
  154. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  155. DMA_TX_TYPE_END);
  156. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  157. }
  158. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  159. {
  160. return chan->device->dev->driver->owner;
  161. }
  162. /**
  163. * balance_ref_count - catch up the channel reference count
  164. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  165. *
  166. * balance_ref_count must be called under dma_list_mutex
  167. */
  168. static void balance_ref_count(struct dma_chan *chan)
  169. {
  170. struct module *owner = dma_chan_to_owner(chan);
  171. while (chan->client_count < dmaengine_ref_count) {
  172. __module_get(owner);
  173. chan->client_count++;
  174. }
  175. }
  176. /**
  177. * dma_chan_get - try to grab a dma channel's parent driver module
  178. * @chan - channel to grab
  179. *
  180. * Must be called under dma_list_mutex
  181. */
  182. static int dma_chan_get(struct dma_chan *chan)
  183. {
  184. int err = -ENODEV;
  185. struct module *owner = dma_chan_to_owner(chan);
  186. if (chan->client_count) {
  187. __module_get(owner);
  188. err = 0;
  189. } else if (try_module_get(owner))
  190. err = 0;
  191. if (err == 0)
  192. chan->client_count++;
  193. /* allocate upon first client reference */
  194. if (chan->client_count == 1 && err == 0) {
  195. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  196. if (desc_cnt < 0) {
  197. err = desc_cnt;
  198. chan->client_count = 0;
  199. module_put(owner);
  200. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  201. balance_ref_count(chan);
  202. }
  203. return err;
  204. }
  205. /**
  206. * dma_chan_put - drop a reference to a dma channel's parent driver module
  207. * @chan - channel to release
  208. *
  209. * Must be called under dma_list_mutex
  210. */
  211. static void dma_chan_put(struct dma_chan *chan)
  212. {
  213. if (!chan->client_count)
  214. return; /* this channel failed alloc_chan_resources */
  215. chan->client_count--;
  216. module_put(dma_chan_to_owner(chan));
  217. if (chan->client_count == 0)
  218. chan->device->device_free_chan_resources(chan);
  219. }
  220. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  221. {
  222. enum dma_status status;
  223. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  224. dma_async_issue_pending(chan);
  225. do {
  226. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  227. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  228. printk(KERN_ERR "dma_sync_wait_timeout!\n");
  229. return DMA_ERROR;
  230. }
  231. } while (status == DMA_IN_PROGRESS);
  232. return status;
  233. }
  234. EXPORT_SYMBOL(dma_sync_wait);
  235. /**
  236. * dma_cap_mask_all - enable iteration over all operation types
  237. */
  238. static dma_cap_mask_t dma_cap_mask_all;
  239. /**
  240. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  241. * @chan - associated channel for this entry
  242. */
  243. struct dma_chan_tbl_ent {
  244. struct dma_chan *chan;
  245. };
  246. /**
  247. * channel_table - percpu lookup table for memory-to-memory offload providers
  248. */
  249. static struct dma_chan_tbl_ent *channel_table[DMA_TX_TYPE_END];
  250. static int __init dma_channel_table_init(void)
  251. {
  252. enum dma_transaction_type cap;
  253. int err = 0;
  254. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  255. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  256. * but are not associated with an operation so they do not need
  257. * an entry in the channel_table
  258. */
  259. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  260. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  261. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  262. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  263. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  264. if (!channel_table[cap]) {
  265. err = -ENOMEM;
  266. break;
  267. }
  268. }
  269. if (err) {
  270. pr_err("dmaengine: initialization failure\n");
  271. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  272. if (channel_table[cap])
  273. free_percpu(channel_table[cap]);
  274. }
  275. return err;
  276. }
  277. arch_initcall(dma_channel_table_init);
  278. /**
  279. * dma_find_channel - find a channel to carry out the operation
  280. * @tx_type: transaction type
  281. */
  282. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  283. {
  284. struct dma_chan *chan;
  285. int cpu;
  286. WARN_ONCE(dmaengine_ref_count == 0,
  287. "client called %s without a reference", __func__);
  288. cpu = get_cpu();
  289. chan = per_cpu_ptr(channel_table[tx_type], cpu)->chan;
  290. put_cpu();
  291. return chan;
  292. }
  293. EXPORT_SYMBOL(dma_find_channel);
  294. /**
  295. * dma_issue_pending_all - flush all pending operations across all channels
  296. */
  297. void dma_issue_pending_all(void)
  298. {
  299. struct dma_device *device;
  300. struct dma_chan *chan;
  301. WARN_ONCE(dmaengine_ref_count == 0,
  302. "client called %s without a reference", __func__);
  303. rcu_read_lock();
  304. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  305. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  306. continue;
  307. list_for_each_entry(chan, &device->channels, device_node)
  308. if (chan->client_count)
  309. device->device_issue_pending(chan);
  310. }
  311. rcu_read_unlock();
  312. }
  313. EXPORT_SYMBOL(dma_issue_pending_all);
  314. /**
  315. * nth_chan - returns the nth channel of the given capability
  316. * @cap: capability to match
  317. * @n: nth channel desired
  318. *
  319. * Defaults to returning the channel with the desired capability and the
  320. * lowest reference count when 'n' cannot be satisfied. Must be called
  321. * under dma_list_mutex.
  322. */
  323. static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
  324. {
  325. struct dma_device *device;
  326. struct dma_chan *chan;
  327. struct dma_chan *ret = NULL;
  328. struct dma_chan *min = NULL;
  329. list_for_each_entry(device, &dma_device_list, global_node) {
  330. if (!dma_has_cap(cap, device->cap_mask) ||
  331. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  332. continue;
  333. list_for_each_entry(chan, &device->channels, device_node) {
  334. if (!chan->client_count)
  335. continue;
  336. if (!min)
  337. min = chan;
  338. else if (chan->table_count < min->table_count)
  339. min = chan;
  340. if (n-- == 0) {
  341. ret = chan;
  342. break; /* done */
  343. }
  344. }
  345. if (ret)
  346. break; /* done */
  347. }
  348. if (!ret)
  349. ret = min;
  350. if (ret)
  351. ret->table_count++;
  352. return ret;
  353. }
  354. /**
  355. * dma_channel_rebalance - redistribute the available channels
  356. *
  357. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  358. * operation type) in the SMP case, and operation isolation (avoid
  359. * multi-tasking channels) in the non-SMP case. Must be called under
  360. * dma_list_mutex.
  361. */
  362. static void dma_channel_rebalance(void)
  363. {
  364. struct dma_chan *chan;
  365. struct dma_device *device;
  366. int cpu;
  367. int cap;
  368. int n;
  369. /* undo the last distribution */
  370. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  371. for_each_possible_cpu(cpu)
  372. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  373. list_for_each_entry(device, &dma_device_list, global_node) {
  374. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  375. continue;
  376. list_for_each_entry(chan, &device->channels, device_node)
  377. chan->table_count = 0;
  378. }
  379. /* don't populate the channel_table if no clients are available */
  380. if (!dmaengine_ref_count)
  381. return;
  382. /* redistribute available channels */
  383. n = 0;
  384. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  385. for_each_online_cpu(cpu) {
  386. if (num_possible_cpus() > 1)
  387. chan = nth_chan(cap, n++);
  388. else
  389. chan = nth_chan(cap, -1);
  390. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  391. }
  392. }
  393. static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
  394. dma_filter_fn fn, void *fn_param)
  395. {
  396. struct dma_chan *chan;
  397. if (!__dma_device_satisfies_mask(dev, mask)) {
  398. pr_debug("%s: wrong capabilities\n", __func__);
  399. return NULL;
  400. }
  401. /* devices with multiple channels need special handling as we need to
  402. * ensure that all channels are either private or public.
  403. */
  404. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  405. list_for_each_entry(chan, &dev->channels, device_node) {
  406. /* some channels are already publicly allocated */
  407. if (chan->client_count)
  408. return NULL;
  409. }
  410. list_for_each_entry(chan, &dev->channels, device_node) {
  411. if (chan->client_count) {
  412. pr_debug("%s: %s busy\n",
  413. __func__, dma_chan_name(chan));
  414. continue;
  415. }
  416. if (fn && !fn(chan, fn_param)) {
  417. pr_debug("%s: %s filter said false\n",
  418. __func__, dma_chan_name(chan));
  419. continue;
  420. }
  421. return chan;
  422. }
  423. return NULL;
  424. }
  425. /**
  426. * dma_request_channel - try to allocate an exclusive channel
  427. * @mask: capabilities that the channel must satisfy
  428. * @fn: optional callback to disposition available channels
  429. * @fn_param: opaque parameter to pass to dma_filter_fn
  430. */
  431. struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
  432. {
  433. struct dma_device *device, *_d;
  434. struct dma_chan *chan = NULL;
  435. int err;
  436. /* Find a channel */
  437. mutex_lock(&dma_list_mutex);
  438. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  439. chan = private_candidate(mask, device, fn, fn_param);
  440. if (chan) {
  441. /* Found a suitable channel, try to grab, prep, and
  442. * return it. We first set DMA_PRIVATE to disable
  443. * balance_ref_count as this channel will not be
  444. * published in the general-purpose allocator
  445. */
  446. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  447. err = dma_chan_get(chan);
  448. if (err == -ENODEV) {
  449. pr_debug("%s: %s module removed\n", __func__,
  450. dma_chan_name(chan));
  451. list_del_rcu(&device->global_node);
  452. } else if (err)
  453. pr_err("dmaengine: failed to get %s: (%d)\n",
  454. dma_chan_name(chan), err);
  455. else
  456. break;
  457. chan = NULL;
  458. }
  459. }
  460. mutex_unlock(&dma_list_mutex);
  461. pr_debug("%s: %s (%s)\n", __func__, chan ? "success" : "fail",
  462. chan ? dma_chan_name(chan) : NULL);
  463. return chan;
  464. }
  465. EXPORT_SYMBOL_GPL(__dma_request_channel);
  466. void dma_release_channel(struct dma_chan *chan)
  467. {
  468. mutex_lock(&dma_list_mutex);
  469. WARN_ONCE(chan->client_count != 1,
  470. "chan reference count %d != 1\n", chan->client_count);
  471. dma_chan_put(chan);
  472. mutex_unlock(&dma_list_mutex);
  473. }
  474. EXPORT_SYMBOL_GPL(dma_release_channel);
  475. /**
  476. * dmaengine_get - register interest in dma_channels
  477. */
  478. void dmaengine_get(void)
  479. {
  480. struct dma_device *device, *_d;
  481. struct dma_chan *chan;
  482. int err;
  483. mutex_lock(&dma_list_mutex);
  484. dmaengine_ref_count++;
  485. /* try to grab channels */
  486. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  487. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  488. continue;
  489. list_for_each_entry(chan, &device->channels, device_node) {
  490. err = dma_chan_get(chan);
  491. if (err == -ENODEV) {
  492. /* module removed before we could use it */
  493. list_del_rcu(&device->global_node);
  494. break;
  495. } else if (err)
  496. pr_err("dmaengine: failed to get %s: (%d)\n",
  497. dma_chan_name(chan), err);
  498. }
  499. }
  500. /* if this is the first reference and there were channels
  501. * waiting we need to rebalance to get those channels
  502. * incorporated into the channel table
  503. */
  504. if (dmaengine_ref_count == 1)
  505. dma_channel_rebalance();
  506. mutex_unlock(&dma_list_mutex);
  507. }
  508. EXPORT_SYMBOL(dmaengine_get);
  509. /**
  510. * dmaengine_put - let dma drivers be removed when ref_count == 0
  511. */
  512. void dmaengine_put(void)
  513. {
  514. struct dma_device *device;
  515. struct dma_chan *chan;
  516. mutex_lock(&dma_list_mutex);
  517. dmaengine_ref_count--;
  518. BUG_ON(dmaengine_ref_count < 0);
  519. /* drop channel references */
  520. list_for_each_entry(device, &dma_device_list, global_node) {
  521. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  522. continue;
  523. list_for_each_entry(chan, &device->channels, device_node)
  524. dma_chan_put(chan);
  525. }
  526. mutex_unlock(&dma_list_mutex);
  527. }
  528. EXPORT_SYMBOL(dmaengine_put);
  529. /**
  530. * dma_async_device_register - registers DMA devices found
  531. * @device: &dma_device
  532. */
  533. int dma_async_device_register(struct dma_device *device)
  534. {
  535. int chancnt = 0, rc;
  536. struct dma_chan* chan;
  537. atomic_t *idr_ref;
  538. if (!device)
  539. return -ENODEV;
  540. /* validate device routines */
  541. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  542. !device->device_prep_dma_memcpy);
  543. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  544. !device->device_prep_dma_xor);
  545. BUG_ON(dma_has_cap(DMA_ZERO_SUM, device->cap_mask) &&
  546. !device->device_prep_dma_zero_sum);
  547. BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
  548. !device->device_prep_dma_memset);
  549. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  550. !device->device_prep_dma_interrupt);
  551. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  552. !device->device_prep_slave_sg);
  553. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  554. !device->device_terminate_all);
  555. BUG_ON(!device->device_alloc_chan_resources);
  556. BUG_ON(!device->device_free_chan_resources);
  557. BUG_ON(!device->device_is_tx_complete);
  558. BUG_ON(!device->device_issue_pending);
  559. BUG_ON(!device->dev);
  560. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  561. if (!idr_ref)
  562. return -ENOMEM;
  563. atomic_set(idr_ref, 0);
  564. idr_retry:
  565. if (!idr_pre_get(&dma_idr, GFP_KERNEL))
  566. return -ENOMEM;
  567. mutex_lock(&dma_list_mutex);
  568. rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
  569. mutex_unlock(&dma_list_mutex);
  570. if (rc == -EAGAIN)
  571. goto idr_retry;
  572. else if (rc != 0)
  573. return rc;
  574. /* represent channels in sysfs. Probably want devs too */
  575. list_for_each_entry(chan, &device->channels, device_node) {
  576. chan->local = alloc_percpu(typeof(*chan->local));
  577. if (chan->local == NULL)
  578. continue;
  579. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  580. if (chan->dev == NULL) {
  581. free_percpu(chan->local);
  582. continue;
  583. }
  584. chan->chan_id = chancnt++;
  585. chan->dev->device.class = &dma_devclass;
  586. chan->dev->device.parent = device->dev;
  587. chan->dev->chan = chan;
  588. chan->dev->idr_ref = idr_ref;
  589. chan->dev->dev_id = device->dev_id;
  590. atomic_inc(idr_ref);
  591. dev_set_name(&chan->dev->device, "dma%dchan%d",
  592. device->dev_id, chan->chan_id);
  593. rc = device_register(&chan->dev->device);
  594. if (rc) {
  595. free_percpu(chan->local);
  596. chan->local = NULL;
  597. goto err_out;
  598. }
  599. chan->client_count = 0;
  600. }
  601. device->chancnt = chancnt;
  602. mutex_lock(&dma_list_mutex);
  603. /* take references on public channels */
  604. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  605. list_for_each_entry(chan, &device->channels, device_node) {
  606. /* if clients are already waiting for channels we need
  607. * to take references on their behalf
  608. */
  609. if (dma_chan_get(chan) == -ENODEV) {
  610. /* note we can only get here for the first
  611. * channel as the remaining channels are
  612. * guaranteed to get a reference
  613. */
  614. rc = -ENODEV;
  615. mutex_unlock(&dma_list_mutex);
  616. goto err_out;
  617. }
  618. }
  619. list_add_tail_rcu(&device->global_node, &dma_device_list);
  620. dma_channel_rebalance();
  621. mutex_unlock(&dma_list_mutex);
  622. return 0;
  623. err_out:
  624. list_for_each_entry(chan, &device->channels, device_node) {
  625. if (chan->local == NULL)
  626. continue;
  627. mutex_lock(&dma_list_mutex);
  628. chan->dev->chan = NULL;
  629. mutex_unlock(&dma_list_mutex);
  630. device_unregister(&chan->dev->device);
  631. free_percpu(chan->local);
  632. }
  633. return rc;
  634. }
  635. EXPORT_SYMBOL(dma_async_device_register);
  636. /**
  637. * dma_async_device_unregister - unregister a DMA device
  638. * @device: &dma_device
  639. *
  640. * This routine is called by dma driver exit routines, dmaengine holds module
  641. * references to prevent it being called while channels are in use.
  642. */
  643. void dma_async_device_unregister(struct dma_device *device)
  644. {
  645. struct dma_chan *chan;
  646. mutex_lock(&dma_list_mutex);
  647. list_del_rcu(&device->global_node);
  648. dma_channel_rebalance();
  649. mutex_unlock(&dma_list_mutex);
  650. list_for_each_entry(chan, &device->channels, device_node) {
  651. WARN_ONCE(chan->client_count,
  652. "%s called while %d clients hold a reference\n",
  653. __func__, chan->client_count);
  654. mutex_lock(&dma_list_mutex);
  655. chan->dev->chan = NULL;
  656. mutex_unlock(&dma_list_mutex);
  657. device_unregister(&chan->dev->device);
  658. }
  659. }
  660. EXPORT_SYMBOL(dma_async_device_unregister);
  661. /**
  662. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  663. * @chan: DMA channel to offload copy to
  664. * @dest: destination address (virtual)
  665. * @src: source address (virtual)
  666. * @len: length
  667. *
  668. * Both @dest and @src must be mappable to a bus address according to the
  669. * DMA mapping API rules for streaming mappings.
  670. * Both @dest and @src must stay memory resident (kernel memory or locked
  671. * user space pages).
  672. */
  673. dma_cookie_t
  674. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  675. void *src, size_t len)
  676. {
  677. struct dma_device *dev = chan->device;
  678. struct dma_async_tx_descriptor *tx;
  679. dma_addr_t dma_dest, dma_src;
  680. dma_cookie_t cookie;
  681. int cpu;
  682. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  683. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  684. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
  685. DMA_CTRL_ACK);
  686. if (!tx) {
  687. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  688. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  689. return -ENOMEM;
  690. }
  691. tx->callback = NULL;
  692. cookie = tx->tx_submit(tx);
  693. cpu = get_cpu();
  694. per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
  695. per_cpu_ptr(chan->local, cpu)->memcpy_count++;
  696. put_cpu();
  697. return cookie;
  698. }
  699. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  700. /**
  701. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  702. * @chan: DMA channel to offload copy to
  703. * @page: destination page
  704. * @offset: offset in page to copy to
  705. * @kdata: source address (virtual)
  706. * @len: length
  707. *
  708. * Both @page/@offset and @kdata must be mappable to a bus address according
  709. * to the DMA mapping API rules for streaming mappings.
  710. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  711. * locked user space pages)
  712. */
  713. dma_cookie_t
  714. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  715. unsigned int offset, void *kdata, size_t len)
  716. {
  717. struct dma_device *dev = chan->device;
  718. struct dma_async_tx_descriptor *tx;
  719. dma_addr_t dma_dest, dma_src;
  720. dma_cookie_t cookie;
  721. int cpu;
  722. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  723. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  724. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
  725. DMA_CTRL_ACK);
  726. if (!tx) {
  727. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  728. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  729. return -ENOMEM;
  730. }
  731. tx->callback = NULL;
  732. cookie = tx->tx_submit(tx);
  733. cpu = get_cpu();
  734. per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
  735. per_cpu_ptr(chan->local, cpu)->memcpy_count++;
  736. put_cpu();
  737. return cookie;
  738. }
  739. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  740. /**
  741. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  742. * @chan: DMA channel to offload copy to
  743. * @dest_pg: destination page
  744. * @dest_off: offset in page to copy to
  745. * @src_pg: source page
  746. * @src_off: offset in page to copy from
  747. * @len: length
  748. *
  749. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  750. * address according to the DMA mapping API rules for streaming mappings.
  751. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  752. * (kernel memory or locked user space pages).
  753. */
  754. dma_cookie_t
  755. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  756. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  757. size_t len)
  758. {
  759. struct dma_device *dev = chan->device;
  760. struct dma_async_tx_descriptor *tx;
  761. dma_addr_t dma_dest, dma_src;
  762. dma_cookie_t cookie;
  763. int cpu;
  764. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  765. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  766. DMA_FROM_DEVICE);
  767. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len,
  768. DMA_CTRL_ACK);
  769. if (!tx) {
  770. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  771. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  772. return -ENOMEM;
  773. }
  774. tx->callback = NULL;
  775. cookie = tx->tx_submit(tx);
  776. cpu = get_cpu();
  777. per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
  778. per_cpu_ptr(chan->local, cpu)->memcpy_count++;
  779. put_cpu();
  780. return cookie;
  781. }
  782. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  783. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  784. struct dma_chan *chan)
  785. {
  786. tx->chan = chan;
  787. spin_lock_init(&tx->lock);
  788. }
  789. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  790. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  791. * @tx: in-flight transaction to wait on
  792. *
  793. * This routine assumes that tx was obtained from a call to async_memcpy,
  794. * async_xor, async_memset, etc which ensures that tx is "in-flight" (prepped
  795. * and submitted). Walking the parent chain is only meant to cover for DMA
  796. * drivers that do not implement the DMA_INTERRUPT capability and may race with
  797. * the driver's descriptor cleanup routine.
  798. */
  799. enum dma_status
  800. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  801. {
  802. enum dma_status status;
  803. struct dma_async_tx_descriptor *iter;
  804. struct dma_async_tx_descriptor *parent;
  805. if (!tx)
  806. return DMA_SUCCESS;
  807. WARN_ONCE(tx->parent, "%s: speculatively walking dependency chain for"
  808. " %s\n", __func__, dma_chan_name(tx->chan));
  809. /* poll through the dependency chain, return when tx is complete */
  810. do {
  811. iter = tx;
  812. /* find the root of the unsubmitted dependency chain */
  813. do {
  814. parent = iter->parent;
  815. if (!parent)
  816. break;
  817. else
  818. iter = parent;
  819. } while (parent);
  820. /* there is a small window for ->parent == NULL and
  821. * ->cookie == -EBUSY
  822. */
  823. while (iter->cookie == -EBUSY)
  824. cpu_relax();
  825. status = dma_sync_wait(iter->chan, iter->cookie);
  826. } while (status == DMA_IN_PROGRESS || (iter != tx));
  827. return status;
  828. }
  829. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  830. /* dma_run_dependencies - helper routine for dma drivers to process
  831. * (start) dependent operations on their target channel
  832. * @tx: transaction with dependencies
  833. */
  834. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  835. {
  836. struct dma_async_tx_descriptor *dep = tx->next;
  837. struct dma_async_tx_descriptor *dep_next;
  838. struct dma_chan *chan;
  839. if (!dep)
  840. return;
  841. chan = dep->chan;
  842. /* keep submitting up until a channel switch is detected
  843. * in that case we will be called again as a result of
  844. * processing the interrupt from async_tx_channel_switch
  845. */
  846. for (; dep; dep = dep_next) {
  847. spin_lock_bh(&dep->lock);
  848. dep->parent = NULL;
  849. dep_next = dep->next;
  850. if (dep_next && dep_next->chan == chan)
  851. dep->next = NULL; /* ->next will be submitted */
  852. else
  853. dep_next = NULL; /* submit current dep and terminate */
  854. spin_unlock_bh(&dep->lock);
  855. dep->tx_submit(dep);
  856. }
  857. chan->device->device_issue_pending(chan);
  858. }
  859. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  860. static int __init dma_bus_init(void)
  861. {
  862. idr_init(&dma_idr);
  863. mutex_init(&dma_list_mutex);
  864. return class_register(&dma_devclass);
  865. }
  866. arch_initcall(dma_bus_init);