mcbsp.c 6.5 KB

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  1. /*
  2. * linux/arch/arm/mach-omap1/mcbsp.c
  3. *
  4. * Copyright (C) 2008 Instituto Nokia de Tecnologia
  5. * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Multichannel mode not supported.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/clk.h>
  16. #include <linux/err.h>
  17. #include <linux/io.h>
  18. #include <linux/platform_device.h>
  19. #include <mach/dma.h>
  20. #include <mach/irqs.h>
  21. #include <mach/mux.h>
  22. #include <mach/cpu.h>
  23. #include <mach/mcbsp.h>
  24. #include <mach/dsp_common.h>
  25. #define DPS_RSTCT2_PER_EN (1 << 0)
  26. #define DSP_RSTCT2_WD_PER_EN (1 << 1)
  27. struct mcbsp_internal_clk {
  28. struct clk clk;
  29. struct clk **childs;
  30. int n_childs;
  31. };
  32. #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  33. static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
  34. {
  35. const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
  36. int i;
  37. mclk->n_childs = ARRAY_SIZE(clk_names);
  38. mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
  39. GFP_KERNEL);
  40. for (i = 0; i < mclk->n_childs; i++) {
  41. /* We fake a platform device to get correct device id */
  42. struct platform_device pdev;
  43. pdev.dev.bus = &platform_bus_type;
  44. pdev.id = mclk->clk.id;
  45. mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
  46. if (IS_ERR(mclk->childs[i]))
  47. printk(KERN_ERR "Could not get clock %s (%d).\n",
  48. clk_names[i], mclk->clk.id);
  49. }
  50. }
  51. static int omap_mcbsp_clk_enable(struct clk *clk)
  52. {
  53. struct mcbsp_internal_clk *mclk = container_of(clk,
  54. struct mcbsp_internal_clk, clk);
  55. int i;
  56. for (i = 0; i < mclk->n_childs; i++)
  57. clk_enable(mclk->childs[i]);
  58. return 0;
  59. }
  60. static void omap_mcbsp_clk_disable(struct clk *clk)
  61. {
  62. struct mcbsp_internal_clk *mclk = container_of(clk,
  63. struct mcbsp_internal_clk, clk);
  64. int i;
  65. for (i = 0; i < mclk->n_childs; i++)
  66. clk_disable(mclk->childs[i]);
  67. }
  68. static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
  69. {
  70. .clk = {
  71. .name = "mcbsp_clk",
  72. .id = 1,
  73. .enable = omap_mcbsp_clk_enable,
  74. .disable = omap_mcbsp_clk_disable,
  75. },
  76. },
  77. {
  78. .clk = {
  79. .name = "mcbsp_clk",
  80. .id = 3,
  81. .enable = omap_mcbsp_clk_enable,
  82. .disable = omap_mcbsp_clk_disable,
  83. },
  84. },
  85. };
  86. #define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
  87. #else
  88. #define omap_mcbsp_clks_size 0
  89. static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
  90. static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
  91. { }
  92. #endif
  93. static void omap1_mcbsp_request(unsigned int id)
  94. {
  95. /*
  96. * On 1510, 1610 and 1710, McBSP1 and McBSP3
  97. * are DSP public peripherals.
  98. */
  99. if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
  100. omap_dsp_request_mem();
  101. /*
  102. * DSP external peripheral reset
  103. * FIXME: This should be moved to dsp code
  104. */
  105. __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
  106. DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
  107. }
  108. }
  109. static void omap1_mcbsp_free(unsigned int id)
  110. {
  111. if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
  112. omap_dsp_release_mem();
  113. }
  114. static struct omap_mcbsp_ops omap1_mcbsp_ops = {
  115. .request = omap1_mcbsp_request,
  116. .free = omap1_mcbsp_free,
  117. };
  118. #ifdef CONFIG_ARCH_OMAP730
  119. static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
  120. {
  121. .phys_base = OMAP730_MCBSP1_BASE,
  122. .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
  123. .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
  124. .rx_irq = INT_730_McBSP1RX,
  125. .tx_irq = INT_730_McBSP1TX,
  126. .ops = &omap1_mcbsp_ops,
  127. },
  128. {
  129. .phys_base = OMAP730_MCBSP2_BASE,
  130. .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
  131. .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
  132. .rx_irq = INT_730_McBSP2RX,
  133. .tx_irq = INT_730_McBSP2TX,
  134. .ops = &omap1_mcbsp_ops,
  135. },
  136. };
  137. #define OMAP730_MCBSP_PDATA_SZ ARRAY_SIZE(omap730_mcbsp_pdata)
  138. #else
  139. #define omap730_mcbsp_pdata NULL
  140. #define OMAP730_MCBSP_PDATA_SZ 0
  141. #endif
  142. #ifdef CONFIG_ARCH_OMAP15XX
  143. static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
  144. {
  145. .phys_base = OMAP1510_MCBSP1_BASE,
  146. .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
  147. .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
  148. .rx_irq = INT_McBSP1RX,
  149. .tx_irq = INT_McBSP1TX,
  150. .ops = &omap1_mcbsp_ops,
  151. .clk_name = "mcbsp_clk",
  152. },
  153. {
  154. .phys_base = OMAP1510_MCBSP2_BASE,
  155. .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
  156. .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
  157. .rx_irq = INT_1510_SPI_RX,
  158. .tx_irq = INT_1510_SPI_TX,
  159. .ops = &omap1_mcbsp_ops,
  160. },
  161. {
  162. .phys_base = OMAP1510_MCBSP3_BASE,
  163. .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
  164. .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
  165. .rx_irq = INT_McBSP3RX,
  166. .tx_irq = INT_McBSP3TX,
  167. .ops = &omap1_mcbsp_ops,
  168. .clk_name = "mcbsp_clk",
  169. },
  170. };
  171. #define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata)
  172. #else
  173. #define omap15xx_mcbsp_pdata NULL
  174. #define OMAP15XX_MCBSP_PDATA_SZ 0
  175. #endif
  176. #ifdef CONFIG_ARCH_OMAP16XX
  177. static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
  178. {
  179. .phys_base = OMAP1610_MCBSP1_BASE,
  180. .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
  181. .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
  182. .rx_irq = INT_McBSP1RX,
  183. .tx_irq = INT_McBSP1TX,
  184. .ops = &omap1_mcbsp_ops,
  185. .clk_name = "mcbsp_clk",
  186. },
  187. {
  188. .phys_base = OMAP1610_MCBSP2_BASE,
  189. .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
  190. .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
  191. .rx_irq = INT_1610_McBSP2_RX,
  192. .tx_irq = INT_1610_McBSP2_TX,
  193. .ops = &omap1_mcbsp_ops,
  194. },
  195. {
  196. .phys_base = OMAP1610_MCBSP3_BASE,
  197. .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
  198. .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
  199. .rx_irq = INT_McBSP3RX,
  200. .tx_irq = INT_McBSP3TX,
  201. .ops = &omap1_mcbsp_ops,
  202. .clk_name = "mcbsp_clk",
  203. },
  204. };
  205. #define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata)
  206. #else
  207. #define omap16xx_mcbsp_pdata NULL
  208. #define OMAP16XX_MCBSP_PDATA_SZ 0
  209. #endif
  210. int __init omap1_mcbsp_init(void)
  211. {
  212. int i;
  213. for (i = 0; i < omap_mcbsp_clks_size; i++) {
  214. if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
  215. omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
  216. clk_register(&omap_mcbsp_clks[i].clk);
  217. }
  218. }
  219. if (cpu_is_omap730())
  220. omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ;
  221. if (cpu_is_omap15xx())
  222. omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
  223. if (cpu_is_omap16xx())
  224. omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
  225. mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
  226. GFP_KERNEL);
  227. if (!mcbsp_ptr)
  228. return -ENOMEM;
  229. if (cpu_is_omap730())
  230. omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
  231. OMAP730_MCBSP_PDATA_SZ);
  232. if (cpu_is_omap15xx())
  233. omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
  234. OMAP15XX_MCBSP_PDATA_SZ);
  235. if (cpu_is_omap16xx())
  236. omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
  237. OMAP16XX_MCBSP_PDATA_SZ);
  238. return omap_mcbsp_init();
  239. }
  240. arch_initcall(omap1_mcbsp_init);