dma.h 6.7 KB

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  1. /*
  2. * dma.h - Blackfin DMA defines/structures/etc...
  3. *
  4. * Copyright 2004-2008 Analog Devices Inc.
  5. * Licensed under the GPL-2 or later.
  6. */
  7. #ifndef _BLACKFIN_DMA_H_
  8. #define _BLACKFIN_DMA_H_
  9. #include <linux/interrupt.h>
  10. #include <mach/dma.h>
  11. #include <asm/blackfin.h>
  12. #include <asm/page.h>
  13. #define MAX_DMA_ADDRESS PAGE_OFFSET
  14. /*****************************************************************************
  15. * Generic DMA Declarations
  16. *
  17. ****************************************************************************/
  18. enum dma_chan_status {
  19. DMA_CHANNEL_FREE,
  20. DMA_CHANNEL_REQUESTED,
  21. DMA_CHANNEL_ENABLED,
  22. };
  23. /*-------------------------
  24. * config reg bits value
  25. *-------------------------*/
  26. #define DATA_SIZE_8 0
  27. #define DATA_SIZE_16 1
  28. #define DATA_SIZE_32 2
  29. #define DMA_FLOW_STOP 0
  30. #define DMA_FLOW_AUTO 1
  31. #define DMA_FLOW_ARRAY 4
  32. #define DMA_FLOW_SMALL 6
  33. #define DMA_FLOW_LARGE 7
  34. #define DIMENSION_LINEAR 0
  35. #define DIMENSION_2D 1
  36. #define DIR_READ 0
  37. #define DIR_WRITE 1
  38. #define INTR_DISABLE 0
  39. #define INTR_ON_BUF 2
  40. #define INTR_ON_ROW 3
  41. #define DMA_NOSYNC_KEEP_DMA_BUF 0
  42. #define DMA_SYNC_RESTART 1
  43. struct dmasg {
  44. unsigned long next_desc_addr;
  45. unsigned long start_addr;
  46. unsigned short cfg;
  47. unsigned short x_count;
  48. short x_modify;
  49. unsigned short y_count;
  50. short y_modify;
  51. } __attribute__((packed));
  52. struct dma_register {
  53. unsigned long next_desc_ptr; /* DMA Next Descriptor Pointer register */
  54. unsigned long start_addr; /* DMA Start address register */
  55. unsigned short cfg; /* DMA Configuration register */
  56. unsigned short dummy1; /* DMA Configuration register */
  57. unsigned long reserved;
  58. unsigned short x_count; /* DMA x_count register */
  59. unsigned short dummy2;
  60. short x_modify; /* DMA x_modify register */
  61. unsigned short dummy3;
  62. unsigned short y_count; /* DMA y_count register */
  63. unsigned short dummy4;
  64. short y_modify; /* DMA y_modify register */
  65. unsigned short dummy5;
  66. unsigned long curr_desc_ptr; /* DMA Current Descriptor Pointer
  67. register */
  68. unsigned long curr_addr_ptr; /* DMA Current Address Pointer
  69. register */
  70. unsigned short irq_status; /* DMA irq status register */
  71. unsigned short dummy6;
  72. unsigned short peripheral_map; /* DMA peripheral map register */
  73. unsigned short dummy7;
  74. unsigned short curr_x_count; /* DMA Current x-count register */
  75. unsigned short dummy8;
  76. unsigned long reserved2;
  77. unsigned short curr_y_count; /* DMA Current y-count register */
  78. unsigned short dummy9;
  79. unsigned long reserved3;
  80. };
  81. struct mutex;
  82. struct dma_channel {
  83. struct mutex dmalock;
  84. const char *device_id;
  85. enum dma_chan_status chan_status;
  86. struct dma_register *regs;
  87. struct dmasg *sg; /* large mode descriptor */
  88. unsigned int ctrl_num; /* controller number */
  89. unsigned int irq;
  90. void *data;
  91. unsigned int dma_enable_flag;
  92. unsigned int loopback_flag;
  93. #ifdef CONFIG_PM
  94. unsigned short saved_peripheral_map;
  95. #endif
  96. };
  97. #ifdef CONFIG_PM
  98. int blackfin_dma_suspend(void);
  99. void blackfin_dma_resume(void);
  100. #endif
  101. /*******************************************************************************
  102. * DMA API's
  103. *******************************************************************************/
  104. extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
  105. extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS];
  106. extern int channel2irq(unsigned int channel);
  107. static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
  108. {
  109. dma_ch[channel].regs->start_addr = addr;
  110. }
  111. static inline void set_dma_next_desc_addr(unsigned int channel, unsigned long addr)
  112. {
  113. dma_ch[channel].regs->next_desc_ptr = addr;
  114. }
  115. static inline void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr)
  116. {
  117. dma_ch[channel].regs->curr_desc_ptr = addr;
  118. }
  119. static inline void set_dma_x_count(unsigned int channel, unsigned short x_count)
  120. {
  121. dma_ch[channel].regs->x_count = x_count;
  122. }
  123. static inline void set_dma_y_count(unsigned int channel, unsigned short y_count)
  124. {
  125. dma_ch[channel].regs->y_count = y_count;
  126. }
  127. static inline void set_dma_x_modify(unsigned int channel, short x_modify)
  128. {
  129. dma_ch[channel].regs->x_modify = x_modify;
  130. }
  131. static inline void set_dma_y_modify(unsigned int channel, short y_modify)
  132. {
  133. dma_ch[channel].regs->y_modify = y_modify;
  134. }
  135. static inline void set_dma_config(unsigned int channel, unsigned short config)
  136. {
  137. dma_ch[channel].regs->cfg = config;
  138. }
  139. static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
  140. {
  141. dma_ch[channel].regs->curr_addr_ptr = addr;
  142. }
  143. static inline unsigned short
  144. set_bfin_dma_config(char direction, char flow_mode,
  145. char intr_mode, char dma_mode, char width, char syncmode)
  146. {
  147. return (direction << 1) | (width << 2) | (dma_mode << 4) |
  148. (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
  149. }
  150. static inline unsigned short get_dma_curr_irqstat(unsigned int channel)
  151. {
  152. return dma_ch[channel].regs->irq_status;
  153. }
  154. static inline unsigned short get_dma_curr_xcount(unsigned int channel)
  155. {
  156. return dma_ch[channel].regs->curr_x_count;
  157. }
  158. static inline unsigned short get_dma_curr_ycount(unsigned int channel)
  159. {
  160. return dma_ch[channel].regs->curr_y_count;
  161. }
  162. static inline unsigned long get_dma_next_desc_ptr(unsigned int channel)
  163. {
  164. return dma_ch[channel].regs->next_desc_ptr;
  165. }
  166. static inline unsigned long get_dma_curr_desc_ptr(unsigned int channel)
  167. {
  168. return dma_ch[channel].regs->curr_desc_ptr;
  169. }
  170. static inline unsigned long get_dma_curr_addr(unsigned int channel)
  171. {
  172. return dma_ch[channel].regs->curr_addr_ptr;
  173. }
  174. static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize)
  175. {
  176. dma_ch[channel].regs->cfg |= ((ndsize & 0x0F) << 8);
  177. dma_ch[channel].regs->next_desc_ptr = (unsigned long)sg;
  178. }
  179. static inline int dma_channel_active(unsigned int channel)
  180. {
  181. if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE)
  182. return 0;
  183. else
  184. return 1;
  185. }
  186. static inline void disable_dma(unsigned int channel)
  187. {
  188. dma_ch[channel].regs->cfg &= ~DMAEN;
  189. SSYNC();
  190. dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
  191. }
  192. static inline void enable_dma(unsigned int channel)
  193. {
  194. dma_ch[channel].regs->curr_x_count = 0;
  195. dma_ch[channel].regs->curr_y_count = 0;
  196. dma_ch[channel].regs->cfg |= DMAEN;
  197. dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
  198. }
  199. void free_dma(unsigned int channel);
  200. int request_dma(unsigned int channel, const char *device_id);
  201. int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data);
  202. static inline void dma_disable_irq(unsigned int channel)
  203. {
  204. disable_irq(dma_ch[channel].irq);
  205. }
  206. static inline void dma_enable_irq(unsigned int channel)
  207. {
  208. enable_irq(dma_ch[channel].irq);
  209. }
  210. static inline void clear_dma_irqstat(unsigned int channel)
  211. {
  212. dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;
  213. }
  214. void *dma_memcpy(void *dest, const void *src, size_t count);
  215. void *safe_dma_memcpy(void *dest, const void *src, size_t count);
  216. void blackfin_dma_early_init(void);
  217. #endif