at91_can.c 31 KB

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  1. /*
  2. * at91_can.c - CAN network driver for AT91 SoC CAN controller
  3. *
  4. * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
  5. * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de>
  6. *
  7. * This software may be distributed under the terms of the GNU General
  8. * Public License ("GPL") version 2 as distributed in the 'COPYING'
  9. * file from the main directory of the linux kernel source.
  10. *
  11. * Send feedback to <socketcan-users@lists.berlios.de>
  12. *
  13. *
  14. * Your platform definition file should specify something like:
  15. *
  16. * static struct at91_can_data ek_can_data = {
  17. * transceiver_switch = sam9263ek_transceiver_switch,
  18. * };
  19. *
  20. * at91_add_device_can(&ek_can_data);
  21. *
  22. */
  23. #include <linux/clk.h>
  24. #include <linux/errno.h>
  25. #include <linux/if_arp.h>
  26. #include <linux/init.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/rtnetlink.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/spinlock.h>
  35. #include <linux/string.h>
  36. #include <linux/types.h>
  37. #include <linux/can/dev.h>
  38. #include <linux/can/error.h>
  39. #include <mach/board.h>
  40. #define AT91_NAPI_WEIGHT 11
  41. /*
  42. * RX/TX Mailbox split
  43. * don't dare to touch
  44. */
  45. #define AT91_MB_RX_NUM 11
  46. #define AT91_MB_TX_SHIFT 2
  47. #define AT91_MB_RX_FIRST 1
  48. #define AT91_MB_RX_LAST (AT91_MB_RX_FIRST + AT91_MB_RX_NUM - 1)
  49. #define AT91_MB_RX_MASK(i) ((1 << (i)) - 1)
  50. #define AT91_MB_RX_SPLIT 8
  51. #define AT91_MB_RX_LOW_LAST (AT91_MB_RX_SPLIT - 1)
  52. #define AT91_MB_RX_LOW_MASK (AT91_MB_RX_MASK(AT91_MB_RX_SPLIT) & \
  53. ~AT91_MB_RX_MASK(AT91_MB_RX_FIRST))
  54. #define AT91_MB_TX_NUM (1 << AT91_MB_TX_SHIFT)
  55. #define AT91_MB_TX_FIRST (AT91_MB_RX_LAST + 1)
  56. #define AT91_MB_TX_LAST (AT91_MB_TX_FIRST + AT91_MB_TX_NUM - 1)
  57. #define AT91_NEXT_PRIO_SHIFT (AT91_MB_TX_SHIFT)
  58. #define AT91_NEXT_PRIO_MASK (0xf << AT91_MB_TX_SHIFT)
  59. #define AT91_NEXT_MB_MASK (AT91_MB_TX_NUM - 1)
  60. #define AT91_NEXT_MASK ((AT91_MB_TX_NUM - 1) | AT91_NEXT_PRIO_MASK)
  61. /* Common registers */
  62. enum at91_reg {
  63. AT91_MR = 0x000,
  64. AT91_IER = 0x004,
  65. AT91_IDR = 0x008,
  66. AT91_IMR = 0x00C,
  67. AT91_SR = 0x010,
  68. AT91_BR = 0x014,
  69. AT91_TIM = 0x018,
  70. AT91_TIMESTP = 0x01C,
  71. AT91_ECR = 0x020,
  72. AT91_TCR = 0x024,
  73. AT91_ACR = 0x028,
  74. };
  75. /* Mailbox registers (0 <= i <= 15) */
  76. #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20))
  77. #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20))
  78. #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20))
  79. #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20))
  80. #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20))
  81. #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20))
  82. #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20))
  83. #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20))
  84. /* Register bits */
  85. #define AT91_MR_CANEN BIT(0)
  86. #define AT91_MR_LPM BIT(1)
  87. #define AT91_MR_ABM BIT(2)
  88. #define AT91_MR_OVL BIT(3)
  89. #define AT91_MR_TEOF BIT(4)
  90. #define AT91_MR_TTM BIT(5)
  91. #define AT91_MR_TIMFRZ BIT(6)
  92. #define AT91_MR_DRPT BIT(7)
  93. #define AT91_SR_RBSY BIT(29)
  94. #define AT91_MMR_PRIO_SHIFT (16)
  95. #define AT91_MID_MIDE BIT(29)
  96. #define AT91_MSR_MRTR BIT(20)
  97. #define AT91_MSR_MABT BIT(22)
  98. #define AT91_MSR_MRDY BIT(23)
  99. #define AT91_MSR_MMI BIT(24)
  100. #define AT91_MCR_MRTR BIT(20)
  101. #define AT91_MCR_MTCR BIT(23)
  102. /* Mailbox Modes */
  103. enum at91_mb_mode {
  104. AT91_MB_MODE_DISABLED = 0,
  105. AT91_MB_MODE_RX = 1,
  106. AT91_MB_MODE_RX_OVRWR = 2,
  107. AT91_MB_MODE_TX = 3,
  108. AT91_MB_MODE_CONSUMER = 4,
  109. AT91_MB_MODE_PRODUCER = 5,
  110. };
  111. /* Interrupt mask bits */
  112. #define AT91_IRQ_MB_RX ((1 << (AT91_MB_RX_LAST + 1)) \
  113. - (1 << AT91_MB_RX_FIRST))
  114. #define AT91_IRQ_MB_TX ((1 << (AT91_MB_TX_LAST + 1)) \
  115. - (1 << AT91_MB_TX_FIRST))
  116. #define AT91_IRQ_MB_ALL (AT91_IRQ_MB_RX | AT91_IRQ_MB_TX)
  117. #define AT91_IRQ_ERRA (1 << 16)
  118. #define AT91_IRQ_WARN (1 << 17)
  119. #define AT91_IRQ_ERRP (1 << 18)
  120. #define AT91_IRQ_BOFF (1 << 19)
  121. #define AT91_IRQ_SLEEP (1 << 20)
  122. #define AT91_IRQ_WAKEUP (1 << 21)
  123. #define AT91_IRQ_TOVF (1 << 22)
  124. #define AT91_IRQ_TSTP (1 << 23)
  125. #define AT91_IRQ_CERR (1 << 24)
  126. #define AT91_IRQ_SERR (1 << 25)
  127. #define AT91_IRQ_AERR (1 << 26)
  128. #define AT91_IRQ_FERR (1 << 27)
  129. #define AT91_IRQ_BERR (1 << 28)
  130. #define AT91_IRQ_ERR_ALL (0x1fff0000)
  131. #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
  132. AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
  133. #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
  134. AT91_IRQ_ERRP | AT91_IRQ_BOFF)
  135. #define AT91_IRQ_ALL (0x1fffffff)
  136. struct at91_priv {
  137. struct can_priv can; /* must be the first member! */
  138. struct net_device *dev;
  139. struct napi_struct napi;
  140. void __iomem *reg_base;
  141. u32 reg_sr;
  142. unsigned int tx_next;
  143. unsigned int tx_echo;
  144. unsigned int rx_next;
  145. struct clk *clk;
  146. struct at91_can_data *pdata;
  147. canid_t mb0_id;
  148. };
  149. static struct can_bittiming_const at91_bittiming_const = {
  150. .name = KBUILD_MODNAME,
  151. .tseg1_min = 4,
  152. .tseg1_max = 16,
  153. .tseg2_min = 2,
  154. .tseg2_max = 8,
  155. .sjw_max = 4,
  156. .brp_min = 2,
  157. .brp_max = 128,
  158. .brp_inc = 1,
  159. };
  160. static inline unsigned int get_tx_next_mb(const struct at91_priv *priv)
  161. {
  162. return (priv->tx_next & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
  163. }
  164. static inline unsigned int get_tx_next_prio(const struct at91_priv *priv)
  165. {
  166. return (priv->tx_next >> AT91_NEXT_PRIO_SHIFT) & 0xf;
  167. }
  168. static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
  169. {
  170. return (priv->tx_echo & AT91_NEXT_MB_MASK) + AT91_MB_TX_FIRST;
  171. }
  172. static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
  173. {
  174. return __raw_readl(priv->reg_base + reg);
  175. }
  176. static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
  177. u32 value)
  178. {
  179. __raw_writel(value, priv->reg_base + reg);
  180. }
  181. static inline void set_mb_mode_prio(const struct at91_priv *priv,
  182. unsigned int mb, enum at91_mb_mode mode, int prio)
  183. {
  184. at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
  185. }
  186. static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
  187. enum at91_mb_mode mode)
  188. {
  189. set_mb_mode_prio(priv, mb, mode, 0);
  190. }
  191. static inline u32 at91_can_id_to_reg_mid(canid_t can_id)
  192. {
  193. u32 reg_mid;
  194. if (can_id & CAN_EFF_FLAG)
  195. reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
  196. else
  197. reg_mid = (can_id & CAN_SFF_MASK) << 18;
  198. return reg_mid;
  199. }
  200. /*
  201. * Swtich transceiver on or off
  202. */
  203. static void at91_transceiver_switch(const struct at91_priv *priv, int on)
  204. {
  205. if (priv->pdata && priv->pdata->transceiver_switch)
  206. priv->pdata->transceiver_switch(on);
  207. }
  208. static void at91_setup_mailboxes(struct net_device *dev)
  209. {
  210. struct at91_priv *priv = netdev_priv(dev);
  211. unsigned int i;
  212. u32 reg_mid;
  213. /*
  214. * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
  215. * mailbox is disabled. The next 11 mailboxes are used as a
  216. * reception FIFO. The last mailbox is configured with
  217. * overwrite option. The overwrite flag indicates a FIFO
  218. * overflow.
  219. */
  220. reg_mid = at91_can_id_to_reg_mid(priv->mb0_id);
  221. for (i = 0; i < AT91_MB_RX_FIRST; i++) {
  222. set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
  223. at91_write(priv, AT91_MID(i), reg_mid);
  224. at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */
  225. }
  226. for (i = AT91_MB_RX_FIRST; i < AT91_MB_RX_LAST; i++)
  227. set_mb_mode(priv, i, AT91_MB_MODE_RX);
  228. set_mb_mode(priv, AT91_MB_RX_LAST, AT91_MB_MODE_RX_OVRWR);
  229. /* reset acceptance mask and id register */
  230. for (i = AT91_MB_RX_FIRST; i <= AT91_MB_RX_LAST; i++) {
  231. at91_write(priv, AT91_MAM(i), 0x0);
  232. at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
  233. }
  234. /* The last 4 mailboxes are used for transmitting. */
  235. for (i = AT91_MB_TX_FIRST; i <= AT91_MB_TX_LAST; i++)
  236. set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
  237. /* Reset tx and rx helper pointers */
  238. priv->tx_next = priv->tx_echo = 0;
  239. priv->rx_next = AT91_MB_RX_FIRST;
  240. }
  241. static int at91_set_bittiming(struct net_device *dev)
  242. {
  243. const struct at91_priv *priv = netdev_priv(dev);
  244. const struct can_bittiming *bt = &priv->can.bittiming;
  245. u32 reg_br;
  246. reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) |
  247. ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) |
  248. ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
  249. ((bt->phase_seg2 - 1) << 0);
  250. netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br);
  251. at91_write(priv, AT91_BR, reg_br);
  252. return 0;
  253. }
  254. static int at91_get_berr_counter(const struct net_device *dev,
  255. struct can_berr_counter *bec)
  256. {
  257. const struct at91_priv *priv = netdev_priv(dev);
  258. u32 reg_ecr = at91_read(priv, AT91_ECR);
  259. bec->rxerr = reg_ecr & 0xff;
  260. bec->txerr = reg_ecr >> 16;
  261. return 0;
  262. }
  263. static void at91_chip_start(struct net_device *dev)
  264. {
  265. struct at91_priv *priv = netdev_priv(dev);
  266. u32 reg_mr, reg_ier;
  267. /* disable interrupts */
  268. at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
  269. /* disable chip */
  270. reg_mr = at91_read(priv, AT91_MR);
  271. at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
  272. at91_set_bittiming(dev);
  273. at91_setup_mailboxes(dev);
  274. at91_transceiver_switch(priv, 1);
  275. /* enable chip */
  276. at91_write(priv, AT91_MR, AT91_MR_CANEN);
  277. priv->can.state = CAN_STATE_ERROR_ACTIVE;
  278. /* Enable interrupts */
  279. reg_ier = AT91_IRQ_MB_RX | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
  280. at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
  281. at91_write(priv, AT91_IER, reg_ier);
  282. }
  283. static void at91_chip_stop(struct net_device *dev, enum can_state state)
  284. {
  285. struct at91_priv *priv = netdev_priv(dev);
  286. u32 reg_mr;
  287. /* disable interrupts */
  288. at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
  289. reg_mr = at91_read(priv, AT91_MR);
  290. at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
  291. at91_transceiver_switch(priv, 0);
  292. priv->can.state = state;
  293. }
  294. /*
  295. * theory of operation:
  296. *
  297. * According to the datasheet priority 0 is the highest priority, 15
  298. * is the lowest. If two mailboxes have the same priority level the
  299. * message of the mailbox with the lowest number is sent first.
  300. *
  301. * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
  302. * the next mailbox with prio 0, and so on, until all mailboxes are
  303. * used. Then we start from the beginning with mailbox
  304. * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
  305. * prio 1. When we reach the last mailbox with prio 15, we have to
  306. * stop sending, waiting for all messages to be delivered, then start
  307. * again with mailbox AT91_MB_TX_FIRST prio 0.
  308. *
  309. * We use the priv->tx_next as counter for the next transmission
  310. * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
  311. * encode the mailbox number, the upper 4 bits the mailbox priority:
  312. *
  313. * priv->tx_next = (prio << AT91_NEXT_PRIO_SHIFT) |
  314. * (mb - AT91_MB_TX_FIRST);
  315. *
  316. */
  317. static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
  318. {
  319. struct at91_priv *priv = netdev_priv(dev);
  320. struct net_device_stats *stats = &dev->stats;
  321. struct can_frame *cf = (struct can_frame *)skb->data;
  322. unsigned int mb, prio;
  323. u32 reg_mid, reg_mcr;
  324. if (can_dropped_invalid_skb(dev, skb))
  325. return NETDEV_TX_OK;
  326. mb = get_tx_next_mb(priv);
  327. prio = get_tx_next_prio(priv);
  328. if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
  329. netif_stop_queue(dev);
  330. netdev_err(dev, "BUG! TX buffer full when queue awake!\n");
  331. return NETDEV_TX_BUSY;
  332. }
  333. reg_mid = at91_can_id_to_reg_mid(cf->can_id);
  334. reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
  335. (cf->can_dlc << 16) | AT91_MCR_MTCR;
  336. /* disable MB while writing ID (see datasheet) */
  337. set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
  338. at91_write(priv, AT91_MID(mb), reg_mid);
  339. set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
  340. at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
  341. at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
  342. /* This triggers transmission */
  343. at91_write(priv, AT91_MCR(mb), reg_mcr);
  344. stats->tx_bytes += cf->can_dlc;
  345. /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
  346. can_put_echo_skb(skb, dev, mb - AT91_MB_TX_FIRST);
  347. /*
  348. * we have to stop the queue and deliver all messages in case
  349. * of a prio+mb counter wrap around. This is the case if
  350. * tx_next buffer prio and mailbox equals 0.
  351. *
  352. * also stop the queue if next buffer is still in use
  353. * (== not ready)
  354. */
  355. priv->tx_next++;
  356. if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
  357. AT91_MSR_MRDY) ||
  358. (priv->tx_next & AT91_NEXT_MASK) == 0)
  359. netif_stop_queue(dev);
  360. /* Enable interrupt for this mailbox */
  361. at91_write(priv, AT91_IER, 1 << mb);
  362. return NETDEV_TX_OK;
  363. }
  364. /**
  365. * at91_activate_rx_low - activate lower rx mailboxes
  366. * @priv: a91 context
  367. *
  368. * Reenables the lower mailboxes for reception of new CAN messages
  369. */
  370. static inline void at91_activate_rx_low(const struct at91_priv *priv)
  371. {
  372. u32 mask = AT91_MB_RX_LOW_MASK;
  373. at91_write(priv, AT91_TCR, mask);
  374. }
  375. /**
  376. * at91_activate_rx_mb - reactive single rx mailbox
  377. * @priv: a91 context
  378. * @mb: mailbox to reactivate
  379. *
  380. * Reenables given mailbox for reception of new CAN messages
  381. */
  382. static inline void at91_activate_rx_mb(const struct at91_priv *priv,
  383. unsigned int mb)
  384. {
  385. u32 mask = 1 << mb;
  386. at91_write(priv, AT91_TCR, mask);
  387. }
  388. /**
  389. * at91_rx_overflow_err - send error frame due to rx overflow
  390. * @dev: net device
  391. */
  392. static void at91_rx_overflow_err(struct net_device *dev)
  393. {
  394. struct net_device_stats *stats = &dev->stats;
  395. struct sk_buff *skb;
  396. struct can_frame *cf;
  397. netdev_dbg(dev, "RX buffer overflow\n");
  398. stats->rx_over_errors++;
  399. stats->rx_errors++;
  400. skb = alloc_can_err_skb(dev, &cf);
  401. if (unlikely(!skb))
  402. return;
  403. cf->can_id |= CAN_ERR_CRTL;
  404. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  405. netif_receive_skb(skb);
  406. stats->rx_packets++;
  407. stats->rx_bytes += cf->can_dlc;
  408. }
  409. /**
  410. * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
  411. * @dev: net device
  412. * @mb: mailbox number to read from
  413. * @cf: can frame where to store message
  414. *
  415. * Reads a CAN message from the given mailbox and stores data into
  416. * given can frame. "mb" and "cf" must be valid.
  417. */
  418. static void at91_read_mb(struct net_device *dev, unsigned int mb,
  419. struct can_frame *cf)
  420. {
  421. const struct at91_priv *priv = netdev_priv(dev);
  422. u32 reg_msr, reg_mid;
  423. reg_mid = at91_read(priv, AT91_MID(mb));
  424. if (reg_mid & AT91_MID_MIDE)
  425. cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
  426. else
  427. cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
  428. reg_msr = at91_read(priv, AT91_MSR(mb));
  429. cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf);
  430. if (reg_msr & AT91_MSR_MRTR)
  431. cf->can_id |= CAN_RTR_FLAG;
  432. else {
  433. *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
  434. *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
  435. }
  436. /* allow RX of extended frames */
  437. at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
  438. if (unlikely(mb == AT91_MB_RX_LAST && reg_msr & AT91_MSR_MMI))
  439. at91_rx_overflow_err(dev);
  440. }
  441. /**
  442. * at91_read_msg - read CAN message from mailbox
  443. * @dev: net device
  444. * @mb: mail box to read from
  445. *
  446. * Reads a CAN message from given mailbox, and put into linux network
  447. * RX queue, does all housekeeping chores (stats, ...)
  448. */
  449. static void at91_read_msg(struct net_device *dev, unsigned int mb)
  450. {
  451. struct net_device_stats *stats = &dev->stats;
  452. struct can_frame *cf;
  453. struct sk_buff *skb;
  454. skb = alloc_can_skb(dev, &cf);
  455. if (unlikely(!skb)) {
  456. stats->rx_dropped++;
  457. return;
  458. }
  459. at91_read_mb(dev, mb, cf);
  460. netif_receive_skb(skb);
  461. stats->rx_packets++;
  462. stats->rx_bytes += cf->can_dlc;
  463. }
  464. /**
  465. * at91_poll_rx - read multiple CAN messages from mailboxes
  466. * @dev: net device
  467. * @quota: max number of pkgs we're allowed to receive
  468. *
  469. * Theory of Operation:
  470. *
  471. * 11 of the 16 mailboxes on the chip are reserved for RX. we split
  472. * them into 2 groups. The lower group holds 7 and upper 4 mailboxes.
  473. *
  474. * Like it or not, but the chip always saves a received CAN message
  475. * into the first free mailbox it finds (starting with the
  476. * lowest). This makes it very difficult to read the messages in the
  477. * right order from the chip. This is how we work around that problem:
  478. *
  479. * The first message goes into mb nr. 1 and issues an interrupt. All
  480. * rx ints are disabled in the interrupt handler and a napi poll is
  481. * scheduled. We read the mailbox, but do _not_ reenable the mb (to
  482. * receive another message).
  483. *
  484. * lower mbxs upper
  485. * ____^______ __^__
  486. * / \ / \
  487. * +-+-+-+-+-+-+-+-++-+-+-+-+
  488. * | |x|x|x|x|x|x|x|| | | | |
  489. * +-+-+-+-+-+-+-+-++-+-+-+-+
  490. * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
  491. * 0 1 2 3 4 5 6 7 8 9 0 1 / box
  492. * ^
  493. * |
  494. * \
  495. * unused, due to chip bug
  496. *
  497. * The variable priv->rx_next points to the next mailbox to read a
  498. * message from. As long we're in the lower mailboxes we just read the
  499. * mailbox but not reenable it.
  500. *
  501. * With completion of the last of the lower mailboxes, we reenable the
  502. * whole first group, but continue to look for filled mailboxes in the
  503. * upper mailboxes. Imagine the second group like overflow mailboxes,
  504. * which takes CAN messages if the lower goup is full. While in the
  505. * upper group we reenable the mailbox right after reading it. Giving
  506. * the chip more room to store messages.
  507. *
  508. * After finishing we look again in the lower group if we've still
  509. * quota.
  510. *
  511. */
  512. static int at91_poll_rx(struct net_device *dev, int quota)
  513. {
  514. struct at91_priv *priv = netdev_priv(dev);
  515. u32 reg_sr = at91_read(priv, AT91_SR);
  516. const unsigned long *addr = (unsigned long *)&reg_sr;
  517. unsigned int mb;
  518. int received = 0;
  519. if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
  520. reg_sr & AT91_MB_RX_LOW_MASK)
  521. netdev_info(dev,
  522. "order of incoming frames cannot be guaranteed\n");
  523. again:
  524. for (mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, priv->rx_next);
  525. mb < AT91_MB_RX_LAST + 1 && quota > 0;
  526. reg_sr = at91_read(priv, AT91_SR),
  527. mb = find_next_bit(addr, AT91_MB_RX_LAST + 1, ++priv->rx_next)) {
  528. at91_read_msg(dev, mb);
  529. /* reactivate mailboxes */
  530. if (mb == AT91_MB_RX_LOW_LAST)
  531. /* all lower mailboxed, if just finished it */
  532. at91_activate_rx_low(priv);
  533. else if (mb > AT91_MB_RX_LOW_LAST)
  534. /* only the mailbox we read */
  535. at91_activate_rx_mb(priv, mb);
  536. received++;
  537. quota--;
  538. }
  539. /* upper group completed, look again in lower */
  540. if (priv->rx_next > AT91_MB_RX_LOW_LAST &&
  541. quota > 0 && mb > AT91_MB_RX_LAST) {
  542. priv->rx_next = AT91_MB_RX_FIRST;
  543. goto again;
  544. }
  545. return received;
  546. }
  547. static void at91_poll_err_frame(struct net_device *dev,
  548. struct can_frame *cf, u32 reg_sr)
  549. {
  550. struct at91_priv *priv = netdev_priv(dev);
  551. /* CRC error */
  552. if (reg_sr & AT91_IRQ_CERR) {
  553. netdev_dbg(dev, "CERR irq\n");
  554. dev->stats.rx_errors++;
  555. priv->can.can_stats.bus_error++;
  556. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  557. }
  558. /* Stuffing Error */
  559. if (reg_sr & AT91_IRQ_SERR) {
  560. netdev_dbg(dev, "SERR irq\n");
  561. dev->stats.rx_errors++;
  562. priv->can.can_stats.bus_error++;
  563. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  564. cf->data[2] |= CAN_ERR_PROT_STUFF;
  565. }
  566. /* Acknowledgement Error */
  567. if (reg_sr & AT91_IRQ_AERR) {
  568. netdev_dbg(dev, "AERR irq\n");
  569. dev->stats.tx_errors++;
  570. cf->can_id |= CAN_ERR_ACK;
  571. }
  572. /* Form error */
  573. if (reg_sr & AT91_IRQ_FERR) {
  574. netdev_dbg(dev, "FERR irq\n");
  575. dev->stats.rx_errors++;
  576. priv->can.can_stats.bus_error++;
  577. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  578. cf->data[2] |= CAN_ERR_PROT_FORM;
  579. }
  580. /* Bit Error */
  581. if (reg_sr & AT91_IRQ_BERR) {
  582. netdev_dbg(dev, "BERR irq\n");
  583. dev->stats.tx_errors++;
  584. priv->can.can_stats.bus_error++;
  585. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  586. cf->data[2] |= CAN_ERR_PROT_BIT;
  587. }
  588. }
  589. static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
  590. {
  591. struct sk_buff *skb;
  592. struct can_frame *cf;
  593. if (quota == 0)
  594. return 0;
  595. skb = alloc_can_err_skb(dev, &cf);
  596. if (unlikely(!skb))
  597. return 0;
  598. at91_poll_err_frame(dev, cf, reg_sr);
  599. netif_receive_skb(skb);
  600. dev->stats.rx_packets++;
  601. dev->stats.rx_bytes += cf->can_dlc;
  602. return 1;
  603. }
  604. static int at91_poll(struct napi_struct *napi, int quota)
  605. {
  606. struct net_device *dev = napi->dev;
  607. const struct at91_priv *priv = netdev_priv(dev);
  608. u32 reg_sr = at91_read(priv, AT91_SR);
  609. int work_done = 0;
  610. if (reg_sr & AT91_IRQ_MB_RX)
  611. work_done += at91_poll_rx(dev, quota - work_done);
  612. /*
  613. * The error bits are clear on read,
  614. * so use saved value from irq handler.
  615. */
  616. reg_sr |= priv->reg_sr;
  617. if (reg_sr & AT91_IRQ_ERR_FRAME)
  618. work_done += at91_poll_err(dev, quota - work_done, reg_sr);
  619. if (work_done < quota) {
  620. /* enable IRQs for frame errors and all mailboxes >= rx_next */
  621. u32 reg_ier = AT91_IRQ_ERR_FRAME;
  622. reg_ier |= AT91_IRQ_MB_RX & ~AT91_MB_RX_MASK(priv->rx_next);
  623. napi_complete(napi);
  624. at91_write(priv, AT91_IER, reg_ier);
  625. }
  626. return work_done;
  627. }
  628. /*
  629. * theory of operation:
  630. *
  631. * priv->tx_echo holds the number of the oldest can_frame put for
  632. * transmission into the hardware, but not yet ACKed by the CAN tx
  633. * complete IRQ.
  634. *
  635. * We iterate from priv->tx_echo to priv->tx_next and check if the
  636. * packet has been transmitted, echo it back to the CAN framework. If
  637. * we discover a not yet transmitted package, stop looking for more.
  638. *
  639. */
  640. static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
  641. {
  642. struct at91_priv *priv = netdev_priv(dev);
  643. u32 reg_msr;
  644. unsigned int mb;
  645. /* masking of reg_sr not needed, already done by at91_irq */
  646. for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
  647. mb = get_tx_echo_mb(priv);
  648. /* no event in mailbox? */
  649. if (!(reg_sr & (1 << mb)))
  650. break;
  651. /* Disable irq for this TX mailbox */
  652. at91_write(priv, AT91_IDR, 1 << mb);
  653. /*
  654. * only echo if mailbox signals us a transfer
  655. * complete (MSR_MRDY). Otherwise it's a tansfer
  656. * abort. "can_bus_off()" takes care about the skbs
  657. * parked in the echo queue.
  658. */
  659. reg_msr = at91_read(priv, AT91_MSR(mb));
  660. if (likely(reg_msr & AT91_MSR_MRDY &&
  661. ~reg_msr & AT91_MSR_MABT)) {
  662. /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
  663. can_get_echo_skb(dev, mb - AT91_MB_TX_FIRST);
  664. dev->stats.tx_packets++;
  665. }
  666. }
  667. /*
  668. * restart queue if we don't have a wrap around but restart if
  669. * we get a TX int for the last can frame directly before a
  670. * wrap around.
  671. */
  672. if ((priv->tx_next & AT91_NEXT_MASK) != 0 ||
  673. (priv->tx_echo & AT91_NEXT_MASK) == 0)
  674. netif_wake_queue(dev);
  675. }
  676. static void at91_irq_err_state(struct net_device *dev,
  677. struct can_frame *cf, enum can_state new_state)
  678. {
  679. struct at91_priv *priv = netdev_priv(dev);
  680. u32 reg_idr = 0, reg_ier = 0;
  681. struct can_berr_counter bec;
  682. at91_get_berr_counter(dev, &bec);
  683. switch (priv->can.state) {
  684. case CAN_STATE_ERROR_ACTIVE:
  685. /*
  686. * from: ERROR_ACTIVE
  687. * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
  688. * => : there was a warning int
  689. */
  690. if (new_state >= CAN_STATE_ERROR_WARNING &&
  691. new_state <= CAN_STATE_BUS_OFF) {
  692. netdev_dbg(dev, "Error Warning IRQ\n");
  693. priv->can.can_stats.error_warning++;
  694. cf->can_id |= CAN_ERR_CRTL;
  695. cf->data[1] = (bec.txerr > bec.rxerr) ?
  696. CAN_ERR_CRTL_TX_WARNING :
  697. CAN_ERR_CRTL_RX_WARNING;
  698. }
  699. case CAN_STATE_ERROR_WARNING: /* fallthrough */
  700. /*
  701. * from: ERROR_ACTIVE, ERROR_WARNING
  702. * to : ERROR_PASSIVE, BUS_OFF
  703. * => : error passive int
  704. */
  705. if (new_state >= CAN_STATE_ERROR_PASSIVE &&
  706. new_state <= CAN_STATE_BUS_OFF) {
  707. netdev_dbg(dev, "Error Passive IRQ\n");
  708. priv->can.can_stats.error_passive++;
  709. cf->can_id |= CAN_ERR_CRTL;
  710. cf->data[1] = (bec.txerr > bec.rxerr) ?
  711. CAN_ERR_CRTL_TX_PASSIVE :
  712. CAN_ERR_CRTL_RX_PASSIVE;
  713. }
  714. break;
  715. case CAN_STATE_BUS_OFF:
  716. /*
  717. * from: BUS_OFF
  718. * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
  719. */
  720. if (new_state <= CAN_STATE_ERROR_PASSIVE) {
  721. cf->can_id |= CAN_ERR_RESTARTED;
  722. netdev_dbg(dev, "restarted\n");
  723. priv->can.can_stats.restarts++;
  724. netif_carrier_on(dev);
  725. netif_wake_queue(dev);
  726. }
  727. break;
  728. default:
  729. break;
  730. }
  731. /* process state changes depending on the new state */
  732. switch (new_state) {
  733. case CAN_STATE_ERROR_ACTIVE:
  734. /*
  735. * actually we want to enable AT91_IRQ_WARN here, but
  736. * it screws up the system under certain
  737. * circumstances. so just enable AT91_IRQ_ERRP, thus
  738. * the "fallthrough"
  739. */
  740. netdev_dbg(dev, "Error Active\n");
  741. cf->can_id |= CAN_ERR_PROT;
  742. cf->data[2] = CAN_ERR_PROT_ACTIVE;
  743. case CAN_STATE_ERROR_WARNING: /* fallthrough */
  744. reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
  745. reg_ier = AT91_IRQ_ERRP;
  746. break;
  747. case CAN_STATE_ERROR_PASSIVE:
  748. reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
  749. reg_ier = AT91_IRQ_BOFF;
  750. break;
  751. case CAN_STATE_BUS_OFF:
  752. reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
  753. AT91_IRQ_WARN | AT91_IRQ_BOFF;
  754. reg_ier = 0;
  755. cf->can_id |= CAN_ERR_BUSOFF;
  756. netdev_dbg(dev, "bus-off\n");
  757. netif_carrier_off(dev);
  758. priv->can.can_stats.bus_off++;
  759. /* turn off chip, if restart is disabled */
  760. if (!priv->can.restart_ms) {
  761. at91_chip_stop(dev, CAN_STATE_BUS_OFF);
  762. return;
  763. }
  764. break;
  765. default:
  766. break;
  767. }
  768. at91_write(priv, AT91_IDR, reg_idr);
  769. at91_write(priv, AT91_IER, reg_ier);
  770. }
  771. static void at91_irq_err(struct net_device *dev)
  772. {
  773. struct at91_priv *priv = netdev_priv(dev);
  774. struct sk_buff *skb;
  775. struct can_frame *cf;
  776. enum can_state new_state;
  777. u32 reg_sr;
  778. reg_sr = at91_read(priv, AT91_SR);
  779. /* we need to look at the unmasked reg_sr */
  780. if (unlikely(reg_sr & AT91_IRQ_BOFF))
  781. new_state = CAN_STATE_BUS_OFF;
  782. else if (unlikely(reg_sr & AT91_IRQ_ERRP))
  783. new_state = CAN_STATE_ERROR_PASSIVE;
  784. else if (unlikely(reg_sr & AT91_IRQ_WARN))
  785. new_state = CAN_STATE_ERROR_WARNING;
  786. else if (likely(reg_sr & AT91_IRQ_ERRA))
  787. new_state = CAN_STATE_ERROR_ACTIVE;
  788. else {
  789. netdev_err(dev, "BUG! hardware in undefined state\n");
  790. return;
  791. }
  792. /* state hasn't changed */
  793. if (likely(new_state == priv->can.state))
  794. return;
  795. skb = alloc_can_err_skb(dev, &cf);
  796. if (unlikely(!skb))
  797. return;
  798. at91_irq_err_state(dev, cf, new_state);
  799. netif_rx(skb);
  800. dev->stats.rx_packets++;
  801. dev->stats.rx_bytes += cf->can_dlc;
  802. priv->can.state = new_state;
  803. }
  804. /*
  805. * interrupt handler
  806. */
  807. static irqreturn_t at91_irq(int irq, void *dev_id)
  808. {
  809. struct net_device *dev = dev_id;
  810. struct at91_priv *priv = netdev_priv(dev);
  811. irqreturn_t handled = IRQ_NONE;
  812. u32 reg_sr, reg_imr;
  813. reg_sr = at91_read(priv, AT91_SR);
  814. reg_imr = at91_read(priv, AT91_IMR);
  815. /* Ignore masked interrupts */
  816. reg_sr &= reg_imr;
  817. if (!reg_sr)
  818. goto exit;
  819. handled = IRQ_HANDLED;
  820. /* Receive or error interrupt? -> napi */
  821. if (reg_sr & (AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME)) {
  822. /*
  823. * The error bits are clear on read,
  824. * save for later use.
  825. */
  826. priv->reg_sr = reg_sr;
  827. at91_write(priv, AT91_IDR,
  828. AT91_IRQ_MB_RX | AT91_IRQ_ERR_FRAME);
  829. napi_schedule(&priv->napi);
  830. }
  831. /* Transmission complete interrupt */
  832. if (reg_sr & AT91_IRQ_MB_TX)
  833. at91_irq_tx(dev, reg_sr);
  834. at91_irq_err(dev);
  835. exit:
  836. return handled;
  837. }
  838. static int at91_open(struct net_device *dev)
  839. {
  840. struct at91_priv *priv = netdev_priv(dev);
  841. int err;
  842. clk_enable(priv->clk);
  843. /* check or determine and set bittime */
  844. err = open_candev(dev);
  845. if (err)
  846. goto out;
  847. /* register interrupt handler */
  848. if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
  849. dev->name, dev)) {
  850. err = -EAGAIN;
  851. goto out_close;
  852. }
  853. /* start chip and queuing */
  854. at91_chip_start(dev);
  855. napi_enable(&priv->napi);
  856. netif_start_queue(dev);
  857. return 0;
  858. out_close:
  859. close_candev(dev);
  860. out:
  861. clk_disable(priv->clk);
  862. return err;
  863. }
  864. /*
  865. * stop CAN bus activity
  866. */
  867. static int at91_close(struct net_device *dev)
  868. {
  869. struct at91_priv *priv = netdev_priv(dev);
  870. netif_stop_queue(dev);
  871. napi_disable(&priv->napi);
  872. at91_chip_stop(dev, CAN_STATE_STOPPED);
  873. free_irq(dev->irq, dev);
  874. clk_disable(priv->clk);
  875. close_candev(dev);
  876. return 0;
  877. }
  878. static int at91_set_mode(struct net_device *dev, enum can_mode mode)
  879. {
  880. switch (mode) {
  881. case CAN_MODE_START:
  882. at91_chip_start(dev);
  883. netif_wake_queue(dev);
  884. break;
  885. default:
  886. return -EOPNOTSUPP;
  887. }
  888. return 0;
  889. }
  890. static const struct net_device_ops at91_netdev_ops = {
  891. .ndo_open = at91_open,
  892. .ndo_stop = at91_close,
  893. .ndo_start_xmit = at91_start_xmit,
  894. };
  895. static ssize_t at91_sysfs_show_mb0_id(struct device *dev,
  896. struct device_attribute *attr, char *buf)
  897. {
  898. struct at91_priv *priv = netdev_priv(to_net_dev(dev));
  899. if (priv->mb0_id & CAN_EFF_FLAG)
  900. return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id);
  901. else
  902. return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id);
  903. }
  904. static ssize_t at91_sysfs_set_mb0_id(struct device *dev,
  905. struct device_attribute *attr, const char *buf, size_t count)
  906. {
  907. struct net_device *ndev = to_net_dev(dev);
  908. struct at91_priv *priv = netdev_priv(ndev);
  909. unsigned long can_id;
  910. ssize_t ret;
  911. int err;
  912. rtnl_lock();
  913. if (ndev->flags & IFF_UP) {
  914. ret = -EBUSY;
  915. goto out;
  916. }
  917. err = strict_strtoul(buf, 0, &can_id);
  918. if (err) {
  919. ret = err;
  920. goto out;
  921. }
  922. if (can_id & CAN_EFF_FLAG)
  923. can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
  924. else
  925. can_id &= CAN_SFF_MASK;
  926. priv->mb0_id = can_id;
  927. ret = count;
  928. out:
  929. rtnl_unlock();
  930. return ret;
  931. }
  932. static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO,
  933. at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id);
  934. static struct attribute *at91_sysfs_attrs[] = {
  935. &dev_attr_mb0_id.attr,
  936. NULL,
  937. };
  938. static struct attribute_group at91_sysfs_attr_group = {
  939. .attrs = at91_sysfs_attrs,
  940. };
  941. static int __devinit at91_can_probe(struct platform_device *pdev)
  942. {
  943. struct net_device *dev;
  944. struct at91_priv *priv;
  945. struct resource *res;
  946. struct clk *clk;
  947. void __iomem *addr;
  948. int err, irq;
  949. clk = clk_get(&pdev->dev, "can_clk");
  950. if (IS_ERR(clk)) {
  951. dev_err(&pdev->dev, "no clock defined\n");
  952. err = -ENODEV;
  953. goto exit;
  954. }
  955. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  956. irq = platform_get_irq(pdev, 0);
  957. if (!res || irq <= 0) {
  958. err = -ENODEV;
  959. goto exit_put;
  960. }
  961. if (!request_mem_region(res->start,
  962. resource_size(res),
  963. pdev->name)) {
  964. err = -EBUSY;
  965. goto exit_put;
  966. }
  967. addr = ioremap_nocache(res->start, resource_size(res));
  968. if (!addr) {
  969. err = -ENOMEM;
  970. goto exit_release;
  971. }
  972. dev = alloc_candev(sizeof(struct at91_priv), AT91_MB_TX_NUM);
  973. if (!dev) {
  974. err = -ENOMEM;
  975. goto exit_iounmap;
  976. }
  977. dev->netdev_ops = &at91_netdev_ops;
  978. dev->irq = irq;
  979. dev->flags |= IFF_ECHO;
  980. dev->sysfs_groups[0] = &at91_sysfs_attr_group;
  981. priv = netdev_priv(dev);
  982. priv->can.clock.freq = clk_get_rate(clk);
  983. priv->can.bittiming_const = &at91_bittiming_const;
  984. priv->can.do_set_mode = at91_set_mode;
  985. priv->can.do_get_berr_counter = at91_get_berr_counter;
  986. priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES;
  987. priv->reg_base = addr;
  988. priv->dev = dev;
  989. priv->clk = clk;
  990. priv->pdata = pdev->dev.platform_data;
  991. priv->mb0_id = 0x7ff;
  992. netif_napi_add(dev, &priv->napi, at91_poll, AT91_NAPI_WEIGHT);
  993. dev_set_drvdata(&pdev->dev, dev);
  994. SET_NETDEV_DEV(dev, &pdev->dev);
  995. err = register_candev(dev);
  996. if (err) {
  997. dev_err(&pdev->dev, "registering netdev failed\n");
  998. goto exit_free;
  999. }
  1000. dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
  1001. priv->reg_base, dev->irq);
  1002. return 0;
  1003. exit_free:
  1004. free_candev(dev);
  1005. exit_iounmap:
  1006. iounmap(addr);
  1007. exit_release:
  1008. release_mem_region(res->start, resource_size(res));
  1009. exit_put:
  1010. clk_put(clk);
  1011. exit:
  1012. return err;
  1013. }
  1014. static int __devexit at91_can_remove(struct platform_device *pdev)
  1015. {
  1016. struct net_device *dev = platform_get_drvdata(pdev);
  1017. struct at91_priv *priv = netdev_priv(dev);
  1018. struct resource *res;
  1019. unregister_netdev(dev);
  1020. platform_set_drvdata(pdev, NULL);
  1021. iounmap(priv->reg_base);
  1022. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1023. release_mem_region(res->start, resource_size(res));
  1024. clk_put(priv->clk);
  1025. free_candev(dev);
  1026. return 0;
  1027. }
  1028. static struct platform_driver at91_can_driver = {
  1029. .probe = at91_can_probe,
  1030. .remove = __devexit_p(at91_can_remove),
  1031. .driver = {
  1032. .name = KBUILD_MODNAME,
  1033. .owner = THIS_MODULE,
  1034. },
  1035. };
  1036. static int __init at91_can_module_init(void)
  1037. {
  1038. return platform_driver_register(&at91_can_driver);
  1039. }
  1040. static void __exit at91_can_module_exit(void)
  1041. {
  1042. platform_driver_unregister(&at91_can_driver);
  1043. }
  1044. module_init(at91_can_module_init);
  1045. module_exit(at91_can_module_exit);
  1046. MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
  1047. MODULE_LICENSE("GPL v2");
  1048. MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver");