s3cmci.c 41 KB

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  1. /*
  2. * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
  3. *
  4. * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
  5. *
  6. * Current driver maintained by Ben Dooks and Simtec Electronics
  7. * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/clk.h>
  16. #include <linux/mmc/host.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/cpufreq.h>
  19. #include <linux/debugfs.h>
  20. #include <linux/seq_file.h>
  21. #include <linux/gpio.h>
  22. #include <linux/irq.h>
  23. #include <linux/io.h>
  24. #include <mach/dma.h>
  25. #include <mach/regs-sdi.h>
  26. #include <mach/regs-gpio.h>
  27. #include <plat/mci.h>
  28. #include "s3cmci.h"
  29. #define DRIVER_NAME "s3c-mci"
  30. enum dbg_channels {
  31. dbg_err = (1 << 0),
  32. dbg_debug = (1 << 1),
  33. dbg_info = (1 << 2),
  34. dbg_irq = (1 << 3),
  35. dbg_sg = (1 << 4),
  36. dbg_dma = (1 << 5),
  37. dbg_pio = (1 << 6),
  38. dbg_fail = (1 << 7),
  39. dbg_conf = (1 << 8),
  40. };
  41. static const int dbgmap_err = dbg_fail;
  42. static const int dbgmap_info = dbg_info | dbg_conf;
  43. static const int dbgmap_debug = dbg_err | dbg_debug;
  44. #define dbg(host, channels, args...) \
  45. do { \
  46. if (dbgmap_err & channels) \
  47. dev_err(&host->pdev->dev, args); \
  48. else if (dbgmap_info & channels) \
  49. dev_info(&host->pdev->dev, args); \
  50. else if (dbgmap_debug & channels) \
  51. dev_dbg(&host->pdev->dev, args); \
  52. } while (0)
  53. static struct s3c2410_dma_client s3cmci_dma_client = {
  54. .name = "s3c-mci",
  55. };
  56. static void finalize_request(struct s3cmci_host *host);
  57. static void s3cmci_send_request(struct mmc_host *mmc);
  58. static void s3cmci_reset(struct s3cmci_host *host);
  59. #ifdef CONFIG_MMC_DEBUG
  60. static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
  61. {
  62. u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
  63. u32 datcon, datcnt, datsta, fsta, imask;
  64. con = readl(host->base + S3C2410_SDICON);
  65. pre = readl(host->base + S3C2410_SDIPRE);
  66. cmdarg = readl(host->base + S3C2410_SDICMDARG);
  67. cmdcon = readl(host->base + S3C2410_SDICMDCON);
  68. cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
  69. r0 = readl(host->base + S3C2410_SDIRSP0);
  70. r1 = readl(host->base + S3C2410_SDIRSP1);
  71. r2 = readl(host->base + S3C2410_SDIRSP2);
  72. r3 = readl(host->base + S3C2410_SDIRSP3);
  73. timer = readl(host->base + S3C2410_SDITIMER);
  74. bsize = readl(host->base + S3C2410_SDIBSIZE);
  75. datcon = readl(host->base + S3C2410_SDIDCON);
  76. datcnt = readl(host->base + S3C2410_SDIDCNT);
  77. datsta = readl(host->base + S3C2410_SDIDSTA);
  78. fsta = readl(host->base + S3C2410_SDIFSTA);
  79. imask = readl(host->base + host->sdiimsk);
  80. dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
  81. prefix, con, pre, timer);
  82. dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
  83. prefix, cmdcon, cmdarg, cmdsta);
  84. dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
  85. " DSTA:[%08x] DCNT:[%08x]\n",
  86. prefix, datcon, fsta, datsta, datcnt);
  87. dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
  88. " R2:[%08x] R3:[%08x]\n",
  89. prefix, r0, r1, r2, r3);
  90. }
  91. static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
  92. int stop)
  93. {
  94. snprintf(host->dbgmsg_cmd, 300,
  95. "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
  96. host->ccnt, (stop ? " (STOP)" : ""),
  97. cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
  98. if (cmd->data) {
  99. snprintf(host->dbgmsg_dat, 300,
  100. "#%u bsize:%u blocks:%u bytes:%u",
  101. host->dcnt, cmd->data->blksz,
  102. cmd->data->blocks,
  103. cmd->data->blocks * cmd->data->blksz);
  104. } else {
  105. host->dbgmsg_dat[0] = '\0';
  106. }
  107. }
  108. static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
  109. int fail)
  110. {
  111. unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
  112. if (!cmd)
  113. return;
  114. if (cmd->error == 0) {
  115. dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
  116. host->dbgmsg_cmd, cmd->resp[0]);
  117. } else {
  118. dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
  119. cmd->error, host->dbgmsg_cmd, host->status);
  120. }
  121. if (!cmd->data)
  122. return;
  123. if (cmd->data->error == 0) {
  124. dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
  125. } else {
  126. dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
  127. cmd->data->error, host->dbgmsg_dat,
  128. readl(host->base + S3C2410_SDIDCNT));
  129. }
  130. }
  131. #else
  132. static void dbg_dumpcmd(struct s3cmci_host *host,
  133. struct mmc_command *cmd, int fail) { }
  134. static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
  135. int stop) { }
  136. static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
  137. #endif /* CONFIG_MMC_DEBUG */
  138. static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
  139. {
  140. u32 newmask;
  141. newmask = readl(host->base + host->sdiimsk);
  142. newmask |= imask;
  143. writel(newmask, host->base + host->sdiimsk);
  144. return newmask;
  145. }
  146. static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
  147. {
  148. u32 newmask;
  149. newmask = readl(host->base + host->sdiimsk);
  150. newmask &= ~imask;
  151. writel(newmask, host->base + host->sdiimsk);
  152. return newmask;
  153. }
  154. static inline void clear_imask(struct s3cmci_host *host)
  155. {
  156. writel(0, host->base + host->sdiimsk);
  157. }
  158. static inline int get_data_buffer(struct s3cmci_host *host,
  159. u32 *bytes, u32 **pointer)
  160. {
  161. struct scatterlist *sg;
  162. if (host->pio_active == XFER_NONE)
  163. return -EINVAL;
  164. if ((!host->mrq) || (!host->mrq->data))
  165. return -EINVAL;
  166. if (host->pio_sgptr >= host->mrq->data->sg_len) {
  167. dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
  168. host->pio_sgptr, host->mrq->data->sg_len);
  169. return -EBUSY;
  170. }
  171. sg = &host->mrq->data->sg[host->pio_sgptr];
  172. *bytes = sg->length;
  173. *pointer = sg_virt(sg);
  174. host->pio_sgptr++;
  175. dbg(host, dbg_sg, "new buffer (%i/%i)\n",
  176. host->pio_sgptr, host->mrq->data->sg_len);
  177. return 0;
  178. }
  179. static inline u32 fifo_count(struct s3cmci_host *host)
  180. {
  181. u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
  182. fifostat &= S3C2410_SDIFSTA_COUNTMASK;
  183. return fifostat;
  184. }
  185. static inline u32 fifo_free(struct s3cmci_host *host)
  186. {
  187. u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
  188. fifostat &= S3C2410_SDIFSTA_COUNTMASK;
  189. return 63 - fifostat;
  190. }
  191. static void do_pio_read(struct s3cmci_host *host)
  192. {
  193. int res;
  194. u32 fifo;
  195. u32 *ptr;
  196. u32 fifo_words;
  197. void __iomem *from_ptr;
  198. /* write real prescaler to host, it might be set slow to fix */
  199. writel(host->prescaler, host->base + S3C2410_SDIPRE);
  200. from_ptr = host->base + host->sdidata;
  201. while ((fifo = fifo_count(host))) {
  202. if (!host->pio_bytes) {
  203. res = get_data_buffer(host, &host->pio_bytes,
  204. &host->pio_ptr);
  205. if (res) {
  206. host->pio_active = XFER_NONE;
  207. host->complete_what = COMPLETION_FINALIZE;
  208. dbg(host, dbg_pio, "pio_read(): "
  209. "complete (no more data).\n");
  210. return;
  211. }
  212. dbg(host, dbg_pio,
  213. "pio_read(): new target: [%i]@[%p]\n",
  214. host->pio_bytes, host->pio_ptr);
  215. }
  216. dbg(host, dbg_pio,
  217. "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
  218. fifo, host->pio_bytes,
  219. readl(host->base + S3C2410_SDIDCNT));
  220. /* If we have reached the end of the block, we can
  221. * read a word and get 1 to 3 bytes. If we in the
  222. * middle of the block, we have to read full words,
  223. * otherwise we will write garbage, so round down to
  224. * an even multiple of 4. */
  225. if (fifo >= host->pio_bytes)
  226. fifo = host->pio_bytes;
  227. else
  228. fifo -= fifo & 3;
  229. host->pio_bytes -= fifo;
  230. host->pio_count += fifo;
  231. fifo_words = fifo >> 2;
  232. ptr = host->pio_ptr;
  233. while (fifo_words--)
  234. *ptr++ = readl(from_ptr);
  235. host->pio_ptr = ptr;
  236. if (fifo & 3) {
  237. u32 n = fifo & 3;
  238. u32 data = readl(from_ptr);
  239. u8 *p = (u8 *)host->pio_ptr;
  240. while (n--) {
  241. *p++ = data;
  242. data >>= 8;
  243. }
  244. }
  245. }
  246. if (!host->pio_bytes) {
  247. res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
  248. if (res) {
  249. dbg(host, dbg_pio,
  250. "pio_read(): complete (no more buffers).\n");
  251. host->pio_active = XFER_NONE;
  252. host->complete_what = COMPLETION_FINALIZE;
  253. return;
  254. }
  255. }
  256. enable_imask(host,
  257. S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
  258. }
  259. static void do_pio_write(struct s3cmci_host *host)
  260. {
  261. void __iomem *to_ptr;
  262. int res;
  263. u32 fifo;
  264. u32 *ptr;
  265. to_ptr = host->base + host->sdidata;
  266. while ((fifo = fifo_free(host)) > 3) {
  267. if (!host->pio_bytes) {
  268. res = get_data_buffer(host, &host->pio_bytes,
  269. &host->pio_ptr);
  270. if (res) {
  271. dbg(host, dbg_pio,
  272. "pio_write(): complete (no more data).\n");
  273. host->pio_active = XFER_NONE;
  274. return;
  275. }
  276. dbg(host, dbg_pio,
  277. "pio_write(): new source: [%i]@[%p]\n",
  278. host->pio_bytes, host->pio_ptr);
  279. }
  280. /* If we have reached the end of the block, we have to
  281. * write exactly the remaining number of bytes. If we
  282. * in the middle of the block, we have to write full
  283. * words, so round down to an even multiple of 4. */
  284. if (fifo >= host->pio_bytes)
  285. fifo = host->pio_bytes;
  286. else
  287. fifo -= fifo & 3;
  288. host->pio_bytes -= fifo;
  289. host->pio_count += fifo;
  290. fifo = (fifo + 3) >> 2;
  291. ptr = host->pio_ptr;
  292. while (fifo--)
  293. writel(*ptr++, to_ptr);
  294. host->pio_ptr = ptr;
  295. }
  296. enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
  297. }
  298. static void pio_tasklet(unsigned long data)
  299. {
  300. struct s3cmci_host *host = (struct s3cmci_host *) data;
  301. disable_irq(host->irq);
  302. if (host->pio_active == XFER_WRITE)
  303. do_pio_write(host);
  304. if (host->pio_active == XFER_READ)
  305. do_pio_read(host);
  306. if (host->complete_what == COMPLETION_FINALIZE) {
  307. clear_imask(host);
  308. if (host->pio_active != XFER_NONE) {
  309. dbg(host, dbg_err, "unfinished %s "
  310. "- pio_count:[%u] pio_bytes:[%u]\n",
  311. (host->pio_active == XFER_READ) ? "read" : "write",
  312. host->pio_count, host->pio_bytes);
  313. if (host->mrq->data)
  314. host->mrq->data->error = -EINVAL;
  315. }
  316. finalize_request(host);
  317. } else
  318. enable_irq(host->irq);
  319. }
  320. /*
  321. * ISR for SDI Interface IRQ
  322. * Communication between driver and ISR works as follows:
  323. * host->mrq points to current request
  324. * host->complete_what Indicates when the request is considered done
  325. * COMPLETION_CMDSENT when the command was sent
  326. * COMPLETION_RSPFIN when a response was received
  327. * COMPLETION_XFERFINISH when the data transfer is finished
  328. * COMPLETION_XFERFINISH_RSPFIN both of the above.
  329. * host->complete_request is the completion-object the driver waits for
  330. *
  331. * 1) Driver sets up host->mrq and host->complete_what
  332. * 2) Driver prepares the transfer
  333. * 3) Driver enables interrupts
  334. * 4) Driver starts transfer
  335. * 5) Driver waits for host->complete_rquest
  336. * 6) ISR checks for request status (errors and success)
  337. * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
  338. * 7) ISR completes host->complete_request
  339. * 8) ISR disables interrupts
  340. * 9) Driver wakes up and takes care of the request
  341. *
  342. * Note: "->error"-fields are expected to be set to 0 before the request
  343. * was issued by mmc.c - therefore they are only set, when an error
  344. * contition comes up
  345. */
  346. static irqreturn_t s3cmci_irq(int irq, void *dev_id)
  347. {
  348. struct s3cmci_host *host = dev_id;
  349. struct mmc_command *cmd;
  350. u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
  351. u32 mci_cclear, mci_dclear;
  352. unsigned long iflags;
  353. spin_lock_irqsave(&host->complete_lock, iflags);
  354. mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
  355. mci_dsta = readl(host->base + S3C2410_SDIDSTA);
  356. mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
  357. mci_fsta = readl(host->base + S3C2410_SDIFSTA);
  358. mci_imsk = readl(host->base + host->sdiimsk);
  359. mci_cclear = 0;
  360. mci_dclear = 0;
  361. if ((host->complete_what == COMPLETION_NONE) ||
  362. (host->complete_what == COMPLETION_FINALIZE)) {
  363. host->status = "nothing to complete";
  364. clear_imask(host);
  365. goto irq_out;
  366. }
  367. if (!host->mrq) {
  368. host->status = "no active mrq";
  369. clear_imask(host);
  370. goto irq_out;
  371. }
  372. cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
  373. if (!cmd) {
  374. host->status = "no active cmd";
  375. clear_imask(host);
  376. goto irq_out;
  377. }
  378. if (!host->dodma) {
  379. if ((host->pio_active == XFER_WRITE) &&
  380. (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
  381. disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
  382. tasklet_schedule(&host->pio_tasklet);
  383. host->status = "pio tx";
  384. }
  385. if ((host->pio_active == XFER_READ) &&
  386. (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
  387. disable_imask(host,
  388. S3C2410_SDIIMSK_RXFIFOHALF |
  389. S3C2410_SDIIMSK_RXFIFOLAST);
  390. tasklet_schedule(&host->pio_tasklet);
  391. host->status = "pio rx";
  392. }
  393. }
  394. if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
  395. dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
  396. cmd->error = -ETIMEDOUT;
  397. host->status = "error: command timeout";
  398. goto fail_transfer;
  399. }
  400. if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
  401. if (host->complete_what == COMPLETION_CMDSENT) {
  402. host->status = "ok: command sent";
  403. goto close_transfer;
  404. }
  405. mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
  406. }
  407. if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
  408. if (cmd->flags & MMC_RSP_CRC) {
  409. if (host->mrq->cmd->flags & MMC_RSP_136) {
  410. dbg(host, dbg_irq,
  411. "fixup: ignore CRC fail with long rsp\n");
  412. } else {
  413. /* note, we used to fail the transfer
  414. * here, but it seems that this is just
  415. * the hardware getting it wrong.
  416. *
  417. * cmd->error = -EILSEQ;
  418. * host->status = "error: bad command crc";
  419. * goto fail_transfer;
  420. */
  421. }
  422. }
  423. mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
  424. }
  425. if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
  426. if (host->complete_what == COMPLETION_RSPFIN) {
  427. host->status = "ok: command response received";
  428. goto close_transfer;
  429. }
  430. if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
  431. host->complete_what = COMPLETION_XFERFINISH;
  432. mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
  433. }
  434. /* errors handled after this point are only relevant
  435. when a data transfer is in progress */
  436. if (!cmd->data)
  437. goto clear_status_bits;
  438. /* Check for FIFO failure */
  439. if (host->is2440) {
  440. if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
  441. dbg(host, dbg_err, "FIFO failure\n");
  442. host->mrq->data->error = -EILSEQ;
  443. host->status = "error: 2440 fifo failure";
  444. goto fail_transfer;
  445. }
  446. } else {
  447. if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
  448. dbg(host, dbg_err, "FIFO failure\n");
  449. cmd->data->error = -EILSEQ;
  450. host->status = "error: fifo failure";
  451. goto fail_transfer;
  452. }
  453. }
  454. if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
  455. dbg(host, dbg_err, "bad data crc (outgoing)\n");
  456. cmd->data->error = -EILSEQ;
  457. host->status = "error: bad data crc (outgoing)";
  458. goto fail_transfer;
  459. }
  460. if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
  461. dbg(host, dbg_err, "bad data crc (incoming)\n");
  462. cmd->data->error = -EILSEQ;
  463. host->status = "error: bad data crc (incoming)";
  464. goto fail_transfer;
  465. }
  466. if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
  467. dbg(host, dbg_err, "data timeout\n");
  468. cmd->data->error = -ETIMEDOUT;
  469. host->status = "error: data timeout";
  470. goto fail_transfer;
  471. }
  472. if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
  473. if (host->complete_what == COMPLETION_XFERFINISH) {
  474. host->status = "ok: data transfer completed";
  475. goto close_transfer;
  476. }
  477. if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
  478. host->complete_what = COMPLETION_RSPFIN;
  479. mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
  480. }
  481. clear_status_bits:
  482. writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
  483. writel(mci_dclear, host->base + S3C2410_SDIDSTA);
  484. goto irq_out;
  485. fail_transfer:
  486. host->pio_active = XFER_NONE;
  487. close_transfer:
  488. host->complete_what = COMPLETION_FINALIZE;
  489. clear_imask(host);
  490. tasklet_schedule(&host->pio_tasklet);
  491. goto irq_out;
  492. irq_out:
  493. dbg(host, dbg_irq,
  494. "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
  495. mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
  496. spin_unlock_irqrestore(&host->complete_lock, iflags);
  497. return IRQ_HANDLED;
  498. }
  499. /*
  500. * ISR for the CardDetect Pin
  501. */
  502. static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
  503. {
  504. struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
  505. dbg(host, dbg_irq, "card detect\n");
  506. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  507. return IRQ_HANDLED;
  508. }
  509. static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
  510. void *buf_id, int size,
  511. enum s3c2410_dma_buffresult result)
  512. {
  513. struct s3cmci_host *host = buf_id;
  514. unsigned long iflags;
  515. u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
  516. mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
  517. mci_dsta = readl(host->base + S3C2410_SDIDSTA);
  518. mci_fsta = readl(host->base + S3C2410_SDIFSTA);
  519. mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
  520. BUG_ON(!host->mrq);
  521. BUG_ON(!host->mrq->data);
  522. BUG_ON(!host->dmatogo);
  523. spin_lock_irqsave(&host->complete_lock, iflags);
  524. if (result != S3C2410_RES_OK) {
  525. dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
  526. "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
  527. mci_csta, mci_dsta, mci_fsta,
  528. mci_dcnt, result, host->dmatogo);
  529. goto fail_request;
  530. }
  531. host->dmatogo--;
  532. if (host->dmatogo) {
  533. dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] "
  534. "DCNT:[%08x] toGo:%u\n",
  535. size, mci_dsta, mci_dcnt, host->dmatogo);
  536. goto out;
  537. }
  538. dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
  539. size, mci_dsta, mci_dcnt);
  540. host->complete_what = COMPLETION_FINALIZE;
  541. out:
  542. tasklet_schedule(&host->pio_tasklet);
  543. spin_unlock_irqrestore(&host->complete_lock, iflags);
  544. return;
  545. fail_request:
  546. host->mrq->data->error = -EINVAL;
  547. host->complete_what = COMPLETION_FINALIZE;
  548. clear_imask(host);
  549. goto out;
  550. }
  551. static void finalize_request(struct s3cmci_host *host)
  552. {
  553. struct mmc_request *mrq = host->mrq;
  554. struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
  555. int debug_as_failure = 0;
  556. if (host->complete_what != COMPLETION_FINALIZE)
  557. return;
  558. if (!mrq)
  559. return;
  560. if (cmd->data && (cmd->error == 0) &&
  561. (cmd->data->error == 0)) {
  562. if (host->dodma && (!host->dma_complete)) {
  563. dbg(host, dbg_dma, "DMA Missing!\n");
  564. return;
  565. }
  566. }
  567. /* Read response from controller. */
  568. cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
  569. cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
  570. cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
  571. cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
  572. writel(host->prescaler, host->base + S3C2410_SDIPRE);
  573. if (cmd->error)
  574. debug_as_failure = 1;
  575. if (cmd->data && cmd->data->error)
  576. debug_as_failure = 1;
  577. dbg_dumpcmd(host, cmd, debug_as_failure);
  578. /* Cleanup controller */
  579. writel(0, host->base + S3C2410_SDICMDARG);
  580. writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
  581. writel(0, host->base + S3C2410_SDICMDCON);
  582. clear_imask(host);
  583. if (cmd->data && cmd->error)
  584. cmd->data->error = cmd->error;
  585. if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
  586. host->cmd_is_stop = 1;
  587. s3cmci_send_request(host->mmc);
  588. return;
  589. }
  590. /* If we have no data transfer we are finished here */
  591. if (!mrq->data)
  592. goto request_done;
  593. /* Calulate the amout of bytes transfer if there was no error */
  594. if (mrq->data->error == 0) {
  595. mrq->data->bytes_xfered =
  596. (mrq->data->blocks * mrq->data->blksz);
  597. } else {
  598. mrq->data->bytes_xfered = 0;
  599. }
  600. /* If we had an error while transfering data we flush the
  601. * DMA channel and the fifo to clear out any garbage. */
  602. if (mrq->data->error != 0) {
  603. if (host->dodma)
  604. s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
  605. if (host->is2440) {
  606. /* Clear failure register and reset fifo. */
  607. writel(S3C2440_SDIFSTA_FIFORESET |
  608. S3C2440_SDIFSTA_FIFOFAIL,
  609. host->base + S3C2410_SDIFSTA);
  610. } else {
  611. u32 mci_con;
  612. /* reset fifo */
  613. mci_con = readl(host->base + S3C2410_SDICON);
  614. mci_con |= S3C2410_SDICON_FIFORESET;
  615. writel(mci_con, host->base + S3C2410_SDICON);
  616. }
  617. }
  618. request_done:
  619. host->complete_what = COMPLETION_NONE;
  620. host->mrq = NULL;
  621. mmc_request_done(host->mmc, mrq);
  622. }
  623. static void s3cmci_dma_setup(struct s3cmci_host *host,
  624. enum s3c2410_dmasrc source)
  625. {
  626. static enum s3c2410_dmasrc last_source = -1;
  627. static int setup_ok;
  628. if (last_source == source)
  629. return;
  630. last_source = source;
  631. s3c2410_dma_devconfig(host->dma, source,
  632. host->mem->start + host->sdidata);
  633. if (!setup_ok) {
  634. s3c2410_dma_config(host->dma, 4);
  635. s3c2410_dma_set_buffdone_fn(host->dma,
  636. s3cmci_dma_done_callback);
  637. s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
  638. setup_ok = 1;
  639. }
  640. }
  641. static void s3cmci_send_command(struct s3cmci_host *host,
  642. struct mmc_command *cmd)
  643. {
  644. u32 ccon, imsk;
  645. imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
  646. S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
  647. S3C2410_SDIIMSK_RESPONSECRC;
  648. enable_imask(host, imsk);
  649. if (cmd->data)
  650. host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
  651. else if (cmd->flags & MMC_RSP_PRESENT)
  652. host->complete_what = COMPLETION_RSPFIN;
  653. else
  654. host->complete_what = COMPLETION_CMDSENT;
  655. writel(cmd->arg, host->base + S3C2410_SDICMDARG);
  656. ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
  657. ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
  658. if (cmd->flags & MMC_RSP_PRESENT)
  659. ccon |= S3C2410_SDICMDCON_WAITRSP;
  660. if (cmd->flags & MMC_RSP_136)
  661. ccon |= S3C2410_SDICMDCON_LONGRSP;
  662. writel(ccon, host->base + S3C2410_SDICMDCON);
  663. }
  664. static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
  665. {
  666. u32 dcon, imsk, stoptries = 3;
  667. /* write DCON register */
  668. if (!data) {
  669. writel(0, host->base + S3C2410_SDIDCON);
  670. return 0;
  671. }
  672. if ((data->blksz & 3) != 0) {
  673. /* We cannot deal with unaligned blocks with more than
  674. * one block being transfered. */
  675. if (data->blocks > 1) {
  676. pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz);
  677. return -EINVAL;
  678. }
  679. }
  680. while (readl(host->base + S3C2410_SDIDSTA) &
  681. (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
  682. dbg(host, dbg_err,
  683. "mci_setup_data() transfer stillin progress.\n");
  684. writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
  685. s3cmci_reset(host);
  686. if ((stoptries--) == 0) {
  687. dbg_dumpregs(host, "DRF");
  688. return -EINVAL;
  689. }
  690. }
  691. dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
  692. if (host->dodma)
  693. dcon |= S3C2410_SDIDCON_DMAEN;
  694. if (host->bus_width == MMC_BUS_WIDTH_4)
  695. dcon |= S3C2410_SDIDCON_WIDEBUS;
  696. if (!(data->flags & MMC_DATA_STREAM))
  697. dcon |= S3C2410_SDIDCON_BLOCKMODE;
  698. if (data->flags & MMC_DATA_WRITE) {
  699. dcon |= S3C2410_SDIDCON_TXAFTERRESP;
  700. dcon |= S3C2410_SDIDCON_XFER_TXSTART;
  701. }
  702. if (data->flags & MMC_DATA_READ) {
  703. dcon |= S3C2410_SDIDCON_RXAFTERCMD;
  704. dcon |= S3C2410_SDIDCON_XFER_RXSTART;
  705. }
  706. if (host->is2440) {
  707. dcon |= S3C2440_SDIDCON_DS_WORD;
  708. dcon |= S3C2440_SDIDCON_DATSTART;
  709. }
  710. writel(dcon, host->base + S3C2410_SDIDCON);
  711. /* write BSIZE register */
  712. writel(data->blksz, host->base + S3C2410_SDIBSIZE);
  713. /* add to IMASK register */
  714. imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
  715. S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
  716. enable_imask(host, imsk);
  717. /* write TIMER register */
  718. if (host->is2440) {
  719. writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
  720. } else {
  721. writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
  722. /* FIX: set slow clock to prevent timeouts on read */
  723. if (data->flags & MMC_DATA_READ)
  724. writel(0xFF, host->base + S3C2410_SDIPRE);
  725. }
  726. return 0;
  727. }
  728. #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
  729. static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
  730. {
  731. int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
  732. BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
  733. host->pio_sgptr = 0;
  734. host->pio_bytes = 0;
  735. host->pio_count = 0;
  736. host->pio_active = rw ? XFER_WRITE : XFER_READ;
  737. if (rw) {
  738. do_pio_write(host);
  739. enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
  740. } else {
  741. enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
  742. | S3C2410_SDIIMSK_RXFIFOLAST);
  743. }
  744. return 0;
  745. }
  746. static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
  747. {
  748. int dma_len, i;
  749. int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
  750. BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
  751. s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW);
  752. s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
  753. dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  754. (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  755. if (dma_len == 0)
  756. return -ENOMEM;
  757. host->dma_complete = 0;
  758. host->dmatogo = dma_len;
  759. for (i = 0; i < dma_len; i++) {
  760. int res;
  761. dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i,
  762. sg_dma_address(&data->sg[i]),
  763. sg_dma_len(&data->sg[i]));
  764. res = s3c2410_dma_enqueue(host->dma, (void *) host,
  765. sg_dma_address(&data->sg[i]),
  766. sg_dma_len(&data->sg[i]));
  767. if (res) {
  768. s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
  769. return -EBUSY;
  770. }
  771. }
  772. s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
  773. return 0;
  774. }
  775. static void s3cmci_send_request(struct mmc_host *mmc)
  776. {
  777. struct s3cmci_host *host = mmc_priv(mmc);
  778. struct mmc_request *mrq = host->mrq;
  779. struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
  780. host->ccnt++;
  781. prepare_dbgmsg(host, cmd, host->cmd_is_stop);
  782. /* Clear command, data and fifo status registers
  783. Fifo clear only necessary on 2440, but doesn't hurt on 2410
  784. */
  785. writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
  786. writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
  787. writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
  788. if (cmd->data) {
  789. int res = s3cmci_setup_data(host, cmd->data);
  790. host->dcnt++;
  791. if (res) {
  792. dbg(host, dbg_err, "setup data error %d\n", res);
  793. cmd->error = res;
  794. cmd->data->error = res;
  795. mmc_request_done(mmc, mrq);
  796. return;
  797. }
  798. if (host->dodma)
  799. res = s3cmci_prepare_dma(host, cmd->data);
  800. else
  801. res = s3cmci_prepare_pio(host, cmd->data);
  802. if (res) {
  803. dbg(host, dbg_err, "data prepare error %d\n", res);
  804. cmd->error = res;
  805. cmd->data->error = res;
  806. mmc_request_done(mmc, mrq);
  807. return;
  808. }
  809. }
  810. /* Send command */
  811. s3cmci_send_command(host, cmd);
  812. /* Enable Interrupt */
  813. enable_irq(host->irq);
  814. }
  815. static int s3cmci_card_present(struct mmc_host *mmc)
  816. {
  817. struct s3cmci_host *host = mmc_priv(mmc);
  818. struct s3c24xx_mci_pdata *pdata = host->pdata;
  819. int ret;
  820. if (pdata->gpio_detect == 0)
  821. return -ENOSYS;
  822. ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
  823. return ret ^ pdata->detect_invert;
  824. }
  825. static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  826. {
  827. struct s3cmci_host *host = mmc_priv(mmc);
  828. host->status = "mmc request";
  829. host->cmd_is_stop = 0;
  830. host->mrq = mrq;
  831. if (s3cmci_card_present(mmc) == 0) {
  832. dbg(host, dbg_err, "%s: no medium present\n", __func__);
  833. host->mrq->cmd->error = -ENOMEDIUM;
  834. mmc_request_done(mmc, mrq);
  835. } else
  836. s3cmci_send_request(mmc);
  837. }
  838. static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
  839. {
  840. u32 mci_psc;
  841. /* Set clock */
  842. for (mci_psc = 0; mci_psc < 255; mci_psc++) {
  843. host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
  844. if (host->real_rate <= ios->clock)
  845. break;
  846. }
  847. if (mci_psc > 255)
  848. mci_psc = 255;
  849. host->prescaler = mci_psc;
  850. writel(host->prescaler, host->base + S3C2410_SDIPRE);
  851. /* If requested clock is 0, real_rate will be 0, too */
  852. if (ios->clock == 0)
  853. host->real_rate = 0;
  854. }
  855. static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  856. {
  857. struct s3cmci_host *host = mmc_priv(mmc);
  858. u32 mci_con;
  859. /* Set the power state */
  860. mci_con = readl(host->base + S3C2410_SDICON);
  861. switch (ios->power_mode) {
  862. case MMC_POWER_ON:
  863. case MMC_POWER_UP:
  864. s3c2410_gpio_cfgpin(S3C2410_GPE(5), S3C2410_GPE5_SDCLK);
  865. s3c2410_gpio_cfgpin(S3C2410_GPE(6), S3C2410_GPE6_SDCMD);
  866. s3c2410_gpio_cfgpin(S3C2410_GPE(7), S3C2410_GPE7_SDDAT0);
  867. s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
  868. s3c2410_gpio_cfgpin(S3C2410_GPE(9), S3C2410_GPE9_SDDAT2);
  869. s3c2410_gpio_cfgpin(S3C2410_GPE(10), S3C2410_GPE10_SDDAT3);
  870. if (host->pdata->set_power)
  871. host->pdata->set_power(ios->power_mode, ios->vdd);
  872. if (!host->is2440)
  873. mci_con |= S3C2410_SDICON_FIFORESET;
  874. break;
  875. case MMC_POWER_OFF:
  876. default:
  877. gpio_direction_output(S3C2410_GPE(5), 0);
  878. if (host->is2440)
  879. mci_con |= S3C2440_SDICON_SDRESET;
  880. if (host->pdata->set_power)
  881. host->pdata->set_power(ios->power_mode, ios->vdd);
  882. break;
  883. }
  884. s3cmci_set_clk(host, ios);
  885. /* Set CLOCK_ENABLE */
  886. if (ios->clock)
  887. mci_con |= S3C2410_SDICON_CLOCKTYPE;
  888. else
  889. mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
  890. writel(mci_con, host->base + S3C2410_SDICON);
  891. if ((ios->power_mode == MMC_POWER_ON) ||
  892. (ios->power_mode == MMC_POWER_UP)) {
  893. dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
  894. host->real_rate/1000, ios->clock/1000);
  895. } else {
  896. dbg(host, dbg_conf, "powered down.\n");
  897. }
  898. host->bus_width = ios->bus_width;
  899. }
  900. static void s3cmci_reset(struct s3cmci_host *host)
  901. {
  902. u32 con = readl(host->base + S3C2410_SDICON);
  903. con |= S3C2440_SDICON_SDRESET;
  904. writel(con, host->base + S3C2410_SDICON);
  905. }
  906. static int s3cmci_get_ro(struct mmc_host *mmc)
  907. {
  908. struct s3cmci_host *host = mmc_priv(mmc);
  909. struct s3c24xx_mci_pdata *pdata = host->pdata;
  910. int ret;
  911. if (pdata->gpio_wprotect == 0)
  912. return 0;
  913. ret = s3c2410_gpio_getpin(pdata->gpio_wprotect);
  914. if (pdata->wprotect_invert)
  915. ret = !ret;
  916. return ret;
  917. }
  918. static struct mmc_host_ops s3cmci_ops = {
  919. .request = s3cmci_request,
  920. .set_ios = s3cmci_set_ios,
  921. .get_ro = s3cmci_get_ro,
  922. .get_cd = s3cmci_card_present,
  923. };
  924. static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
  925. /* This is currently here to avoid a number of if (host->pdata)
  926. * checks. Any zero fields to ensure reaonable defaults are picked. */
  927. };
  928. #ifdef CONFIG_CPU_FREQ
  929. static int s3cmci_cpufreq_transition(struct notifier_block *nb,
  930. unsigned long val, void *data)
  931. {
  932. struct s3cmci_host *host;
  933. struct mmc_host *mmc;
  934. unsigned long newclk;
  935. unsigned long flags;
  936. host = container_of(nb, struct s3cmci_host, freq_transition);
  937. newclk = clk_get_rate(host->clk);
  938. mmc = host->mmc;
  939. if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
  940. (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
  941. spin_lock_irqsave(&mmc->lock, flags);
  942. host->clk_rate = newclk;
  943. if (mmc->ios.power_mode != MMC_POWER_OFF &&
  944. mmc->ios.clock != 0)
  945. s3cmci_set_clk(host, &mmc->ios);
  946. spin_unlock_irqrestore(&mmc->lock, flags);
  947. }
  948. return 0;
  949. }
  950. static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
  951. {
  952. host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
  953. return cpufreq_register_notifier(&host->freq_transition,
  954. CPUFREQ_TRANSITION_NOTIFIER);
  955. }
  956. static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
  957. {
  958. cpufreq_unregister_notifier(&host->freq_transition,
  959. CPUFREQ_TRANSITION_NOTIFIER);
  960. }
  961. #else
  962. static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
  963. {
  964. return 0;
  965. }
  966. static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
  967. {
  968. }
  969. #endif
  970. #ifdef CONFIG_DEBUG_FS
  971. static int s3cmci_state_show(struct seq_file *seq, void *v)
  972. {
  973. struct s3cmci_host *host = seq->private;
  974. seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
  975. seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
  976. seq_printf(seq, "Prescale = %d\n", host->prescaler);
  977. seq_printf(seq, "is2440 = %d\n", host->is2440);
  978. seq_printf(seq, "IRQ = %d\n", host->irq);
  979. seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
  980. seq_printf(seq, "Do DMA = %d\n", host->dodma);
  981. seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
  982. seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
  983. return 0;
  984. }
  985. static int s3cmci_state_open(struct inode *inode, struct file *file)
  986. {
  987. return single_open(file, s3cmci_state_show, inode->i_private);
  988. }
  989. static const struct file_operations s3cmci_fops_state = {
  990. .owner = THIS_MODULE,
  991. .open = s3cmci_state_open,
  992. .read = seq_read,
  993. .llseek = seq_lseek,
  994. .release = single_release,
  995. };
  996. #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
  997. struct s3cmci_reg {
  998. unsigned short addr;
  999. unsigned char *name;
  1000. } debug_regs[] = {
  1001. DBG_REG(CON),
  1002. DBG_REG(PRE),
  1003. DBG_REG(CMDARG),
  1004. DBG_REG(CMDCON),
  1005. DBG_REG(CMDSTAT),
  1006. DBG_REG(RSP0),
  1007. DBG_REG(RSP1),
  1008. DBG_REG(RSP2),
  1009. DBG_REG(RSP3),
  1010. DBG_REG(TIMER),
  1011. DBG_REG(BSIZE),
  1012. DBG_REG(DCON),
  1013. DBG_REG(DCNT),
  1014. DBG_REG(DSTA),
  1015. DBG_REG(FSTA),
  1016. {}
  1017. };
  1018. static int s3cmci_regs_show(struct seq_file *seq, void *v)
  1019. {
  1020. struct s3cmci_host *host = seq->private;
  1021. struct s3cmci_reg *rptr = debug_regs;
  1022. for (; rptr->name; rptr++)
  1023. seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
  1024. readl(host->base + rptr->addr));
  1025. seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
  1026. return 0;
  1027. }
  1028. static int s3cmci_regs_open(struct inode *inode, struct file *file)
  1029. {
  1030. return single_open(file, s3cmci_regs_show, inode->i_private);
  1031. }
  1032. static const struct file_operations s3cmci_fops_regs = {
  1033. .owner = THIS_MODULE,
  1034. .open = s3cmci_regs_open,
  1035. .read = seq_read,
  1036. .llseek = seq_lseek,
  1037. .release = single_release,
  1038. };
  1039. static void s3cmci_debugfs_attach(struct s3cmci_host *host)
  1040. {
  1041. struct device *dev = &host->pdev->dev;
  1042. host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
  1043. if (IS_ERR(host->debug_root)) {
  1044. dev_err(dev, "failed to create debugfs root\n");
  1045. return;
  1046. }
  1047. host->debug_state = debugfs_create_file("state", 0444,
  1048. host->debug_root, host,
  1049. &s3cmci_fops_state);
  1050. if (IS_ERR(host->debug_state))
  1051. dev_err(dev, "failed to create debug state file\n");
  1052. host->debug_regs = debugfs_create_file("regs", 0444,
  1053. host->debug_root, host,
  1054. &s3cmci_fops_regs);
  1055. if (IS_ERR(host->debug_regs))
  1056. dev_err(dev, "failed to create debug regs file\n");
  1057. }
  1058. static void s3cmci_debugfs_remove(struct s3cmci_host *host)
  1059. {
  1060. debugfs_remove(host->debug_regs);
  1061. debugfs_remove(host->debug_state);
  1062. debugfs_remove(host->debug_root);
  1063. }
  1064. #else
  1065. static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
  1066. static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
  1067. #endif /* CONFIG_DEBUG_FS */
  1068. static int __devinit s3cmci_probe(struct platform_device *pdev)
  1069. {
  1070. struct s3cmci_host *host;
  1071. struct mmc_host *mmc;
  1072. int ret;
  1073. int is2440;
  1074. int i;
  1075. is2440 = platform_get_device_id(pdev)->driver_data;
  1076. mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
  1077. if (!mmc) {
  1078. ret = -ENOMEM;
  1079. goto probe_out;
  1080. }
  1081. for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
  1082. ret = gpio_request(i, dev_name(&pdev->dev));
  1083. if (ret) {
  1084. dev_err(&pdev->dev, "failed to get gpio %d\n", i);
  1085. for (i--; i >= S3C2410_GPE(5); i--)
  1086. gpio_free(i);
  1087. goto probe_free_host;
  1088. }
  1089. }
  1090. host = mmc_priv(mmc);
  1091. host->mmc = mmc;
  1092. host->pdev = pdev;
  1093. host->is2440 = is2440;
  1094. host->pdata = pdev->dev.platform_data;
  1095. if (!host->pdata) {
  1096. pdev->dev.platform_data = &s3cmci_def_pdata;
  1097. host->pdata = &s3cmci_def_pdata;
  1098. }
  1099. spin_lock_init(&host->complete_lock);
  1100. tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
  1101. if (is2440) {
  1102. host->sdiimsk = S3C2440_SDIIMSK;
  1103. host->sdidata = S3C2440_SDIDATA;
  1104. host->clk_div = 1;
  1105. } else {
  1106. host->sdiimsk = S3C2410_SDIIMSK;
  1107. host->sdidata = S3C2410_SDIDATA;
  1108. host->clk_div = 2;
  1109. }
  1110. host->dodma = 0;
  1111. host->complete_what = COMPLETION_NONE;
  1112. host->pio_active = XFER_NONE;
  1113. host->dma = S3CMCI_DMA;
  1114. host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1115. if (!host->mem) {
  1116. dev_err(&pdev->dev,
  1117. "failed to get io memory region resouce.\n");
  1118. ret = -ENOENT;
  1119. goto probe_free_gpio;
  1120. }
  1121. host->mem = request_mem_region(host->mem->start,
  1122. resource_size(host->mem), pdev->name);
  1123. if (!host->mem) {
  1124. dev_err(&pdev->dev, "failed to request io memory region.\n");
  1125. ret = -ENOENT;
  1126. goto probe_free_gpio;
  1127. }
  1128. host->base = ioremap(host->mem->start, resource_size(host->mem));
  1129. if (!host->base) {
  1130. dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
  1131. ret = -EINVAL;
  1132. goto probe_free_mem_region;
  1133. }
  1134. host->irq = platform_get_irq(pdev, 0);
  1135. if (host->irq == 0) {
  1136. dev_err(&pdev->dev, "failed to get interrupt resouce.\n");
  1137. ret = -EINVAL;
  1138. goto probe_iounmap;
  1139. }
  1140. if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
  1141. dev_err(&pdev->dev, "failed to request mci interrupt.\n");
  1142. ret = -ENOENT;
  1143. goto probe_iounmap;
  1144. }
  1145. /* We get spurious interrupts even when we have set the IMSK
  1146. * register to ignore everything, so use disable_irq() to make
  1147. * ensure we don't lock the system with un-serviceable requests. */
  1148. disable_irq(host->irq);
  1149. if (host->pdata->gpio_detect) {
  1150. ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
  1151. if (ret) {
  1152. dev_err(&pdev->dev, "failed to get detect gpio\n");
  1153. goto probe_free_irq;
  1154. }
  1155. }
  1156. host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect);
  1157. if (host->irq_cd >= 0) {
  1158. if (request_irq(host->irq_cd, s3cmci_irq_cd,
  1159. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
  1160. DRIVER_NAME, host)) {
  1161. dev_err(&pdev->dev, "can't get card detect irq.\n");
  1162. ret = -ENOENT;
  1163. goto probe_free_gpio_cd;
  1164. }
  1165. } else {
  1166. dev_warn(&pdev->dev, "host detect has no irq available\n");
  1167. gpio_direction_input(host->pdata->gpio_detect);
  1168. }
  1169. if (host->pdata->gpio_wprotect) {
  1170. ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
  1171. if (ret) {
  1172. dev_err(&pdev->dev, "failed to get writeprotect\n");
  1173. goto probe_free_irq_cd;
  1174. }
  1175. gpio_direction_input(host->pdata->gpio_wprotect);
  1176. }
  1177. if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL) < 0) {
  1178. dev_err(&pdev->dev, "unable to get DMA channel.\n");
  1179. ret = -EBUSY;
  1180. goto probe_free_gpio_wp;
  1181. }
  1182. host->clk = clk_get(&pdev->dev, "sdi");
  1183. if (IS_ERR(host->clk)) {
  1184. dev_err(&pdev->dev, "failed to find clock source.\n");
  1185. ret = PTR_ERR(host->clk);
  1186. host->clk = NULL;
  1187. goto probe_free_host;
  1188. }
  1189. ret = clk_enable(host->clk);
  1190. if (ret) {
  1191. dev_err(&pdev->dev, "failed to enable clock source.\n");
  1192. goto clk_free;
  1193. }
  1194. host->clk_rate = clk_get_rate(host->clk);
  1195. mmc->ops = &s3cmci_ops;
  1196. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  1197. mmc->caps = MMC_CAP_4_BIT_DATA;
  1198. mmc->f_min = host->clk_rate / (host->clk_div * 256);
  1199. mmc->f_max = host->clk_rate / host->clk_div;
  1200. if (host->pdata->ocr_avail)
  1201. mmc->ocr_avail = host->pdata->ocr_avail;
  1202. mmc->max_blk_count = 4095;
  1203. mmc->max_blk_size = 4095;
  1204. mmc->max_req_size = 4095 * 512;
  1205. mmc->max_seg_size = mmc->max_req_size;
  1206. mmc->max_phys_segs = 128;
  1207. mmc->max_hw_segs = 128;
  1208. dbg(host, dbg_debug,
  1209. "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
  1210. (host->is2440?"2440":""),
  1211. host->base, host->irq, host->irq_cd, host->dma);
  1212. ret = s3cmci_cpufreq_register(host);
  1213. if (ret) {
  1214. dev_err(&pdev->dev, "failed to register cpufreq\n");
  1215. goto free_dmabuf;
  1216. }
  1217. ret = mmc_add_host(mmc);
  1218. if (ret) {
  1219. dev_err(&pdev->dev, "failed to add mmc host.\n");
  1220. goto free_cpufreq;
  1221. }
  1222. s3cmci_debugfs_attach(host);
  1223. platform_set_drvdata(pdev, mmc);
  1224. dev_info(&pdev->dev, "initialisation done.\n");
  1225. return 0;
  1226. free_cpufreq:
  1227. s3cmci_cpufreq_deregister(host);
  1228. free_dmabuf:
  1229. clk_disable(host->clk);
  1230. clk_free:
  1231. clk_put(host->clk);
  1232. probe_free_gpio_wp:
  1233. if (host->pdata->gpio_wprotect)
  1234. gpio_free(host->pdata->gpio_wprotect);
  1235. probe_free_gpio_cd:
  1236. if (host->pdata->gpio_detect)
  1237. gpio_free(host->pdata->gpio_detect);
  1238. probe_free_irq_cd:
  1239. if (host->irq_cd >= 0)
  1240. free_irq(host->irq_cd, host);
  1241. probe_free_irq:
  1242. free_irq(host->irq, host);
  1243. probe_iounmap:
  1244. iounmap(host->base);
  1245. probe_free_mem_region:
  1246. release_mem_region(host->mem->start, resource_size(host->mem));
  1247. probe_free_gpio:
  1248. for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
  1249. gpio_free(i);
  1250. probe_free_host:
  1251. mmc_free_host(mmc);
  1252. probe_out:
  1253. return ret;
  1254. }
  1255. static void s3cmci_shutdown(struct platform_device *pdev)
  1256. {
  1257. struct mmc_host *mmc = platform_get_drvdata(pdev);
  1258. struct s3cmci_host *host = mmc_priv(mmc);
  1259. if (host->irq_cd >= 0)
  1260. free_irq(host->irq_cd, host);
  1261. s3cmci_debugfs_remove(host);
  1262. s3cmci_cpufreq_deregister(host);
  1263. mmc_remove_host(mmc);
  1264. clk_disable(host->clk);
  1265. }
  1266. static int __devexit s3cmci_remove(struct platform_device *pdev)
  1267. {
  1268. struct mmc_host *mmc = platform_get_drvdata(pdev);
  1269. struct s3cmci_host *host = mmc_priv(mmc);
  1270. struct s3c24xx_mci_pdata *pd = host->pdata;
  1271. int i;
  1272. s3cmci_shutdown(pdev);
  1273. clk_put(host->clk);
  1274. tasklet_disable(&host->pio_tasklet);
  1275. s3c2410_dma_free(S3CMCI_DMA, &s3cmci_dma_client);
  1276. free_irq(host->irq, host);
  1277. if (pd->gpio_wprotect)
  1278. gpio_free(pd->gpio_wprotect);
  1279. if (pd->gpio_detect)
  1280. gpio_free(pd->gpio_detect);
  1281. for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
  1282. gpio_free(i);
  1283. iounmap(host->base);
  1284. release_mem_region(host->mem->start, resource_size(host->mem));
  1285. mmc_free_host(mmc);
  1286. return 0;
  1287. }
  1288. static struct platform_device_id s3cmci_driver_ids[] = {
  1289. {
  1290. .name = "s3c2410-sdi",
  1291. .driver_data = 0,
  1292. }, {
  1293. .name = "s3c2412-sdi",
  1294. .driver_data = 1,
  1295. }, {
  1296. .name = "s3c2440-sdi",
  1297. .driver_data = 1,
  1298. },
  1299. { }
  1300. };
  1301. MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
  1302. #ifdef CONFIG_PM
  1303. static int s3cmci_suspend(struct device *dev)
  1304. {
  1305. struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
  1306. struct pm_message event = { PM_EVENT_SUSPEND };
  1307. return mmc_suspend_host(mmc, event);
  1308. }
  1309. static int s3cmci_resume(struct device *dev)
  1310. {
  1311. struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
  1312. return mmc_resume_host(mmc);
  1313. }
  1314. static struct dev_pm_ops s3cmci_pm = {
  1315. .suspend = s3cmci_suspend,
  1316. .resume = s3cmci_resume,
  1317. };
  1318. #define s3cmci_pm_ops &s3cmci_pm
  1319. #else /* CONFIG_PM */
  1320. #define s3cmci_pm_ops NULL
  1321. #endif /* CONFIG_PM */
  1322. static struct platform_driver s3cmci_driver = {
  1323. .driver = {
  1324. .name = "s3c-sdi",
  1325. .owner = THIS_MODULE,
  1326. .pm = s3cmci_pm_ops,
  1327. },
  1328. .id_table = s3cmci_driver_ids,
  1329. .probe = s3cmci_probe,
  1330. .remove = __devexit_p(s3cmci_remove),
  1331. .shutdown = s3cmci_shutdown,
  1332. };
  1333. static int __init s3cmci_init(void)
  1334. {
  1335. return platform_driver_register(&s3cmci_driver);
  1336. }
  1337. static void __exit s3cmci_exit(void)
  1338. {
  1339. platform_driver_unregister(&s3cmci_driver);
  1340. }
  1341. module_init(s3cmci_init);
  1342. module_exit(s3cmci_exit);
  1343. MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
  1344. MODULE_LICENSE("GPL v2");
  1345. MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");