tx.c 31 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/tcp.h>
  12. #include <linux/ip.h>
  13. #include <linux/in.h>
  14. #include <linux/if_ether.h>
  15. #include <linux/highmem.h>
  16. #include "net_driver.h"
  17. #include "tx.h"
  18. #include "efx.h"
  19. #include "falcon.h"
  20. #include "workarounds.h"
  21. /*
  22. * TX descriptor ring full threshold
  23. *
  24. * The tx_queue descriptor ring fill-level must fall below this value
  25. * before we restart the netif queue
  26. */
  27. #define EFX_TXQ_THRESHOLD (EFX_TXQ_MASK / 2u)
  28. /* We want to be able to nest calls to netif_stop_queue(), since each
  29. * channel can have an individual stop on the queue.
  30. */
  31. void efx_stop_queue(struct efx_nic *efx)
  32. {
  33. spin_lock_bh(&efx->netif_stop_lock);
  34. EFX_TRACE(efx, "stop TX queue\n");
  35. atomic_inc(&efx->netif_stop_count);
  36. netif_stop_queue(efx->net_dev);
  37. spin_unlock_bh(&efx->netif_stop_lock);
  38. }
  39. /* Wake netif's TX queue
  40. * We want to be able to nest calls to netif_stop_queue(), since each
  41. * channel can have an individual stop on the queue.
  42. */
  43. void efx_wake_queue(struct efx_nic *efx)
  44. {
  45. local_bh_disable();
  46. if (atomic_dec_and_lock(&efx->netif_stop_count,
  47. &efx->netif_stop_lock)) {
  48. EFX_TRACE(efx, "waking TX queue\n");
  49. netif_wake_queue(efx->net_dev);
  50. spin_unlock(&efx->netif_stop_lock);
  51. }
  52. local_bh_enable();
  53. }
  54. static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  55. struct efx_tx_buffer *buffer)
  56. {
  57. if (buffer->unmap_len) {
  58. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  59. dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len -
  60. buffer->unmap_len);
  61. if (buffer->unmap_single)
  62. pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len,
  63. PCI_DMA_TODEVICE);
  64. else
  65. pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len,
  66. PCI_DMA_TODEVICE);
  67. buffer->unmap_len = 0;
  68. buffer->unmap_single = false;
  69. }
  70. if (buffer->skb) {
  71. dev_kfree_skb_any((struct sk_buff *) buffer->skb);
  72. buffer->skb = NULL;
  73. EFX_TRACE(tx_queue->efx, "TX queue %d transmission id %x "
  74. "complete\n", tx_queue->queue, read_ptr);
  75. }
  76. }
  77. /**
  78. * struct efx_tso_header - a DMA mapped buffer for packet headers
  79. * @next: Linked list of free ones.
  80. * The list is protected by the TX queue lock.
  81. * @dma_unmap_len: Length to unmap for an oversize buffer, or 0.
  82. * @dma_addr: The DMA address of the header below.
  83. *
  84. * This controls the memory used for a TSO header. Use TSOH_DATA()
  85. * to find the packet header data. Use TSOH_SIZE() to calculate the
  86. * total size required for a given packet header length. TSO headers
  87. * in the free list are exactly %TSOH_STD_SIZE bytes in size.
  88. */
  89. struct efx_tso_header {
  90. union {
  91. struct efx_tso_header *next;
  92. size_t unmap_len;
  93. };
  94. dma_addr_t dma_addr;
  95. };
  96. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  97. struct sk_buff *skb);
  98. static void efx_fini_tso(struct efx_tx_queue *tx_queue);
  99. static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue,
  100. struct efx_tso_header *tsoh);
  101. static void efx_tsoh_free(struct efx_tx_queue *tx_queue,
  102. struct efx_tx_buffer *buffer)
  103. {
  104. if (buffer->tsoh) {
  105. if (likely(!buffer->tsoh->unmap_len)) {
  106. buffer->tsoh->next = tx_queue->tso_headers_free;
  107. tx_queue->tso_headers_free = buffer->tsoh;
  108. } else {
  109. efx_tsoh_heap_free(tx_queue, buffer->tsoh);
  110. }
  111. buffer->tsoh = NULL;
  112. }
  113. }
  114. static inline unsigned
  115. efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr)
  116. {
  117. /* Depending on the NIC revision, we can use descriptor
  118. * lengths up to 8K or 8K-1. However, since PCI Express
  119. * devices must split read requests at 4K boundaries, there is
  120. * little benefit from using descriptors that cross those
  121. * boundaries and we keep things simple by not doing so.
  122. */
  123. unsigned len = (~dma_addr & 0xfff) + 1;
  124. /* Work around hardware bug for unaligned buffers. */
  125. if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf))
  126. len = min_t(unsigned, len, 512 - (dma_addr & 0xf));
  127. return len;
  128. }
  129. /*
  130. * Add a socket buffer to a TX queue
  131. *
  132. * This maps all fragments of a socket buffer for DMA and adds them to
  133. * the TX queue. The queue's insert pointer will be incremented by
  134. * the number of fragments in the socket buffer.
  135. *
  136. * If any DMA mapping fails, any mapped fragments will be unmapped,
  137. * the queue's insert pointer will be restored to its original value.
  138. *
  139. * Returns NETDEV_TX_OK or NETDEV_TX_BUSY
  140. * You must hold netif_tx_lock() to call this function.
  141. */
  142. static netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue,
  143. struct sk_buff *skb)
  144. {
  145. struct efx_nic *efx = tx_queue->efx;
  146. struct pci_dev *pci_dev = efx->pci_dev;
  147. struct efx_tx_buffer *buffer;
  148. skb_frag_t *fragment;
  149. struct page *page;
  150. int page_offset;
  151. unsigned int len, unmap_len = 0, fill_level, insert_ptr;
  152. dma_addr_t dma_addr, unmap_addr = 0;
  153. unsigned int dma_len;
  154. bool unmap_single;
  155. int q_space, i = 0;
  156. netdev_tx_t rc = NETDEV_TX_OK;
  157. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  158. if (skb_shinfo(skb)->gso_size)
  159. return efx_enqueue_skb_tso(tx_queue, skb);
  160. /* Get size of the initial fragment */
  161. len = skb_headlen(skb);
  162. /* Pad if necessary */
  163. if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
  164. EFX_BUG_ON_PARANOID(skb->data_len);
  165. len = 32 + 1;
  166. if (skb_pad(skb, len - skb->len))
  167. return NETDEV_TX_OK;
  168. }
  169. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  170. q_space = EFX_TXQ_MASK - 1 - fill_level;
  171. /* Map for DMA. Use pci_map_single rather than pci_map_page
  172. * since this is more efficient on machines with sparse
  173. * memory.
  174. */
  175. unmap_single = true;
  176. dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  177. /* Process all fragments */
  178. while (1) {
  179. if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr)))
  180. goto pci_err;
  181. /* Store fields for marking in the per-fragment final
  182. * descriptor */
  183. unmap_len = len;
  184. unmap_addr = dma_addr;
  185. /* Add to TX queue, splitting across DMA boundaries */
  186. do {
  187. if (unlikely(q_space-- <= 0)) {
  188. /* It might be that completions have
  189. * happened since the xmit path last
  190. * checked. Update the xmit path's
  191. * copy of read_count.
  192. */
  193. ++tx_queue->stopped;
  194. /* This memory barrier protects the
  195. * change of stopped from the access
  196. * of read_count. */
  197. smp_mb();
  198. tx_queue->old_read_count =
  199. *(volatile unsigned *)
  200. &tx_queue->read_count;
  201. fill_level = (tx_queue->insert_count
  202. - tx_queue->old_read_count);
  203. q_space = EFX_TXQ_MASK - 1 - fill_level;
  204. if (unlikely(q_space-- <= 0))
  205. goto stop;
  206. smp_mb();
  207. --tx_queue->stopped;
  208. }
  209. insert_ptr = tx_queue->insert_count & EFX_TXQ_MASK;
  210. buffer = &tx_queue->buffer[insert_ptr];
  211. efx_tsoh_free(tx_queue, buffer);
  212. EFX_BUG_ON_PARANOID(buffer->tsoh);
  213. EFX_BUG_ON_PARANOID(buffer->skb);
  214. EFX_BUG_ON_PARANOID(buffer->len);
  215. EFX_BUG_ON_PARANOID(!buffer->continuation);
  216. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  217. dma_len = efx_max_tx_len(efx, dma_addr);
  218. if (likely(dma_len >= len))
  219. dma_len = len;
  220. /* Fill out per descriptor fields */
  221. buffer->len = dma_len;
  222. buffer->dma_addr = dma_addr;
  223. len -= dma_len;
  224. dma_addr += dma_len;
  225. ++tx_queue->insert_count;
  226. } while (len);
  227. /* Transfer ownership of the unmapping to the final buffer */
  228. buffer->unmap_single = unmap_single;
  229. buffer->unmap_len = unmap_len;
  230. unmap_len = 0;
  231. /* Get address and size of next fragment */
  232. if (i >= skb_shinfo(skb)->nr_frags)
  233. break;
  234. fragment = &skb_shinfo(skb)->frags[i];
  235. len = fragment->size;
  236. page = fragment->page;
  237. page_offset = fragment->page_offset;
  238. i++;
  239. /* Map for DMA */
  240. unmap_single = false;
  241. dma_addr = pci_map_page(pci_dev, page, page_offset, len,
  242. PCI_DMA_TODEVICE);
  243. }
  244. /* Transfer ownership of the skb to the final buffer */
  245. buffer->skb = skb;
  246. buffer->continuation = false;
  247. /* Pass off to hardware */
  248. falcon_push_buffers(tx_queue);
  249. return NETDEV_TX_OK;
  250. pci_err:
  251. EFX_ERR_RL(efx, " TX queue %d could not map skb with %d bytes %d "
  252. "fragments for DMA\n", tx_queue->queue, skb->len,
  253. skb_shinfo(skb)->nr_frags + 1);
  254. /* Mark the packet as transmitted, and free the SKB ourselves */
  255. dev_kfree_skb_any(skb);
  256. goto unwind;
  257. stop:
  258. rc = NETDEV_TX_BUSY;
  259. if (tx_queue->stopped == 1)
  260. efx_stop_queue(efx);
  261. unwind:
  262. /* Work backwards until we hit the original insert pointer value */
  263. while (tx_queue->insert_count != tx_queue->write_count) {
  264. --tx_queue->insert_count;
  265. insert_ptr = tx_queue->insert_count & EFX_TXQ_MASK;
  266. buffer = &tx_queue->buffer[insert_ptr];
  267. efx_dequeue_buffer(tx_queue, buffer);
  268. buffer->len = 0;
  269. }
  270. /* Free the fragment we were mid-way through pushing */
  271. if (unmap_len) {
  272. if (unmap_single)
  273. pci_unmap_single(pci_dev, unmap_addr, unmap_len,
  274. PCI_DMA_TODEVICE);
  275. else
  276. pci_unmap_page(pci_dev, unmap_addr, unmap_len,
  277. PCI_DMA_TODEVICE);
  278. }
  279. return rc;
  280. }
  281. /* Remove packets from the TX queue
  282. *
  283. * This removes packets from the TX queue, up to and including the
  284. * specified index.
  285. */
  286. static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
  287. unsigned int index)
  288. {
  289. struct efx_nic *efx = tx_queue->efx;
  290. unsigned int stop_index, read_ptr;
  291. stop_index = (index + 1) & EFX_TXQ_MASK;
  292. read_ptr = tx_queue->read_count & EFX_TXQ_MASK;
  293. while (read_ptr != stop_index) {
  294. struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
  295. if (unlikely(buffer->len == 0)) {
  296. EFX_ERR(tx_queue->efx, "TX queue %d spurious TX "
  297. "completion id %x\n", tx_queue->queue,
  298. read_ptr);
  299. efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
  300. return;
  301. }
  302. efx_dequeue_buffer(tx_queue, buffer);
  303. buffer->continuation = true;
  304. buffer->len = 0;
  305. ++tx_queue->read_count;
  306. read_ptr = tx_queue->read_count & EFX_TXQ_MASK;
  307. }
  308. }
  309. /* Initiate a packet transmission on the specified TX queue.
  310. * Note that returning anything other than NETDEV_TX_OK will cause the
  311. * OS to free the skb.
  312. *
  313. * This function is split out from efx_hard_start_xmit to allow the
  314. * loopback test to direct packets via specific TX queues. It is
  315. * therefore a non-static inline, so as not to penalise performance
  316. * for non-loopback transmissions.
  317. *
  318. * Context: netif_tx_lock held
  319. */
  320. inline netdev_tx_t efx_xmit(struct efx_nic *efx,
  321. struct efx_tx_queue *tx_queue, struct sk_buff *skb)
  322. {
  323. /* Map fragments for DMA and add to TX queue */
  324. return efx_enqueue_skb(tx_queue, skb);
  325. }
  326. /* Initiate a packet transmission. We use one channel per CPU
  327. * (sharing when we have more CPUs than channels). On Falcon, the TX
  328. * completion events will be directed back to the CPU that transmitted
  329. * the packet, which should be cache-efficient.
  330. *
  331. * Context: non-blocking.
  332. * Note that returning anything other than NETDEV_TX_OK will cause the
  333. * OS to free the skb.
  334. */
  335. netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
  336. struct net_device *net_dev)
  337. {
  338. struct efx_nic *efx = netdev_priv(net_dev);
  339. struct efx_tx_queue *tx_queue;
  340. if (unlikely(efx->port_inhibited))
  341. return NETDEV_TX_BUSY;
  342. if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
  343. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_OFFLOAD_CSUM];
  344. else
  345. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_NO_CSUM];
  346. return efx_xmit(efx, tx_queue, skb);
  347. }
  348. void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
  349. {
  350. unsigned fill_level;
  351. struct efx_nic *efx = tx_queue->efx;
  352. EFX_BUG_ON_PARANOID(index > EFX_TXQ_MASK);
  353. efx_dequeue_buffers(tx_queue, index);
  354. /* See if we need to restart the netif queue. This barrier
  355. * separates the update of read_count from the test of
  356. * stopped. */
  357. smp_mb();
  358. if (unlikely(tx_queue->stopped) && likely(efx->port_enabled)) {
  359. fill_level = tx_queue->insert_count - tx_queue->read_count;
  360. if (fill_level < EFX_TXQ_THRESHOLD) {
  361. EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
  362. /* Do this under netif_tx_lock(), to avoid racing
  363. * with efx_xmit(). */
  364. netif_tx_lock(efx->net_dev);
  365. if (tx_queue->stopped) {
  366. tx_queue->stopped = 0;
  367. efx_wake_queue(efx);
  368. }
  369. netif_tx_unlock(efx->net_dev);
  370. }
  371. }
  372. }
  373. int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
  374. {
  375. struct efx_nic *efx = tx_queue->efx;
  376. unsigned int txq_size;
  377. int i, rc;
  378. EFX_LOG(efx, "creating TX queue %d\n", tx_queue->queue);
  379. /* Allocate software ring */
  380. txq_size = EFX_TXQ_SIZE * sizeof(*tx_queue->buffer);
  381. tx_queue->buffer = kzalloc(txq_size, GFP_KERNEL);
  382. if (!tx_queue->buffer)
  383. return -ENOMEM;
  384. for (i = 0; i <= EFX_TXQ_MASK; ++i)
  385. tx_queue->buffer[i].continuation = true;
  386. /* Allocate hardware ring */
  387. rc = falcon_probe_tx(tx_queue);
  388. if (rc)
  389. goto fail;
  390. return 0;
  391. fail:
  392. kfree(tx_queue->buffer);
  393. tx_queue->buffer = NULL;
  394. return rc;
  395. }
  396. void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
  397. {
  398. EFX_LOG(tx_queue->efx, "initialising TX queue %d\n", tx_queue->queue);
  399. tx_queue->insert_count = 0;
  400. tx_queue->write_count = 0;
  401. tx_queue->read_count = 0;
  402. tx_queue->old_read_count = 0;
  403. BUG_ON(tx_queue->stopped);
  404. /* Set up TX descriptor ring */
  405. falcon_init_tx(tx_queue);
  406. }
  407. void efx_release_tx_buffers(struct efx_tx_queue *tx_queue)
  408. {
  409. struct efx_tx_buffer *buffer;
  410. if (!tx_queue->buffer)
  411. return;
  412. /* Free any buffers left in the ring */
  413. while (tx_queue->read_count != tx_queue->write_count) {
  414. buffer = &tx_queue->buffer[tx_queue->read_count & EFX_TXQ_MASK];
  415. efx_dequeue_buffer(tx_queue, buffer);
  416. buffer->continuation = true;
  417. buffer->len = 0;
  418. ++tx_queue->read_count;
  419. }
  420. }
  421. void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
  422. {
  423. EFX_LOG(tx_queue->efx, "shutting down TX queue %d\n", tx_queue->queue);
  424. /* Flush TX queue, remove descriptor ring */
  425. falcon_fini_tx(tx_queue);
  426. efx_release_tx_buffers(tx_queue);
  427. /* Free up TSO header cache */
  428. efx_fini_tso(tx_queue);
  429. /* Release queue's stop on port, if any */
  430. if (tx_queue->stopped) {
  431. tx_queue->stopped = 0;
  432. efx_wake_queue(tx_queue->efx);
  433. }
  434. }
  435. void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
  436. {
  437. EFX_LOG(tx_queue->efx, "destroying TX queue %d\n", tx_queue->queue);
  438. falcon_remove_tx(tx_queue);
  439. kfree(tx_queue->buffer);
  440. tx_queue->buffer = NULL;
  441. }
  442. /* Efx TCP segmentation acceleration.
  443. *
  444. * Why? Because by doing it here in the driver we can go significantly
  445. * faster than the GSO.
  446. *
  447. * Requires TX checksum offload support.
  448. */
  449. /* Number of bytes inserted at the start of a TSO header buffer,
  450. * similar to NET_IP_ALIGN.
  451. */
  452. #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  453. #define TSOH_OFFSET 0
  454. #else
  455. #define TSOH_OFFSET NET_IP_ALIGN
  456. #endif
  457. #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET)
  458. /* Total size of struct efx_tso_header, buffer and padding */
  459. #define TSOH_SIZE(hdr_len) \
  460. (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len)
  461. /* Size of blocks on free list. Larger blocks must be allocated from
  462. * the heap.
  463. */
  464. #define TSOH_STD_SIZE 128
  465. #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
  466. #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data)
  467. #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data)
  468. #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data)
  469. /**
  470. * struct tso_state - TSO state for an SKB
  471. * @out_len: Remaining length in current segment
  472. * @seqnum: Current sequence number
  473. * @ipv4_id: Current IPv4 ID, host endian
  474. * @packet_space: Remaining space in current packet
  475. * @dma_addr: DMA address of current position
  476. * @in_len: Remaining length in current SKB fragment
  477. * @unmap_len: Length of SKB fragment
  478. * @unmap_addr: DMA address of SKB fragment
  479. * @unmap_single: DMA single vs page mapping flag
  480. * @header_len: Number of bytes of header
  481. * @full_packet_size: Number of bytes to put in each outgoing segment
  482. *
  483. * The state used during segmentation. It is put into this data structure
  484. * just to make it easy to pass into inline functions.
  485. */
  486. struct tso_state {
  487. /* Output position */
  488. unsigned out_len;
  489. unsigned seqnum;
  490. unsigned ipv4_id;
  491. unsigned packet_space;
  492. /* Input position */
  493. dma_addr_t dma_addr;
  494. unsigned in_len;
  495. unsigned unmap_len;
  496. dma_addr_t unmap_addr;
  497. bool unmap_single;
  498. unsigned header_len;
  499. int full_packet_size;
  500. };
  501. /*
  502. * Verify that our various assumptions about sk_buffs and the conditions
  503. * under which TSO will be attempted hold true.
  504. */
  505. static void efx_tso_check_safe(struct sk_buff *skb)
  506. {
  507. __be16 protocol = skb->protocol;
  508. EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
  509. protocol);
  510. if (protocol == htons(ETH_P_8021Q)) {
  511. /* Find the encapsulated protocol; reset network header
  512. * and transport header based on that. */
  513. struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
  514. protocol = veh->h_vlan_encapsulated_proto;
  515. skb_set_network_header(skb, sizeof(*veh));
  516. if (protocol == htons(ETH_P_IP))
  517. skb_set_transport_header(skb, sizeof(*veh) +
  518. 4 * ip_hdr(skb)->ihl);
  519. }
  520. EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IP));
  521. EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
  522. EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
  523. + (tcp_hdr(skb)->doff << 2u)) >
  524. skb_headlen(skb));
  525. }
  526. /*
  527. * Allocate a page worth of efx_tso_header structures, and string them
  528. * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM.
  529. */
  530. static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue)
  531. {
  532. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  533. struct efx_tso_header *tsoh;
  534. dma_addr_t dma_addr;
  535. u8 *base_kva, *kva;
  536. base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr);
  537. if (base_kva == NULL) {
  538. EFX_ERR(tx_queue->efx, "Unable to allocate page for TSO"
  539. " headers\n");
  540. return -ENOMEM;
  541. }
  542. /* pci_alloc_consistent() allocates pages. */
  543. EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u));
  544. for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) {
  545. tsoh = (struct efx_tso_header *)kva;
  546. tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva);
  547. tsoh->next = tx_queue->tso_headers_free;
  548. tx_queue->tso_headers_free = tsoh;
  549. }
  550. return 0;
  551. }
  552. /* Free up a TSO header, and all others in the same page. */
  553. static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue,
  554. struct efx_tso_header *tsoh,
  555. struct pci_dev *pci_dev)
  556. {
  557. struct efx_tso_header **p;
  558. unsigned long base_kva;
  559. dma_addr_t base_dma;
  560. base_kva = (unsigned long)tsoh & PAGE_MASK;
  561. base_dma = tsoh->dma_addr & PAGE_MASK;
  562. p = &tx_queue->tso_headers_free;
  563. while (*p != NULL) {
  564. if (((unsigned long)*p & PAGE_MASK) == base_kva)
  565. *p = (*p)->next;
  566. else
  567. p = &(*p)->next;
  568. }
  569. pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma);
  570. }
  571. static struct efx_tso_header *
  572. efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len)
  573. {
  574. struct efx_tso_header *tsoh;
  575. tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA);
  576. if (unlikely(!tsoh))
  577. return NULL;
  578. tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev,
  579. TSOH_BUFFER(tsoh), header_len,
  580. PCI_DMA_TODEVICE);
  581. if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev,
  582. tsoh->dma_addr))) {
  583. kfree(tsoh);
  584. return NULL;
  585. }
  586. tsoh->unmap_len = header_len;
  587. return tsoh;
  588. }
  589. static void
  590. efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh)
  591. {
  592. pci_unmap_single(tx_queue->efx->pci_dev,
  593. tsoh->dma_addr, tsoh->unmap_len,
  594. PCI_DMA_TODEVICE);
  595. kfree(tsoh);
  596. }
  597. /**
  598. * efx_tx_queue_insert - push descriptors onto the TX queue
  599. * @tx_queue: Efx TX queue
  600. * @dma_addr: DMA address of fragment
  601. * @len: Length of fragment
  602. * @final_buffer: The final buffer inserted into the queue
  603. *
  604. * Push descriptors onto the TX queue. Return 0 on success or 1 if
  605. * @tx_queue full.
  606. */
  607. static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
  608. dma_addr_t dma_addr, unsigned len,
  609. struct efx_tx_buffer **final_buffer)
  610. {
  611. struct efx_tx_buffer *buffer;
  612. struct efx_nic *efx = tx_queue->efx;
  613. unsigned dma_len, fill_level, insert_ptr;
  614. int q_space;
  615. EFX_BUG_ON_PARANOID(len <= 0);
  616. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  617. /* -1 as there is no way to represent all descriptors used */
  618. q_space = EFX_TXQ_MASK - 1 - fill_level;
  619. while (1) {
  620. if (unlikely(q_space-- <= 0)) {
  621. /* It might be that completions have happened
  622. * since the xmit path last checked. Update
  623. * the xmit path's copy of read_count.
  624. */
  625. ++tx_queue->stopped;
  626. /* This memory barrier protects the change of
  627. * stopped from the access of read_count. */
  628. smp_mb();
  629. tx_queue->old_read_count =
  630. *(volatile unsigned *)&tx_queue->read_count;
  631. fill_level = (tx_queue->insert_count
  632. - tx_queue->old_read_count);
  633. q_space = EFX_TXQ_MASK - 1 - fill_level;
  634. if (unlikely(q_space-- <= 0)) {
  635. *final_buffer = NULL;
  636. return 1;
  637. }
  638. smp_mb();
  639. --tx_queue->stopped;
  640. }
  641. insert_ptr = tx_queue->insert_count & EFX_TXQ_MASK;
  642. buffer = &tx_queue->buffer[insert_ptr];
  643. ++tx_queue->insert_count;
  644. EFX_BUG_ON_PARANOID(tx_queue->insert_count -
  645. tx_queue->read_count >
  646. EFX_TXQ_MASK);
  647. efx_tsoh_free(tx_queue, buffer);
  648. EFX_BUG_ON_PARANOID(buffer->len);
  649. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  650. EFX_BUG_ON_PARANOID(buffer->skb);
  651. EFX_BUG_ON_PARANOID(!buffer->continuation);
  652. EFX_BUG_ON_PARANOID(buffer->tsoh);
  653. buffer->dma_addr = dma_addr;
  654. dma_len = efx_max_tx_len(efx, dma_addr);
  655. /* If there is enough space to send then do so */
  656. if (dma_len >= len)
  657. break;
  658. buffer->len = dma_len; /* Don't set the other members */
  659. dma_addr += dma_len;
  660. len -= dma_len;
  661. }
  662. EFX_BUG_ON_PARANOID(!len);
  663. buffer->len = len;
  664. *final_buffer = buffer;
  665. return 0;
  666. }
  667. /*
  668. * Put a TSO header into the TX queue.
  669. *
  670. * This is special-cased because we know that it is small enough to fit in
  671. * a single fragment, and we know it doesn't cross a page boundary. It
  672. * also allows us to not worry about end-of-packet etc.
  673. */
  674. static void efx_tso_put_header(struct efx_tx_queue *tx_queue,
  675. struct efx_tso_header *tsoh, unsigned len)
  676. {
  677. struct efx_tx_buffer *buffer;
  678. buffer = &tx_queue->buffer[tx_queue->insert_count & EFX_TXQ_MASK];
  679. efx_tsoh_free(tx_queue, buffer);
  680. EFX_BUG_ON_PARANOID(buffer->len);
  681. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  682. EFX_BUG_ON_PARANOID(buffer->skb);
  683. EFX_BUG_ON_PARANOID(!buffer->continuation);
  684. EFX_BUG_ON_PARANOID(buffer->tsoh);
  685. buffer->len = len;
  686. buffer->dma_addr = tsoh->dma_addr;
  687. buffer->tsoh = tsoh;
  688. ++tx_queue->insert_count;
  689. }
  690. /* Remove descriptors put into a tx_queue. */
  691. static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
  692. {
  693. struct efx_tx_buffer *buffer;
  694. dma_addr_t unmap_addr;
  695. /* Work backwards until we hit the original insert pointer value */
  696. while (tx_queue->insert_count != tx_queue->write_count) {
  697. --tx_queue->insert_count;
  698. buffer = &tx_queue->buffer[tx_queue->insert_count &
  699. EFX_TXQ_MASK];
  700. efx_tsoh_free(tx_queue, buffer);
  701. EFX_BUG_ON_PARANOID(buffer->skb);
  702. buffer->len = 0;
  703. buffer->continuation = true;
  704. if (buffer->unmap_len) {
  705. unmap_addr = (buffer->dma_addr + buffer->len -
  706. buffer->unmap_len);
  707. if (buffer->unmap_single)
  708. pci_unmap_single(tx_queue->efx->pci_dev,
  709. unmap_addr, buffer->unmap_len,
  710. PCI_DMA_TODEVICE);
  711. else
  712. pci_unmap_page(tx_queue->efx->pci_dev,
  713. unmap_addr, buffer->unmap_len,
  714. PCI_DMA_TODEVICE);
  715. buffer->unmap_len = 0;
  716. }
  717. }
  718. }
  719. /* Parse the SKB header and initialise state. */
  720. static void tso_start(struct tso_state *st, const struct sk_buff *skb)
  721. {
  722. /* All ethernet/IP/TCP headers combined size is TCP header size
  723. * plus offset of TCP header relative to start of packet.
  724. */
  725. st->header_len = ((tcp_hdr(skb)->doff << 2u)
  726. + PTR_DIFF(tcp_hdr(skb), skb->data));
  727. st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size;
  728. st->ipv4_id = ntohs(ip_hdr(skb)->id);
  729. st->seqnum = ntohl(tcp_hdr(skb)->seq);
  730. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
  731. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
  732. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
  733. st->packet_space = st->full_packet_size;
  734. st->out_len = skb->len - st->header_len;
  735. st->unmap_len = 0;
  736. st->unmap_single = false;
  737. }
  738. static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
  739. skb_frag_t *frag)
  740. {
  741. st->unmap_addr = pci_map_page(efx->pci_dev, frag->page,
  742. frag->page_offset, frag->size,
  743. PCI_DMA_TODEVICE);
  744. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  745. st->unmap_single = false;
  746. st->unmap_len = frag->size;
  747. st->in_len = frag->size;
  748. st->dma_addr = st->unmap_addr;
  749. return 0;
  750. }
  751. return -ENOMEM;
  752. }
  753. static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx,
  754. const struct sk_buff *skb)
  755. {
  756. int hl = st->header_len;
  757. int len = skb_headlen(skb) - hl;
  758. st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl,
  759. len, PCI_DMA_TODEVICE);
  760. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  761. st->unmap_single = true;
  762. st->unmap_len = len;
  763. st->in_len = len;
  764. st->dma_addr = st->unmap_addr;
  765. return 0;
  766. }
  767. return -ENOMEM;
  768. }
  769. /**
  770. * tso_fill_packet_with_fragment - form descriptors for the current fragment
  771. * @tx_queue: Efx TX queue
  772. * @skb: Socket buffer
  773. * @st: TSO state
  774. *
  775. * Form descriptors for the current fragment, until we reach the end
  776. * of fragment or end-of-packet. Return 0 on success, 1 if not enough
  777. * space in @tx_queue.
  778. */
  779. static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
  780. const struct sk_buff *skb,
  781. struct tso_state *st)
  782. {
  783. struct efx_tx_buffer *buffer;
  784. int n, end_of_packet, rc;
  785. if (st->in_len == 0)
  786. return 0;
  787. if (st->packet_space == 0)
  788. return 0;
  789. EFX_BUG_ON_PARANOID(st->in_len <= 0);
  790. EFX_BUG_ON_PARANOID(st->packet_space <= 0);
  791. n = min(st->in_len, st->packet_space);
  792. st->packet_space -= n;
  793. st->out_len -= n;
  794. st->in_len -= n;
  795. rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
  796. if (likely(rc == 0)) {
  797. if (st->out_len == 0)
  798. /* Transfer ownership of the skb */
  799. buffer->skb = skb;
  800. end_of_packet = st->out_len == 0 || st->packet_space == 0;
  801. buffer->continuation = !end_of_packet;
  802. if (st->in_len == 0) {
  803. /* Transfer ownership of the pci mapping */
  804. buffer->unmap_len = st->unmap_len;
  805. buffer->unmap_single = st->unmap_single;
  806. st->unmap_len = 0;
  807. }
  808. }
  809. st->dma_addr += n;
  810. return rc;
  811. }
  812. /**
  813. * tso_start_new_packet - generate a new header and prepare for the new packet
  814. * @tx_queue: Efx TX queue
  815. * @skb: Socket buffer
  816. * @st: TSO state
  817. *
  818. * Generate a new header and prepare for the new packet. Return 0 on
  819. * success, or -1 if failed to alloc header.
  820. */
  821. static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
  822. const struct sk_buff *skb,
  823. struct tso_state *st)
  824. {
  825. struct efx_tso_header *tsoh;
  826. struct iphdr *tsoh_iph;
  827. struct tcphdr *tsoh_th;
  828. unsigned ip_length;
  829. u8 *header;
  830. /* Allocate a DMA-mapped header buffer. */
  831. if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) {
  832. if (tx_queue->tso_headers_free == NULL) {
  833. if (efx_tsoh_block_alloc(tx_queue))
  834. return -1;
  835. }
  836. EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free);
  837. tsoh = tx_queue->tso_headers_free;
  838. tx_queue->tso_headers_free = tsoh->next;
  839. tsoh->unmap_len = 0;
  840. } else {
  841. tx_queue->tso_long_headers++;
  842. tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len);
  843. if (unlikely(!tsoh))
  844. return -1;
  845. }
  846. header = TSOH_BUFFER(tsoh);
  847. tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb));
  848. tsoh_iph = (struct iphdr *)(header + SKB_IPV4_OFF(skb));
  849. /* Copy and update the headers. */
  850. memcpy(header, skb->data, st->header_len);
  851. tsoh_th->seq = htonl(st->seqnum);
  852. st->seqnum += skb_shinfo(skb)->gso_size;
  853. if (st->out_len > skb_shinfo(skb)->gso_size) {
  854. /* This packet will not finish the TSO burst. */
  855. ip_length = st->full_packet_size - ETH_HDR_LEN(skb);
  856. tsoh_th->fin = 0;
  857. tsoh_th->psh = 0;
  858. } else {
  859. /* This packet will be the last in the TSO burst. */
  860. ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len;
  861. tsoh_th->fin = tcp_hdr(skb)->fin;
  862. tsoh_th->psh = tcp_hdr(skb)->psh;
  863. }
  864. tsoh_iph->tot_len = htons(ip_length);
  865. /* Linux leaves suitable gaps in the IP ID space for us to fill. */
  866. tsoh_iph->id = htons(st->ipv4_id);
  867. st->ipv4_id++;
  868. st->packet_space = skb_shinfo(skb)->gso_size;
  869. ++tx_queue->tso_packets;
  870. /* Form a descriptor for this header. */
  871. efx_tso_put_header(tx_queue, tsoh, st->header_len);
  872. return 0;
  873. }
  874. /**
  875. * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
  876. * @tx_queue: Efx TX queue
  877. * @skb: Socket buffer
  878. *
  879. * Context: You must hold netif_tx_lock() to call this function.
  880. *
  881. * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
  882. * @skb was not enqueued. In all cases @skb is consumed. Return
  883. * %NETDEV_TX_OK or %NETDEV_TX_BUSY.
  884. */
  885. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  886. struct sk_buff *skb)
  887. {
  888. struct efx_nic *efx = tx_queue->efx;
  889. int frag_i, rc, rc2 = NETDEV_TX_OK;
  890. struct tso_state state;
  891. /* Verify TSO is safe - these checks should never fail. */
  892. efx_tso_check_safe(skb);
  893. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  894. tso_start(&state, skb);
  895. /* Assume that skb header area contains exactly the headers, and
  896. * all payload is in the frag list.
  897. */
  898. if (skb_headlen(skb) == state.header_len) {
  899. /* Grab the first payload fragment. */
  900. EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
  901. frag_i = 0;
  902. rc = tso_get_fragment(&state, efx,
  903. skb_shinfo(skb)->frags + frag_i);
  904. if (rc)
  905. goto mem_err;
  906. } else {
  907. rc = tso_get_head_fragment(&state, efx, skb);
  908. if (rc)
  909. goto mem_err;
  910. frag_i = -1;
  911. }
  912. if (tso_start_new_packet(tx_queue, skb, &state) < 0)
  913. goto mem_err;
  914. while (1) {
  915. rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
  916. if (unlikely(rc))
  917. goto stop;
  918. /* Move onto the next fragment? */
  919. if (state.in_len == 0) {
  920. if (++frag_i >= skb_shinfo(skb)->nr_frags)
  921. /* End of payload reached. */
  922. break;
  923. rc = tso_get_fragment(&state, efx,
  924. skb_shinfo(skb)->frags + frag_i);
  925. if (rc)
  926. goto mem_err;
  927. }
  928. /* Start at new packet? */
  929. if (state.packet_space == 0 &&
  930. tso_start_new_packet(tx_queue, skb, &state) < 0)
  931. goto mem_err;
  932. }
  933. /* Pass off to hardware */
  934. falcon_push_buffers(tx_queue);
  935. tx_queue->tso_bursts++;
  936. return NETDEV_TX_OK;
  937. mem_err:
  938. EFX_ERR(efx, "Out of memory for TSO headers, or PCI mapping error\n");
  939. dev_kfree_skb_any(skb);
  940. goto unwind;
  941. stop:
  942. rc2 = NETDEV_TX_BUSY;
  943. /* Stop the queue if it wasn't stopped before. */
  944. if (tx_queue->stopped == 1)
  945. efx_stop_queue(efx);
  946. unwind:
  947. /* Free the DMA mapping we were in the process of writing out */
  948. if (state.unmap_len) {
  949. if (state.unmap_single)
  950. pci_unmap_single(efx->pci_dev, state.unmap_addr,
  951. state.unmap_len, PCI_DMA_TODEVICE);
  952. else
  953. pci_unmap_page(efx->pci_dev, state.unmap_addr,
  954. state.unmap_len, PCI_DMA_TODEVICE);
  955. }
  956. efx_enqueue_unwind(tx_queue);
  957. return rc2;
  958. }
  959. /*
  960. * Free up all TSO datastructures associated with tx_queue. This
  961. * routine should be called only once the tx_queue is both empty and
  962. * will no longer be used.
  963. */
  964. static void efx_fini_tso(struct efx_tx_queue *tx_queue)
  965. {
  966. unsigned i;
  967. if (tx_queue->buffer) {
  968. for (i = 0; i <= EFX_TXQ_MASK; ++i)
  969. efx_tsoh_free(tx_queue, &tx_queue->buffer[i]);
  970. }
  971. while (tx_queue->tso_headers_free != NULL)
  972. efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free,
  973. tx_queue->efx->pci_dev);
  974. }