gpiolib.c 4.0 KB

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  1. /* linux/arch/arm/plat-s3c24xx/gpiolib.c
  2. *
  3. * Copyright (c) 2008 Simtec Electronics
  4. * http://armlinux.simtec.co.uk/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * S3C24XX GPIOlib support
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/module.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/sysdev.h>
  18. #include <linux/ioport.h>
  19. #include <linux/io.h>
  20. #include <linux/gpio.h>
  21. #include <plat/gpio-core.h>
  22. #include <plat/gpio-cfg.h>
  23. #include <plat/gpio-cfg-helpers.h>
  24. #include <mach/hardware.h>
  25. #include <asm/irq.h>
  26. #include <plat/pm.h>
  27. #include <mach/regs-gpio.h>
  28. static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
  29. {
  30. return -EINVAL;
  31. }
  32. static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
  33. unsigned offset, int value)
  34. {
  35. struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
  36. void __iomem *base = ourchip->base;
  37. unsigned long flags;
  38. unsigned long dat;
  39. unsigned long con;
  40. local_irq_save(flags);
  41. con = __raw_readl(base + 0x00);
  42. dat = __raw_readl(base + 0x04);
  43. dat &= ~(1 << offset);
  44. if (value)
  45. dat |= 1 << offset;
  46. __raw_writel(dat, base + 0x04);
  47. con &= ~(1 << offset);
  48. __raw_writel(con, base + 0x00);
  49. __raw_writel(dat, base + 0x04);
  50. local_irq_restore(flags);
  51. return 0;
  52. }
  53. static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset)
  54. {
  55. if (offset < 4)
  56. return IRQ_EINT0 + offset;
  57. if (offset < 8)
  58. return IRQ_EINT4 + offset - 4;
  59. return -EINVAL;
  60. }
  61. static int s3c24xx_gpiolib_bankg_toirq(struct gpio_chip *chip, unsigned offset)
  62. {
  63. return IRQ_EINT8 + offset;
  64. }
  65. static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
  66. .set_config = s3c_gpio_setcfg_s3c24xx_a,
  67. };
  68. struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
  69. .set_config = s3c_gpio_setcfg_s3c24xx,
  70. };
  71. struct s3c_gpio_chip s3c24xx_gpios[] = {
  72. [0] = {
  73. .base = S3C2410_GPACON,
  74. .pm = __gpio_pm(&s3c_gpio_pm_1bit),
  75. .config = &s3c24xx_gpiocfg_banka,
  76. .chip = {
  77. .base = S3C2410_GPA(0),
  78. .owner = THIS_MODULE,
  79. .label = "GPIOA",
  80. .ngpio = 24,
  81. .direction_input = s3c24xx_gpiolib_banka_input,
  82. .direction_output = s3c24xx_gpiolib_banka_output,
  83. },
  84. },
  85. [1] = {
  86. .base = S3C2410_GPBCON,
  87. .pm = __gpio_pm(&s3c_gpio_pm_2bit),
  88. .chip = {
  89. .base = S3C2410_GPB(0),
  90. .owner = THIS_MODULE,
  91. .label = "GPIOB",
  92. .ngpio = 16,
  93. },
  94. },
  95. [2] = {
  96. .base = S3C2410_GPCCON,
  97. .pm = __gpio_pm(&s3c_gpio_pm_2bit),
  98. .chip = {
  99. .base = S3C2410_GPC(0),
  100. .owner = THIS_MODULE,
  101. .label = "GPIOC",
  102. .ngpio = 16,
  103. },
  104. },
  105. [3] = {
  106. .base = S3C2410_GPDCON,
  107. .pm = __gpio_pm(&s3c_gpio_pm_2bit),
  108. .chip = {
  109. .base = S3C2410_GPD(0),
  110. .owner = THIS_MODULE,
  111. .label = "GPIOD",
  112. .ngpio = 16,
  113. },
  114. },
  115. [4] = {
  116. .base = S3C2410_GPECON,
  117. .pm = __gpio_pm(&s3c_gpio_pm_2bit),
  118. .chip = {
  119. .base = S3C2410_GPE(0),
  120. .label = "GPIOE",
  121. .owner = THIS_MODULE,
  122. .ngpio = 16,
  123. },
  124. },
  125. [5] = {
  126. .base = S3C2410_GPFCON,
  127. .pm = __gpio_pm(&s3c_gpio_pm_2bit),
  128. .chip = {
  129. .base = S3C2410_GPF(0),
  130. .owner = THIS_MODULE,
  131. .label = "GPIOF",
  132. .ngpio = 8,
  133. .to_irq = s3c24xx_gpiolib_bankf_toirq,
  134. },
  135. },
  136. [6] = {
  137. .base = S3C2410_GPGCON,
  138. .pm = __gpio_pm(&s3c_gpio_pm_2bit),
  139. .chip = {
  140. .base = S3C2410_GPG(0),
  141. .owner = THIS_MODULE,
  142. .label = "GPIOG",
  143. .ngpio = 16,
  144. .to_irq = s3c24xx_gpiolib_bankg_toirq,
  145. },
  146. }, {
  147. .base = S3C2410_GPHCON,
  148. .pm = __gpio_pm(&s3c_gpio_pm_2bit),
  149. .chip = {
  150. .base = S3C2410_GPH(0),
  151. .owner = THIS_MODULE,
  152. .label = "GPIOH",
  153. .ngpio = 11,
  154. },
  155. },
  156. };
  157. static __init int s3c24xx_gpiolib_init(void)
  158. {
  159. struct s3c_gpio_chip *chip = s3c24xx_gpios;
  160. int gpn;
  161. for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) {
  162. if (!chip->config)
  163. chip->config = &s3c24xx_gpiocfg_default;
  164. s3c_gpiolib_add(chip);
  165. }
  166. return 0;
  167. }
  168. core_initcall(s3c24xx_gpiolib_init);