ioctl.h 6.2 KB

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  1. /*
  2. * Marvell Wireless LAN device driver: ioctl data structures & APIs
  3. *
  4. * Copyright (C) 2011, Marvell International Ltd.
  5. *
  6. * This software file (the "File") is distributed by Marvell International
  7. * Ltd. under the terms of the GNU General Public License Version 2, June 1991
  8. * (the "License"). You may use, redistribute and/or modify this File in
  9. * accordance with the terms and conditions of the License, a copy of which
  10. * is available by writing to the Free Software Foundation, Inc.,
  11. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  12. * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  13. *
  14. * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  15. * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  16. * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
  17. * this warranty disclaimer.
  18. */
  19. #ifndef _MWIFIEX_IOCTL_H_
  20. #define _MWIFIEX_IOCTL_H_
  21. #include <net/mac80211.h>
  22. enum {
  23. MWIFIEX_SCAN_TYPE_UNCHANGED = 0,
  24. MWIFIEX_SCAN_TYPE_ACTIVE,
  25. MWIFIEX_SCAN_TYPE_PASSIVE
  26. };
  27. struct mwifiex_user_scan {
  28. u32 scan_cfg_len;
  29. u8 scan_cfg_buf[1];
  30. };
  31. #define MWIFIEX_PROMISC_MODE 1
  32. #define MWIFIEX_MULTICAST_MODE 2
  33. #define MWIFIEX_ALL_MULTI_MODE 4
  34. #define MWIFIEX_MAX_MULTICAST_LIST_SIZE 32
  35. struct mwifiex_multicast_list {
  36. u32 mode;
  37. u32 num_multicast_addr;
  38. u8 mac_list[MWIFIEX_MAX_MULTICAST_LIST_SIZE][ETH_ALEN];
  39. };
  40. struct mwifiex_chan_freq {
  41. u32 channel;
  42. u32 freq;
  43. };
  44. struct mwifiex_ssid_bssid {
  45. struct cfg80211_ssid ssid;
  46. u8 bssid[ETH_ALEN];
  47. };
  48. enum {
  49. BAND_B = 1,
  50. BAND_G = 2,
  51. BAND_A = 4,
  52. BAND_GN = 8,
  53. BAND_AN = 16,
  54. };
  55. #define BAND_CONFIG_MANUAL 0x00
  56. struct mwifiex_uap_bss_param {
  57. u8 channel;
  58. u8 band_cfg;
  59. u16 rts_threshold;
  60. u16 frag_threshold;
  61. u8 retry_limit;
  62. };
  63. enum {
  64. ADHOC_IDLE,
  65. ADHOC_STARTED,
  66. ADHOC_JOINED,
  67. ADHOC_COALESCED
  68. };
  69. struct mwifiex_ds_get_stats {
  70. u32 mcast_tx_frame;
  71. u32 failed;
  72. u32 retry;
  73. u32 multi_retry;
  74. u32 frame_dup;
  75. u32 rts_success;
  76. u32 rts_failure;
  77. u32 ack_failure;
  78. u32 rx_frag;
  79. u32 mcast_rx_frame;
  80. u32 fcs_error;
  81. u32 tx_frame;
  82. u32 wep_icv_error[4];
  83. };
  84. #define MWIFIEX_MAX_VER_STR_LEN 128
  85. struct mwifiex_ver_ext {
  86. u32 version_str_sel;
  87. char version_str[MWIFIEX_MAX_VER_STR_LEN];
  88. };
  89. struct mwifiex_bss_info {
  90. u32 bss_mode;
  91. struct cfg80211_ssid ssid;
  92. u32 bss_chan;
  93. u8 country_code[3];
  94. u32 media_connected;
  95. u32 max_power_level;
  96. u32 min_power_level;
  97. u32 adhoc_state;
  98. signed int bcn_nf_last;
  99. u32 wep_status;
  100. u32 is_hs_configured;
  101. u32 is_deep_sleep;
  102. u8 bssid[ETH_ALEN];
  103. };
  104. #define MAX_NUM_TID 8
  105. #define MAX_RX_WINSIZE 64
  106. struct mwifiex_ds_rx_reorder_tbl {
  107. u16 tid;
  108. u8 ta[ETH_ALEN];
  109. u32 start_win;
  110. u32 win_size;
  111. u32 buffer[MAX_RX_WINSIZE];
  112. };
  113. struct mwifiex_ds_tx_ba_stream_tbl {
  114. u16 tid;
  115. u8 ra[ETH_ALEN];
  116. };
  117. #define DBG_CMD_NUM 5
  118. struct mwifiex_debug_info {
  119. u32 int_counter;
  120. u32 packets_out[MAX_NUM_TID];
  121. u32 max_tx_buf_size;
  122. u32 tx_buf_size;
  123. u32 curr_tx_buf_size;
  124. u32 tx_tbl_num;
  125. struct mwifiex_ds_tx_ba_stream_tbl
  126. tx_tbl[MWIFIEX_MAX_TX_BASTREAM_SUPPORTED];
  127. u32 rx_tbl_num;
  128. struct mwifiex_ds_rx_reorder_tbl rx_tbl
  129. [MWIFIEX_MAX_RX_BASTREAM_SUPPORTED];
  130. u16 ps_mode;
  131. u32 ps_state;
  132. u8 is_deep_sleep;
  133. u8 pm_wakeup_card_req;
  134. u32 pm_wakeup_fw_try;
  135. u8 is_hs_configured;
  136. u8 hs_activated;
  137. u32 num_cmd_host_to_card_failure;
  138. u32 num_cmd_sleep_cfm_host_to_card_failure;
  139. u32 num_tx_host_to_card_failure;
  140. u32 num_event_deauth;
  141. u32 num_event_disassoc;
  142. u32 num_event_link_lost;
  143. u32 num_cmd_deauth;
  144. u32 num_cmd_assoc_success;
  145. u32 num_cmd_assoc_failure;
  146. u32 num_tx_timeout;
  147. u32 num_cmd_timeout;
  148. u16 timeout_cmd_id;
  149. u16 timeout_cmd_act;
  150. u16 last_cmd_id[DBG_CMD_NUM];
  151. u16 last_cmd_act[DBG_CMD_NUM];
  152. u16 last_cmd_index;
  153. u16 last_cmd_resp_id[DBG_CMD_NUM];
  154. u16 last_cmd_resp_index;
  155. u16 last_event[DBG_CMD_NUM];
  156. u16 last_event_index;
  157. u8 data_sent;
  158. u8 cmd_sent;
  159. u8 cmd_resp_received;
  160. u8 event_received;
  161. };
  162. #define MWIFIEX_KEY_INDEX_UNICAST 0x40000000
  163. #define WAPI_RXPN_LEN 16
  164. struct mwifiex_ds_encrypt_key {
  165. u32 key_disable;
  166. u32 key_index;
  167. u32 key_len;
  168. u8 key_material[WLAN_MAX_KEY_LEN];
  169. u8 mac_addr[ETH_ALEN];
  170. u32 is_wapi_key;
  171. u8 wapi_rxpn[WAPI_RXPN_LEN];
  172. };
  173. struct mwifiex_rate_cfg {
  174. u32 action;
  175. u32 is_rate_auto;
  176. u32 rate;
  177. };
  178. struct mwifiex_power_cfg {
  179. u32 is_power_auto;
  180. u32 power_level;
  181. };
  182. struct mwifiex_ds_hs_cfg {
  183. u32 is_invoke_hostcmd;
  184. /* Bit0: non-unicast data
  185. * Bit1: unicast data
  186. * Bit2: mac events
  187. * Bit3: magic packet
  188. */
  189. u32 conditions;
  190. u32 gpio;
  191. u32 gap;
  192. };
  193. #define DEEP_SLEEP_ON 1
  194. #define DEEP_SLEEP_OFF 0
  195. #define DEEP_SLEEP_IDLE_TIME 100
  196. #define PS_MODE_AUTO 1
  197. struct mwifiex_ds_auto_ds {
  198. u16 auto_ds;
  199. u16 idle_time;
  200. };
  201. struct mwifiex_ds_pm_cfg {
  202. union {
  203. u32 ps_mode;
  204. struct mwifiex_ds_hs_cfg hs_cfg;
  205. struct mwifiex_ds_auto_ds auto_deep_sleep;
  206. u32 sleep_period;
  207. } param;
  208. };
  209. struct mwifiex_ds_11n_tx_cfg {
  210. u16 tx_htcap;
  211. u16 tx_htinfo;
  212. };
  213. struct mwifiex_ds_11n_amsdu_aggr_ctrl {
  214. u16 enable;
  215. u16 curr_buf_size;
  216. };
  217. #define MWIFIEX_NUM_OF_CMD_BUFFER 20
  218. #define MWIFIEX_SIZE_OF_CMD_BUFFER 2048
  219. enum {
  220. MWIFIEX_IE_TYPE_GEN_IE = 0,
  221. MWIFIEX_IE_TYPE_ARP_FILTER,
  222. };
  223. enum {
  224. MWIFIEX_REG_MAC = 1,
  225. MWIFIEX_REG_BBP,
  226. MWIFIEX_REG_RF,
  227. MWIFIEX_REG_PMIC,
  228. MWIFIEX_REG_CAU,
  229. };
  230. struct mwifiex_ds_reg_rw {
  231. __le32 type;
  232. __le32 offset;
  233. __le32 value;
  234. };
  235. #define MAX_EEPROM_DATA 256
  236. struct mwifiex_ds_read_eeprom {
  237. __le16 offset;
  238. __le16 byte_count;
  239. u8 value[MAX_EEPROM_DATA];
  240. };
  241. #define IEEE_MAX_IE_SIZE 256
  242. struct mwifiex_ds_misc_gen_ie {
  243. u32 type;
  244. u32 len;
  245. u8 ie_data[IEEE_MAX_IE_SIZE];
  246. };
  247. struct mwifiex_ds_misc_cmd {
  248. u32 len;
  249. u8 cmd[MWIFIEX_SIZE_OF_CMD_BUFFER];
  250. };
  251. #define BITMASK_BCN_RSSI_LOW BIT(0)
  252. #define BITMASK_BCN_RSSI_HIGH BIT(4)
  253. enum subsc_evt_rssi_state {
  254. EVENT_HANDLED,
  255. RSSI_LOW_RECVD,
  256. RSSI_HIGH_RECVD
  257. };
  258. struct subsc_evt_cfg {
  259. u8 abs_value;
  260. u8 evt_freq;
  261. };
  262. struct mwifiex_ds_misc_subsc_evt {
  263. u16 action;
  264. u16 events;
  265. struct subsc_evt_cfg bcn_l_rssi_cfg;
  266. struct subsc_evt_cfg bcn_h_rssi_cfg;
  267. };
  268. #define MWIFIEX_MAX_VSIE_LEN (256)
  269. #define MWIFIEX_MAX_VSIE_NUM (8)
  270. #define MWIFIEX_VSIE_MASK_CLEAR 0x00
  271. #define MWIFIEX_VSIE_MASK_SCAN 0x01
  272. #define MWIFIEX_VSIE_MASK_ASSOC 0x02
  273. #define MWIFIEX_VSIE_MASK_ADHOC 0x04
  274. enum {
  275. MWIFIEX_FUNC_INIT = 1,
  276. MWIFIEX_FUNC_SHUTDOWN,
  277. };
  278. #endif /* !_MWIFIEX_IOCTL_H_ */