uhci-q.c 40 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541
  1. /*
  2. * Universal Host Controller Interface driver for USB.
  3. *
  4. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  5. *
  6. * (C) Copyright 1999 Linus Torvalds
  7. * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
  8. * (C) Copyright 1999 Randy Dunlap
  9. * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10. * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11. * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12. * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13. * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14. * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15. * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16. * (C) Copyright 2004-2006 Alan Stern, stern@rowland.harvard.edu
  17. */
  18. /*
  19. * Technically, updating td->status here is a race, but it's not really a
  20. * problem. The worst that can happen is that we set the IOC bit again
  21. * generating a spurious interrupt. We could fix this by creating another
  22. * QH and leaving the IOC bit always set, but then we would have to play
  23. * games with the FSBR code to make sure we get the correct order in all
  24. * the cases. I don't think it's worth the effort
  25. */
  26. static void uhci_set_next_interrupt(struct uhci_hcd *uhci)
  27. {
  28. if (uhci->is_stopped)
  29. mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
  30. uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
  31. }
  32. static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
  33. {
  34. uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
  35. }
  36. /*
  37. * Full-Speed Bandwidth Reclamation (FSBR).
  38. * We turn on FSBR whenever a queue that wants it is advancing,
  39. * and leave it on for a short time thereafter.
  40. */
  41. static void uhci_fsbr_on(struct uhci_hcd *uhci)
  42. {
  43. uhci->fsbr_is_on = 1;
  44. uhci->skel_term_qh->link = cpu_to_le32(
  45. uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH;
  46. }
  47. static void uhci_fsbr_off(struct uhci_hcd *uhci)
  48. {
  49. uhci->fsbr_is_on = 0;
  50. uhci->skel_term_qh->link = UHCI_PTR_TERM;
  51. }
  52. static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  53. {
  54. struct urb_priv *urbp = urb->hcpriv;
  55. if (!(urb->transfer_flags & URB_NO_FSBR))
  56. urbp->fsbr = 1;
  57. }
  58. static void uhci_urbp_wants_fsbr(struct uhci_hcd *uhci, struct urb_priv *urbp)
  59. {
  60. if (urbp->fsbr) {
  61. uhci->fsbr_is_wanted = 1;
  62. if (!uhci->fsbr_is_on)
  63. uhci_fsbr_on(uhci);
  64. else if (uhci->fsbr_expiring) {
  65. uhci->fsbr_expiring = 0;
  66. del_timer(&uhci->fsbr_timer);
  67. }
  68. }
  69. }
  70. static void uhci_fsbr_timeout(unsigned long _uhci)
  71. {
  72. struct uhci_hcd *uhci = (struct uhci_hcd *) _uhci;
  73. unsigned long flags;
  74. spin_lock_irqsave(&uhci->lock, flags);
  75. if (uhci->fsbr_expiring) {
  76. uhci->fsbr_expiring = 0;
  77. uhci_fsbr_off(uhci);
  78. }
  79. spin_unlock_irqrestore(&uhci->lock, flags);
  80. }
  81. static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci)
  82. {
  83. dma_addr_t dma_handle;
  84. struct uhci_td *td;
  85. td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
  86. if (!td)
  87. return NULL;
  88. td->dma_handle = dma_handle;
  89. td->frame = -1;
  90. INIT_LIST_HEAD(&td->list);
  91. INIT_LIST_HEAD(&td->fl_list);
  92. return td;
  93. }
  94. static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
  95. {
  96. if (!list_empty(&td->list))
  97. dev_warn(uhci_dev(uhci), "td %p still in list!\n", td);
  98. if (!list_empty(&td->fl_list))
  99. dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td);
  100. dma_pool_free(uhci->td_pool, td, td->dma_handle);
  101. }
  102. static inline void uhci_fill_td(struct uhci_td *td, u32 status,
  103. u32 token, u32 buffer)
  104. {
  105. td->status = cpu_to_le32(status);
  106. td->token = cpu_to_le32(token);
  107. td->buffer = cpu_to_le32(buffer);
  108. }
  109. static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp)
  110. {
  111. list_add_tail(&td->list, &urbp->td_list);
  112. }
  113. static void uhci_remove_td_from_urbp(struct uhci_td *td)
  114. {
  115. list_del_init(&td->list);
  116. }
  117. /*
  118. * We insert Isochronous URBs directly into the frame list at the beginning
  119. */
  120. static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci,
  121. struct uhci_td *td, unsigned framenum)
  122. {
  123. framenum &= (UHCI_NUMFRAMES - 1);
  124. td->frame = framenum;
  125. /* Is there a TD already mapped there? */
  126. if (uhci->frame_cpu[framenum]) {
  127. struct uhci_td *ftd, *ltd;
  128. ftd = uhci->frame_cpu[framenum];
  129. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  130. list_add_tail(&td->fl_list, &ftd->fl_list);
  131. td->link = ltd->link;
  132. wmb();
  133. ltd->link = cpu_to_le32(td->dma_handle);
  134. } else {
  135. td->link = uhci->frame[framenum];
  136. wmb();
  137. uhci->frame[framenum] = cpu_to_le32(td->dma_handle);
  138. uhci->frame_cpu[framenum] = td;
  139. }
  140. }
  141. static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci,
  142. struct uhci_td *td)
  143. {
  144. /* If it's not inserted, don't remove it */
  145. if (td->frame == -1) {
  146. WARN_ON(!list_empty(&td->fl_list));
  147. return;
  148. }
  149. if (uhci->frame_cpu[td->frame] == td) {
  150. if (list_empty(&td->fl_list)) {
  151. uhci->frame[td->frame] = td->link;
  152. uhci->frame_cpu[td->frame] = NULL;
  153. } else {
  154. struct uhci_td *ntd;
  155. ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
  156. uhci->frame[td->frame] = cpu_to_le32(ntd->dma_handle);
  157. uhci->frame_cpu[td->frame] = ntd;
  158. }
  159. } else {
  160. struct uhci_td *ptd;
  161. ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
  162. ptd->link = td->link;
  163. }
  164. list_del_init(&td->fl_list);
  165. td->frame = -1;
  166. }
  167. static inline void uhci_remove_tds_from_frame(struct uhci_hcd *uhci,
  168. unsigned int framenum)
  169. {
  170. struct uhci_td *ftd, *ltd;
  171. framenum &= (UHCI_NUMFRAMES - 1);
  172. ftd = uhci->frame_cpu[framenum];
  173. if (ftd) {
  174. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  175. uhci->frame[framenum] = ltd->link;
  176. uhci->frame_cpu[framenum] = NULL;
  177. while (!list_empty(&ftd->fl_list))
  178. list_del_init(ftd->fl_list.prev);
  179. }
  180. }
  181. /*
  182. * Remove all the TDs for an Isochronous URB from the frame list
  183. */
  184. static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb)
  185. {
  186. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  187. struct uhci_td *td;
  188. list_for_each_entry(td, &urbp->td_list, list)
  189. uhci_remove_td_from_frame_list(uhci, td);
  190. }
  191. static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci,
  192. struct usb_device *udev, struct usb_host_endpoint *hep)
  193. {
  194. dma_addr_t dma_handle;
  195. struct uhci_qh *qh;
  196. qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
  197. if (!qh)
  198. return NULL;
  199. memset(qh, 0, sizeof(*qh));
  200. qh->dma_handle = dma_handle;
  201. qh->element = UHCI_PTR_TERM;
  202. qh->link = UHCI_PTR_TERM;
  203. INIT_LIST_HEAD(&qh->queue);
  204. INIT_LIST_HEAD(&qh->node);
  205. if (udev) { /* Normal QH */
  206. qh->dummy_td = uhci_alloc_td(uhci);
  207. if (!qh->dummy_td) {
  208. dma_pool_free(uhci->qh_pool, qh, dma_handle);
  209. return NULL;
  210. }
  211. qh->state = QH_STATE_IDLE;
  212. qh->hep = hep;
  213. qh->udev = udev;
  214. hep->hcpriv = qh;
  215. qh->type = hep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  216. } else { /* Skeleton QH */
  217. qh->state = QH_STATE_ACTIVE;
  218. qh->type = -1;
  219. }
  220. return qh;
  221. }
  222. static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  223. {
  224. WARN_ON(qh->state != QH_STATE_IDLE && qh->udev);
  225. if (!list_empty(&qh->queue))
  226. dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh);
  227. list_del(&qh->node);
  228. if (qh->udev) {
  229. qh->hep->hcpriv = NULL;
  230. uhci_free_td(uhci, qh->dummy_td);
  231. }
  232. dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
  233. }
  234. /*
  235. * When a queue is stopped and a dequeued URB is given back, adjust
  236. * the previous TD link (if the URB isn't first on the queue) or
  237. * save its toggle value (if it is first and is currently executing).
  238. *
  239. * Returns 0 if the URB should not yet be given back, 1 otherwise.
  240. */
  241. static int uhci_cleanup_queue(struct uhci_hcd *uhci, struct uhci_qh *qh,
  242. struct urb *urb)
  243. {
  244. struct urb_priv *urbp = urb->hcpriv;
  245. struct uhci_td *td;
  246. int ret = 1;
  247. /* Isochronous pipes don't use toggles and their TD link pointers
  248. * get adjusted during uhci_urb_dequeue(). But since their queues
  249. * cannot truly be stopped, we have to watch out for dequeues
  250. * occurring after the nominal unlink frame. */
  251. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  252. ret = (uhci->frame_number + uhci->is_stopped !=
  253. qh->unlink_frame);
  254. goto done;
  255. }
  256. /* If the URB isn't first on its queue, adjust the link pointer
  257. * of the last TD in the previous URB. The toggle doesn't need
  258. * to be saved since this URB can't be executing yet. */
  259. if (qh->queue.next != &urbp->node) {
  260. struct urb_priv *purbp;
  261. struct uhci_td *ptd;
  262. purbp = list_entry(urbp->node.prev, struct urb_priv, node);
  263. WARN_ON(list_empty(&purbp->td_list));
  264. ptd = list_entry(purbp->td_list.prev, struct uhci_td,
  265. list);
  266. td = list_entry(urbp->td_list.prev, struct uhci_td,
  267. list);
  268. ptd->link = td->link;
  269. goto done;
  270. }
  271. /* If the QH element pointer is UHCI_PTR_TERM then then currently
  272. * executing URB has already been unlinked, so this one isn't it. */
  273. if (qh_element(qh) == UHCI_PTR_TERM)
  274. goto done;
  275. qh->element = UHCI_PTR_TERM;
  276. /* Control pipes have to worry about toggles */
  277. if (qh->type == USB_ENDPOINT_XFER_CONTROL)
  278. goto done;
  279. /* Save the next toggle value */
  280. WARN_ON(list_empty(&urbp->td_list));
  281. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  282. qh->needs_fixup = 1;
  283. qh->initial_toggle = uhci_toggle(td_token(td));
  284. done:
  285. return ret;
  286. }
  287. /*
  288. * Fix up the data toggles for URBs in a queue, when one of them
  289. * terminates early (short transfer, error, or dequeued).
  290. */
  291. static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first)
  292. {
  293. struct urb_priv *urbp = NULL;
  294. struct uhci_td *td;
  295. unsigned int toggle = qh->initial_toggle;
  296. unsigned int pipe;
  297. /* Fixups for a short transfer start with the second URB in the
  298. * queue (the short URB is the first). */
  299. if (skip_first)
  300. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  301. /* When starting with the first URB, if the QH element pointer is
  302. * still valid then we know the URB's toggles are okay. */
  303. else if (qh_element(qh) != UHCI_PTR_TERM)
  304. toggle = 2;
  305. /* Fix up the toggle for the URBs in the queue. Normally this
  306. * loop won't run more than once: When an error or short transfer
  307. * occurs, the queue usually gets emptied. */
  308. urbp = list_prepare_entry(urbp, &qh->queue, node);
  309. list_for_each_entry_continue(urbp, &qh->queue, node) {
  310. /* If the first TD has the right toggle value, we don't
  311. * need to change any toggles in this URB */
  312. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  313. if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) {
  314. td = list_entry(urbp->td_list.prev, struct uhci_td,
  315. list);
  316. toggle = uhci_toggle(td_token(td)) ^ 1;
  317. /* Otherwise all the toggles in the URB have to be switched */
  318. } else {
  319. list_for_each_entry(td, &urbp->td_list, list) {
  320. td->token ^= __constant_cpu_to_le32(
  321. TD_TOKEN_TOGGLE);
  322. toggle ^= 1;
  323. }
  324. }
  325. }
  326. wmb();
  327. pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe;
  328. usb_settoggle(qh->udev, usb_pipeendpoint(pipe),
  329. usb_pipeout(pipe), toggle);
  330. qh->needs_fixup = 0;
  331. }
  332. /*
  333. * Put a QH on the schedule in both hardware and software
  334. */
  335. static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  336. {
  337. struct uhci_qh *pqh;
  338. WARN_ON(list_empty(&qh->queue));
  339. /* Set the element pointer if it isn't set already.
  340. * This isn't needed for Isochronous queues, but it doesn't hurt. */
  341. if (qh_element(qh) == UHCI_PTR_TERM) {
  342. struct urb_priv *urbp = list_entry(qh->queue.next,
  343. struct urb_priv, node);
  344. struct uhci_td *td = list_entry(urbp->td_list.next,
  345. struct uhci_td, list);
  346. qh->element = cpu_to_le32(td->dma_handle);
  347. }
  348. /* Treat the queue as if it has just advanced */
  349. qh->wait_expired = 0;
  350. qh->advance_jiffies = jiffies;
  351. if (qh->state == QH_STATE_ACTIVE)
  352. return;
  353. qh->state = QH_STATE_ACTIVE;
  354. /* Move the QH from its old list to the end of the appropriate
  355. * skeleton's list */
  356. if (qh == uhci->next_qh)
  357. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  358. node);
  359. list_move_tail(&qh->node, &qh->skel->node);
  360. /* Link it into the schedule */
  361. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  362. qh->link = pqh->link;
  363. wmb();
  364. pqh->link = UHCI_PTR_QH | cpu_to_le32(qh->dma_handle);
  365. }
  366. /*
  367. * Take a QH off the hardware schedule
  368. */
  369. static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  370. {
  371. struct uhci_qh *pqh;
  372. if (qh->state == QH_STATE_UNLINKING)
  373. return;
  374. WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev);
  375. qh->state = QH_STATE_UNLINKING;
  376. /* Unlink the QH from the schedule and record when we did it */
  377. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  378. pqh->link = qh->link;
  379. mb();
  380. uhci_get_current_frame_number(uhci);
  381. qh->unlink_frame = uhci->frame_number;
  382. /* Force an interrupt so we know when the QH is fully unlinked */
  383. if (list_empty(&uhci->skel_unlink_qh->node))
  384. uhci_set_next_interrupt(uhci);
  385. /* Move the QH from its old list to the end of the unlinking list */
  386. if (qh == uhci->next_qh)
  387. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  388. node);
  389. list_move_tail(&qh->node, &uhci->skel_unlink_qh->node);
  390. }
  391. /*
  392. * When we and the controller are through with a QH, it becomes IDLE.
  393. * This happens when a QH has been off the schedule (on the unlinking
  394. * list) for more than one frame, or when an error occurs while adding
  395. * the first URB onto a new QH.
  396. */
  397. static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh)
  398. {
  399. WARN_ON(qh->state == QH_STATE_ACTIVE);
  400. if (qh == uhci->next_qh)
  401. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  402. node);
  403. list_move(&qh->node, &uhci->idle_qh_list);
  404. qh->state = QH_STATE_IDLE;
  405. /* Now that the QH is idle, its post_td isn't being used */
  406. if (qh->post_td) {
  407. uhci_free_td(uhci, qh->post_td);
  408. qh->post_td = NULL;
  409. }
  410. /* If anyone is waiting for a QH to become idle, wake them up */
  411. if (uhci->num_waiting)
  412. wake_up_all(&uhci->waitqh);
  413. }
  414. static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci,
  415. struct urb *urb)
  416. {
  417. struct urb_priv *urbp;
  418. urbp = kmem_cache_alloc(uhci_up_cachep, SLAB_ATOMIC);
  419. if (!urbp)
  420. return NULL;
  421. memset((void *)urbp, 0, sizeof(*urbp));
  422. urbp->urb = urb;
  423. urb->hcpriv = urbp;
  424. INIT_LIST_HEAD(&urbp->node);
  425. INIT_LIST_HEAD(&urbp->td_list);
  426. return urbp;
  427. }
  428. static void uhci_free_urb_priv(struct uhci_hcd *uhci,
  429. struct urb_priv *urbp)
  430. {
  431. struct uhci_td *td, *tmp;
  432. if (!list_empty(&urbp->node))
  433. dev_warn(uhci_dev(uhci), "urb %p still on QH's list!\n",
  434. urbp->urb);
  435. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  436. uhci_remove_td_from_urbp(td);
  437. uhci_free_td(uhci, td);
  438. }
  439. urbp->urb->hcpriv = NULL;
  440. kmem_cache_free(uhci_up_cachep, urbp);
  441. }
  442. /*
  443. * Map status to standard result codes
  444. *
  445. * <status> is (td_status(td) & 0xF60000), a.k.a.
  446. * uhci_status_bits(td_status(td)).
  447. * Note: <status> does not include the TD_CTRL_NAK bit.
  448. * <dir_out> is True for output TDs and False for input TDs.
  449. */
  450. static int uhci_map_status(int status, int dir_out)
  451. {
  452. if (!status)
  453. return 0;
  454. if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
  455. return -EPROTO;
  456. if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
  457. if (dir_out)
  458. return -EPROTO;
  459. else
  460. return -EILSEQ;
  461. }
  462. if (status & TD_CTRL_BABBLE) /* Babble */
  463. return -EOVERFLOW;
  464. if (status & TD_CTRL_DBUFERR) /* Buffer error */
  465. return -ENOSR;
  466. if (status & TD_CTRL_STALLED) /* Stalled */
  467. return -EPIPE;
  468. return 0;
  469. }
  470. /*
  471. * Control transfers
  472. */
  473. static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb,
  474. struct uhci_qh *qh)
  475. {
  476. struct uhci_td *td;
  477. unsigned long destination, status;
  478. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  479. int len = urb->transfer_buffer_length;
  480. dma_addr_t data = urb->transfer_dma;
  481. __le32 *plink;
  482. struct urb_priv *urbp = urb->hcpriv;
  483. /* The "pipe" thing contains the destination in bits 8--18 */
  484. destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
  485. /* 3 errors, dummy TD remains inactive */
  486. status = uhci_maxerr(3);
  487. if (urb->dev->speed == USB_SPEED_LOW)
  488. status |= TD_CTRL_LS;
  489. /*
  490. * Build the TD for the control request setup packet
  491. */
  492. td = qh->dummy_td;
  493. uhci_add_td_to_urbp(td, urbp);
  494. uhci_fill_td(td, status, destination | uhci_explen(8),
  495. urb->setup_dma);
  496. plink = &td->link;
  497. status |= TD_CTRL_ACTIVE;
  498. /*
  499. * If direction is "send", change the packet ID from SETUP (0x2D)
  500. * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
  501. * set Short Packet Detect (SPD) for all data packets.
  502. */
  503. if (usb_pipeout(urb->pipe))
  504. destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
  505. else {
  506. destination ^= (USB_PID_SETUP ^ USB_PID_IN);
  507. status |= TD_CTRL_SPD;
  508. }
  509. /*
  510. * Build the DATA TDs
  511. */
  512. while (len > 0) {
  513. int pktsze = min(len, maxsze);
  514. td = uhci_alloc_td(uhci);
  515. if (!td)
  516. goto nomem;
  517. *plink = cpu_to_le32(td->dma_handle);
  518. /* Alternate Data0/1 (start with Data1) */
  519. destination ^= TD_TOKEN_TOGGLE;
  520. uhci_add_td_to_urbp(td, urbp);
  521. uhci_fill_td(td, status, destination | uhci_explen(pktsze),
  522. data);
  523. plink = &td->link;
  524. data += pktsze;
  525. len -= pktsze;
  526. }
  527. /*
  528. * Build the final TD for control status
  529. */
  530. td = uhci_alloc_td(uhci);
  531. if (!td)
  532. goto nomem;
  533. *plink = cpu_to_le32(td->dma_handle);
  534. /*
  535. * It's IN if the pipe is an output pipe or we're not expecting
  536. * data back.
  537. */
  538. destination &= ~TD_TOKEN_PID_MASK;
  539. if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length)
  540. destination |= USB_PID_IN;
  541. else
  542. destination |= USB_PID_OUT;
  543. destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
  544. status &= ~TD_CTRL_SPD;
  545. uhci_add_td_to_urbp(td, urbp);
  546. uhci_fill_td(td, status | TD_CTRL_IOC,
  547. destination | uhci_explen(0), 0);
  548. plink = &td->link;
  549. /*
  550. * Build the new dummy TD and activate the old one
  551. */
  552. td = uhci_alloc_td(uhci);
  553. if (!td)
  554. goto nomem;
  555. *plink = cpu_to_le32(td->dma_handle);
  556. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  557. wmb();
  558. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  559. qh->dummy_td = td;
  560. /* Low-speed transfers get a different queue, and won't hog the bus.
  561. * Also, some devices enumerate better without FSBR; the easiest way
  562. * to do that is to put URBs on the low-speed queue while the device
  563. * isn't in the CONFIGURED state. */
  564. if (urb->dev->speed == USB_SPEED_LOW ||
  565. urb->dev->state != USB_STATE_CONFIGURED)
  566. qh->skel = uhci->skel_ls_control_qh;
  567. else {
  568. qh->skel = uhci->skel_fs_control_qh;
  569. uhci_add_fsbr(uhci, urb);
  570. }
  571. urb->actual_length = -8; /* Account for the SETUP packet */
  572. return 0;
  573. nomem:
  574. /* Remove the dummy TD from the td_list so it doesn't get freed */
  575. uhci_remove_td_from_urbp(qh->dummy_td);
  576. return -ENOMEM;
  577. }
  578. /*
  579. * Common submit for bulk and interrupt
  580. */
  581. static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb,
  582. struct uhci_qh *qh)
  583. {
  584. struct uhci_td *td;
  585. unsigned long destination, status;
  586. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  587. int len = urb->transfer_buffer_length;
  588. dma_addr_t data = urb->transfer_dma;
  589. __le32 *plink;
  590. struct urb_priv *urbp = urb->hcpriv;
  591. unsigned int toggle;
  592. if (len < 0)
  593. return -EINVAL;
  594. /* The "pipe" thing contains the destination in bits 8--18 */
  595. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  596. toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  597. usb_pipeout(urb->pipe));
  598. /* 3 errors, dummy TD remains inactive */
  599. status = uhci_maxerr(3);
  600. if (urb->dev->speed == USB_SPEED_LOW)
  601. status |= TD_CTRL_LS;
  602. if (usb_pipein(urb->pipe))
  603. status |= TD_CTRL_SPD;
  604. /*
  605. * Build the DATA TDs
  606. */
  607. plink = NULL;
  608. td = qh->dummy_td;
  609. do { /* Allow zero length packets */
  610. int pktsze = maxsze;
  611. if (len <= pktsze) { /* The last packet */
  612. pktsze = len;
  613. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  614. status &= ~TD_CTRL_SPD;
  615. }
  616. if (plink) {
  617. td = uhci_alloc_td(uhci);
  618. if (!td)
  619. goto nomem;
  620. *plink = cpu_to_le32(td->dma_handle);
  621. }
  622. uhci_add_td_to_urbp(td, urbp);
  623. uhci_fill_td(td, status,
  624. destination | uhci_explen(pktsze) |
  625. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  626. data);
  627. plink = &td->link;
  628. status |= TD_CTRL_ACTIVE;
  629. data += pktsze;
  630. len -= maxsze;
  631. toggle ^= 1;
  632. } while (len > 0);
  633. /*
  634. * URB_ZERO_PACKET means adding a 0-length packet, if direction
  635. * is OUT and the transfer_length was an exact multiple of maxsze,
  636. * hence (len = transfer_length - N * maxsze) == 0
  637. * however, if transfer_length == 0, the zero packet was already
  638. * prepared above.
  639. */
  640. if ((urb->transfer_flags & URB_ZERO_PACKET) &&
  641. usb_pipeout(urb->pipe) && len == 0 &&
  642. urb->transfer_buffer_length > 0) {
  643. td = uhci_alloc_td(uhci);
  644. if (!td)
  645. goto nomem;
  646. *plink = cpu_to_le32(td->dma_handle);
  647. uhci_add_td_to_urbp(td, urbp);
  648. uhci_fill_td(td, status,
  649. destination | uhci_explen(0) |
  650. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  651. data);
  652. plink = &td->link;
  653. toggle ^= 1;
  654. }
  655. /* Set the interrupt-on-completion flag on the last packet.
  656. * A more-or-less typical 4 KB URB (= size of one memory page)
  657. * will require about 3 ms to transfer; that's a little on the
  658. * fast side but not enough to justify delaying an interrupt
  659. * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
  660. * flag setting. */
  661. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  662. /*
  663. * Build the new dummy TD and activate the old one
  664. */
  665. td = uhci_alloc_td(uhci);
  666. if (!td)
  667. goto nomem;
  668. *plink = cpu_to_le32(td->dma_handle);
  669. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  670. wmb();
  671. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  672. qh->dummy_td = td;
  673. qh->period = urb->interval;
  674. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  675. usb_pipeout(urb->pipe), toggle);
  676. return 0;
  677. nomem:
  678. /* Remove the dummy TD from the td_list so it doesn't get freed */
  679. uhci_remove_td_from_urbp(qh->dummy_td);
  680. return -ENOMEM;
  681. }
  682. static inline int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb,
  683. struct uhci_qh *qh)
  684. {
  685. int ret;
  686. /* Can't have low-speed bulk transfers */
  687. if (urb->dev->speed == USB_SPEED_LOW)
  688. return -EINVAL;
  689. qh->skel = uhci->skel_bulk_qh;
  690. ret = uhci_submit_common(uhci, urb, qh);
  691. if (ret == 0)
  692. uhci_add_fsbr(uhci, urb);
  693. return ret;
  694. }
  695. static int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb,
  696. struct uhci_qh *qh)
  697. {
  698. int exponent;
  699. /* USB 1.1 interrupt transfers only involve one packet per interval.
  700. * Drivers can submit URBs of any length, but longer ones will need
  701. * multiple intervals to complete.
  702. */
  703. /* Figure out which power-of-two queue to use */
  704. for (exponent = 7; exponent >= 0; --exponent) {
  705. if ((1 << exponent) <= urb->interval)
  706. break;
  707. }
  708. if (exponent < 0)
  709. return -EINVAL;
  710. urb->interval = 1 << exponent;
  711. if (qh->period == 0)
  712. qh->skel = uhci->skelqh[UHCI_SKEL_INDEX(exponent)];
  713. else if (qh->period != urb->interval)
  714. return -EINVAL; /* Can't change the period */
  715. return uhci_submit_common(uhci, urb, qh);
  716. }
  717. /*
  718. * Fix up the data structures following a short transfer
  719. */
  720. static int uhci_fixup_short_transfer(struct uhci_hcd *uhci,
  721. struct uhci_qh *qh, struct urb_priv *urbp)
  722. {
  723. struct uhci_td *td;
  724. struct list_head *tmp;
  725. int ret;
  726. td = list_entry(urbp->td_list.prev, struct uhci_td, list);
  727. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  728. /* When a control transfer is short, we have to restart
  729. * the queue at the status stage transaction, which is
  730. * the last TD. */
  731. WARN_ON(list_empty(&urbp->td_list));
  732. qh->element = cpu_to_le32(td->dma_handle);
  733. tmp = td->list.prev;
  734. ret = -EINPROGRESS;
  735. } else {
  736. /* When a bulk/interrupt transfer is short, we have to
  737. * fix up the toggles of the following URBs on the queue
  738. * before restarting the queue at the next URB. */
  739. qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1;
  740. uhci_fixup_toggles(qh, 1);
  741. if (list_empty(&urbp->td_list))
  742. td = qh->post_td;
  743. qh->element = td->link;
  744. tmp = urbp->td_list.prev;
  745. ret = 0;
  746. }
  747. /* Remove all the TDs we skipped over, from tmp back to the start */
  748. while (tmp != &urbp->td_list) {
  749. td = list_entry(tmp, struct uhci_td, list);
  750. tmp = tmp->prev;
  751. uhci_remove_td_from_urbp(td);
  752. uhci_free_td(uhci, td);
  753. }
  754. return ret;
  755. }
  756. /*
  757. * Common result for control, bulk, and interrupt
  758. */
  759. static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
  760. {
  761. struct urb_priv *urbp = urb->hcpriv;
  762. struct uhci_qh *qh = urbp->qh;
  763. struct uhci_td *td, *tmp;
  764. unsigned status;
  765. int ret = 0;
  766. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  767. unsigned int ctrlstat;
  768. int len;
  769. ctrlstat = td_status(td);
  770. status = uhci_status_bits(ctrlstat);
  771. if (status & TD_CTRL_ACTIVE)
  772. return -EINPROGRESS;
  773. len = uhci_actual_length(ctrlstat);
  774. urb->actual_length += len;
  775. if (status) {
  776. ret = uhci_map_status(status,
  777. uhci_packetout(td_token(td)));
  778. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  779. /* Some debugging code */
  780. dev_dbg(&urb->dev->dev,
  781. "%s: failed with status %x\n",
  782. __FUNCTION__, status);
  783. if (debug > 1 && errbuf) {
  784. /* Print the chain for debugging */
  785. uhci_show_qh(urbp->qh, errbuf,
  786. ERRBUF_LEN, 0);
  787. lprintk(errbuf);
  788. }
  789. }
  790. } else if (len < uhci_expected_length(td_token(td))) {
  791. /* We received a short packet */
  792. if (urb->transfer_flags & URB_SHORT_NOT_OK)
  793. ret = -EREMOTEIO;
  794. /* Fixup needed only if this isn't the URB's last TD */
  795. else if (&td->list != urbp->td_list.prev)
  796. ret = 1;
  797. }
  798. uhci_remove_td_from_urbp(td);
  799. if (qh->post_td)
  800. uhci_free_td(uhci, qh->post_td);
  801. qh->post_td = td;
  802. if (ret != 0)
  803. goto err;
  804. }
  805. return ret;
  806. err:
  807. if (ret < 0) {
  808. /* In case a control transfer gets an error
  809. * during the setup stage */
  810. urb->actual_length = max(urb->actual_length, 0);
  811. /* Note that the queue has stopped and save
  812. * the next toggle value */
  813. qh->element = UHCI_PTR_TERM;
  814. qh->is_stopped = 1;
  815. qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL);
  816. qh->initial_toggle = uhci_toggle(td_token(td)) ^
  817. (ret == -EREMOTEIO);
  818. } else /* Short packet received */
  819. ret = uhci_fixup_short_transfer(uhci, qh, urbp);
  820. return ret;
  821. }
  822. /*
  823. * Isochronous transfers
  824. */
  825. static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb,
  826. struct uhci_qh *qh)
  827. {
  828. struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */
  829. int i, frame;
  830. unsigned long destination, status;
  831. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  832. /* Values must not be too big (could overflow below) */
  833. if (urb->interval >= UHCI_NUMFRAMES ||
  834. urb->number_of_packets >= UHCI_NUMFRAMES)
  835. return -EFBIG;
  836. /* Check the period and figure out the starting frame number */
  837. if (qh->period == 0) {
  838. if (urb->transfer_flags & URB_ISO_ASAP) {
  839. uhci_get_current_frame_number(uhci);
  840. urb->start_frame = uhci->frame_number + 10;
  841. } else {
  842. i = urb->start_frame - uhci->last_iso_frame;
  843. if (i <= 0 || i >= UHCI_NUMFRAMES)
  844. return -EINVAL;
  845. }
  846. } else if (qh->period != urb->interval) {
  847. return -EINVAL; /* Can't change the period */
  848. } else { /* Pick up where the last URB leaves off */
  849. if (list_empty(&qh->queue)) {
  850. frame = qh->iso_frame;
  851. } else {
  852. struct urb *lurb;
  853. lurb = list_entry(qh->queue.prev,
  854. struct urb_priv, node)->urb;
  855. frame = lurb->start_frame +
  856. lurb->number_of_packets *
  857. lurb->interval;
  858. }
  859. if (urb->transfer_flags & URB_ISO_ASAP)
  860. urb->start_frame = frame;
  861. else if (urb->start_frame != frame)
  862. return -EINVAL;
  863. }
  864. /* Make sure we won't have to go too far into the future */
  865. if (uhci_frame_before_eq(uhci->last_iso_frame + UHCI_NUMFRAMES,
  866. urb->start_frame + urb->number_of_packets *
  867. urb->interval))
  868. return -EFBIG;
  869. status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
  870. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  871. for (i = 0; i < urb->number_of_packets; i++) {
  872. td = uhci_alloc_td(uhci);
  873. if (!td)
  874. return -ENOMEM;
  875. uhci_add_td_to_urbp(td, urbp);
  876. uhci_fill_td(td, status, destination |
  877. uhci_explen(urb->iso_frame_desc[i].length),
  878. urb->transfer_dma +
  879. urb->iso_frame_desc[i].offset);
  880. }
  881. /* Set the interrupt-on-completion flag on the last packet. */
  882. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  883. qh->skel = uhci->skel_iso_qh;
  884. qh->period = urb->interval;
  885. /* Add the TDs to the frame list */
  886. frame = urb->start_frame;
  887. list_for_each_entry(td, &urbp->td_list, list) {
  888. uhci_insert_td_in_frame_list(uhci, td, frame);
  889. frame += qh->period;
  890. }
  891. if (list_empty(&qh->queue)) {
  892. qh->iso_packet_desc = &urb->iso_frame_desc[0];
  893. qh->iso_frame = urb->start_frame;
  894. qh->iso_status = 0;
  895. }
  896. return 0;
  897. }
  898. static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
  899. {
  900. struct uhci_td *td, *tmp;
  901. struct urb_priv *urbp = urb->hcpriv;
  902. struct uhci_qh *qh = urbp->qh;
  903. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  904. unsigned int ctrlstat;
  905. int status;
  906. int actlength;
  907. if (uhci_frame_before_eq(uhci->cur_iso_frame, qh->iso_frame))
  908. return -EINPROGRESS;
  909. uhci_remove_tds_from_frame(uhci, qh->iso_frame);
  910. ctrlstat = td_status(td);
  911. if (ctrlstat & TD_CTRL_ACTIVE) {
  912. status = -EXDEV; /* TD was added too late? */
  913. } else {
  914. status = uhci_map_status(uhci_status_bits(ctrlstat),
  915. usb_pipeout(urb->pipe));
  916. actlength = uhci_actual_length(ctrlstat);
  917. urb->actual_length += actlength;
  918. qh->iso_packet_desc->actual_length = actlength;
  919. qh->iso_packet_desc->status = status;
  920. }
  921. if (status) {
  922. urb->error_count++;
  923. qh->iso_status = status;
  924. }
  925. uhci_remove_td_from_urbp(td);
  926. uhci_free_td(uhci, td);
  927. qh->iso_frame += qh->period;
  928. ++qh->iso_packet_desc;
  929. }
  930. return qh->iso_status;
  931. }
  932. static int uhci_urb_enqueue(struct usb_hcd *hcd,
  933. struct usb_host_endpoint *hep,
  934. struct urb *urb, gfp_t mem_flags)
  935. {
  936. int ret;
  937. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  938. unsigned long flags;
  939. struct urb_priv *urbp;
  940. struct uhci_qh *qh;
  941. int bustime;
  942. spin_lock_irqsave(&uhci->lock, flags);
  943. ret = urb->status;
  944. if (ret != -EINPROGRESS) /* URB already unlinked! */
  945. goto done;
  946. ret = -ENOMEM;
  947. urbp = uhci_alloc_urb_priv(uhci, urb);
  948. if (!urbp)
  949. goto done;
  950. if (hep->hcpriv)
  951. qh = (struct uhci_qh *) hep->hcpriv;
  952. else {
  953. qh = uhci_alloc_qh(uhci, urb->dev, hep);
  954. if (!qh)
  955. goto err_no_qh;
  956. }
  957. urbp->qh = qh;
  958. switch (qh->type) {
  959. case USB_ENDPOINT_XFER_CONTROL:
  960. ret = uhci_submit_control(uhci, urb, qh);
  961. break;
  962. case USB_ENDPOINT_XFER_BULK:
  963. ret = uhci_submit_bulk(uhci, urb, qh);
  964. break;
  965. case USB_ENDPOINT_XFER_INT:
  966. if (list_empty(&qh->queue)) {
  967. bustime = usb_check_bandwidth(urb->dev, urb);
  968. if (bustime < 0)
  969. ret = bustime;
  970. else {
  971. ret = uhci_submit_interrupt(uhci, urb, qh);
  972. if (ret == 0)
  973. usb_claim_bandwidth(urb->dev, urb, bustime, 0);
  974. }
  975. } else { /* inherit from parent */
  976. struct urb_priv *eurbp;
  977. eurbp = list_entry(qh->queue.prev, struct urb_priv,
  978. node);
  979. urb->bandwidth = eurbp->urb->bandwidth;
  980. ret = uhci_submit_interrupt(uhci, urb, qh);
  981. }
  982. break;
  983. case USB_ENDPOINT_XFER_ISOC:
  984. urb->error_count = 0;
  985. bustime = usb_check_bandwidth(urb->dev, urb);
  986. if (bustime < 0) {
  987. ret = bustime;
  988. break;
  989. }
  990. ret = uhci_submit_isochronous(uhci, urb, qh);
  991. if (ret == 0)
  992. usb_claim_bandwidth(urb->dev, urb, bustime, 1);
  993. break;
  994. }
  995. if (ret != 0)
  996. goto err_submit_failed;
  997. /* Add this URB to the QH */
  998. urbp->qh = qh;
  999. list_add_tail(&urbp->node, &qh->queue);
  1000. /* If the new URB is the first and only one on this QH then either
  1001. * the QH is new and idle or else it's unlinked and waiting to
  1002. * become idle, so we can activate it right away. But only if the
  1003. * queue isn't stopped. */
  1004. if (qh->queue.next == &urbp->node && !qh->is_stopped) {
  1005. uhci_activate_qh(uhci, qh);
  1006. uhci_urbp_wants_fsbr(uhci, urbp);
  1007. }
  1008. goto done;
  1009. err_submit_failed:
  1010. if (qh->state == QH_STATE_IDLE)
  1011. uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */
  1012. err_no_qh:
  1013. uhci_free_urb_priv(uhci, urbp);
  1014. done:
  1015. spin_unlock_irqrestore(&uhci->lock, flags);
  1016. return ret;
  1017. }
  1018. static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
  1019. {
  1020. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  1021. unsigned long flags;
  1022. struct urb_priv *urbp;
  1023. struct uhci_qh *qh;
  1024. spin_lock_irqsave(&uhci->lock, flags);
  1025. urbp = urb->hcpriv;
  1026. if (!urbp) /* URB was never linked! */
  1027. goto done;
  1028. qh = urbp->qh;
  1029. /* Remove Isochronous TDs from the frame list ASAP */
  1030. if (qh->type == USB_ENDPOINT_XFER_ISOC) {
  1031. uhci_unlink_isochronous_tds(uhci, urb);
  1032. mb();
  1033. /* If the URB has already started, update the QH unlink time */
  1034. uhci_get_current_frame_number(uhci);
  1035. if (uhci_frame_before_eq(urb->start_frame, uhci->frame_number))
  1036. qh->unlink_frame = uhci->frame_number;
  1037. }
  1038. uhci_unlink_qh(uhci, qh);
  1039. done:
  1040. spin_unlock_irqrestore(&uhci->lock, flags);
  1041. return 0;
  1042. }
  1043. /*
  1044. * Finish unlinking an URB and give it back
  1045. */
  1046. static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh,
  1047. struct urb *urb)
  1048. __releases(uhci->lock)
  1049. __acquires(uhci->lock)
  1050. {
  1051. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  1052. /* When giving back the first URB in an Isochronous queue,
  1053. * reinitialize the QH's iso-related members for the next URB. */
  1054. if (qh->type == USB_ENDPOINT_XFER_ISOC &&
  1055. urbp->node.prev == &qh->queue &&
  1056. urbp->node.next != &qh->queue) {
  1057. struct urb *nurb = list_entry(urbp->node.next,
  1058. struct urb_priv, node)->urb;
  1059. qh->iso_packet_desc = &nurb->iso_frame_desc[0];
  1060. qh->iso_frame = nurb->start_frame;
  1061. qh->iso_status = 0;
  1062. }
  1063. /* Take the URB off the QH's queue. If the queue is now empty,
  1064. * this is a perfect time for a toggle fixup. */
  1065. list_del_init(&urbp->node);
  1066. if (list_empty(&qh->queue) && qh->needs_fixup) {
  1067. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  1068. usb_pipeout(urb->pipe), qh->initial_toggle);
  1069. qh->needs_fixup = 0;
  1070. }
  1071. uhci_free_urb_priv(uhci, urbp);
  1072. switch (qh->type) {
  1073. case USB_ENDPOINT_XFER_ISOC:
  1074. /* Release bandwidth for Interrupt or Isoc. transfers */
  1075. if (urb->bandwidth)
  1076. usb_release_bandwidth(urb->dev, urb, 1);
  1077. break;
  1078. case USB_ENDPOINT_XFER_INT:
  1079. /* Release bandwidth for Interrupt or Isoc. transfers */
  1080. /* Make sure we don't release if we have a queued URB */
  1081. if (list_empty(&qh->queue) && urb->bandwidth)
  1082. usb_release_bandwidth(urb->dev, urb, 0);
  1083. else
  1084. /* bandwidth was passed on to queued URB, */
  1085. /* so don't let usb_unlink_urb() release it */
  1086. urb->bandwidth = 0;
  1087. break;
  1088. }
  1089. spin_unlock(&uhci->lock);
  1090. usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb);
  1091. spin_lock(&uhci->lock);
  1092. /* If the queue is now empty, we can unlink the QH and give up its
  1093. * reserved bandwidth. */
  1094. if (list_empty(&qh->queue)) {
  1095. uhci_unlink_qh(uhci, qh);
  1096. /* Bandwidth stuff not yet implemented */
  1097. qh->period = 0;
  1098. }
  1099. }
  1100. /*
  1101. * Scan the URBs in a QH's queue
  1102. */
  1103. #define QH_FINISHED_UNLINKING(qh) \
  1104. (qh->state == QH_STATE_UNLINKING && \
  1105. uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
  1106. static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1107. {
  1108. struct urb_priv *urbp;
  1109. struct urb *urb;
  1110. int status;
  1111. while (!list_empty(&qh->queue)) {
  1112. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1113. urb = urbp->urb;
  1114. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1115. status = uhci_result_isochronous(uhci, urb);
  1116. else
  1117. status = uhci_result_common(uhci, urb);
  1118. if (status == -EINPROGRESS)
  1119. break;
  1120. spin_lock(&urb->lock);
  1121. if (urb->status == -EINPROGRESS) /* Not dequeued */
  1122. urb->status = status;
  1123. else
  1124. status = ECONNRESET; /* Not -ECONNRESET */
  1125. spin_unlock(&urb->lock);
  1126. /* Dequeued but completed URBs can't be given back unless
  1127. * the QH is stopped or has finished unlinking. */
  1128. if (status == ECONNRESET) {
  1129. if (QH_FINISHED_UNLINKING(qh))
  1130. qh->is_stopped = 1;
  1131. else if (!qh->is_stopped)
  1132. return;
  1133. }
  1134. uhci_giveback_urb(uhci, qh, urb);
  1135. if (status < 0 && qh->type != USB_ENDPOINT_XFER_ISOC)
  1136. break;
  1137. }
  1138. /* If the QH is neither stopped nor finished unlinking (normal case),
  1139. * our work here is done. */
  1140. if (QH_FINISHED_UNLINKING(qh))
  1141. qh->is_stopped = 1;
  1142. else if (!qh->is_stopped)
  1143. return;
  1144. /* Otherwise give back each of the dequeued URBs */
  1145. restart:
  1146. list_for_each_entry(urbp, &qh->queue, node) {
  1147. urb = urbp->urb;
  1148. if (urb->status != -EINPROGRESS) {
  1149. /* Fix up the TD links and save the toggles for
  1150. * non-Isochronous queues. For Isochronous queues,
  1151. * test for too-recent dequeues. */
  1152. if (!uhci_cleanup_queue(uhci, qh, urb)) {
  1153. qh->is_stopped = 0;
  1154. return;
  1155. }
  1156. uhci_giveback_urb(uhci, qh, urb);
  1157. goto restart;
  1158. }
  1159. }
  1160. qh->is_stopped = 0;
  1161. /* There are no more dequeued URBs. If there are still URBs on the
  1162. * queue, the QH can now be re-activated. */
  1163. if (!list_empty(&qh->queue)) {
  1164. if (qh->needs_fixup)
  1165. uhci_fixup_toggles(qh, 0);
  1166. /* If the first URB on the queue wants FSBR but its time
  1167. * limit has expired, set the next TD to interrupt on
  1168. * completion before reactivating the QH. */
  1169. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1170. if (urbp->fsbr && qh->wait_expired) {
  1171. struct uhci_td *td = list_entry(urbp->td_list.next,
  1172. struct uhci_td, list);
  1173. td->status |= __cpu_to_le32(TD_CTRL_IOC);
  1174. }
  1175. uhci_activate_qh(uhci, qh);
  1176. }
  1177. /* The queue is empty. The QH can become idle if it is fully
  1178. * unlinked. */
  1179. else if (QH_FINISHED_UNLINKING(qh))
  1180. uhci_make_qh_idle(uhci, qh);
  1181. }
  1182. /*
  1183. * Check for queues that have made some forward progress.
  1184. * Returns 0 if the queue is not Isochronous, is ACTIVE, and
  1185. * has not advanced since last examined; 1 otherwise.
  1186. *
  1187. * Early Intel controllers have a bug which causes qh->element sometimes
  1188. * not to advance when a TD completes successfully. The queue remains
  1189. * stuck on the inactive completed TD. We detect such cases and advance
  1190. * the element pointer by hand.
  1191. */
  1192. static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1193. {
  1194. struct urb_priv *urbp = NULL;
  1195. struct uhci_td *td;
  1196. int ret = 1;
  1197. unsigned status;
  1198. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1199. goto done;
  1200. /* Treat an UNLINKING queue as though it hasn't advanced.
  1201. * This is okay because reactivation will treat it as though
  1202. * it has advanced, and if it is going to become IDLE then
  1203. * this doesn't matter anyway. Furthermore it's possible
  1204. * for an UNLINKING queue not to have any URBs at all, or
  1205. * for its first URB not to have any TDs (if it was dequeued
  1206. * just as it completed). So it's not easy in any case to
  1207. * test whether such queues have advanced. */
  1208. if (qh->state != QH_STATE_ACTIVE) {
  1209. urbp = NULL;
  1210. status = 0;
  1211. } else {
  1212. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1213. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  1214. status = td_status(td);
  1215. if (!(status & TD_CTRL_ACTIVE)) {
  1216. /* We're okay, the queue has advanced */
  1217. qh->wait_expired = 0;
  1218. qh->advance_jiffies = jiffies;
  1219. goto done;
  1220. }
  1221. ret = 0;
  1222. }
  1223. /* The queue hasn't advanced; check for timeout */
  1224. if (qh->wait_expired)
  1225. goto done;
  1226. if (time_after(jiffies, qh->advance_jiffies + QH_WAIT_TIMEOUT)) {
  1227. /* Detect the Intel bug and work around it */
  1228. if (qh->post_td && qh_element(qh) ==
  1229. cpu_to_le32(qh->post_td->dma_handle)) {
  1230. qh->element = qh->post_td->link;
  1231. qh->advance_jiffies = jiffies;
  1232. ret = 1;
  1233. goto done;
  1234. }
  1235. qh->wait_expired = 1;
  1236. /* If the current URB wants FSBR, unlink it temporarily
  1237. * so that we can safely set the next TD to interrupt on
  1238. * completion. That way we'll know as soon as the queue
  1239. * starts moving again. */
  1240. if (urbp && urbp->fsbr && !(status & TD_CTRL_IOC))
  1241. uhci_unlink_qh(uhci, qh);
  1242. } else {
  1243. /* Unmoving but not-yet-expired queues keep FSBR alive */
  1244. if (urbp)
  1245. uhci_urbp_wants_fsbr(uhci, urbp);
  1246. }
  1247. done:
  1248. return ret;
  1249. }
  1250. /*
  1251. * Process events in the schedule, but only in one thread at a time
  1252. */
  1253. static void uhci_scan_schedule(struct uhci_hcd *uhci)
  1254. {
  1255. int i;
  1256. struct uhci_qh *qh;
  1257. /* Don't allow re-entrant calls */
  1258. if (uhci->scan_in_progress) {
  1259. uhci->need_rescan = 1;
  1260. return;
  1261. }
  1262. uhci->scan_in_progress = 1;
  1263. rescan:
  1264. uhci->need_rescan = 0;
  1265. uhci->fsbr_is_wanted = 0;
  1266. uhci_clear_next_interrupt(uhci);
  1267. uhci_get_current_frame_number(uhci);
  1268. uhci->cur_iso_frame = uhci->frame_number;
  1269. /* Go through all the QH queues and process the URBs in each one */
  1270. for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) {
  1271. uhci->next_qh = list_entry(uhci->skelqh[i]->node.next,
  1272. struct uhci_qh, node);
  1273. while ((qh = uhci->next_qh) != uhci->skelqh[i]) {
  1274. uhci->next_qh = list_entry(qh->node.next,
  1275. struct uhci_qh, node);
  1276. if (uhci_advance_check(uhci, qh)) {
  1277. uhci_scan_qh(uhci, qh);
  1278. if (qh->state == QH_STATE_ACTIVE) {
  1279. uhci_urbp_wants_fsbr(uhci,
  1280. list_entry(qh->queue.next, struct urb_priv, node));
  1281. }
  1282. }
  1283. }
  1284. }
  1285. uhci->last_iso_frame = uhci->cur_iso_frame;
  1286. if (uhci->need_rescan)
  1287. goto rescan;
  1288. uhci->scan_in_progress = 0;
  1289. if (uhci->fsbr_is_on && !uhci->fsbr_is_wanted &&
  1290. !uhci->fsbr_expiring) {
  1291. uhci->fsbr_expiring = 1;
  1292. mod_timer(&uhci->fsbr_timer, jiffies + FSBR_OFF_DELAY);
  1293. }
  1294. if (list_empty(&uhci->skel_unlink_qh->node))
  1295. uhci_clear_next_interrupt(uhci);
  1296. else
  1297. uhci_set_next_interrupt(uhci);
  1298. }