mach_apic.h 4.2 KB

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  1. #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H
  2. #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H
  3. #ifdef CONFIG_X86_LOCAL_APIC
  4. #include <mach_apicdef.h>
  5. #include <asm/smp.h>
  6. #define APIC_DFR_VALUE (APIC_DFR_FLAT)
  7. static inline const struct cpumask *target_cpus(void)
  8. {
  9. #ifdef CONFIG_SMP
  10. return cpu_online_mask;
  11. #else
  12. return cpumask_of(0);
  13. #endif
  14. }
  15. #define NO_BALANCE_IRQ (0)
  16. #define esr_disable (0)
  17. #ifdef CONFIG_X86_64
  18. #include <asm/genapic.h>
  19. #define IRQ_DEST_MODE (apic->irq_dest_mode)
  20. #define TARGET_CPUS (apic->target_cpus())
  21. #define init_apic_ldr (apic->init_apic_ldr)
  22. #define cpu_mask_to_apicid (apic->cpu_mask_to_apicid)
  23. #define cpu_mask_to_apicid_and (apic->cpu_mask_to_apicid_and)
  24. #define phys_pkg_id (apic->phys_pkg_id)
  25. #define vector_allocation_domain (apic->vector_allocation_domain)
  26. #define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID)))
  27. #define send_IPI_self (apic->send_IPI_self)
  28. #define wakeup_secondary_cpu (apic->wakeup_cpu)
  29. extern void setup_apic_routing(void);
  30. #else
  31. #define DEFAULT_IRQ_DELIVERY_MODE dest_LowestPrio
  32. #define DEFAULT_IRQ_DEST_MODE 1 /* logical delivery broadcast to all procs */
  33. #define TARGET_CPUS (target_cpus())
  34. #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init
  35. /*
  36. * Set up the logical destination ID.
  37. *
  38. * Intel recommends to set DFR, LDR and TPR before enabling
  39. * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
  40. * document number 292116). So here it goes...
  41. */
  42. static inline void init_apic_ldr(void)
  43. {
  44. unsigned long val;
  45. apic_write(APIC_DFR, APIC_DFR_VALUE);
  46. val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  47. val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
  48. apic_write(APIC_LDR, val);
  49. }
  50. static inline int default_apic_id_registered(void)
  51. {
  52. return physid_isset(read_apic_id(), phys_cpu_present_map);
  53. }
  54. static inline unsigned int cpu_mask_to_apicid(const struct cpumask *cpumask)
  55. {
  56. return cpumask_bits(cpumask)[0];
  57. }
  58. static inline unsigned int cpu_mask_to_apicid_and(const struct cpumask *cpumask,
  59. const struct cpumask *andmask)
  60. {
  61. unsigned long mask1 = cpumask_bits(cpumask)[0];
  62. unsigned long mask2 = cpumask_bits(andmask)[0];
  63. unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
  64. return (unsigned int)(mask1 & mask2 & mask3);
  65. }
  66. static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
  67. {
  68. return cpuid_apic >> index_msb;
  69. }
  70. static inline void setup_apic_routing(void)
  71. {
  72. #ifdef CONFIG_X86_IO_APIC
  73. printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
  74. "Flat", nr_ioapics);
  75. #endif
  76. }
  77. static inline int apicid_to_node(int logical_apicid)
  78. {
  79. #ifdef CONFIG_SMP
  80. return apicid_2_node[hard_smp_processor_id()];
  81. #else
  82. return 0;
  83. #endif
  84. }
  85. static inline void vector_allocation_domain(int cpu, struct cpumask *retmask)
  86. {
  87. /* Careful. Some cpus do not strictly honor the set of cpus
  88. * specified in the interrupt destination when using lowest
  89. * priority interrupt delivery mode.
  90. *
  91. * In particular there was a hyperthreading cpu observed to
  92. * deliver interrupts to the wrong hyperthread when only one
  93. * hyperthread was specified in the interrupt desitination.
  94. */
  95. *retmask = (cpumask_t) { { [0] = APIC_ALL_CPUS } };
  96. }
  97. #endif
  98. static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
  99. {
  100. return physid_isset(apicid, bitmap);
  101. }
  102. static inline unsigned long check_apicid_present(int bit)
  103. {
  104. return physid_isset(bit, phys_cpu_present_map);
  105. }
  106. static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
  107. {
  108. return phys_map;
  109. }
  110. static inline int multi_timer_check(int apic, int irq)
  111. {
  112. return 0;
  113. }
  114. /* Mapping from cpu number to logical apicid */
  115. static inline int cpu_to_logical_apicid(int cpu)
  116. {
  117. return 1 << cpu;
  118. }
  119. static inline int cpu_present_to_apicid(int mps_cpu)
  120. {
  121. if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
  122. return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
  123. else
  124. return BAD_APICID;
  125. }
  126. static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
  127. {
  128. return physid_mask_of_physid(phys_apicid);
  129. }
  130. static inline void setup_portio_remap(void)
  131. {
  132. }
  133. static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
  134. {
  135. return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
  136. }
  137. static inline void enable_apic_mode(void)
  138. {
  139. }
  140. #endif /* CONFIG_X86_LOCAL_APIC */
  141. #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */