gsc-core.c 30 KB

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  1. /*
  2. * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * Samsung EXYNOS5 SoC series G-Scaler driver
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published
  9. * by the Free Software Foundation, either version 2 of the License,
  10. * or (at your option) any later version.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/errno.h>
  16. #include <linux/bug.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/workqueue.h>
  19. #include <linux/device.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/list.h>
  22. #include <linux/io.h>
  23. #include <linux/slab.h>
  24. #include <linux/clk.h>
  25. #include <linux/of.h>
  26. #include <media/v4l2-ioctl.h>
  27. #include "gsc-core.h"
  28. #define GSC_CLOCK_GATE_NAME "gscl"
  29. static const struct gsc_fmt gsc_formats[] = {
  30. {
  31. .name = "RGB565",
  32. .pixelformat = V4L2_PIX_FMT_RGB565X,
  33. .depth = { 16 },
  34. .color = GSC_RGB,
  35. .num_planes = 1,
  36. .num_comp = 1,
  37. }, {
  38. .name = "XRGB-8-8-8-8, 32 bpp",
  39. .pixelformat = V4L2_PIX_FMT_RGB32,
  40. .depth = { 32 },
  41. .color = GSC_RGB,
  42. .num_planes = 1,
  43. .num_comp = 1,
  44. }, {
  45. .name = "YUV 4:2:2 packed, YCbYCr",
  46. .pixelformat = V4L2_PIX_FMT_YUYV,
  47. .depth = { 16 },
  48. .color = GSC_YUV422,
  49. .yorder = GSC_LSB_Y,
  50. .corder = GSC_CBCR,
  51. .num_planes = 1,
  52. .num_comp = 1,
  53. .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
  54. }, {
  55. .name = "YUV 4:2:2 packed, CbYCrY",
  56. .pixelformat = V4L2_PIX_FMT_UYVY,
  57. .depth = { 16 },
  58. .color = GSC_YUV422,
  59. .yorder = GSC_LSB_C,
  60. .corder = GSC_CBCR,
  61. .num_planes = 1,
  62. .num_comp = 1,
  63. .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
  64. }, {
  65. .name = "YUV 4:2:2 packed, CrYCbY",
  66. .pixelformat = V4L2_PIX_FMT_VYUY,
  67. .depth = { 16 },
  68. .color = GSC_YUV422,
  69. .yorder = GSC_LSB_C,
  70. .corder = GSC_CRCB,
  71. .num_planes = 1,
  72. .num_comp = 1,
  73. .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
  74. }, {
  75. .name = "YUV 4:2:2 packed, YCrYCb",
  76. .pixelformat = V4L2_PIX_FMT_YVYU,
  77. .depth = { 16 },
  78. .color = GSC_YUV422,
  79. .yorder = GSC_LSB_Y,
  80. .corder = GSC_CRCB,
  81. .num_planes = 1,
  82. .num_comp = 1,
  83. .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
  84. }, {
  85. .name = "YUV 4:4:4 planar, YCbYCr",
  86. .pixelformat = V4L2_PIX_FMT_YUV32,
  87. .depth = { 32 },
  88. .color = GSC_YUV444,
  89. .yorder = GSC_LSB_Y,
  90. .corder = GSC_CBCR,
  91. .num_planes = 1,
  92. .num_comp = 1,
  93. }, {
  94. .name = "YUV 4:2:2 planar, Y/Cb/Cr",
  95. .pixelformat = V4L2_PIX_FMT_YUV422P,
  96. .depth = { 16 },
  97. .color = GSC_YUV422,
  98. .yorder = GSC_LSB_Y,
  99. .corder = GSC_CBCR,
  100. .num_planes = 1,
  101. .num_comp = 3,
  102. }, {
  103. .name = "YUV 4:2:2 planar, Y/CbCr",
  104. .pixelformat = V4L2_PIX_FMT_NV16,
  105. .depth = { 16 },
  106. .color = GSC_YUV422,
  107. .yorder = GSC_LSB_Y,
  108. .corder = GSC_CBCR,
  109. .num_planes = 1,
  110. .num_comp = 2,
  111. }, {
  112. .name = "YUV 4:2:2 planar, Y/CrCb",
  113. .pixelformat = V4L2_PIX_FMT_NV61,
  114. .depth = { 16 },
  115. .color = GSC_YUV422,
  116. .yorder = GSC_LSB_Y,
  117. .corder = GSC_CRCB,
  118. .num_planes = 1,
  119. .num_comp = 2,
  120. }, {
  121. .name = "YUV 4:2:0 planar, YCbCr",
  122. .pixelformat = V4L2_PIX_FMT_YUV420,
  123. .depth = { 12 },
  124. .color = GSC_YUV420,
  125. .yorder = GSC_LSB_Y,
  126. .corder = GSC_CBCR,
  127. .num_planes = 1,
  128. .num_comp = 3,
  129. }, {
  130. .name = "YUV 4:2:0 planar, YCrCb",
  131. .pixelformat = V4L2_PIX_FMT_YVU420,
  132. .depth = { 12 },
  133. .color = GSC_YUV420,
  134. .yorder = GSC_LSB_Y,
  135. .corder = GSC_CRCB,
  136. .num_planes = 1,
  137. .num_comp = 3,
  138. }, {
  139. .name = "YUV 4:2:0 planar, Y/CbCr",
  140. .pixelformat = V4L2_PIX_FMT_NV12,
  141. .depth = { 12 },
  142. .color = GSC_YUV420,
  143. .yorder = GSC_LSB_Y,
  144. .corder = GSC_CBCR,
  145. .num_planes = 1,
  146. .num_comp = 2,
  147. }, {
  148. .name = "YUV 4:2:0 planar, Y/CrCb",
  149. .pixelformat = V4L2_PIX_FMT_NV21,
  150. .depth = { 12 },
  151. .color = GSC_YUV420,
  152. .yorder = GSC_LSB_Y,
  153. .corder = GSC_CRCB,
  154. .num_planes = 1,
  155. .num_comp = 2,
  156. }, {
  157. .name = "YUV 4:2:0 non-contig. 2p, Y/CbCr",
  158. .pixelformat = V4L2_PIX_FMT_NV12M,
  159. .depth = { 8, 4 },
  160. .color = GSC_YUV420,
  161. .yorder = GSC_LSB_Y,
  162. .corder = GSC_CBCR,
  163. .num_planes = 2,
  164. .num_comp = 2,
  165. }, {
  166. .name = "YUV 4:2:0 non-contig. 3p, Y/Cb/Cr",
  167. .pixelformat = V4L2_PIX_FMT_YUV420M,
  168. .depth = { 8, 2, 2 },
  169. .color = GSC_YUV420,
  170. .yorder = GSC_LSB_Y,
  171. .corder = GSC_CBCR,
  172. .num_planes = 3,
  173. .num_comp = 3,
  174. }, {
  175. .name = "YUV 4:2:0 non-contig. 3p, Y/Cr/Cb",
  176. .pixelformat = V4L2_PIX_FMT_YVU420M,
  177. .depth = { 8, 2, 2 },
  178. .color = GSC_YUV420,
  179. .yorder = GSC_LSB_Y,
  180. .corder = GSC_CRCB,
  181. .num_planes = 3,
  182. .num_comp = 3,
  183. }
  184. };
  185. const struct gsc_fmt *get_format(int index)
  186. {
  187. if (index >= ARRAY_SIZE(gsc_formats))
  188. return NULL;
  189. return (struct gsc_fmt *)&gsc_formats[index];
  190. }
  191. const struct gsc_fmt *find_fmt(u32 *pixelformat, u32 *mbus_code, u32 index)
  192. {
  193. const struct gsc_fmt *fmt, *def_fmt = NULL;
  194. unsigned int i;
  195. if (index >= ARRAY_SIZE(gsc_formats))
  196. return NULL;
  197. for (i = 0; i < ARRAY_SIZE(gsc_formats); ++i) {
  198. fmt = get_format(i);
  199. if (pixelformat && fmt->pixelformat == *pixelformat)
  200. return fmt;
  201. if (mbus_code && fmt->mbus_code == *mbus_code)
  202. return fmt;
  203. if (index == i)
  204. def_fmt = fmt;
  205. }
  206. return def_fmt;
  207. }
  208. void gsc_set_frame_size(struct gsc_frame *frame, int width, int height)
  209. {
  210. frame->f_width = width;
  211. frame->f_height = height;
  212. frame->crop.width = width;
  213. frame->crop.height = height;
  214. frame->crop.left = 0;
  215. frame->crop.top = 0;
  216. }
  217. int gsc_cal_prescaler_ratio(struct gsc_variant *var, u32 src, u32 dst,
  218. u32 *ratio)
  219. {
  220. if ((dst > src) || (dst >= src / var->poly_sc_down_max)) {
  221. *ratio = 1;
  222. return 0;
  223. }
  224. if ((src / var->poly_sc_down_max / var->pre_sc_down_max) > dst) {
  225. pr_err("Exceeded maximum downscaling ratio (1/16))");
  226. return -EINVAL;
  227. }
  228. *ratio = (dst > (src / 8)) ? 2 : 4;
  229. return 0;
  230. }
  231. void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *sh)
  232. {
  233. if (hratio == 4 && vratio == 4)
  234. *sh = 4;
  235. else if ((hratio == 4 && vratio == 2) ||
  236. (hratio == 2 && vratio == 4))
  237. *sh = 3;
  238. else if ((hratio == 4 && vratio == 1) ||
  239. (hratio == 1 && vratio == 4) ||
  240. (hratio == 2 && vratio == 2))
  241. *sh = 2;
  242. else if (hratio == 1 && vratio == 1)
  243. *sh = 0;
  244. else
  245. *sh = 1;
  246. }
  247. void gsc_check_src_scale_info(struct gsc_variant *var,
  248. struct gsc_frame *s_frame, u32 *wratio,
  249. u32 tx, u32 ty, u32 *hratio)
  250. {
  251. int remainder = 0, walign, halign;
  252. if (is_yuv420(s_frame->fmt->color)) {
  253. walign = GSC_SC_ALIGN_4;
  254. halign = GSC_SC_ALIGN_4;
  255. } else if (is_yuv422(s_frame->fmt->color)) {
  256. walign = GSC_SC_ALIGN_4;
  257. halign = GSC_SC_ALIGN_2;
  258. } else {
  259. walign = GSC_SC_ALIGN_2;
  260. halign = GSC_SC_ALIGN_2;
  261. }
  262. remainder = s_frame->crop.width % (*wratio * walign);
  263. if (remainder) {
  264. s_frame->crop.width -= remainder;
  265. gsc_cal_prescaler_ratio(var, s_frame->crop.width, tx, wratio);
  266. pr_info("cropped src width size is recalculated from %d to %d",
  267. s_frame->crop.width + remainder, s_frame->crop.width);
  268. }
  269. remainder = s_frame->crop.height % (*hratio * halign);
  270. if (remainder) {
  271. s_frame->crop.height -= remainder;
  272. gsc_cal_prescaler_ratio(var, s_frame->crop.height, ty, hratio);
  273. pr_info("cropped src height size is recalculated from %d to %d",
  274. s_frame->crop.height + remainder, s_frame->crop.height);
  275. }
  276. }
  277. int gsc_enum_fmt_mplane(struct v4l2_fmtdesc *f)
  278. {
  279. const struct gsc_fmt *fmt;
  280. fmt = find_fmt(NULL, NULL, f->index);
  281. if (!fmt)
  282. return -EINVAL;
  283. strlcpy(f->description, fmt->name, sizeof(f->description));
  284. f->pixelformat = fmt->pixelformat;
  285. return 0;
  286. }
  287. u32 get_plane_info(struct gsc_frame *frm, u32 addr, u32 *index)
  288. {
  289. if (frm->addr.y == addr) {
  290. *index = 0;
  291. return frm->addr.y;
  292. } else if (frm->addr.cb == addr) {
  293. *index = 1;
  294. return frm->addr.cb;
  295. } else if (frm->addr.cr == addr) {
  296. *index = 2;
  297. return frm->addr.cr;
  298. } else {
  299. pr_err("Plane address is wrong");
  300. return -EINVAL;
  301. }
  302. }
  303. void gsc_set_prefbuf(struct gsc_dev *gsc, struct gsc_frame *frm)
  304. {
  305. u32 f_chk_addr, f_chk_len, s_chk_addr, s_chk_len;
  306. f_chk_addr = f_chk_len = s_chk_addr = s_chk_len = 0;
  307. f_chk_addr = frm->addr.y;
  308. f_chk_len = frm->payload[0];
  309. if (frm->fmt->num_planes == 2) {
  310. s_chk_addr = frm->addr.cb;
  311. s_chk_len = frm->payload[1];
  312. } else if (frm->fmt->num_planes == 3) {
  313. u32 low_addr, low_plane, mid_addr, mid_plane;
  314. u32 high_addr, high_plane;
  315. u32 t_min, t_max;
  316. t_min = min3(frm->addr.y, frm->addr.cb, frm->addr.cr);
  317. low_addr = get_plane_info(frm, t_min, &low_plane);
  318. t_max = max3(frm->addr.y, frm->addr.cb, frm->addr.cr);
  319. high_addr = get_plane_info(frm, t_max, &high_plane);
  320. mid_plane = 3 - (low_plane + high_plane);
  321. if (mid_plane == 0)
  322. mid_addr = frm->addr.y;
  323. else if (mid_plane == 1)
  324. mid_addr = frm->addr.cb;
  325. else if (mid_plane == 2)
  326. mid_addr = frm->addr.cr;
  327. else
  328. return;
  329. f_chk_addr = low_addr;
  330. if (mid_addr + frm->payload[mid_plane] - low_addr >
  331. high_addr + frm->payload[high_plane] - mid_addr) {
  332. f_chk_len = frm->payload[low_plane];
  333. s_chk_addr = mid_addr;
  334. s_chk_len = high_addr +
  335. frm->payload[high_plane] - mid_addr;
  336. } else {
  337. f_chk_len = mid_addr +
  338. frm->payload[mid_plane] - low_addr;
  339. s_chk_addr = high_addr;
  340. s_chk_len = frm->payload[high_plane];
  341. }
  342. }
  343. pr_debug("f_addr = 0x%08x, f_len = %d, s_addr = 0x%08x, s_len = %d\n",
  344. f_chk_addr, f_chk_len, s_chk_addr, s_chk_len);
  345. }
  346. int gsc_try_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f)
  347. {
  348. struct gsc_dev *gsc = ctx->gsc_dev;
  349. struct gsc_variant *variant = gsc->variant;
  350. struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
  351. const struct gsc_fmt *fmt;
  352. u32 max_w, max_h, mod_x, mod_y;
  353. u32 min_w, min_h, tmp_w, tmp_h;
  354. int i;
  355. pr_debug("user put w: %d, h: %d", pix_mp->width, pix_mp->height);
  356. fmt = find_fmt(&pix_mp->pixelformat, NULL, 0);
  357. if (!fmt) {
  358. pr_err("pixelformat format (0x%X) invalid\n",
  359. pix_mp->pixelformat);
  360. return -EINVAL;
  361. }
  362. if (pix_mp->field == V4L2_FIELD_ANY)
  363. pix_mp->field = V4L2_FIELD_NONE;
  364. else if (pix_mp->field != V4L2_FIELD_NONE) {
  365. pr_err("Not supported field order(%d)\n", pix_mp->field);
  366. return -EINVAL;
  367. }
  368. max_w = variant->pix_max->target_rot_dis_w;
  369. max_h = variant->pix_max->target_rot_dis_h;
  370. mod_x = ffs(variant->pix_align->org_w) - 1;
  371. if (is_yuv420(fmt->color))
  372. mod_y = ffs(variant->pix_align->org_h) - 1;
  373. else
  374. mod_y = ffs(variant->pix_align->org_h) - 2;
  375. if (V4L2_TYPE_IS_OUTPUT(f->type)) {
  376. min_w = variant->pix_min->org_w;
  377. min_h = variant->pix_min->org_h;
  378. } else {
  379. min_w = variant->pix_min->target_rot_dis_w;
  380. min_h = variant->pix_min->target_rot_dis_h;
  381. }
  382. pr_debug("mod_x: %d, mod_y: %d, max_w: %d, max_h = %d",
  383. mod_x, mod_y, max_w, max_h);
  384. /* To check if image size is modified to adjust parameter against
  385. hardware abilities */
  386. tmp_w = pix_mp->width;
  387. tmp_h = pix_mp->height;
  388. v4l_bound_align_image(&pix_mp->width, min_w, max_w, mod_x,
  389. &pix_mp->height, min_h, max_h, mod_y, 0);
  390. if (tmp_w != pix_mp->width || tmp_h != pix_mp->height)
  391. pr_info("Image size has been modified from %dx%d to %dx%d",
  392. tmp_w, tmp_h, pix_mp->width, pix_mp->height);
  393. pix_mp->num_planes = fmt->num_planes;
  394. if (pix_mp->width >= 1280) /* HD */
  395. pix_mp->colorspace = V4L2_COLORSPACE_REC709;
  396. else /* SD */
  397. pix_mp->colorspace = V4L2_COLORSPACE_SMPTE170M;
  398. for (i = 0; i < pix_mp->num_planes; ++i) {
  399. int bpl = (pix_mp->width * fmt->depth[i]) >> 3;
  400. pix_mp->plane_fmt[i].bytesperline = bpl;
  401. pix_mp->plane_fmt[i].sizeimage = bpl * pix_mp->height;
  402. pr_debug("[%d]: bpl: %d, sizeimage: %d",
  403. i, bpl, pix_mp->plane_fmt[i].sizeimage);
  404. }
  405. return 0;
  406. }
  407. int gsc_g_fmt_mplane(struct gsc_ctx *ctx, struct v4l2_format *f)
  408. {
  409. struct gsc_frame *frame;
  410. struct v4l2_pix_format_mplane *pix_mp;
  411. int i;
  412. frame = ctx_get_frame(ctx, f->type);
  413. if (IS_ERR(frame))
  414. return PTR_ERR(frame);
  415. pix_mp = &f->fmt.pix_mp;
  416. pix_mp->width = frame->f_width;
  417. pix_mp->height = frame->f_height;
  418. pix_mp->field = V4L2_FIELD_NONE;
  419. pix_mp->pixelformat = frame->fmt->pixelformat;
  420. pix_mp->colorspace = V4L2_COLORSPACE_REC709;
  421. pix_mp->num_planes = frame->fmt->num_planes;
  422. for (i = 0; i < pix_mp->num_planes; ++i) {
  423. pix_mp->plane_fmt[i].bytesperline = (frame->f_width *
  424. frame->fmt->depth[i]) / 8;
  425. pix_mp->plane_fmt[i].sizeimage =
  426. pix_mp->plane_fmt[i].bytesperline * frame->f_height;
  427. }
  428. return 0;
  429. }
  430. void gsc_check_crop_change(u32 tmp_w, u32 tmp_h, u32 *w, u32 *h)
  431. {
  432. if (tmp_w != *w || tmp_h != *h) {
  433. pr_info("Cropped size has been modified from %dx%d to %dx%d",
  434. *w, *h, tmp_w, tmp_h);
  435. *w = tmp_w;
  436. *h = tmp_h;
  437. }
  438. }
  439. int gsc_g_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr)
  440. {
  441. struct gsc_frame *frame;
  442. frame = ctx_get_frame(ctx, cr->type);
  443. if (IS_ERR(frame))
  444. return PTR_ERR(frame);
  445. cr->c = frame->crop;
  446. return 0;
  447. }
  448. int gsc_try_crop(struct gsc_ctx *ctx, struct v4l2_crop *cr)
  449. {
  450. struct gsc_frame *f;
  451. struct gsc_dev *gsc = ctx->gsc_dev;
  452. struct gsc_variant *variant = gsc->variant;
  453. u32 mod_x = 0, mod_y = 0, tmp_w, tmp_h;
  454. u32 min_w, min_h, max_w, max_h;
  455. if (cr->c.top < 0 || cr->c.left < 0) {
  456. pr_err("doesn't support negative values for top & left\n");
  457. return -EINVAL;
  458. }
  459. pr_debug("user put w: %d, h: %d", cr->c.width, cr->c.height);
  460. if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
  461. f = &ctx->d_frame;
  462. else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
  463. f = &ctx->s_frame;
  464. else
  465. return -EINVAL;
  466. max_w = f->f_width;
  467. max_h = f->f_height;
  468. tmp_w = cr->c.width;
  469. tmp_h = cr->c.height;
  470. if (V4L2_TYPE_IS_OUTPUT(cr->type)) {
  471. if ((is_yuv422(f->fmt->color) && f->fmt->num_comp == 1) ||
  472. is_rgb(f->fmt->color))
  473. min_w = 32;
  474. else
  475. min_w = 64;
  476. if ((is_yuv422(f->fmt->color) && f->fmt->num_comp == 3) ||
  477. is_yuv420(f->fmt->color))
  478. min_h = 32;
  479. else
  480. min_h = 16;
  481. } else {
  482. if (is_yuv420(f->fmt->color) || is_yuv422(f->fmt->color))
  483. mod_x = ffs(variant->pix_align->target_w) - 1;
  484. if (is_yuv420(f->fmt->color))
  485. mod_y = ffs(variant->pix_align->target_h) - 1;
  486. if (ctx->gsc_ctrls.rotate->val == 90 ||
  487. ctx->gsc_ctrls.rotate->val == 270) {
  488. max_w = f->f_height;
  489. max_h = f->f_width;
  490. min_w = variant->pix_min->target_rot_en_w;
  491. min_h = variant->pix_min->target_rot_en_h;
  492. tmp_w = cr->c.height;
  493. tmp_h = cr->c.width;
  494. } else {
  495. min_w = variant->pix_min->target_rot_dis_w;
  496. min_h = variant->pix_min->target_rot_dis_h;
  497. }
  498. }
  499. pr_debug("mod_x: %d, mod_y: %d, min_w: %d, min_h = %d",
  500. mod_x, mod_y, min_w, min_h);
  501. pr_debug("tmp_w : %d, tmp_h : %d", tmp_w, tmp_h);
  502. v4l_bound_align_image(&tmp_w, min_w, max_w, mod_x,
  503. &tmp_h, min_h, max_h, mod_y, 0);
  504. if (!V4L2_TYPE_IS_OUTPUT(cr->type) &&
  505. (ctx->gsc_ctrls.rotate->val == 90 ||
  506. ctx->gsc_ctrls.rotate->val == 270))
  507. gsc_check_crop_change(tmp_h, tmp_w,
  508. &cr->c.width, &cr->c.height);
  509. else
  510. gsc_check_crop_change(tmp_w, tmp_h,
  511. &cr->c.width, &cr->c.height);
  512. /* adjust left/top if cropping rectangle is out of bounds */
  513. /* Need to add code to algin left value with 2's multiple */
  514. if (cr->c.left + tmp_w > max_w)
  515. cr->c.left = max_w - tmp_w;
  516. if (cr->c.top + tmp_h > max_h)
  517. cr->c.top = max_h - tmp_h;
  518. if ((is_yuv420(f->fmt->color) || is_yuv422(f->fmt->color)) &&
  519. cr->c.left & 1)
  520. cr->c.left -= 1;
  521. pr_debug("Aligned l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
  522. cr->c.left, cr->c.top, cr->c.width, cr->c.height, max_w, max_h);
  523. return 0;
  524. }
  525. int gsc_check_scaler_ratio(struct gsc_variant *var, int sw, int sh, int dw,
  526. int dh, int rot, int out_path)
  527. {
  528. int tmp_w, tmp_h, sc_down_max;
  529. if (out_path == GSC_DMA)
  530. sc_down_max = var->sc_down_max;
  531. else
  532. sc_down_max = var->local_sc_down;
  533. if (rot == 90 || rot == 270) {
  534. tmp_w = dh;
  535. tmp_h = dw;
  536. } else {
  537. tmp_w = dw;
  538. tmp_h = dh;
  539. }
  540. if ((sw / tmp_w) > sc_down_max ||
  541. (sh / tmp_h) > sc_down_max ||
  542. (tmp_w / sw) > var->sc_up_max ||
  543. (tmp_h / sh) > var->sc_up_max)
  544. return -EINVAL;
  545. return 0;
  546. }
  547. int gsc_set_scaler_info(struct gsc_ctx *ctx)
  548. {
  549. struct gsc_scaler *sc = &ctx->scaler;
  550. struct gsc_frame *s_frame = &ctx->s_frame;
  551. struct gsc_frame *d_frame = &ctx->d_frame;
  552. struct gsc_variant *variant = ctx->gsc_dev->variant;
  553. struct device *dev = &ctx->gsc_dev->pdev->dev;
  554. int tx, ty;
  555. int ret;
  556. ret = gsc_check_scaler_ratio(variant, s_frame->crop.width,
  557. s_frame->crop.height, d_frame->crop.width, d_frame->crop.height,
  558. ctx->gsc_ctrls.rotate->val, ctx->out_path);
  559. if (ret) {
  560. pr_err("out of scaler range");
  561. return ret;
  562. }
  563. if (ctx->gsc_ctrls.rotate->val == 90 ||
  564. ctx->gsc_ctrls.rotate->val == 270) {
  565. ty = d_frame->crop.width;
  566. tx = d_frame->crop.height;
  567. } else {
  568. tx = d_frame->crop.width;
  569. ty = d_frame->crop.height;
  570. }
  571. if (tx <= 0 || ty <= 0) {
  572. dev_err(dev, "Invalid target size: %dx%d", tx, ty);
  573. return -EINVAL;
  574. }
  575. ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.width,
  576. tx, &sc->pre_hratio);
  577. if (ret) {
  578. pr_err("Horizontal scale ratio is out of range");
  579. return ret;
  580. }
  581. ret = gsc_cal_prescaler_ratio(variant, s_frame->crop.height,
  582. ty, &sc->pre_vratio);
  583. if (ret) {
  584. pr_err("Vertical scale ratio is out of range");
  585. return ret;
  586. }
  587. gsc_check_src_scale_info(variant, s_frame, &sc->pre_hratio,
  588. tx, ty, &sc->pre_vratio);
  589. gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
  590. &sc->pre_shfactor);
  591. sc->main_hratio = (s_frame->crop.width << 16) / tx;
  592. sc->main_vratio = (s_frame->crop.height << 16) / ty;
  593. pr_debug("scaler input/output size : sx = %d, sy = %d, tx = %d, ty = %d",
  594. s_frame->crop.width, s_frame->crop.height, tx, ty);
  595. pr_debug("scaler ratio info : pre_shfactor : %d, pre_h : %d",
  596. sc->pre_shfactor, sc->pre_hratio);
  597. pr_debug("pre_v :%d, main_h : %d, main_v : %d",
  598. sc->pre_vratio, sc->main_hratio, sc->main_vratio);
  599. return 0;
  600. }
  601. static int __gsc_s_ctrl(struct gsc_ctx *ctx, struct v4l2_ctrl *ctrl)
  602. {
  603. struct gsc_dev *gsc = ctx->gsc_dev;
  604. struct gsc_variant *variant = gsc->variant;
  605. unsigned int flags = GSC_DST_FMT | GSC_SRC_FMT;
  606. int ret = 0;
  607. if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
  608. return 0;
  609. switch (ctrl->id) {
  610. case V4L2_CID_HFLIP:
  611. ctx->hflip = ctrl->val;
  612. break;
  613. case V4L2_CID_VFLIP:
  614. ctx->vflip = ctrl->val;
  615. break;
  616. case V4L2_CID_ROTATE:
  617. if ((ctx->state & flags) == flags) {
  618. ret = gsc_check_scaler_ratio(variant,
  619. ctx->s_frame.crop.width,
  620. ctx->s_frame.crop.height,
  621. ctx->d_frame.crop.width,
  622. ctx->d_frame.crop.height,
  623. ctx->gsc_ctrls.rotate->val,
  624. ctx->out_path);
  625. if (ret)
  626. return -EINVAL;
  627. }
  628. ctx->rotation = ctrl->val;
  629. break;
  630. case V4L2_CID_ALPHA_COMPONENT:
  631. ctx->d_frame.alpha = ctrl->val;
  632. break;
  633. }
  634. ctx->state |= GSC_PARAMS;
  635. return 0;
  636. }
  637. static int gsc_s_ctrl(struct v4l2_ctrl *ctrl)
  638. {
  639. struct gsc_ctx *ctx = ctrl_to_ctx(ctrl);
  640. unsigned long flags;
  641. int ret;
  642. spin_lock_irqsave(&ctx->gsc_dev->slock, flags);
  643. ret = __gsc_s_ctrl(ctx, ctrl);
  644. spin_unlock_irqrestore(&ctx->gsc_dev->slock, flags);
  645. return ret;
  646. }
  647. const struct v4l2_ctrl_ops gsc_ctrl_ops = {
  648. .s_ctrl = gsc_s_ctrl,
  649. };
  650. int gsc_ctrls_create(struct gsc_ctx *ctx)
  651. {
  652. if (ctx->ctrls_rdy) {
  653. pr_err("Control handler of this context was created already");
  654. return 0;
  655. }
  656. v4l2_ctrl_handler_init(&ctx->ctrl_handler, GSC_MAX_CTRL_NUM);
  657. ctx->gsc_ctrls.rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler,
  658. &gsc_ctrl_ops, V4L2_CID_ROTATE, 0, 270, 90, 0);
  659. ctx->gsc_ctrls.hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler,
  660. &gsc_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
  661. ctx->gsc_ctrls.vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler,
  662. &gsc_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
  663. ctx->gsc_ctrls.global_alpha = v4l2_ctrl_new_std(&ctx->ctrl_handler,
  664. &gsc_ctrl_ops, V4L2_CID_ALPHA_COMPONENT, 0, 255, 1, 0);
  665. ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
  666. if (ctx->ctrl_handler.error) {
  667. int err = ctx->ctrl_handler.error;
  668. v4l2_ctrl_handler_free(&ctx->ctrl_handler);
  669. pr_err("Failed to create G-Scaler control handlers");
  670. return err;
  671. }
  672. return 0;
  673. }
  674. void gsc_ctrls_delete(struct gsc_ctx *ctx)
  675. {
  676. if (ctx->ctrls_rdy) {
  677. v4l2_ctrl_handler_free(&ctx->ctrl_handler);
  678. ctx->ctrls_rdy = false;
  679. }
  680. }
  681. /* The color format (num_comp, num_planes) must be already configured. */
  682. int gsc_prepare_addr(struct gsc_ctx *ctx, struct vb2_buffer *vb,
  683. struct gsc_frame *frame, struct gsc_addr *addr)
  684. {
  685. int ret = 0;
  686. u32 pix_size;
  687. if ((vb == NULL) || (frame == NULL))
  688. return -EINVAL;
  689. pix_size = frame->f_width * frame->f_height;
  690. pr_debug("num_planes= %d, num_comp= %d, pix_size= %d",
  691. frame->fmt->num_planes, frame->fmt->num_comp, pix_size);
  692. addr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
  693. if (frame->fmt->num_planes == 1) {
  694. switch (frame->fmt->num_comp) {
  695. case 1:
  696. addr->cb = 0;
  697. addr->cr = 0;
  698. break;
  699. case 2:
  700. /* decompose Y into Y/Cb */
  701. addr->cb = (dma_addr_t)(addr->y + pix_size);
  702. addr->cr = 0;
  703. break;
  704. case 3:
  705. /* decompose Y into Y/Cb/Cr */
  706. addr->cb = (dma_addr_t)(addr->y + pix_size);
  707. if (GSC_YUV420 == frame->fmt->color)
  708. addr->cr = (dma_addr_t)(addr->cb
  709. + (pix_size >> 2));
  710. else /* 422 */
  711. addr->cr = (dma_addr_t)(addr->cb
  712. + (pix_size >> 1));
  713. break;
  714. default:
  715. pr_err("Invalid the number of color planes");
  716. return -EINVAL;
  717. }
  718. } else {
  719. if (frame->fmt->num_planes >= 2)
  720. addr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
  721. if (frame->fmt->num_planes == 3)
  722. addr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
  723. }
  724. if ((frame->fmt->pixelformat == V4L2_PIX_FMT_VYUY) ||
  725. (frame->fmt->pixelformat == V4L2_PIX_FMT_YVYU) ||
  726. (frame->fmt->pixelformat == V4L2_PIX_FMT_NV61) ||
  727. (frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420) ||
  728. (frame->fmt->pixelformat == V4L2_PIX_FMT_NV21) ||
  729. (frame->fmt->pixelformat == V4L2_PIX_FMT_YVU420M))
  730. swap(addr->cb, addr->cr);
  731. pr_debug("ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
  732. addr->y, addr->cb, addr->cr, ret);
  733. return ret;
  734. }
  735. static irqreturn_t gsc_irq_handler(int irq, void *priv)
  736. {
  737. struct gsc_dev *gsc = priv;
  738. struct gsc_ctx *ctx;
  739. int gsc_irq;
  740. gsc_irq = gsc_hw_get_irq_status(gsc);
  741. gsc_hw_clear_irq(gsc, gsc_irq);
  742. if (gsc_irq == GSC_IRQ_OVERRUN) {
  743. pr_err("Local path input over-run interrupt has occurred!\n");
  744. return IRQ_HANDLED;
  745. }
  746. spin_lock(&gsc->slock);
  747. if (test_and_clear_bit(ST_M2M_PEND, &gsc->state)) {
  748. gsc_hw_enable_control(gsc, false);
  749. if (test_and_clear_bit(ST_M2M_SUSPENDING, &gsc->state)) {
  750. set_bit(ST_M2M_SUSPENDED, &gsc->state);
  751. wake_up(&gsc->irq_queue);
  752. goto isr_unlock;
  753. }
  754. ctx = v4l2_m2m_get_curr_priv(gsc->m2m.m2m_dev);
  755. if (!ctx || !ctx->m2m_ctx)
  756. goto isr_unlock;
  757. spin_unlock(&gsc->slock);
  758. gsc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
  759. /* wake_up job_abort, stop_streaming */
  760. if (ctx->state & GSC_CTX_STOP_REQ) {
  761. ctx->state &= ~GSC_CTX_STOP_REQ;
  762. wake_up(&gsc->irq_queue);
  763. }
  764. return IRQ_HANDLED;
  765. }
  766. isr_unlock:
  767. spin_unlock(&gsc->slock);
  768. return IRQ_HANDLED;
  769. }
  770. static struct gsc_pix_max gsc_v_100_max = {
  771. .org_scaler_bypass_w = 8192,
  772. .org_scaler_bypass_h = 8192,
  773. .org_scaler_input_w = 4800,
  774. .org_scaler_input_h = 3344,
  775. .real_rot_dis_w = 4800,
  776. .real_rot_dis_h = 3344,
  777. .real_rot_en_w = 2047,
  778. .real_rot_en_h = 2047,
  779. .target_rot_dis_w = 4800,
  780. .target_rot_dis_h = 3344,
  781. .target_rot_en_w = 2016,
  782. .target_rot_en_h = 2016,
  783. };
  784. static struct gsc_pix_min gsc_v_100_min = {
  785. .org_w = 64,
  786. .org_h = 32,
  787. .real_w = 64,
  788. .real_h = 32,
  789. .target_rot_dis_w = 64,
  790. .target_rot_dis_h = 32,
  791. .target_rot_en_w = 32,
  792. .target_rot_en_h = 16,
  793. };
  794. static struct gsc_pix_align gsc_v_100_align = {
  795. .org_h = 16,
  796. .org_w = 16, /* yuv420 : 16, others : 8 */
  797. .offset_h = 2, /* yuv420/422 : 2, others : 1 */
  798. .real_w = 16, /* yuv420/422 : 4~16, others : 2~8 */
  799. .real_h = 16, /* yuv420 : 4~16, others : 1 */
  800. .target_w = 2, /* yuv420/422 : 2, others : 1 */
  801. .target_h = 2, /* yuv420 : 2, others : 1 */
  802. };
  803. static struct gsc_variant gsc_v_100_variant = {
  804. .pix_max = &gsc_v_100_max,
  805. .pix_min = &gsc_v_100_min,
  806. .pix_align = &gsc_v_100_align,
  807. .in_buf_cnt = 8,
  808. .out_buf_cnt = 16,
  809. .sc_up_max = 8,
  810. .sc_down_max = 16,
  811. .poly_sc_down_max = 4,
  812. .pre_sc_down_max = 4,
  813. .local_sc_down = 2,
  814. };
  815. static struct gsc_driverdata gsc_v_100_drvdata = {
  816. .variant = {
  817. [0] = &gsc_v_100_variant,
  818. [1] = &gsc_v_100_variant,
  819. [2] = &gsc_v_100_variant,
  820. [3] = &gsc_v_100_variant,
  821. },
  822. .num_entities = 4,
  823. .lclk_frequency = 266000000UL,
  824. };
  825. static struct platform_device_id gsc_driver_ids[] = {
  826. {
  827. .name = "exynos-gsc",
  828. .driver_data = (unsigned long)&gsc_v_100_drvdata,
  829. },
  830. {},
  831. };
  832. MODULE_DEVICE_TABLE(platform, gsc_driver_ids);
  833. static const struct of_device_id exynos_gsc_match[] = {
  834. { .compatible = "samsung,exynos5250-gsc",
  835. .data = &gsc_v_100_drvdata, },
  836. {},
  837. };
  838. MODULE_DEVICE_TABLE(of, exynos_gsc_match);
  839. static void *gsc_get_drv_data(struct platform_device *pdev)
  840. {
  841. struct gsc_driverdata *driver_data = NULL;
  842. if (pdev->dev.of_node) {
  843. const struct of_device_id *match;
  844. match = of_match_node(of_match_ptr(exynos_gsc_match),
  845. pdev->dev.of_node);
  846. if (match)
  847. driver_data = match->data;
  848. } else {
  849. driver_data = (struct gsc_driverdata *)
  850. platform_get_device_id(pdev)->driver_data;
  851. }
  852. return driver_data;
  853. }
  854. static void gsc_clk_put(struct gsc_dev *gsc)
  855. {
  856. if (IS_ERR_OR_NULL(gsc->clock))
  857. return;
  858. clk_unprepare(gsc->clock);
  859. clk_put(gsc->clock);
  860. gsc->clock = NULL;
  861. }
  862. static int gsc_clk_get(struct gsc_dev *gsc)
  863. {
  864. int ret;
  865. dev_dbg(&gsc->pdev->dev, "gsc_clk_get Called\n");
  866. gsc->clock = clk_get(&gsc->pdev->dev, GSC_CLOCK_GATE_NAME);
  867. if (IS_ERR(gsc->clock))
  868. goto err_print;
  869. ret = clk_prepare(gsc->clock);
  870. if (ret < 0) {
  871. clk_put(gsc->clock);
  872. gsc->clock = NULL;
  873. goto err;
  874. }
  875. return 0;
  876. err:
  877. dev_err(&gsc->pdev->dev, "clock prepare failed for clock: %s\n",
  878. GSC_CLOCK_GATE_NAME);
  879. gsc_clk_put(gsc);
  880. err_print:
  881. dev_err(&gsc->pdev->dev, "failed to get clock~~~: %s\n",
  882. GSC_CLOCK_GATE_NAME);
  883. return -ENXIO;
  884. }
  885. static int gsc_m2m_suspend(struct gsc_dev *gsc)
  886. {
  887. unsigned long flags;
  888. int timeout;
  889. spin_lock_irqsave(&gsc->slock, flags);
  890. if (!gsc_m2m_pending(gsc)) {
  891. spin_unlock_irqrestore(&gsc->slock, flags);
  892. return 0;
  893. }
  894. clear_bit(ST_M2M_SUSPENDED, &gsc->state);
  895. set_bit(ST_M2M_SUSPENDING, &gsc->state);
  896. spin_unlock_irqrestore(&gsc->slock, flags);
  897. timeout = wait_event_timeout(gsc->irq_queue,
  898. test_bit(ST_M2M_SUSPENDED, &gsc->state),
  899. GSC_SHUTDOWN_TIMEOUT);
  900. clear_bit(ST_M2M_SUSPENDING, &gsc->state);
  901. return timeout == 0 ? -EAGAIN : 0;
  902. }
  903. static int gsc_m2m_resume(struct gsc_dev *gsc)
  904. {
  905. unsigned long flags;
  906. spin_lock_irqsave(&gsc->slock, flags);
  907. /* Clear for full H/W setup in first run after resume */
  908. gsc->m2m.ctx = NULL;
  909. spin_unlock_irqrestore(&gsc->slock, flags);
  910. if (test_and_clear_bit(ST_M2M_SUSPENDED, &gsc->state))
  911. gsc_m2m_job_finish(gsc->m2m.ctx,
  912. VB2_BUF_STATE_ERROR);
  913. return 0;
  914. }
  915. static int gsc_probe(struct platform_device *pdev)
  916. {
  917. struct gsc_dev *gsc;
  918. struct resource *res;
  919. struct gsc_driverdata *drv_data = gsc_get_drv_data(pdev);
  920. struct device *dev = &pdev->dev;
  921. int ret = 0;
  922. gsc = devm_kzalloc(dev, sizeof(struct gsc_dev), GFP_KERNEL);
  923. if (!gsc)
  924. return -ENOMEM;
  925. if (dev->of_node)
  926. gsc->id = of_alias_get_id(pdev->dev.of_node, "gsc");
  927. else
  928. gsc->id = pdev->id;
  929. if (gsc->id < 0 || gsc->id >= drv_data->num_entities) {
  930. dev_err(dev, "Invalid platform device id: %d\n", gsc->id);
  931. return -EINVAL;
  932. }
  933. gsc->variant = drv_data->variant[gsc->id];
  934. gsc->pdev = pdev;
  935. gsc->pdata = dev->platform_data;
  936. init_waitqueue_head(&gsc->irq_queue);
  937. spin_lock_init(&gsc->slock);
  938. mutex_init(&gsc->lock);
  939. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  940. gsc->regs = devm_request_and_ioremap(dev, res);
  941. if (!gsc->regs) {
  942. dev_err(dev, "failed to map registers\n");
  943. return -ENOENT;
  944. }
  945. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  946. if (!res) {
  947. dev_err(dev, "failed to get IRQ resource\n");
  948. return -ENXIO;
  949. }
  950. ret = gsc_clk_get(gsc);
  951. if (ret)
  952. return ret;
  953. ret = devm_request_irq(dev, res->start, gsc_irq_handler,
  954. 0, pdev->name, gsc);
  955. if (ret) {
  956. dev_err(dev, "failed to install irq (%d)\n", ret);
  957. goto err_clk;
  958. }
  959. ret = gsc_register_m2m_device(gsc);
  960. if (ret)
  961. goto err_clk;
  962. platform_set_drvdata(pdev, gsc);
  963. pm_runtime_enable(dev);
  964. ret = pm_runtime_get_sync(&pdev->dev);
  965. if (ret < 0)
  966. goto err_m2m;
  967. /* Initialize continious memory allocator */
  968. gsc->alloc_ctx = vb2_dma_contig_init_ctx(dev);
  969. if (IS_ERR(gsc->alloc_ctx)) {
  970. ret = PTR_ERR(gsc->alloc_ctx);
  971. goto err_pm;
  972. }
  973. dev_dbg(dev, "gsc-%d registered successfully\n", gsc->id);
  974. pm_runtime_put(dev);
  975. return 0;
  976. err_pm:
  977. pm_runtime_put(dev);
  978. err_m2m:
  979. gsc_unregister_m2m_device(gsc);
  980. err_clk:
  981. gsc_clk_put(gsc);
  982. return ret;
  983. }
  984. static int __devexit gsc_remove(struct platform_device *pdev)
  985. {
  986. struct gsc_dev *gsc = platform_get_drvdata(pdev);
  987. gsc_unregister_m2m_device(gsc);
  988. vb2_dma_contig_cleanup_ctx(gsc->alloc_ctx);
  989. pm_runtime_disable(&pdev->dev);
  990. dev_dbg(&pdev->dev, "%s driver unloaded\n", pdev->name);
  991. return 0;
  992. }
  993. static int gsc_runtime_resume(struct device *dev)
  994. {
  995. struct gsc_dev *gsc = dev_get_drvdata(dev);
  996. int ret = 0;
  997. pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
  998. ret = clk_enable(gsc->clock);
  999. if (ret)
  1000. return ret;
  1001. gsc_hw_set_sw_reset(gsc);
  1002. gsc_wait_reset(gsc);
  1003. return gsc_m2m_resume(gsc);
  1004. }
  1005. static int gsc_runtime_suspend(struct device *dev)
  1006. {
  1007. struct gsc_dev *gsc = dev_get_drvdata(dev);
  1008. int ret = 0;
  1009. ret = gsc_m2m_suspend(gsc);
  1010. if (!ret)
  1011. clk_disable(gsc->clock);
  1012. pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
  1013. return ret;
  1014. }
  1015. static int gsc_resume(struct device *dev)
  1016. {
  1017. struct gsc_dev *gsc = dev_get_drvdata(dev);
  1018. unsigned long flags;
  1019. pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
  1020. /* Do not resume if the device was idle before system suspend */
  1021. spin_lock_irqsave(&gsc->slock, flags);
  1022. if (!test_and_clear_bit(ST_SUSPEND, &gsc->state) ||
  1023. !gsc_m2m_active(gsc)) {
  1024. spin_unlock_irqrestore(&gsc->slock, flags);
  1025. return 0;
  1026. }
  1027. gsc_hw_set_sw_reset(gsc);
  1028. gsc_wait_reset(gsc);
  1029. spin_unlock_irqrestore(&gsc->slock, flags);
  1030. return gsc_m2m_resume(gsc);
  1031. }
  1032. static int gsc_suspend(struct device *dev)
  1033. {
  1034. struct gsc_dev *gsc = dev_get_drvdata(dev);
  1035. pr_debug("gsc%d: state: 0x%lx", gsc->id, gsc->state);
  1036. if (test_and_set_bit(ST_SUSPEND, &gsc->state))
  1037. return 0;
  1038. return gsc_m2m_suspend(gsc);
  1039. }
  1040. static const struct dev_pm_ops gsc_pm_ops = {
  1041. .suspend = gsc_suspend,
  1042. .resume = gsc_resume,
  1043. .runtime_suspend = gsc_runtime_suspend,
  1044. .runtime_resume = gsc_runtime_resume,
  1045. };
  1046. static struct platform_driver gsc_driver = {
  1047. .probe = gsc_probe,
  1048. .remove = __devexit_p(gsc_remove),
  1049. .id_table = gsc_driver_ids,
  1050. .driver = {
  1051. .name = GSC_MODULE_NAME,
  1052. .owner = THIS_MODULE,
  1053. .pm = &gsc_pm_ops,
  1054. .of_match_table = exynos_gsc_match,
  1055. }
  1056. };
  1057. module_platform_driver(gsc_driver);
  1058. MODULE_AUTHOR("Hyunwong Kim <khw0178.kim@samsung.com>");
  1059. MODULE_DESCRIPTION("Samsung EXYNOS5 Soc series G-Scaler driver");
  1060. MODULE_LICENSE("GPL");