imx28.dtsi 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880
  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. gpio3 = &gpio3;
  19. gpio4 = &gpio4;
  20. saif0 = &saif0;
  21. saif1 = &saif1;
  22. serial0 = &auart0;
  23. serial1 = &auart1;
  24. serial2 = &auart2;
  25. serial3 = &auart3;
  26. serial4 = &auart4;
  27. };
  28. cpus {
  29. cpu@0 {
  30. compatible = "arm,arm926ejs";
  31. };
  32. };
  33. apb@80000000 {
  34. compatible = "simple-bus";
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. reg = <0x80000000 0x80000>;
  38. ranges;
  39. apbh@80000000 {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. reg = <0x80000000 0x3c900>;
  44. ranges;
  45. icoll: interrupt-controller@80000000 {
  46. compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
  47. interrupt-controller;
  48. #interrupt-cells = <1>;
  49. reg = <0x80000000 0x2000>;
  50. };
  51. hsadc@80002000 {
  52. reg = <0x80002000 0x2000>;
  53. interrupts = <13 87>;
  54. status = "disabled";
  55. };
  56. dma-apbh@80004000 {
  57. compatible = "fsl,imx28-dma-apbh";
  58. reg = <0x80004000 0x2000>;
  59. };
  60. perfmon@80006000 {
  61. reg = <0x80006000 0x800>;
  62. interrupts = <27>;
  63. status = "disabled";
  64. };
  65. gpmi-nand@8000c000 {
  66. compatible = "fsl,imx28-gpmi-nand";
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
  70. reg-names = "gpmi-nand", "bch";
  71. interrupts = <88>, <41>;
  72. interrupt-names = "gpmi-dma", "bch";
  73. fsl,gpmi-dma-channel = <4>;
  74. status = "disabled";
  75. };
  76. ssp0: ssp@80010000 {
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. reg = <0x80010000 0x2000>;
  80. interrupts = <96 82>;
  81. fsl,ssp-dma-channel = <0>;
  82. status = "disabled";
  83. };
  84. ssp1: ssp@80012000 {
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. reg = <0x80012000 0x2000>;
  88. interrupts = <97 83>;
  89. fsl,ssp-dma-channel = <1>;
  90. status = "disabled";
  91. };
  92. ssp2: ssp@80014000 {
  93. #address-cells = <1>;
  94. #size-cells = <0>;
  95. reg = <0x80014000 0x2000>;
  96. interrupts = <98 84>;
  97. fsl,ssp-dma-channel = <2>;
  98. status = "disabled";
  99. };
  100. ssp3: ssp@80016000 {
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. reg = <0x80016000 0x2000>;
  104. interrupts = <99 85>;
  105. fsl,ssp-dma-channel = <3>;
  106. status = "disabled";
  107. };
  108. pinctrl@80018000 {
  109. #address-cells = <1>;
  110. #size-cells = <0>;
  111. compatible = "fsl,imx28-pinctrl", "simple-bus";
  112. reg = <0x80018000 0x2000>;
  113. gpio0: gpio@0 {
  114. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  115. interrupts = <127>;
  116. gpio-controller;
  117. #gpio-cells = <2>;
  118. interrupt-controller;
  119. #interrupt-cells = <2>;
  120. };
  121. gpio1: gpio@1 {
  122. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  123. interrupts = <126>;
  124. gpio-controller;
  125. #gpio-cells = <2>;
  126. interrupt-controller;
  127. #interrupt-cells = <2>;
  128. };
  129. gpio2: gpio@2 {
  130. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  131. interrupts = <125>;
  132. gpio-controller;
  133. #gpio-cells = <2>;
  134. interrupt-controller;
  135. #interrupt-cells = <2>;
  136. };
  137. gpio3: gpio@3 {
  138. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  139. interrupts = <124>;
  140. gpio-controller;
  141. #gpio-cells = <2>;
  142. interrupt-controller;
  143. #interrupt-cells = <2>;
  144. };
  145. gpio4: gpio@4 {
  146. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  147. interrupts = <123>;
  148. gpio-controller;
  149. #gpio-cells = <2>;
  150. interrupt-controller;
  151. #interrupt-cells = <2>;
  152. };
  153. duart_pins_a: duart@0 {
  154. reg = <0>;
  155. fsl,pinmux-ids = <
  156. 0x3102 /* MX28_PAD_PWM0__DUART_RX */
  157. 0x3112 /* MX28_PAD_PWM1__DUART_TX */
  158. >;
  159. fsl,drive-strength = <0>;
  160. fsl,voltage = <1>;
  161. fsl,pull-up = <0>;
  162. };
  163. duart_pins_b: duart@1 {
  164. reg = <1>;
  165. fsl,pinmux-ids = <
  166. 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
  167. 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
  168. >;
  169. fsl,drive-strength = <0>;
  170. fsl,voltage = <1>;
  171. fsl,pull-up = <0>;
  172. };
  173. duart_4pins_a: duart-4pins@0 {
  174. reg = <0>;
  175. fsl,pinmux-ids = <
  176. 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
  177. 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
  178. 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
  179. 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
  180. >;
  181. fsl,drive-strength = <0>;
  182. fsl,voltage = <1>;
  183. fsl,pull-up = <0>;
  184. };
  185. gpmi_pins_a: gpmi-nand@0 {
  186. reg = <0>;
  187. fsl,pinmux-ids = <
  188. 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
  189. 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
  190. 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
  191. 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
  192. 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
  193. 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
  194. 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
  195. 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
  196. 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
  197. 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
  198. 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
  199. 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
  200. 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
  201. 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
  202. 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
  203. >;
  204. fsl,drive-strength = <0>;
  205. fsl,voltage = <1>;
  206. fsl,pull-up = <0>;
  207. };
  208. gpmi_status_cfg: gpmi-status-cfg {
  209. fsl,pinmux-ids = <
  210. 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
  211. 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
  212. 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
  213. >;
  214. fsl,drive-strength = <2>;
  215. };
  216. auart0_pins_a: auart0@0 {
  217. reg = <0>;
  218. fsl,pinmux-ids = <
  219. 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
  220. 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
  221. 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
  222. 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
  223. >;
  224. fsl,drive-strength = <0>;
  225. fsl,voltage = <1>;
  226. fsl,pull-up = <0>;
  227. };
  228. auart0_2pins_a: auart0-2pins@0 {
  229. reg = <0>;
  230. fsl,pinmux-ids = <
  231. 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
  232. 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
  233. >;
  234. fsl,drive-strength = <0>;
  235. fsl,voltage = <1>;
  236. fsl,pull-up = <0>;
  237. };
  238. auart1_pins_a: auart1@0 {
  239. reg = <0>;
  240. fsl,pinmux-ids = <
  241. 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
  242. 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
  243. 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
  244. 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
  245. >;
  246. fsl,drive-strength = <0>;
  247. fsl,voltage = <1>;
  248. fsl,pull-up = <0>;
  249. };
  250. auart1_2pins_a: auart1-2pins@0 {
  251. reg = <0>;
  252. fsl,pinmux-ids = <
  253. 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
  254. 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
  255. >;
  256. fsl,drive-strength = <0>;
  257. fsl,voltage = <1>;
  258. fsl,pull-up = <0>;
  259. };
  260. auart2_2pins_a: auart2-2pins@0 {
  261. reg = <0>;
  262. fsl,pinmux-ids = <
  263. 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
  264. 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
  265. >;
  266. fsl,drive-strength = <0>;
  267. fsl,voltage = <1>;
  268. fsl,pull-up = <0>;
  269. };
  270. auart3_pins_a: auart3@0 {
  271. reg = <0>;
  272. fsl,pinmux-ids = <
  273. 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
  274. 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
  275. 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
  276. 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
  277. >;
  278. fsl,drive-strength = <0>;
  279. fsl,voltage = <1>;
  280. fsl,pull-up = <0>;
  281. };
  282. auart3_2pins_a: auart3-2pins@0 {
  283. reg = <0>;
  284. fsl,pinmux-ids = <
  285. 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
  286. 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
  287. >;
  288. fsl,drive-strength = <0>;
  289. fsl,voltage = <1>;
  290. fsl,pull-up = <0>;
  291. };
  292. mac0_pins_a: mac0@0 {
  293. reg = <0>;
  294. fsl,pinmux-ids = <
  295. 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
  296. 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
  297. 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
  298. 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
  299. 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
  300. 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
  301. 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
  302. 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
  303. 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
  304. >;
  305. fsl,drive-strength = <1>;
  306. fsl,voltage = <1>;
  307. fsl,pull-up = <1>;
  308. };
  309. mac1_pins_a: mac1@0 {
  310. reg = <0>;
  311. fsl,pinmux-ids = <
  312. 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
  313. 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
  314. 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
  315. 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
  316. 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
  317. 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
  318. >;
  319. fsl,drive-strength = <1>;
  320. fsl,voltage = <1>;
  321. fsl,pull-up = <1>;
  322. };
  323. mmc0_8bit_pins_a: mmc0-8bit@0 {
  324. reg = <0>;
  325. fsl,pinmux-ids = <
  326. 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
  327. 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
  328. 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
  329. 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
  330. 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
  331. 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
  332. 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
  333. 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
  334. 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
  335. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  336. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  337. >;
  338. fsl,drive-strength = <1>;
  339. fsl,voltage = <1>;
  340. fsl,pull-up = <1>;
  341. };
  342. mmc0_4bit_pins_a: mmc0-4bit@0 {
  343. reg = <0>;
  344. fsl,pinmux-ids = <
  345. 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
  346. 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
  347. 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
  348. 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
  349. 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
  350. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  351. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  352. >;
  353. fsl,drive-strength = <1>;
  354. fsl,voltage = <1>;
  355. fsl,pull-up = <1>;
  356. };
  357. mmc0_cd_cfg: mmc0-cd-cfg {
  358. fsl,pinmux-ids = <
  359. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  360. >;
  361. fsl,pull-up = <0>;
  362. };
  363. mmc0_sck_cfg: mmc0-sck-cfg {
  364. fsl,pinmux-ids = <
  365. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  366. >;
  367. fsl,drive-strength = <2>;
  368. fsl,pull-up = <0>;
  369. };
  370. i2c0_pins_a: i2c0@0 {
  371. reg = <0>;
  372. fsl,pinmux-ids = <
  373. 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
  374. 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
  375. >;
  376. fsl,drive-strength = <1>;
  377. fsl,voltage = <1>;
  378. fsl,pull-up = <1>;
  379. };
  380. i2c0_pins_b: i2c0@1 {
  381. reg = <1>;
  382. fsl,pinmux-ids = <
  383. 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
  384. 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
  385. >;
  386. fsl,drive-strength = <1>;
  387. fsl,voltage = <1>;
  388. fsl,pull-up = <1>;
  389. };
  390. i2c1_pins_a: i2c1@0 {
  391. reg = <0>;
  392. fsl,pinmux-ids = <
  393. 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
  394. 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
  395. >;
  396. fsl,drive-strength = <1>;
  397. fsl,voltage = <1>;
  398. fsl,pull-up = <1>;
  399. };
  400. saif0_pins_a: saif0@0 {
  401. reg = <0>;
  402. fsl,pinmux-ids = <
  403. 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
  404. 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
  405. 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
  406. 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
  407. >;
  408. fsl,drive-strength = <2>;
  409. fsl,voltage = <1>;
  410. fsl,pull-up = <1>;
  411. };
  412. saif1_pins_a: saif1@0 {
  413. reg = <0>;
  414. fsl,pinmux-ids = <
  415. 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
  416. >;
  417. fsl,drive-strength = <2>;
  418. fsl,voltage = <1>;
  419. fsl,pull-up = <1>;
  420. };
  421. pwm0_pins_a: pwm0@0 {
  422. reg = <0>;
  423. fsl,pinmux-ids = <
  424. 0x3100 /* MX28_PAD_PWM0__PWM_0 */
  425. >;
  426. fsl,drive-strength = <0>;
  427. fsl,voltage = <1>;
  428. fsl,pull-up = <0>;
  429. };
  430. pwm2_pins_a: pwm2@0 {
  431. reg = <0>;
  432. fsl,pinmux-ids = <
  433. 0x3120 /* MX28_PAD_PWM2__PWM_2 */
  434. >;
  435. fsl,drive-strength = <0>;
  436. fsl,voltage = <1>;
  437. fsl,pull-up = <0>;
  438. };
  439. pwm4_pins_a: pwm4@0 {
  440. reg = <0>;
  441. fsl,pinmux-ids = <
  442. 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
  443. >;
  444. fsl,drive-strength = <0>;
  445. fsl,voltage = <1>;
  446. fsl,pull-up = <0>;
  447. };
  448. lcdif_24bit_pins_a: lcdif-24bit@0 {
  449. reg = <0>;
  450. fsl,pinmux-ids = <
  451. 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
  452. 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
  453. 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
  454. 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
  455. 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
  456. 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
  457. 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
  458. 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
  459. 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
  460. 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
  461. 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
  462. 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
  463. 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
  464. 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
  465. 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
  466. 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
  467. 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
  468. 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
  469. 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
  470. 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
  471. 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
  472. 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
  473. 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
  474. 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
  475. >;
  476. fsl,drive-strength = <0>;
  477. fsl,voltage = <1>;
  478. fsl,pull-up = <0>;
  479. };
  480. can0_pins_a: can0@0 {
  481. reg = <0>;
  482. fsl,pinmux-ids = <
  483. 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
  484. 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
  485. >;
  486. fsl,drive-strength = <0>;
  487. fsl,voltage = <1>;
  488. fsl,pull-up = <0>;
  489. };
  490. can1_pins_a: can1@0 {
  491. reg = <0>;
  492. fsl,pinmux-ids = <
  493. 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
  494. 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
  495. >;
  496. fsl,drive-strength = <0>;
  497. fsl,voltage = <1>;
  498. fsl,pull-up = <0>;
  499. };
  500. spi2_pins_a: spi2@0 {
  501. reg = <0>;
  502. fsl,pinmux-ids = <
  503. 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
  504. 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
  505. 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
  506. 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
  507. >;
  508. fsl,drive-strength = <1>;
  509. fsl,voltage = <1>;
  510. fsl,pull-up = <1>;
  511. };
  512. usbphy0_pins_a: usbphy0@0 {
  513. reg = <0>;
  514. fsl,pinmux-ids = <
  515. 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
  516. >;
  517. fsl,drive-strength = <2>;
  518. fsl,voltage = <1>;
  519. fsl,pull-up = <0>;
  520. };
  521. usbphy0_pins_b: usbphy0@1 {
  522. reg = <1>;
  523. fsl,pinmux-ids = <
  524. 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
  525. >;
  526. fsl,drive-strength = <2>;
  527. fsl,voltage = <1>;
  528. fsl,pull-up = <0>;
  529. };
  530. usbphy1_pins_a: usbphy1@0 {
  531. reg = <0>;
  532. fsl,pinmux-ids = <
  533. 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
  534. >;
  535. fsl,drive-strength = <2>;
  536. fsl,voltage = <1>;
  537. fsl,pull-up = <0>;
  538. };
  539. };
  540. digctl@8001c000 {
  541. reg = <0x8001c000 0x2000>;
  542. interrupts = <89>;
  543. status = "disabled";
  544. };
  545. etm@80022000 {
  546. reg = <0x80022000 0x2000>;
  547. status = "disabled";
  548. };
  549. dma-apbx@80024000 {
  550. compatible = "fsl,imx28-dma-apbx";
  551. reg = <0x80024000 0x2000>;
  552. };
  553. dcp@80028000 {
  554. reg = <0x80028000 0x2000>;
  555. interrupts = <52 53 54>;
  556. status = "disabled";
  557. };
  558. pxp@8002a000 {
  559. reg = <0x8002a000 0x2000>;
  560. interrupts = <39>;
  561. status = "disabled";
  562. };
  563. ocotp@8002c000 {
  564. reg = <0x8002c000 0x2000>;
  565. status = "disabled";
  566. };
  567. axi-ahb@8002e000 {
  568. reg = <0x8002e000 0x2000>;
  569. status = "disabled";
  570. };
  571. lcdif@80030000 {
  572. compatible = "fsl,imx28-lcdif";
  573. reg = <0x80030000 0x2000>;
  574. interrupts = <38 86>;
  575. status = "disabled";
  576. };
  577. can0: can@80032000 {
  578. compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
  579. reg = <0x80032000 0x2000>;
  580. interrupts = <8>;
  581. status = "disabled";
  582. };
  583. can1: can@80034000 {
  584. compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
  585. reg = <0x80034000 0x2000>;
  586. interrupts = <9>;
  587. status = "disabled";
  588. };
  589. simdbg@8003c000 {
  590. reg = <0x8003c000 0x200>;
  591. status = "disabled";
  592. };
  593. simgpmisel@8003c200 {
  594. reg = <0x8003c200 0x100>;
  595. status = "disabled";
  596. };
  597. simsspsel@8003c300 {
  598. reg = <0x8003c300 0x100>;
  599. status = "disabled";
  600. };
  601. simmemsel@8003c400 {
  602. reg = <0x8003c400 0x100>;
  603. status = "disabled";
  604. };
  605. gpiomon@8003c500 {
  606. reg = <0x8003c500 0x100>;
  607. status = "disabled";
  608. };
  609. simenet@8003c700 {
  610. reg = <0x8003c700 0x100>;
  611. status = "disabled";
  612. };
  613. armjtag@8003c800 {
  614. reg = <0x8003c800 0x100>;
  615. status = "disabled";
  616. };
  617. };
  618. apbx@80040000 {
  619. compatible = "simple-bus";
  620. #address-cells = <1>;
  621. #size-cells = <1>;
  622. reg = <0x80040000 0x40000>;
  623. ranges;
  624. clkctl@80040000 {
  625. reg = <0x80040000 0x2000>;
  626. status = "disabled";
  627. };
  628. saif0: saif@80042000 {
  629. compatible = "fsl,imx28-saif";
  630. reg = <0x80042000 0x2000>;
  631. interrupts = <59 80>;
  632. fsl,saif-dma-channel = <4>;
  633. status = "disabled";
  634. };
  635. power@80044000 {
  636. reg = <0x80044000 0x2000>;
  637. status = "disabled";
  638. };
  639. saif1: saif@80046000 {
  640. compatible = "fsl,imx28-saif";
  641. reg = <0x80046000 0x2000>;
  642. interrupts = <58 81>;
  643. fsl,saif-dma-channel = <5>;
  644. status = "disabled";
  645. };
  646. lradc@80050000 {
  647. compatible = "fsl,imx28-lradc";
  648. reg = <0x80050000 0x2000>;
  649. interrupts = <10 14 15 16 17 18 19
  650. 20 21 22 23 24 25>;
  651. status = "disabled";
  652. };
  653. spdif@80054000 {
  654. reg = <0x80054000 0x2000>;
  655. interrupts = <45 66>;
  656. status = "disabled";
  657. };
  658. rtc@80056000 {
  659. compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
  660. reg = <0x80056000 0x2000>;
  661. interrupts = <29>;
  662. };
  663. i2c0: i2c@80058000 {
  664. #address-cells = <1>;
  665. #size-cells = <0>;
  666. compatible = "fsl,imx28-i2c";
  667. reg = <0x80058000 0x2000>;
  668. interrupts = <111 68>;
  669. clock-frequency = <100000>;
  670. status = "disabled";
  671. };
  672. i2c1: i2c@8005a000 {
  673. #address-cells = <1>;
  674. #size-cells = <0>;
  675. compatible = "fsl,imx28-i2c";
  676. reg = <0x8005a000 0x2000>;
  677. interrupts = <110 69>;
  678. clock-frequency = <100000>;
  679. status = "disabled";
  680. };
  681. pwm: pwm@80064000 {
  682. compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
  683. reg = <0x80064000 0x2000>;
  684. #pwm-cells = <2>;
  685. fsl,pwm-number = <8>;
  686. status = "disabled";
  687. };
  688. timrot@80068000 {
  689. reg = <0x80068000 0x2000>;
  690. status = "disabled";
  691. };
  692. auart0: serial@8006a000 {
  693. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  694. reg = <0x8006a000 0x2000>;
  695. interrupts = <112 70 71>;
  696. status = "disabled";
  697. };
  698. auart1: serial@8006c000 {
  699. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  700. reg = <0x8006c000 0x2000>;
  701. interrupts = <113 72 73>;
  702. status = "disabled";
  703. };
  704. auart2: serial@8006e000 {
  705. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  706. reg = <0x8006e000 0x2000>;
  707. interrupts = <114 74 75>;
  708. status = "disabled";
  709. };
  710. auart3: serial@80070000 {
  711. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  712. reg = <0x80070000 0x2000>;
  713. interrupts = <115 76 77>;
  714. status = "disabled";
  715. };
  716. auart4: serial@80072000 {
  717. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  718. reg = <0x80072000 0x2000>;
  719. interrupts = <116 78 79>;
  720. status = "disabled";
  721. };
  722. duart: serial@80074000 {
  723. compatible = "arm,pl011", "arm,primecell";
  724. reg = <0x80074000 0x1000>;
  725. interrupts = <47>;
  726. status = "disabled";
  727. };
  728. usbphy0: usbphy@8007c000 {
  729. compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
  730. reg = <0x8007c000 0x2000>;
  731. status = "disabled";
  732. };
  733. usbphy1: usbphy@8007e000 {
  734. compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
  735. reg = <0x8007e000 0x2000>;
  736. status = "disabled";
  737. };
  738. };
  739. };
  740. ahb@80080000 {
  741. compatible = "simple-bus";
  742. #address-cells = <1>;
  743. #size-cells = <1>;
  744. reg = <0x80080000 0x80000>;
  745. ranges;
  746. usb0: usb@80080000 {
  747. compatible = "fsl,imx28-usb", "fsl,imx27-usb";
  748. reg = <0x80080000 0x10000>;
  749. interrupts = <93>;
  750. fsl,usbphy = <&usbphy0>;
  751. status = "disabled";
  752. };
  753. usb1: usb@80090000 {
  754. compatible = "fsl,imx28-usb", "fsl,imx27-usb";
  755. reg = <0x80090000 0x10000>;
  756. interrupts = <92>;
  757. fsl,usbphy = <&usbphy1>;
  758. status = "disabled";
  759. };
  760. dflpt@800c0000 {
  761. reg = <0x800c0000 0x10000>;
  762. status = "disabled";
  763. };
  764. mac0: ethernet@800f0000 {
  765. compatible = "fsl,imx28-fec";
  766. reg = <0x800f0000 0x4000>;
  767. interrupts = <101>;
  768. status = "disabled";
  769. };
  770. mac1: ethernet@800f4000 {
  771. compatible = "fsl,imx28-fec";
  772. reg = <0x800f4000 0x4000>;
  773. interrupts = <102>;
  774. status = "disabled";
  775. };
  776. switch@800f8000 {
  777. reg = <0x800f8000 0x8000>;
  778. status = "disabled";
  779. };
  780. };
  781. };