Kconfig 8.3 KB

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  1. #
  2. # EDAC Kconfig
  3. # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
  4. # Licensed and distributed under the GPL
  5. #
  6. menuconfig EDAC
  7. bool "EDAC (Error Detection And Correction) reporting"
  8. depends on HAS_IOMEM
  9. depends on X86 || PPC
  10. help
  11. EDAC is designed to report errors in the core system.
  12. These are low-level errors that are reported in the CPU or
  13. supporting chipset or other subsystems:
  14. memory errors, cache errors, PCI errors, thermal throttling, etc..
  15. If unsure, select 'Y'.
  16. If this code is reporting problems on your system, please
  17. see the EDAC project web pages for more information at:
  18. <http://bluesmoke.sourceforge.net/>
  19. and:
  20. <http://buttersideup.com/edacwiki>
  21. There is also a mailing list for the EDAC project, which can
  22. be found via the sourceforge page.
  23. if EDAC
  24. comment "Reporting subsystems"
  25. config EDAC_DEBUG
  26. bool "Debugging"
  27. help
  28. This turns on debugging information for the entire EDAC
  29. sub-system. You can insert module with "debug_level=x", current
  30. there're four debug levels (x=0,1,2,3 from low to high).
  31. Usually you should select 'N'.
  32. config EDAC_DEBUG_VERBOSE
  33. bool "More verbose debugging"
  34. depends on EDAC_DEBUG
  35. help
  36. This option makes debugging information more verbose.
  37. Source file name and line number where debugging message
  38. printed will be added to debugging message.
  39. config EDAC_DECODE_MCE
  40. tristate "Decode MCEs in human-readable form (only on AMD for now)"
  41. depends on CPU_SUP_AMD && X86_MCE
  42. default y
  43. ---help---
  44. Enable this option if you want to decode Machine Check Exceptions
  45. occuring on your machine in human-readable form.
  46. You should definitely say Y here in case you want to decode MCEs
  47. which occur really early upon boot, before the module infrastructure
  48. has been initialized.
  49. config EDAC_MM_EDAC
  50. tristate "Main Memory EDAC (Error Detection And Correction) reporting"
  51. help
  52. Some systems are able to detect and correct errors in main
  53. memory. EDAC can report statistics on memory error
  54. detection and correction (EDAC - or commonly referred to ECC
  55. errors). EDAC will also try to decode where these errors
  56. occurred so that a particular failing memory module can be
  57. replaced. If unsure, select 'Y'.
  58. config EDAC_MCE
  59. bool
  60. config EDAC_AMD64
  61. tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
  62. depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
  63. help
  64. Support for error detection and correction on the AMD 64
  65. Families of Memory Controllers (K8, F10h and F11h)
  66. config EDAC_AMD64_ERROR_INJECTION
  67. bool "Sysfs Error Injection facilities"
  68. depends on EDAC_AMD64
  69. help
  70. Recent Opterons (Family 10h and later) provide for Memory Error
  71. Injection into the ECC detection circuits. The amd64_edac module
  72. allows the operator/user to inject Uncorrectable and Correctable
  73. errors into DRAM.
  74. When enabled, in each of the respective memory controller directories
  75. (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  76. - inject_section (0..3, 16-byte section of 64-byte cacheline),
  77. - inject_word (0..8, 16-bit word of 16-byte section),
  78. - inject_ecc_vector (hex ecc vector: select bits of inject word)
  79. In addition, there are two control files, inject_read and inject_write,
  80. which trigger the DRAM ECC Read and Write respectively.
  81. config EDAC_AMD76X
  82. tristate "AMD 76x (760, 762, 768)"
  83. depends on EDAC_MM_EDAC && PCI && X86_32
  84. help
  85. Support for error detection and correction on the AMD 76x
  86. series of chipsets used with the Athlon processor.
  87. config EDAC_E7XXX
  88. tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
  89. depends on EDAC_MM_EDAC && PCI && X86_32
  90. help
  91. Support for error detection and correction on the Intel
  92. E7205, E7500, E7501 and E7505 server chipsets.
  93. config EDAC_E752X
  94. tristate "Intel e752x (e7520, e7525, e7320) and 3100"
  95. depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
  96. help
  97. Support for error detection and correction on the Intel
  98. E7520, E7525, E7320 server chipsets.
  99. config EDAC_I82443BXGX
  100. tristate "Intel 82443BX/GX (440BX/GX)"
  101. depends on EDAC_MM_EDAC && PCI && X86_32
  102. depends on BROKEN
  103. help
  104. Support for error detection and correction on the Intel
  105. 82443BX/GX memory controllers (440BX/GX chipsets).
  106. config EDAC_I82875P
  107. tristate "Intel 82875p (D82875P, E7210)"
  108. depends on EDAC_MM_EDAC && PCI && X86_32
  109. help
  110. Support for error detection and correction on the Intel
  111. DP82785P and E7210 server chipsets.
  112. config EDAC_I82975X
  113. tristate "Intel 82975x (D82975x)"
  114. depends on EDAC_MM_EDAC && PCI && X86
  115. help
  116. Support for error detection and correction on the Intel
  117. DP82975x server chipsets.
  118. config EDAC_I3000
  119. tristate "Intel 3000/3010"
  120. depends on EDAC_MM_EDAC && PCI && X86
  121. help
  122. Support for error detection and correction on the Intel
  123. 3000 and 3010 server chipsets.
  124. config EDAC_I3200
  125. tristate "Intel 3200"
  126. depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
  127. help
  128. Support for error detection and correction on the Intel
  129. 3200 and 3210 server chipsets.
  130. config EDAC_X38
  131. tristate "Intel X38"
  132. depends on EDAC_MM_EDAC && PCI && X86
  133. help
  134. Support for error detection and correction on the Intel
  135. X38 server chipsets.
  136. config EDAC_I5400
  137. tristate "Intel 5400 (Seaburg) chipsets"
  138. depends on EDAC_MM_EDAC && PCI && X86
  139. help
  140. Support for error detection and correction the Intel
  141. i5400 MCH chipset (Seaburg).
  142. config EDAC_I7CORE
  143. tristate "Intel i7 Core (Nehalem) processors"
  144. depends on EDAC_MM_EDAC && PCI && X86
  145. select EDAC_MCE
  146. help
  147. Support for error detection and correction the Intel
  148. i7 Core (Nehalem) Integrated Memory Controller that exists on
  149. newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
  150. and Xeon 55xx processors.
  151. config EDAC_I82860
  152. tristate "Intel 82860"
  153. depends on EDAC_MM_EDAC && PCI && X86_32
  154. help
  155. Support for error detection and correction on the Intel
  156. 82860 chipset.
  157. config EDAC_R82600
  158. tristate "Radisys 82600 embedded chipset"
  159. depends on EDAC_MM_EDAC && PCI && X86_32
  160. help
  161. Support for error detection and correction on the Radisys
  162. 82600 embedded chipset.
  163. config EDAC_I5000
  164. tristate "Intel Greencreek/Blackford chipset"
  165. depends on EDAC_MM_EDAC && X86 && PCI
  166. help
  167. Support for error detection and correction the Intel
  168. Greekcreek/Blackford chipsets.
  169. config EDAC_I5100
  170. tristate "Intel San Clemente MCH"
  171. depends on EDAC_MM_EDAC && X86 && PCI
  172. help
  173. Support for error detection and correction the Intel
  174. San Clemente MCH.
  175. config EDAC_MPC85XX
  176. tristate "Freescale MPC83xx / MPC85xx"
  177. depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || MPC85xx)
  178. help
  179. Support for error detection and correction on the Freescale
  180. MPC8349, MPC8560, MPC8540, MPC8548
  181. config EDAC_MV64X60
  182. tristate "Marvell MV64x60"
  183. depends on EDAC_MM_EDAC && MV64X60
  184. help
  185. Support for error detection and correction on the Marvell
  186. MV64360 and MV64460 chipsets.
  187. config EDAC_PASEMI
  188. tristate "PA Semi PWRficient"
  189. depends on EDAC_MM_EDAC && PCI
  190. depends on PPC_PASEMI
  191. help
  192. Support for error detection and correction on PA Semi
  193. PWRficient.
  194. config EDAC_CELL
  195. tristate "Cell Broadband Engine memory controller"
  196. depends on EDAC_MM_EDAC && PPC_CELL_COMMON
  197. help
  198. Support for error detection and correction on the
  199. Cell Broadband Engine internal memory controller
  200. on platform without a hypervisor
  201. config EDAC_PPC4XX
  202. tristate "PPC4xx IBM DDR2 Memory Controller"
  203. depends on EDAC_MM_EDAC && 4xx
  204. help
  205. This enables support for EDAC on the ECC memory used
  206. with the IBM DDR2 memory controller found in various
  207. PowerPC 4xx embedded processors such as the 405EX[r],
  208. 440SP, 440SPe, 460EX, 460GT and 460SX.
  209. config EDAC_AMD8131
  210. tristate "AMD8131 HyperTransport PCI-X Tunnel"
  211. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  212. help
  213. Support for error detection and correction on the
  214. AMD8131 HyperTransport PCI-X Tunnel chip.
  215. Note, add more Kconfig dependency if it's adopted
  216. on some machine other than Maple.
  217. config EDAC_AMD8111
  218. tristate "AMD8111 HyperTransport I/O Hub"
  219. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  220. help
  221. Support for error detection and correction on the
  222. AMD8111 HyperTransport I/O Hub chip.
  223. Note, add more Kconfig dependency if it's adopted
  224. on some machine other than Maple.
  225. config EDAC_CPC925
  226. tristate "IBM CPC925 Memory Controller (PPC970FX)"
  227. depends on EDAC_MM_EDAC && PPC64
  228. help
  229. Support for error detection and correction on the
  230. IBM CPC925 Bridge and Memory Controller, which is
  231. a companion chip to the PowerPC 970 family of
  232. processors.
  233. endif # EDAC