p54pci.c 16 KB

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  1. /*
  2. * Linux device driver for PCI based Prism54
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/firmware.h>
  17. #include <linux/etherdevice.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <net/mac80211.h>
  21. #include "p54.h"
  22. #include "p54pci.h"
  23. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  24. MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  25. MODULE_LICENSE("GPL");
  26. MODULE_ALIAS("prism54pci");
  27. MODULE_FIRMWARE("isl3886pci");
  28. static struct pci_device_id p54p_table[] __devinitdata = {
  29. /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  30. { PCI_DEVICE(0x1260, 0x3890) },
  31. /* 3COM 3CRWE154G72 Wireless LAN adapter */
  32. { PCI_DEVICE(0x10b7, 0x6001) },
  33. /* Intersil PRISM Indigo Wireless LAN adapter */
  34. { PCI_DEVICE(0x1260, 0x3877) },
  35. /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  36. { PCI_DEVICE(0x1260, 0x3886) },
  37. { },
  38. };
  39. MODULE_DEVICE_TABLE(pci, p54p_table);
  40. static int p54p_upload_firmware(struct ieee80211_hw *dev)
  41. {
  42. struct p54p_priv *priv = dev->priv;
  43. const struct firmware *fw_entry = NULL;
  44. __le32 reg;
  45. int err;
  46. __le32 *data;
  47. u32 remains, left, device_addr;
  48. P54P_WRITE(int_enable, cpu_to_le32(0));
  49. P54P_READ(int_enable);
  50. udelay(10);
  51. reg = P54P_READ(ctrl_stat);
  52. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  53. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  54. P54P_WRITE(ctrl_stat, reg);
  55. P54P_READ(ctrl_stat);
  56. udelay(10);
  57. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  58. P54P_WRITE(ctrl_stat, reg);
  59. wmb();
  60. udelay(10);
  61. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  62. P54P_WRITE(ctrl_stat, reg);
  63. wmb();
  64. err = request_firmware(&fw_entry, "isl3886pci", &priv->pdev->dev);
  65. if (err) {
  66. printk(KERN_ERR "%s (p54pci): cannot find firmware "
  67. "(isl3886pci)\n", pci_name(priv->pdev));
  68. err = request_firmware(&fw_entry, "isl3886", &priv->pdev->dev);
  69. if (err)
  70. return err;
  71. }
  72. err = p54_parse_firmware(dev, fw_entry);
  73. if (err) {
  74. release_firmware(fw_entry);
  75. return err;
  76. }
  77. data = (__le32 *) fw_entry->data;
  78. remains = fw_entry->size;
  79. device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  80. while (remains) {
  81. u32 i = 0;
  82. left = min((u32)0x1000, remains);
  83. P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  84. P54P_READ(int_enable);
  85. device_addr += 0x1000;
  86. while (i < left) {
  87. P54P_WRITE(direct_mem_win[i], *data++);
  88. i += sizeof(u32);
  89. }
  90. remains -= left;
  91. P54P_READ(int_enable);
  92. }
  93. release_firmware(fw_entry);
  94. reg = P54P_READ(ctrl_stat);
  95. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
  96. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  97. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
  98. P54P_WRITE(ctrl_stat, reg);
  99. P54P_READ(ctrl_stat);
  100. udelay(10);
  101. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  102. P54P_WRITE(ctrl_stat, reg);
  103. wmb();
  104. udelay(10);
  105. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  106. P54P_WRITE(ctrl_stat, reg);
  107. wmb();
  108. udelay(10);
  109. /* wait for the firmware to boot properly */
  110. mdelay(100);
  111. return 0;
  112. }
  113. static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
  114. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  115. struct sk_buff **rx_buf)
  116. {
  117. struct p54p_priv *priv = dev->priv;
  118. struct p54p_ring_control *ring_control = priv->ring_control;
  119. u32 limit, idx, i;
  120. idx = le32_to_cpu(ring_control->host_idx[ring_index]);
  121. limit = idx;
  122. limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
  123. limit = ring_limit - limit;
  124. i = idx % ring_limit;
  125. while (limit-- > 1) {
  126. struct p54p_desc *desc = &ring[i];
  127. if (!desc->host_addr) {
  128. struct sk_buff *skb;
  129. dma_addr_t mapping;
  130. skb = dev_alloc_skb(priv->common.rx_mtu + 32);
  131. if (!skb)
  132. break;
  133. mapping = pci_map_single(priv->pdev,
  134. skb_tail_pointer(skb),
  135. priv->common.rx_mtu + 32,
  136. PCI_DMA_FROMDEVICE);
  137. desc->host_addr = cpu_to_le32(mapping);
  138. desc->device_addr = 0; // FIXME: necessary?
  139. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  140. desc->flags = 0;
  141. rx_buf[i] = skb;
  142. }
  143. i++;
  144. idx++;
  145. i %= ring_limit;
  146. }
  147. wmb();
  148. ring_control->host_idx[ring_index] = cpu_to_le32(idx);
  149. }
  150. static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
  151. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  152. struct sk_buff **rx_buf)
  153. {
  154. struct p54p_priv *priv = dev->priv;
  155. struct p54p_ring_control *ring_control = priv->ring_control;
  156. struct p54p_desc *desc;
  157. u32 idx, i;
  158. i = (*index) % ring_limit;
  159. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  160. idx %= ring_limit;
  161. while (i != idx) {
  162. u16 len;
  163. struct sk_buff *skb;
  164. desc = &ring[i];
  165. len = le16_to_cpu(desc->len);
  166. skb = rx_buf[i];
  167. if (!skb) {
  168. i++;
  169. i %= ring_limit;
  170. continue;
  171. }
  172. skb_put(skb, len);
  173. if (p54_rx(dev, skb)) {
  174. pci_unmap_single(priv->pdev,
  175. le32_to_cpu(desc->host_addr),
  176. priv->common.rx_mtu + 32,
  177. PCI_DMA_FROMDEVICE);
  178. rx_buf[i] = NULL;
  179. desc->host_addr = 0;
  180. } else {
  181. skb_trim(skb, 0);
  182. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  183. }
  184. i++;
  185. i %= ring_limit;
  186. }
  187. p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
  188. }
  189. /* caller must hold priv->lock */
  190. static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
  191. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  192. void **tx_buf)
  193. {
  194. struct p54p_priv *priv = dev->priv;
  195. struct p54p_ring_control *ring_control = priv->ring_control;
  196. struct p54p_desc *desc;
  197. u32 idx, i;
  198. i = (*index) % ring_limit;
  199. (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
  200. idx %= ring_limit;
  201. while (i != idx) {
  202. desc = &ring[i];
  203. p54_free_skb(dev, tx_buf[i]);
  204. tx_buf[i] = NULL;
  205. pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
  206. le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
  207. desc->host_addr = 0;
  208. desc->device_addr = 0;
  209. desc->len = 0;
  210. desc->flags = 0;
  211. i++;
  212. i %= ring_limit;
  213. }
  214. }
  215. static void p54p_rx_tasklet(unsigned long dev_id)
  216. {
  217. struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
  218. struct p54p_priv *priv = dev->priv;
  219. struct p54p_ring_control *ring_control = priv->ring_control;
  220. p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
  221. ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
  222. p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
  223. ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
  224. wmb();
  225. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  226. }
  227. static irqreturn_t p54p_interrupt(int irq, void *dev_id)
  228. {
  229. struct ieee80211_hw *dev = dev_id;
  230. struct p54p_priv *priv = dev->priv;
  231. struct p54p_ring_control *ring_control = priv->ring_control;
  232. __le32 reg;
  233. spin_lock(&priv->lock);
  234. reg = P54P_READ(int_ident);
  235. if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
  236. spin_unlock(&priv->lock);
  237. return IRQ_HANDLED;
  238. }
  239. P54P_WRITE(int_ack, reg);
  240. reg &= P54P_READ(int_enable);
  241. if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
  242. p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
  243. 3, ring_control->tx_mgmt,
  244. ARRAY_SIZE(ring_control->tx_mgmt),
  245. priv->tx_buf_mgmt);
  246. p54p_check_tx_ring(dev, &priv->tx_idx_data,
  247. 1, ring_control->tx_data,
  248. ARRAY_SIZE(ring_control->tx_data),
  249. priv->tx_buf_data);
  250. tasklet_schedule(&priv->rx_tasklet);
  251. } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
  252. complete(&priv->boot_comp);
  253. spin_unlock(&priv->lock);
  254. return reg ? IRQ_HANDLED : IRQ_NONE;
  255. }
  256. static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
  257. int free_on_tx)
  258. {
  259. struct p54p_priv *priv = dev->priv;
  260. struct p54p_ring_control *ring_control = priv->ring_control;
  261. unsigned long flags;
  262. struct p54p_desc *desc;
  263. dma_addr_t mapping;
  264. u32 device_idx, idx, i;
  265. spin_lock_irqsave(&priv->lock, flags);
  266. device_idx = le32_to_cpu(ring_control->device_idx[1]);
  267. idx = le32_to_cpu(ring_control->host_idx[1]);
  268. i = idx % ARRAY_SIZE(ring_control->tx_data);
  269. mapping = pci_map_single(priv->pdev, skb->data, skb->len,
  270. PCI_DMA_TODEVICE);
  271. desc = &ring_control->tx_data[i];
  272. desc->host_addr = cpu_to_le32(mapping);
  273. desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
  274. desc->len = cpu_to_le16(skb->len);
  275. desc->flags = 0;
  276. wmb();
  277. ring_control->host_idx[1] = cpu_to_le32(idx + 1);
  278. if (free_on_tx)
  279. priv->tx_buf_data[i] = skb;
  280. spin_unlock_irqrestore(&priv->lock, flags);
  281. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  282. P54P_READ(dev_int);
  283. /* FIXME: unlikely to happen because the device usually runs out of
  284. memory before we fill the ring up, but we can make it impossible */
  285. if (idx - device_idx > ARRAY_SIZE(ring_control->tx_data) - 2) {
  286. p54_free_skb(dev, skb);
  287. printk(KERN_INFO "%s: tx overflow.\n", wiphy_name(dev->wiphy));
  288. }
  289. }
  290. static void p54p_stop(struct ieee80211_hw *dev)
  291. {
  292. struct p54p_priv *priv = dev->priv;
  293. struct p54p_ring_control *ring_control = priv->ring_control;
  294. unsigned int i;
  295. struct p54p_desc *desc;
  296. tasklet_kill(&priv->rx_tasklet);
  297. P54P_WRITE(int_enable, cpu_to_le32(0));
  298. P54P_READ(int_enable);
  299. udelay(10);
  300. free_irq(priv->pdev->irq, dev);
  301. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  302. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
  303. desc = &ring_control->rx_data[i];
  304. if (desc->host_addr)
  305. pci_unmap_single(priv->pdev,
  306. le32_to_cpu(desc->host_addr),
  307. priv->common.rx_mtu + 32,
  308. PCI_DMA_FROMDEVICE);
  309. kfree_skb(priv->rx_buf_data[i]);
  310. priv->rx_buf_data[i] = NULL;
  311. }
  312. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
  313. desc = &ring_control->rx_mgmt[i];
  314. if (desc->host_addr)
  315. pci_unmap_single(priv->pdev,
  316. le32_to_cpu(desc->host_addr),
  317. priv->common.rx_mtu + 32,
  318. PCI_DMA_FROMDEVICE);
  319. kfree_skb(priv->rx_buf_mgmt[i]);
  320. priv->rx_buf_mgmt[i] = NULL;
  321. }
  322. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
  323. desc = &ring_control->tx_data[i];
  324. if (desc->host_addr)
  325. pci_unmap_single(priv->pdev,
  326. le32_to_cpu(desc->host_addr),
  327. le16_to_cpu(desc->len),
  328. PCI_DMA_TODEVICE);
  329. p54_free_skb(dev, priv->tx_buf_data[i]);
  330. priv->tx_buf_data[i] = NULL;
  331. }
  332. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
  333. desc = &ring_control->tx_mgmt[i];
  334. if (desc->host_addr)
  335. pci_unmap_single(priv->pdev,
  336. le32_to_cpu(desc->host_addr),
  337. le16_to_cpu(desc->len),
  338. PCI_DMA_TODEVICE);
  339. p54_free_skb(dev, priv->tx_buf_mgmt[i]);
  340. priv->tx_buf_mgmt[i] = NULL;
  341. }
  342. memset(ring_control, 0, sizeof(*ring_control));
  343. }
  344. static int p54p_open(struct ieee80211_hw *dev)
  345. {
  346. struct p54p_priv *priv = dev->priv;
  347. int err;
  348. init_completion(&priv->boot_comp);
  349. err = request_irq(priv->pdev->irq, &p54p_interrupt,
  350. IRQF_SHARED, "p54pci", dev);
  351. if (err) {
  352. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  353. wiphy_name(dev->wiphy));
  354. return err;
  355. }
  356. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  357. err = p54p_upload_firmware(dev);
  358. if (err) {
  359. free_irq(priv->pdev->irq, dev);
  360. return err;
  361. }
  362. priv->rx_idx_data = priv->tx_idx_data = 0;
  363. priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
  364. p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
  365. ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
  366. p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
  367. ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
  368. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  369. P54P_READ(ring_control_base);
  370. wmb();
  371. udelay(10);
  372. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  373. P54P_READ(int_enable);
  374. wmb();
  375. udelay(10);
  376. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  377. P54P_READ(dev_int);
  378. if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
  379. printk(KERN_ERR "%s: Cannot boot firmware!\n",
  380. wiphy_name(dev->wiphy));
  381. p54p_stop(dev);
  382. return -ETIMEDOUT;
  383. }
  384. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  385. P54P_READ(int_enable);
  386. wmb();
  387. udelay(10);
  388. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  389. P54P_READ(dev_int);
  390. wmb();
  391. udelay(10);
  392. return 0;
  393. }
  394. static int __devinit p54p_probe(struct pci_dev *pdev,
  395. const struct pci_device_id *id)
  396. {
  397. struct p54p_priv *priv;
  398. struct ieee80211_hw *dev;
  399. unsigned long mem_addr, mem_len;
  400. int err;
  401. err = pci_enable_device(pdev);
  402. if (err) {
  403. printk(KERN_ERR "%s (p54pci): Cannot enable new PCI device\n",
  404. pci_name(pdev));
  405. return err;
  406. }
  407. mem_addr = pci_resource_start(pdev, 0);
  408. mem_len = pci_resource_len(pdev, 0);
  409. if (mem_len < sizeof(struct p54p_csr)) {
  410. printk(KERN_ERR "%s (p54pci): Too short PCI resources\n",
  411. pci_name(pdev));
  412. pci_disable_device(pdev);
  413. return err;
  414. }
  415. err = pci_request_regions(pdev, "p54pci");
  416. if (err) {
  417. printk(KERN_ERR "%s (p54pci): Cannot obtain PCI resources\n",
  418. pci_name(pdev));
  419. return err;
  420. }
  421. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
  422. pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
  423. printk(KERN_ERR "%s (p54pci): No suitable DMA available\n",
  424. pci_name(pdev));
  425. goto err_free_reg;
  426. }
  427. pci_set_master(pdev);
  428. pci_try_set_mwi(pdev);
  429. pci_write_config_byte(pdev, 0x40, 0);
  430. pci_write_config_byte(pdev, 0x41, 0);
  431. dev = p54_init_common(sizeof(*priv));
  432. if (!dev) {
  433. printk(KERN_ERR "%s (p54pci): ieee80211 alloc failed\n",
  434. pci_name(pdev));
  435. err = -ENOMEM;
  436. goto err_free_reg;
  437. }
  438. priv = dev->priv;
  439. priv->pdev = pdev;
  440. SET_IEEE80211_DEV(dev, &pdev->dev);
  441. pci_set_drvdata(pdev, dev);
  442. priv->map = ioremap(mem_addr, mem_len);
  443. if (!priv->map) {
  444. printk(KERN_ERR "%s (p54pci): Cannot map device memory\n",
  445. pci_name(pdev));
  446. err = -EINVAL; // TODO: use a better error code?
  447. goto err_free_dev;
  448. }
  449. priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
  450. &priv->ring_control_dma);
  451. if (!priv->ring_control) {
  452. printk(KERN_ERR "%s (p54pci): Cannot allocate rings\n",
  453. pci_name(pdev));
  454. err = -ENOMEM;
  455. goto err_iounmap;
  456. }
  457. priv->common.open = p54p_open;
  458. priv->common.stop = p54p_stop;
  459. priv->common.tx = p54p_tx;
  460. spin_lock_init(&priv->lock);
  461. tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
  462. err = p54p_open(dev);
  463. if (err)
  464. goto err_free_common;
  465. err = p54_read_eeprom(dev);
  466. p54p_stop(dev);
  467. if (err)
  468. goto err_free_common;
  469. err = ieee80211_register_hw(dev);
  470. if (err) {
  471. printk(KERN_ERR "%s (p54pci): Cannot register netdevice\n",
  472. pci_name(pdev));
  473. goto err_free_common;
  474. }
  475. return 0;
  476. err_free_common:
  477. p54_free_common(dev);
  478. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  479. priv->ring_control, priv->ring_control_dma);
  480. err_iounmap:
  481. iounmap(priv->map);
  482. err_free_dev:
  483. pci_set_drvdata(pdev, NULL);
  484. ieee80211_free_hw(dev);
  485. err_free_reg:
  486. pci_release_regions(pdev);
  487. pci_disable_device(pdev);
  488. return err;
  489. }
  490. static void __devexit p54p_remove(struct pci_dev *pdev)
  491. {
  492. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  493. struct p54p_priv *priv;
  494. if (!dev)
  495. return;
  496. ieee80211_unregister_hw(dev);
  497. priv = dev->priv;
  498. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  499. priv->ring_control, priv->ring_control_dma);
  500. p54_free_common(dev);
  501. iounmap(priv->map);
  502. pci_release_regions(pdev);
  503. pci_disable_device(pdev);
  504. ieee80211_free_hw(dev);
  505. }
  506. #ifdef CONFIG_PM
  507. static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
  508. {
  509. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  510. struct p54p_priv *priv = dev->priv;
  511. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  512. ieee80211_stop_queues(dev);
  513. p54p_stop(dev);
  514. }
  515. pci_save_state(pdev);
  516. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  517. return 0;
  518. }
  519. static int p54p_resume(struct pci_dev *pdev)
  520. {
  521. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  522. struct p54p_priv *priv = dev->priv;
  523. pci_set_power_state(pdev, PCI_D0);
  524. pci_restore_state(pdev);
  525. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  526. p54p_open(dev);
  527. ieee80211_wake_queues(dev);
  528. }
  529. return 0;
  530. }
  531. #endif /* CONFIG_PM */
  532. static struct pci_driver p54p_driver = {
  533. .name = "p54pci",
  534. .id_table = p54p_table,
  535. .probe = p54p_probe,
  536. .remove = __devexit_p(p54p_remove),
  537. #ifdef CONFIG_PM
  538. .suspend = p54p_suspend,
  539. .resume = p54p_resume,
  540. #endif /* CONFIG_PM */
  541. };
  542. static int __init p54p_init(void)
  543. {
  544. return pci_register_driver(&p54p_driver);
  545. }
  546. static void __exit p54p_exit(void)
  547. {
  548. pci_unregister_driver(&p54p_driver);
  549. }
  550. module_init(p54p_init);
  551. module_exit(p54p_exit);