mlx4.h 10 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
  6. * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
  7. *
  8. * This software is available to you under a choice of one of two
  9. * licenses. You may choose to be licensed under the terms of the GNU
  10. * General Public License (GPL) Version 2, available from the file
  11. * COPYING in the main directory of this source tree, or the
  12. * OpenIB.org BSD license below:
  13. *
  14. * Redistribution and use in source and binary forms, with or
  15. * without modification, are permitted provided that the following
  16. * conditions are met:
  17. *
  18. * - Redistributions of source code must retain the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer.
  21. *
  22. * - Redistributions in binary form must reproduce the above
  23. * copyright notice, this list of conditions and the following
  24. * disclaimer in the documentation and/or other materials
  25. * provided with the distribution.
  26. *
  27. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34. * SOFTWARE.
  35. */
  36. #ifndef MLX4_H
  37. #define MLX4_H
  38. #include <linux/mutex.h>
  39. #include <linux/radix-tree.h>
  40. #include <linux/timer.h>
  41. #include <linux/mlx4/device.h>
  42. #include <linux/mlx4/driver.h>
  43. #include <linux/mlx4/doorbell.h>
  44. #define DRV_NAME "mlx4_core"
  45. #define PFX DRV_NAME ": "
  46. #define DRV_VERSION "0.01"
  47. #define DRV_RELDATE "May 1, 2007"
  48. enum {
  49. MLX4_HCR_BASE = 0x80680,
  50. MLX4_HCR_SIZE = 0x0001c,
  51. MLX4_CLR_INT_SIZE = 0x00008
  52. };
  53. enum {
  54. MLX4_MGM_ENTRY_SIZE = 0x100,
  55. MLX4_QP_PER_MGM = 4 * (MLX4_MGM_ENTRY_SIZE / 16 - 2),
  56. MLX4_MTT_ENTRY_PER_SEG = 8
  57. };
  58. enum {
  59. MLX4_EQ_ASYNC,
  60. MLX4_EQ_COMP,
  61. MLX4_NUM_EQ
  62. };
  63. enum {
  64. MLX4_NUM_PDS = 1 << 15
  65. };
  66. enum {
  67. MLX4_CMPT_TYPE_QP = 0,
  68. MLX4_CMPT_TYPE_SRQ = 1,
  69. MLX4_CMPT_TYPE_CQ = 2,
  70. MLX4_CMPT_TYPE_EQ = 3,
  71. MLX4_CMPT_NUM_TYPE
  72. };
  73. enum {
  74. MLX4_CMPT_SHIFT = 24,
  75. MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
  76. };
  77. #ifdef CONFIG_MLX4_DEBUG
  78. extern int mlx4_debug_level;
  79. #else /* CONFIG_MLX4_DEBUG */
  80. #define mlx4_debug_level (0)
  81. #endif /* CONFIG_MLX4_DEBUG */
  82. #define mlx4_dbg(mdev, format, arg...) \
  83. do { \
  84. if (mlx4_debug_level) \
  85. dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
  86. } while (0)
  87. #define mlx4_err(mdev, format, arg...) \
  88. dev_err(&mdev->pdev->dev, format, ## arg)
  89. #define mlx4_info(mdev, format, arg...) \
  90. dev_info(&mdev->pdev->dev, format, ## arg)
  91. #define mlx4_warn(mdev, format, arg...) \
  92. dev_warn(&mdev->pdev->dev, format, ## arg)
  93. struct mlx4_bitmap {
  94. u32 last;
  95. u32 top;
  96. u32 max;
  97. u32 reserved_top;
  98. u32 mask;
  99. spinlock_t lock;
  100. unsigned long *table;
  101. };
  102. struct mlx4_buddy {
  103. unsigned long **bits;
  104. unsigned int *num_free;
  105. int max_order;
  106. spinlock_t lock;
  107. };
  108. struct mlx4_icm;
  109. struct mlx4_icm_table {
  110. u64 virt;
  111. int num_icm;
  112. int num_obj;
  113. int obj_size;
  114. int lowmem;
  115. int coherent;
  116. struct mutex mutex;
  117. struct mlx4_icm **icm;
  118. };
  119. struct mlx4_eq {
  120. struct mlx4_dev *dev;
  121. void __iomem *doorbell;
  122. int eqn;
  123. u32 cons_index;
  124. u16 irq;
  125. u16 have_irq;
  126. int nent;
  127. struct mlx4_buf_list *page_list;
  128. struct mlx4_mtt mtt;
  129. };
  130. struct mlx4_profile {
  131. int num_qp;
  132. int rdmarc_per_qp;
  133. int num_srq;
  134. int num_cq;
  135. int num_mcg;
  136. int num_mpt;
  137. int num_mtt;
  138. };
  139. struct mlx4_fw {
  140. u64 clr_int_base;
  141. u64 catas_offset;
  142. struct mlx4_icm *fw_icm;
  143. struct mlx4_icm *aux_icm;
  144. u32 catas_size;
  145. u16 fw_pages;
  146. u8 clr_int_bar;
  147. u8 catas_bar;
  148. };
  149. struct mlx4_cmd {
  150. struct pci_pool *pool;
  151. void __iomem *hcr;
  152. struct mutex hcr_mutex;
  153. struct semaphore poll_sem;
  154. struct semaphore event_sem;
  155. int max_cmds;
  156. spinlock_t context_lock;
  157. int free_head;
  158. struct mlx4_cmd_context *context;
  159. u16 token_mask;
  160. u8 use_events;
  161. u8 toggle;
  162. };
  163. struct mlx4_uar_table {
  164. struct mlx4_bitmap bitmap;
  165. };
  166. struct mlx4_mr_table {
  167. struct mlx4_bitmap mpt_bitmap;
  168. struct mlx4_buddy mtt_buddy;
  169. u64 mtt_base;
  170. u64 mpt_base;
  171. struct mlx4_icm_table mtt_table;
  172. struct mlx4_icm_table dmpt_table;
  173. };
  174. struct mlx4_cq_table {
  175. struct mlx4_bitmap bitmap;
  176. spinlock_t lock;
  177. struct radix_tree_root tree;
  178. struct mlx4_icm_table table;
  179. struct mlx4_icm_table cmpt_table;
  180. };
  181. struct mlx4_eq_table {
  182. struct mlx4_bitmap bitmap;
  183. void __iomem *clr_int;
  184. void __iomem *uar_map[(MLX4_NUM_EQ + 6) / 4];
  185. u32 clr_mask;
  186. struct mlx4_eq eq[MLX4_NUM_EQ];
  187. u64 icm_virt;
  188. struct page *icm_page;
  189. dma_addr_t icm_dma;
  190. struct mlx4_icm_table cmpt_table;
  191. int have_irq;
  192. u8 inta_pin;
  193. };
  194. struct mlx4_srq_table {
  195. struct mlx4_bitmap bitmap;
  196. spinlock_t lock;
  197. struct radix_tree_root tree;
  198. struct mlx4_icm_table table;
  199. struct mlx4_icm_table cmpt_table;
  200. };
  201. struct mlx4_qp_table {
  202. struct mlx4_bitmap bitmap;
  203. u32 rdmarc_base;
  204. int rdmarc_shift;
  205. spinlock_t lock;
  206. struct mlx4_icm_table qp_table;
  207. struct mlx4_icm_table auxc_table;
  208. struct mlx4_icm_table altc_table;
  209. struct mlx4_icm_table rdmarc_table;
  210. struct mlx4_icm_table cmpt_table;
  211. };
  212. struct mlx4_mcg_table {
  213. struct mutex mutex;
  214. struct mlx4_bitmap bitmap;
  215. struct mlx4_icm_table table;
  216. };
  217. struct mlx4_catas_err {
  218. u32 __iomem *map;
  219. struct timer_list timer;
  220. struct list_head list;
  221. };
  222. #define MLX4_MAX_MAC_NUM 128
  223. #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
  224. struct mlx4_mac_table {
  225. __be64 entries[MLX4_MAX_MAC_NUM];
  226. int refs[MLX4_MAX_MAC_NUM];
  227. struct mutex mutex;
  228. int total;
  229. int max;
  230. };
  231. #define MLX4_MAX_VLAN_NUM 128
  232. #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
  233. struct mlx4_vlan_table {
  234. __be32 entries[MLX4_MAX_VLAN_NUM];
  235. int refs[MLX4_MAX_VLAN_NUM];
  236. struct mutex mutex;
  237. int total;
  238. int max;
  239. };
  240. struct mlx4_port_info {
  241. struct mlx4_dev *dev;
  242. int port;
  243. char dev_name[16];
  244. struct device_attribute port_attr;
  245. enum mlx4_port_type tmp_type;
  246. struct mlx4_mac_table mac_table;
  247. struct mlx4_vlan_table vlan_table;
  248. };
  249. struct mlx4_priv {
  250. struct mlx4_dev dev;
  251. struct list_head dev_list;
  252. struct list_head ctx_list;
  253. spinlock_t ctx_lock;
  254. struct list_head pgdir_list;
  255. struct mutex pgdir_mutex;
  256. struct mlx4_fw fw;
  257. struct mlx4_cmd cmd;
  258. struct mlx4_bitmap pd_bitmap;
  259. struct mlx4_uar_table uar_table;
  260. struct mlx4_mr_table mr_table;
  261. struct mlx4_cq_table cq_table;
  262. struct mlx4_eq_table eq_table;
  263. struct mlx4_srq_table srq_table;
  264. struct mlx4_qp_table qp_table;
  265. struct mlx4_mcg_table mcg_table;
  266. struct mlx4_catas_err catas_err;
  267. void __iomem *clr_base;
  268. struct mlx4_uar driver_uar;
  269. void __iomem *kar;
  270. struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
  271. struct mutex port_mutex;
  272. };
  273. static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
  274. {
  275. return container_of(dev, struct mlx4_priv, dev);
  276. }
  277. u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
  278. void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
  279. u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
  280. void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
  281. int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
  282. u32 reserved_bot, u32 resetrved_top);
  283. void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
  284. int mlx4_reset(struct mlx4_dev *dev);
  285. int mlx4_init_pd_table(struct mlx4_dev *dev);
  286. int mlx4_init_uar_table(struct mlx4_dev *dev);
  287. int mlx4_init_mr_table(struct mlx4_dev *dev);
  288. int mlx4_init_eq_table(struct mlx4_dev *dev);
  289. int mlx4_init_cq_table(struct mlx4_dev *dev);
  290. int mlx4_init_qp_table(struct mlx4_dev *dev);
  291. int mlx4_init_srq_table(struct mlx4_dev *dev);
  292. int mlx4_init_mcg_table(struct mlx4_dev *dev);
  293. void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
  294. void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
  295. void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
  296. void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
  297. void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
  298. void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
  299. void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
  300. void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
  301. void mlx4_start_catas_poll(struct mlx4_dev *dev);
  302. void mlx4_stop_catas_poll(struct mlx4_dev *dev);
  303. int mlx4_catas_init(void);
  304. void mlx4_catas_cleanup(void);
  305. int mlx4_restart_one(struct pci_dev *pdev);
  306. int mlx4_register_device(struct mlx4_dev *dev);
  307. void mlx4_unregister_device(struct mlx4_dev *dev);
  308. void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
  309. struct mlx4_dev_cap;
  310. struct mlx4_init_hca_param;
  311. u64 mlx4_make_profile(struct mlx4_dev *dev,
  312. struct mlx4_profile *request,
  313. struct mlx4_dev_cap *dev_cap,
  314. struct mlx4_init_hca_param *init_hca);
  315. int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt);
  316. void mlx4_unmap_eq_icm(struct mlx4_dev *dev);
  317. int mlx4_cmd_init(struct mlx4_dev *dev);
  318. void mlx4_cmd_cleanup(struct mlx4_dev *dev);
  319. void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
  320. int mlx4_cmd_use_events(struct mlx4_dev *dev);
  321. void mlx4_cmd_use_polling(struct mlx4_dev *dev);
  322. void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
  323. void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
  324. void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
  325. void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
  326. void mlx4_handle_catas_err(struct mlx4_dev *dev);
  327. void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
  328. void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
  329. int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
  330. int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
  331. #endif /* MLX4_H */