pasemi_mac.c 34 KB

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  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/dmaengine.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <asm/dma-mapping.h>
  28. #include <linux/in.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/ip.h>
  31. #include <linux/tcp.h>
  32. #include <net/checksum.h>
  33. #include <asm/irq.h>
  34. #include "pasemi_mac.h"
  35. /* TODO list
  36. *
  37. * - Get rid of pci_{read,write}_config(), map registers with ioremap
  38. * for performance
  39. * - PHY support
  40. * - Multicast support
  41. * - Large MTU support
  42. * - Other performance improvements
  43. */
  44. /* Must be a power of two */
  45. #define RX_RING_SIZE 512
  46. #define TX_RING_SIZE 512
  47. #define DEFAULT_MSG_ENABLE \
  48. (NETIF_MSG_DRV | \
  49. NETIF_MSG_PROBE | \
  50. NETIF_MSG_LINK | \
  51. NETIF_MSG_TIMER | \
  52. NETIF_MSG_IFDOWN | \
  53. NETIF_MSG_IFUP | \
  54. NETIF_MSG_RX_ERR | \
  55. NETIF_MSG_TX_ERR)
  56. #define TX_RING(mac, num) ((mac)->tx->ring[(num) & (TX_RING_SIZE-1)])
  57. #define TX_RING_INFO(mac, num) ((mac)->tx->ring_info[(num) & (TX_RING_SIZE-1)])
  58. #define RX_RING(mac, num) ((mac)->rx->ring[(num) & (RX_RING_SIZE-1)])
  59. #define RX_RING_INFO(mac, num) ((mac)->rx->ring_info[(num) & (RX_RING_SIZE-1)])
  60. #define RX_BUFF(mac, num) ((mac)->rx->buffers[(num) & (RX_RING_SIZE-1)])
  61. #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
  62. & ((ring)->size - 1))
  63. #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring))
  64. #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
  65. MODULE_LICENSE("GPL");
  66. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  67. MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
  68. static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
  69. module_param(debug, int, 0);
  70. MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
  71. static struct pasdma_status *dma_status;
  72. static void write_iob_reg(struct pasemi_mac *mac, unsigned int reg,
  73. unsigned int val)
  74. {
  75. out_le32(mac->iob_regs+reg, val);
  76. }
  77. static unsigned int read_mac_reg(struct pasemi_mac *mac, unsigned int reg)
  78. {
  79. return in_le32(mac->regs+reg);
  80. }
  81. static void write_mac_reg(struct pasemi_mac *mac, unsigned int reg,
  82. unsigned int val)
  83. {
  84. out_le32(mac->regs+reg, val);
  85. }
  86. static unsigned int read_dma_reg(struct pasemi_mac *mac, unsigned int reg)
  87. {
  88. return in_le32(mac->dma_regs+reg);
  89. }
  90. static void write_dma_reg(struct pasemi_mac *mac, unsigned int reg,
  91. unsigned int val)
  92. {
  93. out_le32(mac->dma_regs+reg, val);
  94. }
  95. static int pasemi_get_mac_addr(struct pasemi_mac *mac)
  96. {
  97. struct pci_dev *pdev = mac->pdev;
  98. struct device_node *dn = pci_device_to_OF_node(pdev);
  99. int len;
  100. const u8 *maddr;
  101. u8 addr[6];
  102. if (!dn) {
  103. dev_dbg(&pdev->dev,
  104. "No device node for mac, not configuring\n");
  105. return -ENOENT;
  106. }
  107. maddr = of_get_property(dn, "local-mac-address", &len);
  108. if (maddr && len == 6) {
  109. memcpy(mac->mac_addr, maddr, 6);
  110. return 0;
  111. }
  112. /* Some old versions of firmware mistakenly uses mac-address
  113. * (and as a string) instead of a byte array in local-mac-address.
  114. */
  115. if (maddr == NULL)
  116. maddr = of_get_property(dn, "mac-address", NULL);
  117. if (maddr == NULL) {
  118. dev_warn(&pdev->dev,
  119. "no mac address in device tree, not configuring\n");
  120. return -ENOENT;
  121. }
  122. if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
  123. &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
  124. dev_warn(&pdev->dev,
  125. "can't parse mac address, not configuring\n");
  126. return -EINVAL;
  127. }
  128. memcpy(mac->mac_addr, addr, 6);
  129. return 0;
  130. }
  131. static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
  132. struct sk_buff *skb,
  133. dma_addr_t *dmas)
  134. {
  135. int f;
  136. int nfrags = skb_shinfo(skb)->nr_frags;
  137. pci_unmap_single(mac->dma_pdev, dmas[0], skb_headlen(skb),
  138. PCI_DMA_TODEVICE);
  139. for (f = 0; f < nfrags; f++) {
  140. skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
  141. pci_unmap_page(mac->dma_pdev, dmas[f+1], frag->size,
  142. PCI_DMA_TODEVICE);
  143. }
  144. dev_kfree_skb_irq(skb);
  145. /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
  146. * aligned up to a power of 2
  147. */
  148. return (nfrags + 3) & ~1;
  149. }
  150. static int pasemi_mac_setup_rx_resources(struct net_device *dev)
  151. {
  152. struct pasemi_mac_rxring *ring;
  153. struct pasemi_mac *mac = netdev_priv(dev);
  154. int chan_id = mac->dma_rxch;
  155. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  156. if (!ring)
  157. goto out_ring;
  158. spin_lock_init(&ring->lock);
  159. ring->size = RX_RING_SIZE;
  160. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  161. RX_RING_SIZE, GFP_KERNEL);
  162. if (!ring->ring_info)
  163. goto out_ring_info;
  164. /* Allocate descriptors */
  165. ring->ring = dma_alloc_coherent(&mac->dma_pdev->dev,
  166. RX_RING_SIZE * sizeof(u64),
  167. &ring->dma, GFP_KERNEL);
  168. if (!ring->ring)
  169. goto out_ring_desc;
  170. memset(ring->ring, 0, RX_RING_SIZE * sizeof(u64));
  171. ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
  172. RX_RING_SIZE * sizeof(u64),
  173. &ring->buf_dma, GFP_KERNEL);
  174. if (!ring->buffers)
  175. goto out_buffers;
  176. memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
  177. write_dma_reg(mac, PAS_DMA_RXCHAN_BASEL(chan_id), PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma));
  178. write_dma_reg(mac, PAS_DMA_RXCHAN_BASEU(chan_id),
  179. PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) |
  180. PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
  181. write_dma_reg(mac, PAS_DMA_RXCHAN_CFG(chan_id),
  182. PAS_DMA_RXCHAN_CFG_HBU(2));
  183. write_dma_reg(mac, PAS_DMA_RXINT_BASEL(mac->dma_if),
  184. PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers)));
  185. write_dma_reg(mac, PAS_DMA_RXINT_BASEU(mac->dma_if),
  186. PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) |
  187. PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
  188. write_dma_reg(mac, PAS_DMA_RXINT_CFG(mac->dma_if),
  189. PAS_DMA_RXINT_CFG_DHL(3) |
  190. PAS_DMA_RXINT_CFG_L2 |
  191. PAS_DMA_RXINT_CFG_LW);
  192. ring->next_to_fill = 0;
  193. ring->next_to_clean = 0;
  194. snprintf(ring->irq_name, sizeof(ring->irq_name),
  195. "%s rx", dev->name);
  196. mac->rx = ring;
  197. return 0;
  198. out_buffers:
  199. dma_free_coherent(&mac->dma_pdev->dev,
  200. RX_RING_SIZE * sizeof(u64),
  201. mac->rx->ring, mac->rx->dma);
  202. out_ring_desc:
  203. kfree(ring->ring_info);
  204. out_ring_info:
  205. kfree(ring);
  206. out_ring:
  207. return -ENOMEM;
  208. }
  209. static int pasemi_mac_setup_tx_resources(struct net_device *dev)
  210. {
  211. struct pasemi_mac *mac = netdev_priv(dev);
  212. u32 val;
  213. int chan_id = mac->dma_txch;
  214. struct pasemi_mac_txring *ring;
  215. ring = kzalloc(sizeof(*ring), GFP_KERNEL);
  216. if (!ring)
  217. goto out_ring;
  218. spin_lock_init(&ring->lock);
  219. ring->size = TX_RING_SIZE;
  220. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  221. TX_RING_SIZE, GFP_KERNEL);
  222. if (!ring->ring_info)
  223. goto out_ring_info;
  224. /* Allocate descriptors */
  225. ring->ring = dma_alloc_coherent(&mac->dma_pdev->dev,
  226. TX_RING_SIZE * sizeof(u64),
  227. &ring->dma, GFP_KERNEL);
  228. if (!ring->ring)
  229. goto out_ring_desc;
  230. memset(ring->ring, 0, TX_RING_SIZE * sizeof(u64));
  231. write_dma_reg(mac, PAS_DMA_TXCHAN_BASEL(chan_id),
  232. PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma));
  233. val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32);
  234. val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
  235. write_dma_reg(mac, PAS_DMA_TXCHAN_BASEU(chan_id), val);
  236. write_dma_reg(mac, PAS_DMA_TXCHAN_CFG(chan_id),
  237. PAS_DMA_TXCHAN_CFG_TY_IFACE |
  238. PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
  239. PAS_DMA_TXCHAN_CFG_UP |
  240. PAS_DMA_TXCHAN_CFG_WT(2));
  241. ring->next_to_fill = 0;
  242. ring->next_to_clean = 0;
  243. snprintf(ring->irq_name, sizeof(ring->irq_name),
  244. "%s tx", dev->name);
  245. mac->tx = ring;
  246. return 0;
  247. out_ring_desc:
  248. kfree(ring->ring_info);
  249. out_ring_info:
  250. kfree(ring);
  251. out_ring:
  252. return -ENOMEM;
  253. }
  254. static void pasemi_mac_free_tx_resources(struct net_device *dev)
  255. {
  256. struct pasemi_mac *mac = netdev_priv(dev);
  257. unsigned int i, j;
  258. struct pasemi_mac_buffer *info;
  259. dma_addr_t dmas[MAX_SKB_FRAGS+1];
  260. int freed;
  261. for (i = 0; i < TX_RING_SIZE; i += freed) {
  262. info = &TX_RING_INFO(mac, i+1);
  263. if (info->dma && info->skb) {
  264. for (j = 0; j <= skb_shinfo(info->skb)->nr_frags; j++)
  265. dmas[j] = TX_RING_INFO(mac, i+1+j).dma;
  266. freed = pasemi_mac_unmap_tx_skb(mac, info->skb, dmas);
  267. } else
  268. freed = 2;
  269. }
  270. for (i = 0; i < TX_RING_SIZE; i++)
  271. TX_RING(mac, i) = 0;
  272. dma_free_coherent(&mac->dma_pdev->dev,
  273. TX_RING_SIZE * sizeof(u64),
  274. mac->tx->ring, mac->tx->dma);
  275. kfree(mac->tx->ring_info);
  276. kfree(mac->tx);
  277. mac->tx = NULL;
  278. }
  279. static void pasemi_mac_free_rx_resources(struct net_device *dev)
  280. {
  281. struct pasemi_mac *mac = netdev_priv(dev);
  282. unsigned int i;
  283. struct pasemi_mac_buffer *info;
  284. for (i = 0; i < RX_RING_SIZE; i++) {
  285. info = &RX_RING_INFO(mac, i);
  286. if (info->skb && info->dma) {
  287. pci_unmap_single(mac->dma_pdev,
  288. info->dma,
  289. info->skb->len,
  290. PCI_DMA_FROMDEVICE);
  291. dev_kfree_skb_any(info->skb);
  292. }
  293. info->dma = 0;
  294. info->skb = NULL;
  295. }
  296. for (i = 0; i < RX_RING_SIZE; i++)
  297. RX_RING(mac, i) = 0;
  298. dma_free_coherent(&mac->dma_pdev->dev,
  299. RX_RING_SIZE * sizeof(u64),
  300. mac->rx->ring, mac->rx->dma);
  301. dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
  302. mac->rx->buffers, mac->rx->buf_dma);
  303. kfree(mac->rx->ring_info);
  304. kfree(mac->rx);
  305. mac->rx = NULL;
  306. }
  307. static void pasemi_mac_replenish_rx_ring(struct net_device *dev, int limit)
  308. {
  309. struct pasemi_mac *mac = netdev_priv(dev);
  310. int start = mac->rx->next_to_fill;
  311. unsigned int fill, count;
  312. if (limit <= 0)
  313. return;
  314. fill = start;
  315. for (count = 0; count < limit; count++) {
  316. struct pasemi_mac_buffer *info = &RX_RING_INFO(mac, fill);
  317. u64 *buff = &RX_BUFF(mac, fill);
  318. struct sk_buff *skb;
  319. dma_addr_t dma;
  320. /* Entry in use? */
  321. WARN_ON(*buff);
  322. /* skb might still be in there for recycle on short receives */
  323. if (info->skb)
  324. skb = info->skb;
  325. else
  326. skb = dev_alloc_skb(BUF_SIZE);
  327. if (unlikely(!skb))
  328. break;
  329. dma = pci_map_single(mac->dma_pdev, skb->data, BUF_SIZE,
  330. PCI_DMA_FROMDEVICE);
  331. if (unlikely(dma_mapping_error(dma))) {
  332. dev_kfree_skb_irq(info->skb);
  333. break;
  334. }
  335. info->skb = skb;
  336. info->dma = dma;
  337. *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
  338. fill++;
  339. }
  340. wmb();
  341. write_dma_reg(mac, PAS_DMA_RXCHAN_INCR(mac->dma_rxch), count);
  342. write_dma_reg(mac, PAS_DMA_RXINT_INCR(mac->dma_if), count);
  343. mac->rx->next_to_fill += count;
  344. }
  345. static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac)
  346. {
  347. unsigned int reg, pcnt;
  348. /* Re-enable packet count interrupts: finally
  349. * ack the packet count interrupt we got in rx_intr.
  350. */
  351. pcnt = *mac->rx_status & PAS_STATUS_PCNT_M;
  352. reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
  353. write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
  354. }
  355. static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac)
  356. {
  357. unsigned int reg, pcnt;
  358. /* Re-enable packet count interrupts */
  359. pcnt = *mac->tx_status & PAS_STATUS_PCNT_M;
  360. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  361. write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
  362. }
  363. static inline void pasemi_mac_rx_error(struct pasemi_mac *mac, u64 macrx)
  364. {
  365. unsigned int rcmdsta, ccmdsta;
  366. if (!netif_msg_rx_err(mac))
  367. return;
  368. rcmdsta = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  369. ccmdsta = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch));
  370. printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n",
  371. macrx, *mac->rx_status);
  372. printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
  373. rcmdsta, ccmdsta);
  374. }
  375. static inline void pasemi_mac_tx_error(struct pasemi_mac *mac, u64 mactx)
  376. {
  377. unsigned int cmdsta;
  378. if (!netif_msg_tx_err(mac))
  379. return;
  380. cmdsta = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch));
  381. printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\
  382. "tx status 0x%016lx\n", mactx, *mac->tx_status);
  383. printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
  384. }
  385. static int pasemi_mac_clean_rx(struct pasemi_mac *mac, int limit)
  386. {
  387. unsigned int n;
  388. int count;
  389. struct pasemi_mac_buffer *info;
  390. struct sk_buff *skb;
  391. unsigned int i, len;
  392. u64 macrx;
  393. dma_addr_t dma;
  394. spin_lock(&mac->rx->lock);
  395. n = mac->rx->next_to_clean;
  396. for (count = limit; count; count--) {
  397. rmb();
  398. macrx = RX_RING(mac, n);
  399. if ((macrx & XCT_MACRX_E) ||
  400. (*mac->rx_status & PAS_STATUS_ERROR))
  401. pasemi_mac_rx_error(mac, macrx);
  402. if (!(macrx & XCT_MACRX_O))
  403. break;
  404. info = NULL;
  405. /* We have to scan for our skb since there's no way
  406. * to back-map them from the descriptor, and if we
  407. * have several receive channels then they might not
  408. * show up in the same order as they were put on the
  409. * interface ring.
  410. */
  411. dma = (RX_RING(mac, n+1) & XCT_PTR_ADDR_M);
  412. for (i = mac->rx->next_to_fill;
  413. i < (mac->rx->next_to_fill + RX_RING_SIZE);
  414. i++) {
  415. info = &RX_RING_INFO(mac, i);
  416. if (info->dma == dma)
  417. break;
  418. }
  419. prefetchw(info);
  420. skb = info->skb;
  421. prefetchw(skb);
  422. info->dma = 0;
  423. pci_unmap_single(mac->dma_pdev, dma, skb->len,
  424. PCI_DMA_FROMDEVICE);
  425. len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
  426. if (len < 256) {
  427. struct sk_buff *new_skb =
  428. netdev_alloc_skb(mac->netdev, len + NET_IP_ALIGN);
  429. if (new_skb) {
  430. skb_reserve(new_skb, NET_IP_ALIGN);
  431. memcpy(new_skb->data, skb->data, len);
  432. /* save the skb in buffer_info as good */
  433. skb = new_skb;
  434. }
  435. /* else just continue with the old one */
  436. } else
  437. info->skb = NULL;
  438. /* Need to zero it out since hardware doesn't, since the
  439. * replenish loop uses it to tell when it's done.
  440. */
  441. RX_BUFF(mac, i) = 0;
  442. skb_put(skb, len);
  443. if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
  444. skb->ip_summed = CHECKSUM_UNNECESSARY;
  445. skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
  446. XCT_MACRX_CSUM_S;
  447. } else
  448. skb->ip_summed = CHECKSUM_NONE;
  449. mac->netdev->stats.rx_bytes += len;
  450. mac->netdev->stats.rx_packets++;
  451. skb->protocol = eth_type_trans(skb, mac->netdev);
  452. netif_receive_skb(skb);
  453. RX_RING(mac, n) = 0;
  454. RX_RING(mac, n+1) = 0;
  455. n += 2;
  456. }
  457. if (n > RX_RING_SIZE) {
  458. /* Errata 5971 workaround: L2 target of headers */
  459. write_iob_reg(mac, PAS_IOB_COM_PKTHDRCNT, 0);
  460. n &= (RX_RING_SIZE-1);
  461. }
  462. mac->rx->next_to_clean = n;
  463. pasemi_mac_replenish_rx_ring(mac->netdev, limit-count);
  464. spin_unlock(&mac->rx->lock);
  465. return count;
  466. }
  467. /* Can't make this too large or we blow the kernel stack limits */
  468. #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
  469. static int pasemi_mac_clean_tx(struct pasemi_mac *mac)
  470. {
  471. int i, j;
  472. struct pasemi_mac_buffer *info;
  473. unsigned int start, descr_count, buf_count, limit;
  474. unsigned int total_count;
  475. unsigned long flags;
  476. struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
  477. dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
  478. total_count = 0;
  479. limit = TX_CLEAN_BATCHSIZE;
  480. restart:
  481. spin_lock_irqsave(&mac->tx->lock, flags);
  482. start = mac->tx->next_to_clean;
  483. buf_count = 0;
  484. descr_count = 0;
  485. for (i = start;
  486. descr_count < limit && i < mac->tx->next_to_fill;
  487. i += buf_count) {
  488. u64 mactx = TX_RING(mac, i);
  489. if ((mactx & XCT_MACTX_E) ||
  490. (*mac->tx_status & PAS_STATUS_ERROR))
  491. pasemi_mac_tx_error(mac, mactx);
  492. if (unlikely(mactx & XCT_MACTX_O))
  493. /* Not yet transmitted */
  494. break;
  495. info = &TX_RING_INFO(mac, i+1);
  496. skbs[descr_count] = info->skb;
  497. buf_count = 2 + skb_shinfo(info->skb)->nr_frags;
  498. for (j = 0; j <= skb_shinfo(info->skb)->nr_frags; j++)
  499. dmas[descr_count][j] = TX_RING_INFO(mac, i+1+j).dma;
  500. info->dma = 0;
  501. TX_RING(mac, i) = 0;
  502. TX_RING(mac, i+1) = 0;
  503. TX_RING_INFO(mac, i+1).skb = 0;
  504. TX_RING_INFO(mac, i+1).dma = 0;
  505. /* Since we always fill with an even number of entries, make
  506. * sure we skip any unused one at the end as well.
  507. */
  508. if (buf_count & 1)
  509. buf_count++;
  510. descr_count++;
  511. }
  512. mac->tx->next_to_clean = i;
  513. spin_unlock_irqrestore(&mac->tx->lock, flags);
  514. netif_wake_queue(mac->netdev);
  515. for (i = 0; i < descr_count; i++)
  516. pasemi_mac_unmap_tx_skb(mac, skbs[i], dmas[i]);
  517. total_count += descr_count;
  518. /* If the batch was full, try to clean more */
  519. if (descr_count == limit)
  520. goto restart;
  521. return total_count;
  522. }
  523. static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
  524. {
  525. struct net_device *dev = data;
  526. struct pasemi_mac *mac = netdev_priv(dev);
  527. unsigned int reg;
  528. if (!(*mac->rx_status & PAS_STATUS_CAUSE_M))
  529. return IRQ_NONE;
  530. /* Don't reset packet count so it won't fire again but clear
  531. * all others.
  532. */
  533. reg = 0;
  534. if (*mac->rx_status & PAS_STATUS_SOFT)
  535. reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
  536. if (*mac->rx_status & PAS_STATUS_ERROR)
  537. reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
  538. if (*mac->rx_status & PAS_STATUS_TIMER)
  539. reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
  540. netif_rx_schedule(dev, &mac->napi);
  541. write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg);
  542. return IRQ_HANDLED;
  543. }
  544. static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
  545. {
  546. struct net_device *dev = data;
  547. struct pasemi_mac *mac = netdev_priv(dev);
  548. unsigned int reg, pcnt;
  549. if (!(*mac->tx_status & PAS_STATUS_CAUSE_M))
  550. return IRQ_NONE;
  551. pasemi_mac_clean_tx(mac);
  552. pcnt = *mac->tx_status & PAS_STATUS_PCNT_M;
  553. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  554. if (*mac->tx_status & PAS_STATUS_SOFT)
  555. reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
  556. if (*mac->tx_status & PAS_STATUS_ERROR)
  557. reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
  558. write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg);
  559. return IRQ_HANDLED;
  560. }
  561. static void pasemi_adjust_link(struct net_device *dev)
  562. {
  563. struct pasemi_mac *mac = netdev_priv(dev);
  564. int msg;
  565. unsigned int flags;
  566. unsigned int new_flags;
  567. if (!mac->phydev->link) {
  568. /* If no link, MAC speed settings don't matter. Just report
  569. * link down and return.
  570. */
  571. if (mac->link && netif_msg_link(mac))
  572. printk(KERN_INFO "%s: Link is down.\n", dev->name);
  573. netif_carrier_off(dev);
  574. mac->link = 0;
  575. return;
  576. } else
  577. netif_carrier_on(dev);
  578. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  579. new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
  580. PAS_MAC_CFG_PCFG_TSR_M);
  581. if (!mac->phydev->duplex)
  582. new_flags |= PAS_MAC_CFG_PCFG_HD;
  583. switch (mac->phydev->speed) {
  584. case 1000:
  585. new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
  586. PAS_MAC_CFG_PCFG_TSR_1G;
  587. break;
  588. case 100:
  589. new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
  590. PAS_MAC_CFG_PCFG_TSR_100M;
  591. break;
  592. case 10:
  593. new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
  594. PAS_MAC_CFG_PCFG_TSR_10M;
  595. break;
  596. default:
  597. printk("Unsupported speed %d\n", mac->phydev->speed);
  598. }
  599. /* Print on link or speed/duplex change */
  600. msg = mac->link != mac->phydev->link || flags != new_flags;
  601. mac->duplex = mac->phydev->duplex;
  602. mac->speed = mac->phydev->speed;
  603. mac->link = mac->phydev->link;
  604. if (new_flags != flags)
  605. write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
  606. if (msg && netif_msg_link(mac))
  607. printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
  608. dev->name, mac->speed, mac->duplex ? "full" : "half");
  609. }
  610. static int pasemi_mac_phy_init(struct net_device *dev)
  611. {
  612. struct pasemi_mac *mac = netdev_priv(dev);
  613. struct device_node *dn, *phy_dn;
  614. struct phy_device *phydev;
  615. unsigned int phy_id;
  616. const phandle *ph;
  617. const unsigned int *prop;
  618. struct resource r;
  619. int ret;
  620. dn = pci_device_to_OF_node(mac->pdev);
  621. ph = of_get_property(dn, "phy-handle", NULL);
  622. if (!ph)
  623. return -ENODEV;
  624. phy_dn = of_find_node_by_phandle(*ph);
  625. prop = of_get_property(phy_dn, "reg", NULL);
  626. ret = of_address_to_resource(phy_dn->parent, 0, &r);
  627. if (ret)
  628. goto err;
  629. phy_id = *prop;
  630. snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id);
  631. of_node_put(phy_dn);
  632. mac->link = 0;
  633. mac->speed = 0;
  634. mac->duplex = -1;
  635. phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII);
  636. if (IS_ERR(phydev)) {
  637. printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
  638. return PTR_ERR(phydev);
  639. }
  640. mac->phydev = phydev;
  641. return 0;
  642. err:
  643. of_node_put(phy_dn);
  644. return -ENODEV;
  645. }
  646. static int pasemi_mac_open(struct net_device *dev)
  647. {
  648. struct pasemi_mac *mac = netdev_priv(dev);
  649. int base_irq;
  650. unsigned int flags;
  651. int ret;
  652. /* enable rx section */
  653. write_dma_reg(mac, PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
  654. /* enable tx section */
  655. write_dma_reg(mac, PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
  656. flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
  657. PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
  658. PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
  659. write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
  660. write_iob_reg(mac, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch),
  661. PAS_IOB_DMA_RXCH_CFG_CNTTH(0));
  662. write_iob_reg(mac, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch),
  663. PAS_IOB_DMA_TXCH_CFG_CNTTH(128));
  664. /* Clear out any residual packet count state from firmware */
  665. pasemi_mac_restart_rx_intr(mac);
  666. pasemi_mac_restart_tx_intr(mac);
  667. /* 0xffffff is max value, about 16ms */
  668. write_iob_reg(mac, PAS_IOB_DMA_COM_TIMEOUTCFG,
  669. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff));
  670. ret = pasemi_mac_setup_rx_resources(dev);
  671. if (ret)
  672. goto out_rx_resources;
  673. ret = pasemi_mac_setup_tx_resources(dev);
  674. if (ret)
  675. goto out_tx_resources;
  676. write_mac_reg(mac, PAS_MAC_IPC_CHNL,
  677. PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) |
  678. PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch));
  679. /* enable rx if */
  680. write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  681. PAS_DMA_RXINT_RCMDSTA_EN);
  682. /* enable rx channel */
  683. write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch),
  684. PAS_DMA_RXCHAN_CCMDSTA_EN |
  685. PAS_DMA_RXCHAN_CCMDSTA_DU);
  686. /* enable tx channel */
  687. write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch),
  688. PAS_DMA_TXCHAN_TCMDSTA_EN);
  689. pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
  690. flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
  691. PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
  692. if (mac->type == MAC_TYPE_GMAC)
  693. flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
  694. else
  695. flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
  696. /* Enable interface in MAC */
  697. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  698. ret = pasemi_mac_phy_init(dev);
  699. /* Some configs don't have PHYs (XAUI etc), so don't complain about
  700. * failed init due to -ENODEV.
  701. */
  702. if (ret && ret != -ENODEV)
  703. dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret);
  704. netif_start_queue(dev);
  705. napi_enable(&mac->napi);
  706. /* Interrupts are a bit different for our DMA controller: While
  707. * it's got one a regular PCI device header, the interrupt there
  708. * is really the base of the range it's using. Each tx and rx
  709. * channel has it's own interrupt source.
  710. */
  711. base_irq = virq_to_hw(mac->dma_pdev->irq);
  712. mac->tx_irq = irq_create_mapping(NULL, base_irq + mac->dma_txch);
  713. mac->rx_irq = irq_create_mapping(NULL, base_irq + 20 + mac->dma_txch);
  714. ret = request_irq(mac->tx_irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
  715. mac->tx->irq_name, dev);
  716. if (ret) {
  717. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  718. base_irq + mac->dma_txch, ret);
  719. goto out_tx_int;
  720. }
  721. ret = request_irq(mac->rx_irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
  722. mac->rx->irq_name, dev);
  723. if (ret) {
  724. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  725. base_irq + 20 + mac->dma_rxch, ret);
  726. goto out_rx_int;
  727. }
  728. if (mac->phydev)
  729. phy_start(mac->phydev);
  730. return 0;
  731. out_rx_int:
  732. free_irq(mac->tx_irq, dev);
  733. out_tx_int:
  734. napi_disable(&mac->napi);
  735. netif_stop_queue(dev);
  736. pasemi_mac_free_tx_resources(dev);
  737. out_tx_resources:
  738. pasemi_mac_free_rx_resources(dev);
  739. out_rx_resources:
  740. return ret;
  741. }
  742. #define MAX_RETRIES 5000
  743. static int pasemi_mac_close(struct net_device *dev)
  744. {
  745. struct pasemi_mac *mac = netdev_priv(dev);
  746. unsigned int stat;
  747. int retries;
  748. if (mac->phydev) {
  749. phy_stop(mac->phydev);
  750. phy_disconnect(mac->phydev);
  751. }
  752. netif_stop_queue(dev);
  753. napi_disable(&mac->napi);
  754. /* Clean out any pending buffers */
  755. pasemi_mac_clean_tx(mac);
  756. pasemi_mac_clean_rx(mac, RX_RING_SIZE);
  757. /* Disable interface */
  758. write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), PAS_DMA_TXCHAN_TCMDSTA_ST);
  759. write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), PAS_DMA_RXINT_RCMDSTA_ST);
  760. write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), PAS_DMA_RXCHAN_CCMDSTA_ST);
  761. for (retries = 0; retries < MAX_RETRIES; retries++) {
  762. stat = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch));
  763. if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT))
  764. break;
  765. cond_resched();
  766. }
  767. if (stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)
  768. dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
  769. for (retries = 0; retries < MAX_RETRIES; retries++) {
  770. stat = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch));
  771. if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT))
  772. break;
  773. cond_resched();
  774. }
  775. if (stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)
  776. dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
  777. for (retries = 0; retries < MAX_RETRIES; retries++) {
  778. stat = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  779. if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT))
  780. break;
  781. cond_resched();
  782. }
  783. if (stat & PAS_DMA_RXINT_RCMDSTA_ACT)
  784. dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
  785. /* Then, disable the channel. This must be done separately from
  786. * stopping, since you can't disable when active.
  787. */
  788. write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0);
  789. write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0);
  790. write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
  791. free_irq(mac->tx_irq, dev);
  792. free_irq(mac->rx_irq, dev);
  793. /* Free resources */
  794. pasemi_mac_free_rx_resources(dev);
  795. pasemi_mac_free_tx_resources(dev);
  796. return 0;
  797. }
  798. static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
  799. {
  800. struct pasemi_mac *mac = netdev_priv(dev);
  801. struct pasemi_mac_txring *txring;
  802. u64 dflags, mactx;
  803. dma_addr_t map[MAX_SKB_FRAGS+1];
  804. unsigned int map_size[MAX_SKB_FRAGS+1];
  805. unsigned long flags;
  806. int i, nfrags;
  807. dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_SS | XCT_MACTX_CRC_PAD;
  808. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  809. const unsigned char *nh = skb_network_header(skb);
  810. switch (ip_hdr(skb)->protocol) {
  811. case IPPROTO_TCP:
  812. dflags |= XCT_MACTX_CSUM_TCP;
  813. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  814. dflags |= XCT_MACTX_IPO(nh - skb->data);
  815. break;
  816. case IPPROTO_UDP:
  817. dflags |= XCT_MACTX_CSUM_UDP;
  818. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  819. dflags |= XCT_MACTX_IPO(nh - skb->data);
  820. break;
  821. }
  822. }
  823. nfrags = skb_shinfo(skb)->nr_frags;
  824. map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
  825. PCI_DMA_TODEVICE);
  826. map_size[0] = skb_headlen(skb);
  827. if (dma_mapping_error(map[0]))
  828. goto out_err_nolock;
  829. for (i = 0; i < nfrags; i++) {
  830. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  831. map[i+1] = pci_map_page(mac->dma_pdev, frag->page,
  832. frag->page_offset, frag->size,
  833. PCI_DMA_TODEVICE);
  834. map_size[i+1] = frag->size;
  835. if (dma_mapping_error(map[i+1])) {
  836. nfrags = i;
  837. goto out_err_nolock;
  838. }
  839. }
  840. mactx = dflags | XCT_MACTX_LLEN(skb->len);
  841. txring = mac->tx;
  842. spin_lock_irqsave(&txring->lock, flags);
  843. if (RING_AVAIL(txring) <= nfrags+3) {
  844. spin_unlock_irqrestore(&txring->lock, flags);
  845. pasemi_mac_clean_tx(mac);
  846. pasemi_mac_restart_tx_intr(mac);
  847. spin_lock_irqsave(&txring->lock, flags);
  848. if (RING_AVAIL(txring) <= nfrags+3) {
  849. /* Still no room -- stop the queue and wait for tx
  850. * intr when there's room.
  851. */
  852. netif_stop_queue(dev);
  853. goto out_err;
  854. }
  855. }
  856. TX_RING(mac, txring->next_to_fill) = mactx;
  857. txring->next_to_fill++;
  858. TX_RING_INFO(mac, txring->next_to_fill).skb = skb;
  859. for (i = 0; i <= nfrags; i++) {
  860. TX_RING(mac, txring->next_to_fill+i) =
  861. XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
  862. TX_RING_INFO(mac, txring->next_to_fill+i).dma = map[i];
  863. }
  864. /* We have to add an even number of 8-byte entries to the ring
  865. * even if the last one is unused. That means always an odd number
  866. * of pointers + one mactx descriptor.
  867. */
  868. if (nfrags & 1)
  869. nfrags++;
  870. txring->next_to_fill += nfrags + 1;
  871. dev->stats.tx_packets++;
  872. dev->stats.tx_bytes += skb->len;
  873. spin_unlock_irqrestore(&txring->lock, flags);
  874. write_dma_reg(mac, PAS_DMA_TXCHAN_INCR(mac->dma_txch), (nfrags+2) >> 1);
  875. return NETDEV_TX_OK;
  876. out_err:
  877. spin_unlock_irqrestore(&txring->lock, flags);
  878. out_err_nolock:
  879. while (nfrags--)
  880. pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
  881. PCI_DMA_TODEVICE);
  882. return NETDEV_TX_BUSY;
  883. }
  884. static void pasemi_mac_set_rx_mode(struct net_device *dev)
  885. {
  886. struct pasemi_mac *mac = netdev_priv(dev);
  887. unsigned int flags;
  888. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  889. /* Set promiscuous */
  890. if (dev->flags & IFF_PROMISC)
  891. flags |= PAS_MAC_CFG_PCFG_PR;
  892. else
  893. flags &= ~PAS_MAC_CFG_PCFG_PR;
  894. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  895. }
  896. static int pasemi_mac_poll(struct napi_struct *napi, int budget)
  897. {
  898. struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
  899. struct net_device *dev = mac->netdev;
  900. int pkts;
  901. pasemi_mac_clean_tx(mac);
  902. pkts = pasemi_mac_clean_rx(mac, budget);
  903. if (pkts < budget) {
  904. /* all done, no more packets present */
  905. netif_rx_complete(dev, napi);
  906. pasemi_mac_restart_rx_intr(mac);
  907. }
  908. return pkts;
  909. }
  910. static void __iomem * __devinit map_onedev(struct pci_dev *p, int index)
  911. {
  912. struct device_node *dn;
  913. void __iomem *ret;
  914. dn = pci_device_to_OF_node(p);
  915. if (!dn)
  916. goto fallback;
  917. ret = of_iomap(dn, index);
  918. if (!ret)
  919. goto fallback;
  920. return ret;
  921. fallback:
  922. /* This is hardcoded and ugly, but we have some firmware versions
  923. * that don't provide the register space in the device tree. Luckily
  924. * they are at well-known locations so we can just do the math here.
  925. */
  926. return ioremap(0xe0000000 + (p->devfn << 12), 0x2000);
  927. }
  928. static int __devinit pasemi_mac_map_regs(struct pasemi_mac *mac)
  929. {
  930. struct resource res;
  931. struct device_node *dn;
  932. int err;
  933. mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
  934. if (!mac->dma_pdev) {
  935. dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
  936. return -ENODEV;
  937. }
  938. mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
  939. if (!mac->iob_pdev) {
  940. dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
  941. return -ENODEV;
  942. }
  943. mac->regs = map_onedev(mac->pdev, 0);
  944. mac->dma_regs = map_onedev(mac->dma_pdev, 0);
  945. mac->iob_regs = map_onedev(mac->iob_pdev, 0);
  946. if (!mac->regs || !mac->dma_regs || !mac->iob_regs) {
  947. dev_err(&mac->pdev->dev, "Can't map registers\n");
  948. return -ENODEV;
  949. }
  950. /* The dma status structure is located in the I/O bridge, and
  951. * is cache coherent.
  952. */
  953. if (!dma_status) {
  954. dn = pci_device_to_OF_node(mac->iob_pdev);
  955. if (dn)
  956. err = of_address_to_resource(dn, 1, &res);
  957. if (!dn || err) {
  958. /* Fallback for old firmware */
  959. res.start = 0xfd800000;
  960. res.end = res.start + 0x1000;
  961. }
  962. dma_status = __ioremap(res.start, res.end-res.start, 0);
  963. }
  964. return 0;
  965. }
  966. static int __devinit
  967. pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  968. {
  969. static int index = 0;
  970. struct net_device *dev;
  971. struct pasemi_mac *mac;
  972. int err;
  973. DECLARE_MAC_BUF(mac_buf);
  974. err = pci_enable_device(pdev);
  975. if (err)
  976. return err;
  977. dev = alloc_etherdev(sizeof(struct pasemi_mac));
  978. if (dev == NULL) {
  979. dev_err(&pdev->dev,
  980. "pasemi_mac: Could not allocate ethernet device.\n");
  981. err = -ENOMEM;
  982. goto out_disable_device;
  983. }
  984. pci_set_drvdata(pdev, dev);
  985. SET_NETDEV_DEV(dev, &pdev->dev);
  986. mac = netdev_priv(dev);
  987. mac->pdev = pdev;
  988. mac->netdev = dev;
  989. netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
  990. dev->features = NETIF_F_HW_CSUM | NETIF_F_LLTX | NETIF_F_SG;
  991. /* These should come out of the device tree eventually */
  992. mac->dma_txch = index;
  993. mac->dma_rxch = index;
  994. /* We probe GMAC before XAUI, but the DMA interfaces are
  995. * in XAUI, GMAC order.
  996. */
  997. if (index < 4)
  998. mac->dma_if = index + 2;
  999. else
  1000. mac->dma_if = index - 4;
  1001. index++;
  1002. switch (pdev->device) {
  1003. case 0xa005:
  1004. mac->type = MAC_TYPE_GMAC;
  1005. break;
  1006. case 0xa006:
  1007. mac->type = MAC_TYPE_XAUI;
  1008. break;
  1009. default:
  1010. err = -ENODEV;
  1011. goto out;
  1012. }
  1013. /* get mac addr from device tree */
  1014. if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
  1015. err = -ENODEV;
  1016. goto out;
  1017. }
  1018. memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
  1019. dev->open = pasemi_mac_open;
  1020. dev->stop = pasemi_mac_close;
  1021. dev->hard_start_xmit = pasemi_mac_start_tx;
  1022. dev->set_multicast_list = pasemi_mac_set_rx_mode;
  1023. err = pasemi_mac_map_regs(mac);
  1024. if (err)
  1025. goto out;
  1026. mac->rx_status = &dma_status->rx_sta[mac->dma_rxch];
  1027. mac->tx_status = &dma_status->tx_sta[mac->dma_txch];
  1028. mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
  1029. /* Enable most messages by default */
  1030. mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  1031. err = register_netdev(dev);
  1032. if (err) {
  1033. dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
  1034. err);
  1035. goto out;
  1036. } else if netif_msg_probe(mac)
  1037. printk(KERN_INFO "%s: PA Semi %s: intf %d, txch %d, rxch %d, "
  1038. "hw addr %s\n",
  1039. dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
  1040. mac->dma_if, mac->dma_txch, mac->dma_rxch,
  1041. print_mac(mac_buf, dev->dev_addr));
  1042. return err;
  1043. out:
  1044. if (mac->iob_pdev)
  1045. pci_dev_put(mac->iob_pdev);
  1046. if (mac->dma_pdev)
  1047. pci_dev_put(mac->dma_pdev);
  1048. if (mac->dma_regs)
  1049. iounmap(mac->dma_regs);
  1050. if (mac->iob_regs)
  1051. iounmap(mac->iob_regs);
  1052. if (mac->regs)
  1053. iounmap(mac->regs);
  1054. free_netdev(dev);
  1055. out_disable_device:
  1056. pci_disable_device(pdev);
  1057. return err;
  1058. }
  1059. static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
  1060. {
  1061. struct net_device *netdev = pci_get_drvdata(pdev);
  1062. struct pasemi_mac *mac;
  1063. if (!netdev)
  1064. return;
  1065. mac = netdev_priv(netdev);
  1066. unregister_netdev(netdev);
  1067. pci_disable_device(pdev);
  1068. pci_dev_put(mac->dma_pdev);
  1069. pci_dev_put(mac->iob_pdev);
  1070. iounmap(mac->regs);
  1071. iounmap(mac->dma_regs);
  1072. iounmap(mac->iob_regs);
  1073. pci_set_drvdata(pdev, NULL);
  1074. free_netdev(netdev);
  1075. }
  1076. static struct pci_device_id pasemi_mac_pci_tbl[] = {
  1077. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
  1078. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
  1079. { },
  1080. };
  1081. MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
  1082. static struct pci_driver pasemi_mac_driver = {
  1083. .name = "pasemi_mac",
  1084. .id_table = pasemi_mac_pci_tbl,
  1085. .probe = pasemi_mac_probe,
  1086. .remove = __devexit_p(pasemi_mac_remove),
  1087. };
  1088. static void __exit pasemi_mac_cleanup_module(void)
  1089. {
  1090. pci_unregister_driver(&pasemi_mac_driver);
  1091. __iounmap(dma_status);
  1092. dma_status = NULL;
  1093. }
  1094. int pasemi_mac_init_module(void)
  1095. {
  1096. return pci_register_driver(&pasemi_mac_driver);
  1097. }
  1098. module_init(pasemi_mac_init_module);
  1099. module_exit(pasemi_mac_cleanup_module);