dm9000.c 30 KB

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  1. /*
  2. * dm9000.c: Version 1.2 03/18/2003
  3. *
  4. * A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
  5. * Copyright (C) 1997 Sten Wang
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version 2
  10. * of the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
  18. *
  19. * V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
  20. * 06/22/2001 Support DM9801 progrmming
  21. * E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
  22. * E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
  23. * R17 = (R17 & 0xfff0) | NF + 3
  24. * E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
  25. * R17 = (R17 & 0xfff0) | NF
  26. *
  27. * v1.00 modify by simon 2001.9.5
  28. * change for kernel 2.4.x
  29. *
  30. * v1.1 11/09/2001 fix force mode bug
  31. *
  32. * v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
  33. * Fixed phy reset.
  34. * Added tx/rx 32 bit mode.
  35. * Cleaned up for kernel merge.
  36. *
  37. * 03/03/2004 Sascha Hauer <s.hauer@pengutronix.de>
  38. * Port to 2.6 kernel
  39. *
  40. * 24-Sep-2004 Ben Dooks <ben@simtec.co.uk>
  41. * Cleanup of code to remove ifdefs
  42. * Allowed platform device data to influence access width
  43. * Reformatting areas of code
  44. *
  45. * 17-Mar-2005 Sascha Hauer <s.hauer@pengutronix.de>
  46. * * removed 2.4 style module parameters
  47. * * removed removed unused stat counter and fixed
  48. * net_device_stats
  49. * * introduced tx_timeout function
  50. * * reworked locking
  51. *
  52. * 01-Jul-2005 Ben Dooks <ben@simtec.co.uk>
  53. * * fixed spinlock call without pointer
  54. * * ensure spinlock is initialised
  55. */
  56. #include <linux/module.h>
  57. #include <linux/ioport.h>
  58. #include <linux/netdevice.h>
  59. #include <linux/etherdevice.h>
  60. #include <linux/init.h>
  61. #include <linux/skbuff.h>
  62. #include <linux/spinlock.h>
  63. #include <linux/crc32.h>
  64. #include <linux/mii.h>
  65. #include <linux/ethtool.h>
  66. #include <linux/dm9000.h>
  67. #include <linux/delay.h>
  68. #include <linux/platform_device.h>
  69. #include <linux/irq.h>
  70. #include <asm/delay.h>
  71. #include <asm/irq.h>
  72. #include <asm/io.h>
  73. #include "dm9000.h"
  74. /* Board/System/Debug information/definition ---------------- */
  75. #define DM9000_PHY 0x40 /* PHY address 0x01 */
  76. #define CARDNAME "dm9000"
  77. #define PFX CARDNAME ": "
  78. #define DRV_VERSION "1.30"
  79. #ifdef CONFIG_BLACKFIN
  80. #define readsb insb
  81. #define readsw insw
  82. #define readsl insl
  83. #define writesb outsb
  84. #define writesw outsw
  85. #define writesl outsl
  86. #define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH
  87. #else
  88. #define DEFAULT_TRIGGER (0)
  89. #endif
  90. /*
  91. * Transmit timeout, default 5 seconds.
  92. */
  93. static int watchdog = 5000;
  94. module_param(watchdog, int, 0400);
  95. MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
  96. /* DM9000 register address locking.
  97. *
  98. * The DM9000 uses an address register to control where data written
  99. * to the data register goes. This means that the address register
  100. * must be preserved over interrupts or similar calls.
  101. *
  102. * During interrupt and other critical calls, a spinlock is used to
  103. * protect the system, but the calls themselves save the address
  104. * in the address register in case they are interrupting another
  105. * access to the device.
  106. *
  107. * For general accesses a lock is provided so that calls which are
  108. * allowed to sleep are serialised so that the address register does
  109. * not need to be saved. This lock also serves to serialise access
  110. * to the EEPROM and PHY access registers which are shared between
  111. * these two devices.
  112. */
  113. /* Structure/enum declaration ------------------------------- */
  114. typedef struct board_info {
  115. void __iomem *io_addr; /* Register I/O base address */
  116. void __iomem *io_data; /* Data I/O address */
  117. u16 irq; /* IRQ */
  118. u16 tx_pkt_cnt;
  119. u16 queue_pkt_len;
  120. u16 queue_start_addr;
  121. u16 dbug_cnt;
  122. u8 io_mode; /* 0:word, 2:byte */
  123. u8 phy_addr;
  124. unsigned int flags;
  125. unsigned int in_suspend :1;
  126. int debug_level;
  127. void (*inblk)(void __iomem *port, void *data, int length);
  128. void (*outblk)(void __iomem *port, void *data, int length);
  129. void (*dumpblk)(void __iomem *port, int length);
  130. struct device *dev; /* parent device */
  131. struct resource *addr_res; /* resources found */
  132. struct resource *data_res;
  133. struct resource *addr_req; /* resources requested */
  134. struct resource *data_req;
  135. struct resource *irq_res;
  136. struct mutex addr_lock; /* phy and eeprom access lock */
  137. spinlock_t lock;
  138. struct mii_if_info mii;
  139. u32 msg_enable;
  140. } board_info_t;
  141. /* debug code */
  142. #define dm9000_dbg(db, lev, msg...) do { \
  143. if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \
  144. (lev) < db->debug_level) { \
  145. dev_dbg(db->dev, msg); \
  146. } \
  147. } while (0)
  148. static inline board_info_t *to_dm9000_board(struct net_device *dev)
  149. {
  150. return dev->priv;
  151. }
  152. /* function declaration ------------------------------------- */
  153. static int dm9000_probe(struct platform_device *);
  154. static int dm9000_open(struct net_device *);
  155. static int dm9000_start_xmit(struct sk_buff *, struct net_device *);
  156. static int dm9000_stop(struct net_device *);
  157. static void dm9000_init_dm9000(struct net_device *);
  158. static irqreturn_t dm9000_interrupt(int, void *);
  159. static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg);
  160. static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg,
  161. int value);
  162. static void dm9000_read_eeprom(board_info_t *, int addr, unsigned char *to);
  163. static void dm9000_rx(struct net_device *);
  164. static void dm9000_hash_table(struct net_device *);
  165. //#define DM9000_PROGRAM_EEPROM
  166. #ifdef DM9000_PROGRAM_EEPROM
  167. static void program_eeprom(board_info_t * db);
  168. #endif
  169. /* DM9000 network board routine ---------------------------- */
  170. static void
  171. dm9000_reset(board_info_t * db)
  172. {
  173. dev_dbg(db->dev, "resetting device\n");
  174. /* RESET device */
  175. writeb(DM9000_NCR, db->io_addr);
  176. udelay(200);
  177. writeb(NCR_RST, db->io_data);
  178. udelay(200);
  179. }
  180. /*
  181. * Read a byte from I/O port
  182. */
  183. static u8
  184. ior(board_info_t * db, int reg)
  185. {
  186. writeb(reg, db->io_addr);
  187. return readb(db->io_data);
  188. }
  189. /*
  190. * Write a byte to I/O port
  191. */
  192. static void
  193. iow(board_info_t * db, int reg, int value)
  194. {
  195. writeb(reg, db->io_addr);
  196. writeb(value, db->io_data);
  197. }
  198. /* routines for sending block to chip */
  199. static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
  200. {
  201. writesb(reg, data, count);
  202. }
  203. static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count)
  204. {
  205. writesw(reg, data, (count+1) >> 1);
  206. }
  207. static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count)
  208. {
  209. writesl(reg, data, (count+3) >> 2);
  210. }
  211. /* input block from chip to memory */
  212. static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count)
  213. {
  214. readsb(reg, data, count);
  215. }
  216. static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count)
  217. {
  218. readsw(reg, data, (count+1) >> 1);
  219. }
  220. static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count)
  221. {
  222. readsl(reg, data, (count+3) >> 2);
  223. }
  224. /* dump block from chip to null */
  225. static void dm9000_dumpblk_8bit(void __iomem *reg, int count)
  226. {
  227. int i;
  228. int tmp;
  229. for (i = 0; i < count; i++)
  230. tmp = readb(reg);
  231. }
  232. static void dm9000_dumpblk_16bit(void __iomem *reg, int count)
  233. {
  234. int i;
  235. int tmp;
  236. count = (count + 1) >> 1;
  237. for (i = 0; i < count; i++)
  238. tmp = readw(reg);
  239. }
  240. static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
  241. {
  242. int i;
  243. int tmp;
  244. count = (count + 3) >> 2;
  245. for (i = 0; i < count; i++)
  246. tmp = readl(reg);
  247. }
  248. /* dm9000_set_io
  249. *
  250. * select the specified set of io routines to use with the
  251. * device
  252. */
  253. static void dm9000_set_io(struct board_info *db, int byte_width)
  254. {
  255. /* use the size of the data resource to work out what IO
  256. * routines we want to use
  257. */
  258. switch (byte_width) {
  259. case 1:
  260. db->dumpblk = dm9000_dumpblk_8bit;
  261. db->outblk = dm9000_outblk_8bit;
  262. db->inblk = dm9000_inblk_8bit;
  263. break;
  264. case 3:
  265. dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n");
  266. case 2:
  267. db->dumpblk = dm9000_dumpblk_16bit;
  268. db->outblk = dm9000_outblk_16bit;
  269. db->inblk = dm9000_inblk_16bit;
  270. break;
  271. case 4:
  272. default:
  273. db->dumpblk = dm9000_dumpblk_32bit;
  274. db->outblk = dm9000_outblk_32bit;
  275. db->inblk = dm9000_inblk_32bit;
  276. break;
  277. }
  278. }
  279. /* Our watchdog timed out. Called by the networking layer */
  280. static void dm9000_timeout(struct net_device *dev)
  281. {
  282. board_info_t *db = (board_info_t *) dev->priv;
  283. u8 reg_save;
  284. unsigned long flags;
  285. /* Save previous register address */
  286. reg_save = readb(db->io_addr);
  287. spin_lock_irqsave(&db->lock,flags);
  288. netif_stop_queue(dev);
  289. dm9000_reset(db);
  290. dm9000_init_dm9000(dev);
  291. /* We can accept TX packets again */
  292. dev->trans_start = jiffies;
  293. netif_wake_queue(dev);
  294. /* Restore previous register address */
  295. writeb(reg_save, db->io_addr);
  296. spin_unlock_irqrestore(&db->lock,flags);
  297. }
  298. #ifdef CONFIG_NET_POLL_CONTROLLER
  299. /*
  300. *Used by netconsole
  301. */
  302. static void dm9000_poll_controller(struct net_device *dev)
  303. {
  304. disable_irq(dev->irq);
  305. dm9000_interrupt(dev->irq,dev);
  306. enable_irq(dev->irq);
  307. }
  308. #endif
  309. /* ethtool ops */
  310. static void dm9000_get_drvinfo(struct net_device *dev,
  311. struct ethtool_drvinfo *info)
  312. {
  313. board_info_t *dm = to_dm9000_board(dev);
  314. strcpy(info->driver, CARDNAME);
  315. strcpy(info->version, DRV_VERSION);
  316. strcpy(info->bus_info, to_platform_device(dm->dev)->name);
  317. }
  318. static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  319. {
  320. board_info_t *dm = to_dm9000_board(dev);
  321. mii_ethtool_gset(&dm->mii, cmd);
  322. return 0;
  323. }
  324. static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  325. {
  326. board_info_t *dm = to_dm9000_board(dev);
  327. return mii_ethtool_sset(&dm->mii, cmd);
  328. }
  329. static int dm9000_nway_reset(struct net_device *dev)
  330. {
  331. board_info_t *dm = to_dm9000_board(dev);
  332. return mii_nway_restart(&dm->mii);
  333. }
  334. static u32 dm9000_get_link(struct net_device *dev)
  335. {
  336. board_info_t *dm = to_dm9000_board(dev);
  337. return mii_link_ok(&dm->mii);
  338. }
  339. static const struct ethtool_ops dm9000_ethtool_ops = {
  340. .get_drvinfo = dm9000_get_drvinfo,
  341. .get_settings = dm9000_get_settings,
  342. .set_settings = dm9000_set_settings,
  343. .nway_reset = dm9000_nway_reset,
  344. .get_link = dm9000_get_link,
  345. };
  346. /* dm9000_release_board
  347. *
  348. * release a board, and any mapped resources
  349. */
  350. static void
  351. dm9000_release_board(struct platform_device *pdev, struct board_info *db)
  352. {
  353. if (db->data_res == NULL) {
  354. if (db->addr_res != NULL)
  355. release_mem_region((unsigned long)db->io_addr, 4);
  356. return;
  357. }
  358. /* unmap our resources */
  359. iounmap(db->io_addr);
  360. iounmap(db->io_data);
  361. /* release the resources */
  362. if (db->data_req != NULL) {
  363. release_resource(db->data_req);
  364. kfree(db->data_req);
  365. }
  366. if (db->addr_req != NULL) {
  367. release_resource(db->addr_req);
  368. kfree(db->addr_req);
  369. }
  370. }
  371. #define res_size(_r) (((_r)->end - (_r)->start) + 1)
  372. /*
  373. * Search DM9000 board, allocate space and register it
  374. */
  375. static int
  376. dm9000_probe(struct platform_device *pdev)
  377. {
  378. struct dm9000_plat_data *pdata = pdev->dev.platform_data;
  379. struct board_info *db; /* Point a board information structure */
  380. struct net_device *ndev;
  381. unsigned long base;
  382. int ret = 0;
  383. int iosize;
  384. int i;
  385. u32 id_val;
  386. /* Init network device */
  387. ndev = alloc_etherdev(sizeof (struct board_info));
  388. if (!ndev) {
  389. dev_err(&pdev->dev, "could not allocate device.\n");
  390. return -ENOMEM;
  391. }
  392. SET_NETDEV_DEV(ndev, &pdev->dev);
  393. dev_dbg(&pdev->dev, "dm9000_probe()");
  394. /* setup board info structure */
  395. db = (struct board_info *) ndev->priv;
  396. memset(db, 0, sizeof (*db));
  397. db->dev = &pdev->dev;
  398. spin_lock_init(&db->lock);
  399. mutex_init(&db->addr_lock);
  400. if (pdev->num_resources < 2) {
  401. ret = -ENODEV;
  402. goto out;
  403. } else if (pdev->num_resources == 2) {
  404. base = pdev->resource[0].start;
  405. if (!request_mem_region(base, 4, ndev->name)) {
  406. ret = -EBUSY;
  407. goto out;
  408. }
  409. ndev->base_addr = base;
  410. ndev->irq = pdev->resource[1].start;
  411. db->io_addr = (void __iomem *)base;
  412. db->io_data = (void __iomem *)(base + 4);
  413. /* ensure at least we have a default set of IO routines */
  414. dm9000_set_io(db, 2);
  415. } else {
  416. db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  417. db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  418. db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  419. if (db->addr_res == NULL || db->data_res == NULL ||
  420. db->irq_res == NULL) {
  421. dev_err(db->dev, "insufficient resources\n");
  422. ret = -ENOENT;
  423. goto out;
  424. }
  425. i = res_size(db->addr_res);
  426. db->addr_req = request_mem_region(db->addr_res->start, i,
  427. pdev->name);
  428. if (db->addr_req == NULL) {
  429. dev_err(db->dev, "cannot claim address reg area\n");
  430. ret = -EIO;
  431. goto out;
  432. }
  433. db->io_addr = ioremap(db->addr_res->start, i);
  434. if (db->io_addr == NULL) {
  435. dev_err(db->dev, "failed to ioremap address reg\n");
  436. ret = -EINVAL;
  437. goto out;
  438. }
  439. iosize = res_size(db->data_res);
  440. db->data_req = request_mem_region(db->data_res->start, iosize,
  441. pdev->name);
  442. if (db->data_req == NULL) {
  443. dev_err(db->dev, "cannot claim data reg area\n");
  444. ret = -EIO;
  445. goto out;
  446. }
  447. db->io_data = ioremap(db->data_res->start, iosize);
  448. if (db->io_data == NULL) {
  449. dev_err(db->dev,"failed to ioremap data reg\n");
  450. ret = -EINVAL;
  451. goto out;
  452. }
  453. /* fill in parameters for net-dev structure */
  454. ndev->base_addr = (unsigned long)db->io_addr;
  455. ndev->irq = db->irq_res->start;
  456. /* ensure at least we have a default set of IO routines */
  457. dm9000_set_io(db, iosize);
  458. }
  459. /* check to see if anything is being over-ridden */
  460. if (pdata != NULL) {
  461. /* check to see if the driver wants to over-ride the
  462. * default IO width */
  463. if (pdata->flags & DM9000_PLATF_8BITONLY)
  464. dm9000_set_io(db, 1);
  465. if (pdata->flags & DM9000_PLATF_16BITONLY)
  466. dm9000_set_io(db, 2);
  467. if (pdata->flags & DM9000_PLATF_32BITONLY)
  468. dm9000_set_io(db, 4);
  469. /* check to see if there are any IO routine
  470. * over-rides */
  471. if (pdata->inblk != NULL)
  472. db->inblk = pdata->inblk;
  473. if (pdata->outblk != NULL)
  474. db->outblk = pdata->outblk;
  475. if (pdata->dumpblk != NULL)
  476. db->dumpblk = pdata->dumpblk;
  477. db->flags = pdata->flags;
  478. }
  479. dm9000_reset(db);
  480. /* try two times, DM9000 sometimes gets the first read wrong */
  481. for (i = 0; i < 2; i++) {
  482. id_val = ior(db, DM9000_VIDL);
  483. id_val |= (u32)ior(db, DM9000_VIDH) << 8;
  484. id_val |= (u32)ior(db, DM9000_PIDL) << 16;
  485. id_val |= (u32)ior(db, DM9000_PIDH) << 24;
  486. if (id_val == DM9000_ID)
  487. break;
  488. dev_err(db->dev, "read wrong id 0x%08x\n", id_val);
  489. }
  490. if (id_val != DM9000_ID) {
  491. dev_err(db->dev, "wrong id: 0x%08x\n", id_val);
  492. ret = -ENODEV;
  493. goto out;
  494. }
  495. /* from this point we assume that we have found a DM9000 */
  496. /* driver system function */
  497. ether_setup(ndev);
  498. ndev->open = &dm9000_open;
  499. ndev->hard_start_xmit = &dm9000_start_xmit;
  500. ndev->tx_timeout = &dm9000_timeout;
  501. ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
  502. ndev->stop = &dm9000_stop;
  503. ndev->set_multicast_list = &dm9000_hash_table;
  504. ndev->ethtool_ops = &dm9000_ethtool_ops;
  505. #ifdef CONFIG_NET_POLL_CONTROLLER
  506. ndev->poll_controller = &dm9000_poll_controller;
  507. #endif
  508. #ifdef DM9000_PROGRAM_EEPROM
  509. program_eeprom(db);
  510. #endif
  511. db->msg_enable = NETIF_MSG_LINK;
  512. db->mii.phy_id_mask = 0x1f;
  513. db->mii.reg_num_mask = 0x1f;
  514. db->mii.force_media = 0;
  515. db->mii.full_duplex = 0;
  516. db->mii.dev = ndev;
  517. db->mii.mdio_read = dm9000_phy_read;
  518. db->mii.mdio_write = dm9000_phy_write;
  519. /* try reading the node address from the attached EEPROM */
  520. for (i = 0; i < 6; i += 2)
  521. dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i);
  522. if (!is_valid_ether_addr(ndev->dev_addr)) {
  523. /* try reading from mac */
  524. for (i = 0; i < 6; i++)
  525. ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
  526. }
  527. if (!is_valid_ether_addr(ndev->dev_addr))
  528. dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please "
  529. "set using ifconfig\n", ndev->name);
  530. platform_set_drvdata(pdev, ndev);
  531. ret = register_netdev(ndev);
  532. if (ret == 0) {
  533. DECLARE_MAC_BUF(mac);
  534. printk("%s: dm9000 at %p,%p IRQ %d MAC: %s\n",
  535. ndev->name, db->io_addr, db->io_data, ndev->irq,
  536. print_mac(mac, ndev->dev_addr));
  537. }
  538. return 0;
  539. out:
  540. dev_err(db->dev, "not found (%d).\n", ret);
  541. dm9000_release_board(pdev, db);
  542. free_netdev(ndev);
  543. return ret;
  544. }
  545. /*
  546. * Open the interface.
  547. * The interface is opened whenever "ifconfig" actives it.
  548. */
  549. static int
  550. dm9000_open(struct net_device *dev)
  551. {
  552. board_info_t *db = (board_info_t *) dev->priv;
  553. unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK;
  554. dev_dbg(db->dev, "entering %s\n", __func__);
  555. /* If there is no IRQ type specified, default to something that
  556. * may work, and tell the user that this is a problem */
  557. if (irqflags == IRQF_TRIGGER_NONE) {
  558. dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n");
  559. irqflags = DEFAULT_TRIGGER;
  560. }
  561. irqflags |= IRQF_SHARED;
  562. if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev))
  563. return -EAGAIN;
  564. /* Initialize DM9000 board */
  565. dm9000_reset(db);
  566. dm9000_init_dm9000(dev);
  567. /* Init driver variable */
  568. db->dbug_cnt = 0;
  569. mii_check_media(&db->mii, netif_msg_link(db), 1);
  570. netif_start_queue(dev);
  571. return 0;
  572. }
  573. /*
  574. * Initilize dm9000 board
  575. */
  576. static void
  577. dm9000_init_dm9000(struct net_device *dev)
  578. {
  579. board_info_t *db = (board_info_t *) dev->priv;
  580. dm9000_dbg(db, 1, "entering %s\n", __func__);
  581. /* I/O mode */
  582. db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
  583. /* GPIO0 on pre-activate PHY */
  584. iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
  585. iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
  586. iow(db, DM9000_GPR, 0); /* Enable PHY */
  587. if (db->flags & DM9000_PLATF_EXT_PHY)
  588. iow(db, DM9000_NCR, NCR_EXT_PHY);
  589. /* Program operating register */
  590. iow(db, DM9000_TCR, 0); /* TX Polling clear */
  591. iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
  592. iow(db, DM9000_FCR, 0xff); /* Flow Control */
  593. iow(db, DM9000_SMCR, 0); /* Special Mode */
  594. /* clear TX status */
  595. iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
  596. iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
  597. /* Set address filter table */
  598. dm9000_hash_table(dev);
  599. /* Activate DM9000 */
  600. iow(db, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
  601. /* Enable TX/RX interrupt mask */
  602. iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
  603. /* Init Driver variable */
  604. db->tx_pkt_cnt = 0;
  605. db->queue_pkt_len = 0;
  606. dev->trans_start = 0;
  607. }
  608. /*
  609. * Hardware start transmission.
  610. * Send a packet to media from the upper layer.
  611. */
  612. static int
  613. dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
  614. {
  615. unsigned long flags;
  616. board_info_t *db = (board_info_t *) dev->priv;
  617. dm9000_dbg(db, 3, "%s:\n", __func__);
  618. if (db->tx_pkt_cnt > 1)
  619. return 1;
  620. spin_lock_irqsave(&db->lock, flags);
  621. /* Move data to DM9000 TX RAM */
  622. writeb(DM9000_MWCMD, db->io_addr);
  623. (db->outblk)(db->io_data, skb->data, skb->len);
  624. dev->stats.tx_bytes += skb->len;
  625. db->tx_pkt_cnt++;
  626. /* TX control: First packet immediately send, second packet queue */
  627. if (db->tx_pkt_cnt == 1) {
  628. /* Set TX length to DM9000 */
  629. iow(db, DM9000_TXPLL, skb->len & 0xff);
  630. iow(db, DM9000_TXPLH, (skb->len >> 8) & 0xff);
  631. /* Issue TX polling command */
  632. iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
  633. dev->trans_start = jiffies; /* save the time stamp */
  634. } else {
  635. /* Second packet */
  636. db->queue_pkt_len = skb->len;
  637. netif_stop_queue(dev);
  638. }
  639. spin_unlock_irqrestore(&db->lock, flags);
  640. /* free this SKB */
  641. dev_kfree_skb(skb);
  642. return 0;
  643. }
  644. static void
  645. dm9000_shutdown(struct net_device *dev)
  646. {
  647. board_info_t *db = (board_info_t *) dev->priv;
  648. /* RESET device */
  649. dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
  650. iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
  651. iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */
  652. iow(db, DM9000_RCR, 0x00); /* Disable RX */
  653. }
  654. /*
  655. * Stop the interface.
  656. * The interface is stopped when it is brought.
  657. */
  658. static int
  659. dm9000_stop(struct net_device *ndev)
  660. {
  661. board_info_t *db = (board_info_t *) ndev->priv;
  662. dm9000_dbg(db, 1, "entering %s\n", __func__);
  663. netif_stop_queue(ndev);
  664. netif_carrier_off(ndev);
  665. /* free interrupt */
  666. free_irq(ndev->irq, ndev);
  667. dm9000_shutdown(ndev);
  668. return 0;
  669. }
  670. /*
  671. * DM9000 interrupt handler
  672. * receive the packet to upper layer, free the transmitted packet
  673. */
  674. static void
  675. dm9000_tx_done(struct net_device *dev, board_info_t * db)
  676. {
  677. int tx_status = ior(db, DM9000_NSR); /* Got TX status */
  678. if (tx_status & (NSR_TX2END | NSR_TX1END)) {
  679. /* One packet sent complete */
  680. db->tx_pkt_cnt--;
  681. dev->stats.tx_packets++;
  682. /* Queue packet check & send */
  683. if (db->tx_pkt_cnt > 0) {
  684. iow(db, DM9000_TXPLL, db->queue_pkt_len & 0xff);
  685. iow(db, DM9000_TXPLH, (db->queue_pkt_len >> 8) & 0xff);
  686. iow(db, DM9000_TCR, TCR_TXREQ);
  687. dev->trans_start = jiffies;
  688. }
  689. netif_wake_queue(dev);
  690. }
  691. }
  692. static irqreturn_t
  693. dm9000_interrupt(int irq, void *dev_id)
  694. {
  695. struct net_device *dev = dev_id;
  696. board_info_t *db = (board_info_t *) dev->priv;
  697. int int_status;
  698. u8 reg_save;
  699. dm9000_dbg(db, 3, "entering %s\n", __func__);
  700. /* A real interrupt coming */
  701. spin_lock(&db->lock);
  702. /* Save previous register address */
  703. reg_save = readb(db->io_addr);
  704. /* Disable all interrupts */
  705. iow(db, DM9000_IMR, IMR_PAR);
  706. /* Got DM9000 interrupt status */
  707. int_status = ior(db, DM9000_ISR); /* Got ISR */
  708. iow(db, DM9000_ISR, int_status); /* Clear ISR status */
  709. /* Received the coming packet */
  710. if (int_status & ISR_PRS)
  711. dm9000_rx(dev);
  712. /* Trnasmit Interrupt check */
  713. if (int_status & ISR_PTS)
  714. dm9000_tx_done(dev, db);
  715. /* Re-enable interrupt mask */
  716. iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
  717. /* Restore previous register address */
  718. writeb(reg_save, db->io_addr);
  719. spin_unlock(&db->lock);
  720. return IRQ_HANDLED;
  721. }
  722. struct dm9000_rxhdr {
  723. u8 RxPktReady;
  724. u8 RxStatus;
  725. u16 RxLen;
  726. } __attribute__((__packed__));
  727. /*
  728. * Received a packet and pass to upper layer
  729. */
  730. static void
  731. dm9000_rx(struct net_device *dev)
  732. {
  733. board_info_t *db = (board_info_t *) dev->priv;
  734. struct dm9000_rxhdr rxhdr;
  735. struct sk_buff *skb;
  736. u8 rxbyte, *rdptr;
  737. bool GoodPacket;
  738. int RxLen;
  739. /* Check packet ready or not */
  740. do {
  741. ior(db, DM9000_MRCMDX); /* Dummy read */
  742. /* Get most updated data */
  743. rxbyte = readb(db->io_data);
  744. /* Status check: this byte must be 0 or 1 */
  745. if (rxbyte > DM9000_PKT_RDY) {
  746. dev_warn(db->dev, "status check fail: %d\n", rxbyte);
  747. iow(db, DM9000_RCR, 0x00); /* Stop Device */
  748. iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */
  749. return;
  750. }
  751. if (rxbyte != DM9000_PKT_RDY)
  752. return;
  753. /* A packet ready now & Get status/length */
  754. GoodPacket = true;
  755. writeb(DM9000_MRCMD, db->io_addr);
  756. (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));
  757. RxLen = le16_to_cpu(rxhdr.RxLen);
  758. /* Packet Status check */
  759. if (RxLen < 0x40) {
  760. GoodPacket = false;
  761. dev_dbg(db->dev, "Bad Packet received (runt)\n");
  762. }
  763. if (RxLen > DM9000_PKT_MAX) {
  764. dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen);
  765. }
  766. if (rxhdr.RxStatus & 0xbf) {
  767. GoodPacket = false;
  768. if (rxhdr.RxStatus & 0x01) {
  769. dev_dbg(db->dev, "fifo error\n");
  770. dev->stats.rx_fifo_errors++;
  771. }
  772. if (rxhdr.RxStatus & 0x02) {
  773. dev_dbg(db->dev, "crc error\n");
  774. dev->stats.rx_crc_errors++;
  775. }
  776. if (rxhdr.RxStatus & 0x80) {
  777. dev_dbg(db->dev, "length error\n");
  778. dev->stats.rx_length_errors++;
  779. }
  780. }
  781. /* Move data from DM9000 */
  782. if (GoodPacket
  783. && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) {
  784. skb_reserve(skb, 2);
  785. rdptr = (u8 *) skb_put(skb, RxLen - 4);
  786. /* Read received packet from RX SRAM */
  787. (db->inblk)(db->io_data, rdptr, RxLen);
  788. dev->stats.rx_bytes += RxLen;
  789. /* Pass to upper layer */
  790. skb->protocol = eth_type_trans(skb, dev);
  791. netif_rx(skb);
  792. dev->stats.rx_packets++;
  793. } else {
  794. /* need to dump the packet's data */
  795. (db->dumpblk)(db->io_data, RxLen);
  796. }
  797. } while (rxbyte == DM9000_PKT_RDY);
  798. }
  799. /*
  800. * Read a word data from EEPROM
  801. */
  802. static void
  803. dm9000_read_eeprom(board_info_t *db, int offset, unsigned char *to)
  804. {
  805. mutex_lock(&db->addr_lock);
  806. iow(db, DM9000_EPAR, offset);
  807. iow(db, DM9000_EPCR, EPCR_ERPRR);
  808. mdelay(8); /* according to the datasheet 200us should be enough,
  809. but it doesn't work */
  810. iow(db, DM9000_EPCR, 0x0);
  811. to[0] = ior(db, DM9000_EPDRL);
  812. to[1] = ior(db, DM9000_EPDRH);
  813. mutex_unlock(&db->addr_lock);
  814. }
  815. #ifdef DM9000_PROGRAM_EEPROM
  816. /*
  817. * Write a word data to SROM
  818. */
  819. static void
  820. write_srom_word(board_info_t * db, int offset, u16 val)
  821. {
  822. mutex_lock(&db->addr_lock);
  823. iow(db, DM9000_EPAR, offset);
  824. iow(db, DM9000_EPDRH, ((val >> 8) & 0xff));
  825. iow(db, DM9000_EPDRL, (val & 0xff));
  826. iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
  827. mdelay(8); /* same shit */
  828. iow(db, DM9000_EPCR, 0);
  829. mutex_unlock(&db->addr_lock);
  830. }
  831. /*
  832. * Only for development:
  833. * Here we write static data to the eeprom in case
  834. * we don't have valid content on a new board
  835. */
  836. static void
  837. program_eeprom(board_info_t * db)
  838. {
  839. u16 eeprom[] = { 0x0c00, 0x007f, 0x1300, /* MAC Address */
  840. 0x0000, /* Autoload: accept nothing */
  841. 0x0a46, 0x9000, /* Vendor / Product ID */
  842. 0x0000, /* pin control */
  843. 0x0000,
  844. }; /* Wake-up mode control */
  845. int i;
  846. for (i = 0; i < 8; i++)
  847. write_srom_word(db, i, eeprom[i]);
  848. }
  849. #endif
  850. /*
  851. * Calculate the CRC valude of the Rx packet
  852. * flag = 1 : return the reverse CRC (for the received packet CRC)
  853. * 0 : return the normal CRC (for Hash Table index)
  854. */
  855. static unsigned long
  856. cal_CRC(unsigned char *Data, unsigned int Len, u8 flag)
  857. {
  858. u32 crc = ether_crc_le(Len, Data);
  859. if (flag)
  860. return ~crc;
  861. return crc;
  862. }
  863. /*
  864. * Set DM9000 multicast address
  865. */
  866. static void
  867. dm9000_hash_table(struct net_device *dev)
  868. {
  869. board_info_t *db = (board_info_t *) dev->priv;
  870. struct dev_mc_list *mcptr = dev->mc_list;
  871. int mc_cnt = dev->mc_count;
  872. u32 hash_val;
  873. u16 i, oft, hash_table[4];
  874. unsigned long flags;
  875. dm9000_dbg(db, 1, "entering %s\n", __func__);
  876. spin_lock_irqsave(&db->lock,flags);
  877. for (i = 0, oft = 0x10; i < 6; i++, oft++)
  878. iow(db, oft, dev->dev_addr[i]);
  879. /* Clear Hash Table */
  880. for (i = 0; i < 4; i++)
  881. hash_table[i] = 0x0;
  882. /* broadcast address */
  883. hash_table[3] = 0x8000;
  884. /* the multicast address in Hash Table : 64 bits */
  885. for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
  886. hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
  887. hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
  888. }
  889. /* Write the hash table to MAC MD table */
  890. for (i = 0, oft = 0x16; i < 4; i++) {
  891. iow(db, oft++, hash_table[i] & 0xff);
  892. iow(db, oft++, (hash_table[i] >> 8) & 0xff);
  893. }
  894. spin_unlock_irqrestore(&db->lock,flags);
  895. }
  896. /*
  897. * Sleep, either by using msleep() or if we are suspending, then
  898. * use mdelay() to sleep.
  899. */
  900. static void dm9000_msleep(board_info_t *db, unsigned int ms)
  901. {
  902. if (db->in_suspend)
  903. mdelay(ms);
  904. else
  905. msleep(ms);
  906. }
  907. /*
  908. * Read a word from phyxcer
  909. */
  910. static int
  911. dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
  912. {
  913. board_info_t *db = (board_info_t *) dev->priv;
  914. unsigned long flags;
  915. unsigned int reg_save;
  916. int ret;
  917. mutex_lock(&db->addr_lock);
  918. spin_lock_irqsave(&db->lock,flags);
  919. /* Save previous register address */
  920. reg_save = readb(db->io_addr);
  921. /* Fill the phyxcer register into REG_0C */
  922. iow(db, DM9000_EPAR, DM9000_PHY | reg);
  923. iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */
  924. writeb(reg_save, db->io_addr);
  925. spin_unlock_irqrestore(&db->lock,flags);
  926. dm9000_msleep(db, 1); /* Wait read complete */
  927. spin_lock_irqsave(&db->lock,flags);
  928. reg_save = readb(db->io_addr);
  929. iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
  930. /* The read data keeps on REG_0D & REG_0E */
  931. ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
  932. /* restore the previous address */
  933. writeb(reg_save, db->io_addr);
  934. spin_unlock_irqrestore(&db->lock,flags);
  935. mutex_unlock(&db->addr_lock);
  936. return ret;
  937. }
  938. /*
  939. * Write a word to phyxcer
  940. */
  941. static void
  942. dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value)
  943. {
  944. board_info_t *db = (board_info_t *) dev->priv;
  945. unsigned long flags;
  946. unsigned long reg_save;
  947. mutex_lock(&db->addr_lock);
  948. spin_lock_irqsave(&db->lock,flags);
  949. /* Save previous register address */
  950. reg_save = readb(db->io_addr);
  951. /* Fill the phyxcer register into REG_0C */
  952. iow(db, DM9000_EPAR, DM9000_PHY | reg);
  953. /* Fill the written data into REG_0D & REG_0E */
  954. iow(db, DM9000_EPDRL, (value & 0xff));
  955. iow(db, DM9000_EPDRH, ((value >> 8) & 0xff));
  956. iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */
  957. writeb(reg_save, db->io_addr);
  958. spin_unlock_irqrestore(&db->lock, flags);
  959. dm9000_msleep(db, 1); /* Wait write complete */
  960. spin_lock_irqsave(&db->lock,flags);
  961. reg_save = readb(db->io_addr);
  962. iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
  963. /* restore the previous address */
  964. writeb(reg_save, db->io_addr);
  965. spin_unlock_irqrestore(&db->lock, flags);
  966. mutex_unlock(&db->addr_lock);
  967. }
  968. static int
  969. dm9000_drv_suspend(struct platform_device *dev, pm_message_t state)
  970. {
  971. struct net_device *ndev = platform_get_drvdata(dev);
  972. board_info_t *db;
  973. if (ndev) {
  974. db = (board_info_t *) ndev->priv;
  975. db->in_suspend = 1;
  976. if (netif_running(ndev)) {
  977. netif_device_detach(ndev);
  978. dm9000_shutdown(ndev);
  979. }
  980. }
  981. return 0;
  982. }
  983. static int
  984. dm9000_drv_resume(struct platform_device *dev)
  985. {
  986. struct net_device *ndev = platform_get_drvdata(dev);
  987. board_info_t *db = (board_info_t *) ndev->priv;
  988. if (ndev) {
  989. if (netif_running(ndev)) {
  990. dm9000_reset(db);
  991. dm9000_init_dm9000(ndev);
  992. netif_device_attach(ndev);
  993. }
  994. db->in_suspend = 0;
  995. }
  996. return 0;
  997. }
  998. static int
  999. dm9000_drv_remove(struct platform_device *pdev)
  1000. {
  1001. struct net_device *ndev = platform_get_drvdata(pdev);
  1002. platform_set_drvdata(pdev, NULL);
  1003. unregister_netdev(ndev);
  1004. dm9000_release_board(pdev, (board_info_t *) ndev->priv);
  1005. free_netdev(ndev); /* free device structure */
  1006. dev_dbg(&pdev->dev, "released and freed device\n");
  1007. return 0;
  1008. }
  1009. static struct platform_driver dm9000_driver = {
  1010. .driver = {
  1011. .name = "dm9000",
  1012. .owner = THIS_MODULE,
  1013. },
  1014. .probe = dm9000_probe,
  1015. .remove = dm9000_drv_remove,
  1016. .suspend = dm9000_drv_suspend,
  1017. .resume = dm9000_drv_resume,
  1018. };
  1019. static int __init
  1020. dm9000_init(void)
  1021. {
  1022. printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION);
  1023. return platform_driver_register(&dm9000_driver); /* search board and register */
  1024. }
  1025. static void __exit
  1026. dm9000_cleanup(void)
  1027. {
  1028. platform_driver_unregister(&dm9000_driver);
  1029. }
  1030. module_init(dm9000_init);
  1031. module_exit(dm9000_cleanup);
  1032. MODULE_AUTHOR("Sascha Hauer, Ben Dooks");
  1033. MODULE_DESCRIPTION("Davicom DM9000 network driver");
  1034. MODULE_LICENSE("GPL");