bnx2x_sriov.c 69 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599
  1. /* bnx2x_sriov.c: Broadcom Everest network driver.
  2. *
  3. * Copyright 2009-2012 Broadcom Corporation
  4. *
  5. * Unless you and Broadcom execute a separate written software license
  6. * agreement governing use of this software, this software is licensed to you
  7. * under the terms of the GNU General Public License version 2, available
  8. * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
  9. *
  10. * Notwithstanding the above, under no circumstances may you combine this
  11. * software in any way with any other Broadcom software provided under a
  12. * license other than the GPL, without Broadcom's express prior written
  13. * consent.
  14. *
  15. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  16. * Written by: Shmulik Ravid <shmulikr@broadcom.com>
  17. * Ariel Elior <ariele@broadcom.com>
  18. *
  19. */
  20. #include "bnx2x.h"
  21. #include "bnx2x_init.h"
  22. #include "bnx2x_cmn.h"
  23. #include "bnx2x_sriov.h"
  24. /* General service functions */
  25. static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
  26. u16 pf_id)
  27. {
  28. REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
  29. pf_id);
  30. REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
  31. pf_id);
  32. REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
  33. pf_id);
  34. REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
  35. pf_id);
  36. }
  37. static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
  38. u8 enable)
  39. {
  40. REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
  41. enable);
  42. REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
  43. enable);
  44. REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
  45. enable);
  46. REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
  47. enable);
  48. }
  49. int bnx2x_vf_idx_by_abs_fid(struct bnx2x *bp, u16 abs_vfid)
  50. {
  51. int idx;
  52. for_each_vf(bp, idx)
  53. if (bnx2x_vf(bp, idx, abs_vfid) == abs_vfid)
  54. break;
  55. return idx;
  56. }
  57. static
  58. struct bnx2x_virtf *bnx2x_vf_by_abs_fid(struct bnx2x *bp, u16 abs_vfid)
  59. {
  60. u16 idx = (u16)bnx2x_vf_idx_by_abs_fid(bp, abs_vfid);
  61. return (idx < BNX2X_NR_VIRTFN(bp)) ? BP_VF(bp, idx) : NULL;
  62. }
  63. static void bnx2x_vf_igu_ack_sb(struct bnx2x *bp, struct bnx2x_virtf *vf,
  64. u8 igu_sb_id, u8 segment, u16 index, u8 op,
  65. u8 update)
  66. {
  67. /* acking a VF sb through the PF - use the GRC */
  68. u32 ctl;
  69. u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
  70. u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
  71. u32 func_encode = vf->abs_vfid;
  72. u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + igu_sb_id;
  73. struct igu_regular cmd_data = {0};
  74. cmd_data.sb_id_and_flags =
  75. ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
  76. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  77. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  78. (op << IGU_REGULAR_ENABLE_INT_SHIFT));
  79. ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
  80. func_encode << IGU_CTRL_REG_FID_SHIFT |
  81. IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
  82. DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
  83. cmd_data.sb_id_and_flags, igu_addr_data);
  84. REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags);
  85. mmiowb();
  86. barrier();
  87. DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
  88. ctl, igu_addr_ctl);
  89. REG_WR(bp, igu_addr_ctl, ctl);
  90. mmiowb();
  91. barrier();
  92. }
  93. /* VFOP - VF slow-path operation support */
  94. #define BNX2X_VFOP_FILTER_ADD_CNT_MAX 0x10000
  95. /* VFOP operations states */
  96. enum bnx2x_vfop_qctor_state {
  97. BNX2X_VFOP_QCTOR_INIT,
  98. BNX2X_VFOP_QCTOR_SETUP,
  99. BNX2X_VFOP_QCTOR_INT_EN
  100. };
  101. enum bnx2x_vfop_qdtor_state {
  102. BNX2X_VFOP_QDTOR_HALT,
  103. BNX2X_VFOP_QDTOR_TERMINATE,
  104. BNX2X_VFOP_QDTOR_CFCDEL,
  105. BNX2X_VFOP_QDTOR_DONE
  106. };
  107. enum bnx2x_vfop_vlan_mac_state {
  108. BNX2X_VFOP_VLAN_MAC_CONFIG_SINGLE,
  109. BNX2X_VFOP_VLAN_MAC_CLEAR,
  110. BNX2X_VFOP_VLAN_MAC_CHK_DONE,
  111. BNX2X_VFOP_MAC_CONFIG_LIST,
  112. BNX2X_VFOP_VLAN_CONFIG_LIST,
  113. BNX2X_VFOP_VLAN_CONFIG_LIST_0
  114. };
  115. enum bnx2x_vfop_qsetup_state {
  116. BNX2X_VFOP_QSETUP_CTOR,
  117. BNX2X_VFOP_QSETUP_VLAN0,
  118. BNX2X_VFOP_QSETUP_DONE
  119. };
  120. enum bnx2x_vfop_mcast_state {
  121. BNX2X_VFOP_MCAST_DEL,
  122. BNX2X_VFOP_MCAST_ADD,
  123. BNX2X_VFOP_MCAST_CHK_DONE
  124. };
  125. enum bnx2x_vfop_close_state {
  126. BNX2X_VFOP_CLOSE_QUEUES,
  127. BNX2X_VFOP_CLOSE_HW
  128. };
  129. enum bnx2x_vfop_rxmode_state {
  130. BNX2X_VFOP_RXMODE_CONFIG,
  131. BNX2X_VFOP_RXMODE_DONE
  132. };
  133. enum bnx2x_vfop_qteardown_state {
  134. BNX2X_VFOP_QTEARDOWN_RXMODE,
  135. BNX2X_VFOP_QTEARDOWN_CLR_VLAN,
  136. BNX2X_VFOP_QTEARDOWN_CLR_MAC,
  137. BNX2X_VFOP_QTEARDOWN_QDTOR,
  138. BNX2X_VFOP_QTEARDOWN_DONE
  139. };
  140. #define bnx2x_vfop_reset_wq(vf) atomic_set(&vf->op_in_progress, 0)
  141. void bnx2x_vfop_qctor_dump_tx(struct bnx2x *bp, struct bnx2x_virtf *vf,
  142. struct bnx2x_queue_init_params *init_params,
  143. struct bnx2x_queue_setup_params *setup_params,
  144. u16 q_idx, u16 sb_idx)
  145. {
  146. DP(BNX2X_MSG_IOV,
  147. "VF[%d] Q_SETUP: txq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, flags=0x%lx, traffic-type=%d",
  148. vf->abs_vfid,
  149. q_idx,
  150. sb_idx,
  151. init_params->tx.sb_cq_index,
  152. init_params->tx.hc_rate,
  153. setup_params->flags,
  154. setup_params->txq_params.traffic_type);
  155. }
  156. void bnx2x_vfop_qctor_dump_rx(struct bnx2x *bp, struct bnx2x_virtf *vf,
  157. struct bnx2x_queue_init_params *init_params,
  158. struct bnx2x_queue_setup_params *setup_params,
  159. u16 q_idx, u16 sb_idx)
  160. {
  161. struct bnx2x_rxq_setup_params *rxq_params = &setup_params->rxq_params;
  162. DP(BNX2X_MSG_IOV, "VF[%d] Q_SETUP: rxq[%d]-- vfsb=%d, sb-index=%d, hc-rate=%d, mtu=%d, buf-size=%d\n"
  163. "sge-size=%d, max_sge_pkt=%d, tpa-agg-size=%d, flags=0x%lx, drop-flags=0x%x, cache-log=%d\n",
  164. vf->abs_vfid,
  165. q_idx,
  166. sb_idx,
  167. init_params->rx.sb_cq_index,
  168. init_params->rx.hc_rate,
  169. setup_params->gen_params.mtu,
  170. rxq_params->buf_sz,
  171. rxq_params->sge_buf_sz,
  172. rxq_params->max_sges_pkt,
  173. rxq_params->tpa_agg_sz,
  174. setup_params->flags,
  175. rxq_params->drop_flags,
  176. rxq_params->cache_line_log);
  177. }
  178. void bnx2x_vfop_qctor_prep(struct bnx2x *bp,
  179. struct bnx2x_virtf *vf,
  180. struct bnx2x_vf_queue *q,
  181. struct bnx2x_vfop_qctor_params *p,
  182. unsigned long q_type)
  183. {
  184. struct bnx2x_queue_init_params *init_p = &p->qstate.params.init;
  185. struct bnx2x_queue_setup_params *setup_p = &p->prep_qsetup;
  186. /* INIT */
  187. /* Enable host coalescing in the transition to INIT state */
  188. if (test_bit(BNX2X_Q_FLG_HC, &init_p->rx.flags))
  189. __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->rx.flags);
  190. if (test_bit(BNX2X_Q_FLG_HC, &init_p->tx.flags))
  191. __set_bit(BNX2X_Q_FLG_HC_EN, &init_p->tx.flags);
  192. /* FW SB ID */
  193. init_p->rx.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
  194. init_p->tx.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
  195. /* context */
  196. init_p->cxts[0] = q->cxt;
  197. /* SETUP */
  198. /* Setup-op general parameters */
  199. setup_p->gen_params.spcl_id = vf->sp_cl_id;
  200. setup_p->gen_params.stat_id = vfq_stat_id(vf, q);
  201. /* Setup-op pause params:
  202. * Nothing to do, the pause thresholds are set by default to 0 which
  203. * effectively turns off the feature for this queue. We don't want
  204. * one queue (VF) to interfering with another queue (another VF)
  205. */
  206. if (vf->cfg_flags & VF_CFG_FW_FC)
  207. BNX2X_ERR("No support for pause to VFs (abs_vfid: %d)\n",
  208. vf->abs_vfid);
  209. /* Setup-op flags:
  210. * collect statistics, zero statistics, local-switching, security,
  211. * OV for Flex10, RSS and MCAST for leading
  212. */
  213. if (test_bit(BNX2X_Q_FLG_STATS, &setup_p->flags))
  214. __set_bit(BNX2X_Q_FLG_ZERO_STATS, &setup_p->flags);
  215. /* for VFs, enable tx switching, bd coherency, and mac address
  216. * anti-spoofing
  217. */
  218. __set_bit(BNX2X_Q_FLG_TX_SWITCH, &setup_p->flags);
  219. __set_bit(BNX2X_Q_FLG_TX_SEC, &setup_p->flags);
  220. __set_bit(BNX2X_Q_FLG_ANTI_SPOOF, &setup_p->flags);
  221. if (vfq_is_leading(q)) {
  222. __set_bit(BNX2X_Q_FLG_LEADING_RSS, &setup_p->flags);
  223. __set_bit(BNX2X_Q_FLG_MCAST, &setup_p->flags);
  224. }
  225. /* Setup-op rx parameters */
  226. if (test_bit(BNX2X_Q_TYPE_HAS_RX, &q_type)) {
  227. struct bnx2x_rxq_setup_params *rxq_p = &setup_p->rxq_params;
  228. rxq_p->cl_qzone_id = vfq_qzone_id(vf, q);
  229. rxq_p->fw_sb_id = vf_igu_sb(vf, q->sb_idx);
  230. rxq_p->rss_engine_id = FW_VF_HANDLE(vf->abs_vfid);
  231. if (test_bit(BNX2X_Q_FLG_TPA, &setup_p->flags))
  232. rxq_p->max_tpa_queues = BNX2X_VF_MAX_TPA_AGG_QUEUES;
  233. }
  234. /* Setup-op tx parameters */
  235. if (test_bit(BNX2X_Q_TYPE_HAS_TX, &q_type)) {
  236. setup_p->txq_params.tss_leading_cl_id = vf->leading_rss;
  237. setup_p->txq_params.fw_sb_id = vf_igu_sb(vf, q->sb_idx);
  238. }
  239. }
  240. /* VFOP queue construction */
  241. static void bnx2x_vfop_qctor(struct bnx2x *bp, struct bnx2x_virtf *vf)
  242. {
  243. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  244. struct bnx2x_vfop_args_qctor *args = &vfop->args.qctor;
  245. struct bnx2x_queue_state_params *q_params = &vfop->op_p->qctor.qstate;
  246. enum bnx2x_vfop_qctor_state state = vfop->state;
  247. bnx2x_vfop_reset_wq(vf);
  248. if (vfop->rc < 0)
  249. goto op_err;
  250. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  251. switch (state) {
  252. case BNX2X_VFOP_QCTOR_INIT:
  253. /* has this queue already been opened? */
  254. if (bnx2x_get_q_logical_state(bp, q_params->q_obj) ==
  255. BNX2X_Q_LOGICAL_STATE_ACTIVE) {
  256. DP(BNX2X_MSG_IOV,
  257. "Entered qctor but queue was already up. Aborting gracefully\n");
  258. goto op_done;
  259. }
  260. /* next state */
  261. vfop->state = BNX2X_VFOP_QCTOR_SETUP;
  262. q_params->cmd = BNX2X_Q_CMD_INIT;
  263. vfop->rc = bnx2x_queue_state_change(bp, q_params);
  264. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  265. case BNX2X_VFOP_QCTOR_SETUP:
  266. /* next state */
  267. vfop->state = BNX2X_VFOP_QCTOR_INT_EN;
  268. /* copy pre-prepared setup params to the queue-state params */
  269. vfop->op_p->qctor.qstate.params.setup =
  270. vfop->op_p->qctor.prep_qsetup;
  271. q_params->cmd = BNX2X_Q_CMD_SETUP;
  272. vfop->rc = bnx2x_queue_state_change(bp, q_params);
  273. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  274. case BNX2X_VFOP_QCTOR_INT_EN:
  275. /* enable interrupts */
  276. bnx2x_vf_igu_ack_sb(bp, vf, vf_igu_sb(vf, args->sb_idx),
  277. USTORM_ID, 0, IGU_INT_ENABLE, 0);
  278. goto op_done;
  279. default:
  280. bnx2x_vfop_default(state);
  281. }
  282. op_err:
  283. BNX2X_ERR("QCTOR[%d:%d] error: cmd %d, rc %d\n",
  284. vf->abs_vfid, args->qid, q_params->cmd, vfop->rc);
  285. op_done:
  286. bnx2x_vfop_end(bp, vf, vfop);
  287. op_pending:
  288. return;
  289. }
  290. static int bnx2x_vfop_qctor_cmd(struct bnx2x *bp,
  291. struct bnx2x_virtf *vf,
  292. struct bnx2x_vfop_cmd *cmd,
  293. int qid)
  294. {
  295. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  296. if (vfop) {
  297. vf->op_params.qctor.qstate.q_obj = &bnx2x_vfq(vf, qid, sp_obj);
  298. vfop->args.qctor.qid = qid;
  299. vfop->args.qctor.sb_idx = bnx2x_vfq(vf, qid, sb_idx);
  300. bnx2x_vfop_opset(BNX2X_VFOP_QCTOR_INIT,
  301. bnx2x_vfop_qctor, cmd->done);
  302. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_qctor,
  303. cmd->block);
  304. }
  305. return -ENOMEM;
  306. }
  307. /* VFOP queue destruction */
  308. static void bnx2x_vfop_qdtor(struct bnx2x *bp, struct bnx2x_virtf *vf)
  309. {
  310. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  311. struct bnx2x_vfop_args_qdtor *qdtor = &vfop->args.qdtor;
  312. struct bnx2x_queue_state_params *q_params = &vfop->op_p->qctor.qstate;
  313. enum bnx2x_vfop_qdtor_state state = vfop->state;
  314. bnx2x_vfop_reset_wq(vf);
  315. if (vfop->rc < 0)
  316. goto op_err;
  317. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  318. switch (state) {
  319. case BNX2X_VFOP_QDTOR_HALT:
  320. /* has this queue already been stopped? */
  321. if (bnx2x_get_q_logical_state(bp, q_params->q_obj) ==
  322. BNX2X_Q_LOGICAL_STATE_STOPPED) {
  323. DP(BNX2X_MSG_IOV,
  324. "Entered qdtor but queue was already stopped. Aborting gracefully\n");
  325. goto op_done;
  326. }
  327. /* next state */
  328. vfop->state = BNX2X_VFOP_QDTOR_TERMINATE;
  329. q_params->cmd = BNX2X_Q_CMD_HALT;
  330. vfop->rc = bnx2x_queue_state_change(bp, q_params);
  331. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  332. case BNX2X_VFOP_QDTOR_TERMINATE:
  333. /* next state */
  334. vfop->state = BNX2X_VFOP_QDTOR_CFCDEL;
  335. q_params->cmd = BNX2X_Q_CMD_TERMINATE;
  336. vfop->rc = bnx2x_queue_state_change(bp, q_params);
  337. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  338. case BNX2X_VFOP_QDTOR_CFCDEL:
  339. /* next state */
  340. vfop->state = BNX2X_VFOP_QDTOR_DONE;
  341. q_params->cmd = BNX2X_Q_CMD_CFC_DEL;
  342. vfop->rc = bnx2x_queue_state_change(bp, q_params);
  343. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  344. op_err:
  345. BNX2X_ERR("QDTOR[%d:%d] error: cmd %d, rc %d\n",
  346. vf->abs_vfid, qdtor->qid, q_params->cmd, vfop->rc);
  347. op_done:
  348. case BNX2X_VFOP_QDTOR_DONE:
  349. /* invalidate the context */
  350. qdtor->cxt->ustorm_ag_context.cdu_usage = 0;
  351. qdtor->cxt->xstorm_ag_context.cdu_reserved = 0;
  352. bnx2x_vfop_end(bp, vf, vfop);
  353. return;
  354. default:
  355. bnx2x_vfop_default(state);
  356. }
  357. op_pending:
  358. return;
  359. }
  360. static int bnx2x_vfop_qdtor_cmd(struct bnx2x *bp,
  361. struct bnx2x_virtf *vf,
  362. struct bnx2x_vfop_cmd *cmd,
  363. int qid)
  364. {
  365. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  366. if (vfop) {
  367. struct bnx2x_queue_state_params *qstate =
  368. &vf->op_params.qctor.qstate;
  369. memset(qstate, 0, sizeof(*qstate));
  370. qstate->q_obj = &bnx2x_vfq(vf, qid, sp_obj);
  371. vfop->args.qdtor.qid = qid;
  372. vfop->args.qdtor.cxt = bnx2x_vfq(vf, qid, cxt);
  373. bnx2x_vfop_opset(BNX2X_VFOP_QDTOR_HALT,
  374. bnx2x_vfop_qdtor, cmd->done);
  375. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_qdtor,
  376. cmd->block);
  377. }
  378. DP(BNX2X_MSG_IOV, "VF[%d] failed to add a vfop. rc %d\n",
  379. vf->abs_vfid, vfop->rc);
  380. return -ENOMEM;
  381. }
  382. static void
  383. bnx2x_vf_set_igu_info(struct bnx2x *bp, u8 igu_sb_id, u8 abs_vfid)
  384. {
  385. struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
  386. if (vf) {
  387. if (!vf_sb_count(vf))
  388. vf->igu_base_id = igu_sb_id;
  389. ++vf_sb_count(vf);
  390. }
  391. }
  392. /* VFOP MAC/VLAN helpers */
  393. static inline void bnx2x_vfop_credit(struct bnx2x *bp,
  394. struct bnx2x_vfop *vfop,
  395. struct bnx2x_vlan_mac_obj *obj)
  396. {
  397. struct bnx2x_vfop_args_filters *args = &vfop->args.filters;
  398. /* update credit only if there is no error
  399. * and a valid credit counter
  400. */
  401. if (!vfop->rc && args->credit) {
  402. int cnt = 0;
  403. struct list_head *pos;
  404. list_for_each(pos, &obj->head)
  405. cnt++;
  406. atomic_set(args->credit, cnt);
  407. }
  408. }
  409. static int bnx2x_vfop_set_user_req(struct bnx2x *bp,
  410. struct bnx2x_vfop_filter *pos,
  411. struct bnx2x_vlan_mac_data *user_req)
  412. {
  413. user_req->cmd = pos->add ? BNX2X_VLAN_MAC_ADD :
  414. BNX2X_VLAN_MAC_DEL;
  415. switch (pos->type) {
  416. case BNX2X_VFOP_FILTER_MAC:
  417. memcpy(user_req->u.mac.mac, pos->mac, ETH_ALEN);
  418. break;
  419. case BNX2X_VFOP_FILTER_VLAN:
  420. user_req->u.vlan.vlan = pos->vid;
  421. break;
  422. default:
  423. BNX2X_ERR("Invalid filter type, skipping\n");
  424. return 1;
  425. }
  426. return 0;
  427. }
  428. static int
  429. bnx2x_vfop_config_vlan0(struct bnx2x *bp,
  430. struct bnx2x_vlan_mac_ramrod_params *vlan_mac,
  431. bool add)
  432. {
  433. int rc;
  434. vlan_mac->user_req.cmd = add ? BNX2X_VLAN_MAC_ADD :
  435. BNX2X_VLAN_MAC_DEL;
  436. vlan_mac->user_req.u.vlan.vlan = 0;
  437. rc = bnx2x_config_vlan_mac(bp, vlan_mac);
  438. if (rc == -EEXIST)
  439. rc = 0;
  440. return rc;
  441. }
  442. static int bnx2x_vfop_config_list(struct bnx2x *bp,
  443. struct bnx2x_vfop_filters *filters,
  444. struct bnx2x_vlan_mac_ramrod_params *vlan_mac)
  445. {
  446. struct bnx2x_vfop_filter *pos, *tmp;
  447. struct list_head rollback_list, *filters_list = &filters->head;
  448. struct bnx2x_vlan_mac_data *user_req = &vlan_mac->user_req;
  449. int rc = 0, cnt = 0;
  450. INIT_LIST_HEAD(&rollback_list);
  451. list_for_each_entry_safe(pos, tmp, filters_list, link) {
  452. if (bnx2x_vfop_set_user_req(bp, pos, user_req))
  453. continue;
  454. rc = bnx2x_config_vlan_mac(bp, vlan_mac);
  455. if (rc >= 0) {
  456. cnt += pos->add ? 1 : -1;
  457. list_del(&pos->link);
  458. list_add(&pos->link, &rollback_list);
  459. rc = 0;
  460. } else if (rc == -EEXIST) {
  461. rc = 0;
  462. } else {
  463. BNX2X_ERR("Failed to add a new vlan_mac command\n");
  464. break;
  465. }
  466. }
  467. /* rollback if error or too many rules added */
  468. if (rc || cnt > filters->add_cnt) {
  469. BNX2X_ERR("error or too many rules added. Performing rollback\n");
  470. list_for_each_entry_safe(pos, tmp, &rollback_list, link) {
  471. pos->add = !pos->add; /* reverse op */
  472. bnx2x_vfop_set_user_req(bp, pos, user_req);
  473. bnx2x_config_vlan_mac(bp, vlan_mac);
  474. list_del(&pos->link);
  475. }
  476. cnt = 0;
  477. if (!rc)
  478. rc = -EINVAL;
  479. }
  480. filters->add_cnt = cnt;
  481. return rc;
  482. }
  483. /* VFOP set VLAN/MAC */
  484. static void bnx2x_vfop_vlan_mac(struct bnx2x *bp, struct bnx2x_virtf *vf)
  485. {
  486. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  487. struct bnx2x_vlan_mac_ramrod_params *vlan_mac = &vfop->op_p->vlan_mac;
  488. struct bnx2x_vlan_mac_obj *obj = vlan_mac->vlan_mac_obj;
  489. struct bnx2x_vfop_filters *filters = vfop->args.filters.multi_filter;
  490. enum bnx2x_vfop_vlan_mac_state state = vfop->state;
  491. if (vfop->rc < 0)
  492. goto op_err;
  493. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  494. bnx2x_vfop_reset_wq(vf);
  495. switch (state) {
  496. case BNX2X_VFOP_VLAN_MAC_CLEAR:
  497. /* next state */
  498. vfop->state = BNX2X_VFOP_VLAN_MAC_CHK_DONE;
  499. /* do delete */
  500. vfop->rc = obj->delete_all(bp, obj,
  501. &vlan_mac->user_req.vlan_mac_flags,
  502. &vlan_mac->ramrod_flags);
  503. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  504. case BNX2X_VFOP_VLAN_MAC_CONFIG_SINGLE:
  505. /* next state */
  506. vfop->state = BNX2X_VFOP_VLAN_MAC_CHK_DONE;
  507. /* do config */
  508. vfop->rc = bnx2x_config_vlan_mac(bp, vlan_mac);
  509. if (vfop->rc == -EEXIST)
  510. vfop->rc = 0;
  511. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  512. case BNX2X_VFOP_VLAN_MAC_CHK_DONE:
  513. vfop->rc = !!obj->raw.check_pending(&obj->raw);
  514. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  515. case BNX2X_VFOP_MAC_CONFIG_LIST:
  516. /* next state */
  517. vfop->state = BNX2X_VFOP_VLAN_MAC_CHK_DONE;
  518. /* do list config */
  519. vfop->rc = bnx2x_vfop_config_list(bp, filters, vlan_mac);
  520. if (vfop->rc)
  521. goto op_err;
  522. set_bit(RAMROD_CONT, &vlan_mac->ramrod_flags);
  523. vfop->rc = bnx2x_config_vlan_mac(bp, vlan_mac);
  524. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  525. case BNX2X_VFOP_VLAN_CONFIG_LIST:
  526. /* next state */
  527. vfop->state = BNX2X_VFOP_VLAN_CONFIG_LIST_0;
  528. /* remove vlan0 - could be no-op */
  529. vfop->rc = bnx2x_vfop_config_vlan0(bp, vlan_mac, false);
  530. if (vfop->rc)
  531. goto op_err;
  532. /* Do vlan list config. if this operation fails we try to
  533. * restore vlan0 to keep the queue is working order
  534. */
  535. vfop->rc = bnx2x_vfop_config_list(bp, filters, vlan_mac);
  536. if (!vfop->rc) {
  537. set_bit(RAMROD_CONT, &vlan_mac->ramrod_flags);
  538. vfop->rc = bnx2x_config_vlan_mac(bp, vlan_mac);
  539. }
  540. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT); /* fall-through */
  541. case BNX2X_VFOP_VLAN_CONFIG_LIST_0:
  542. /* next state */
  543. vfop->state = BNX2X_VFOP_VLAN_MAC_CHK_DONE;
  544. if (list_empty(&obj->head))
  545. /* add vlan0 */
  546. vfop->rc = bnx2x_vfop_config_vlan0(bp, vlan_mac, true);
  547. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  548. default:
  549. bnx2x_vfop_default(state);
  550. }
  551. op_err:
  552. BNX2X_ERR("VLAN-MAC error: rc %d\n", vfop->rc);
  553. op_done:
  554. kfree(filters);
  555. bnx2x_vfop_credit(bp, vfop, obj);
  556. bnx2x_vfop_end(bp, vf, vfop);
  557. op_pending:
  558. return;
  559. }
  560. struct bnx2x_vfop_vlan_mac_flags {
  561. bool drv_only;
  562. bool dont_consume;
  563. bool single_cmd;
  564. bool add;
  565. };
  566. static void
  567. bnx2x_vfop_vlan_mac_prep_ramrod(struct bnx2x_vlan_mac_ramrod_params *ramrod,
  568. struct bnx2x_vfop_vlan_mac_flags *flags)
  569. {
  570. struct bnx2x_vlan_mac_data *ureq = &ramrod->user_req;
  571. memset(ramrod, 0, sizeof(*ramrod));
  572. /* ramrod flags */
  573. if (flags->drv_only)
  574. set_bit(RAMROD_DRV_CLR_ONLY, &ramrod->ramrod_flags);
  575. if (flags->single_cmd)
  576. set_bit(RAMROD_EXEC, &ramrod->ramrod_flags);
  577. /* mac_vlan flags */
  578. if (flags->dont_consume)
  579. set_bit(BNX2X_DONT_CONSUME_CAM_CREDIT, &ureq->vlan_mac_flags);
  580. /* cmd */
  581. ureq->cmd = flags->add ? BNX2X_VLAN_MAC_ADD : BNX2X_VLAN_MAC_DEL;
  582. }
  583. static inline void
  584. bnx2x_vfop_mac_prep_ramrod(struct bnx2x_vlan_mac_ramrod_params *ramrod,
  585. struct bnx2x_vfop_vlan_mac_flags *flags)
  586. {
  587. bnx2x_vfop_vlan_mac_prep_ramrod(ramrod, flags);
  588. set_bit(BNX2X_ETH_MAC, &ramrod->user_req.vlan_mac_flags);
  589. }
  590. static int bnx2x_vfop_mac_delall_cmd(struct bnx2x *bp,
  591. struct bnx2x_virtf *vf,
  592. struct bnx2x_vfop_cmd *cmd,
  593. int qid, bool drv_only)
  594. {
  595. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  596. if (vfop) {
  597. struct bnx2x_vfop_args_filters filters = {
  598. .multi_filter = NULL, /* single */
  599. .credit = NULL, /* consume credit */
  600. };
  601. struct bnx2x_vfop_vlan_mac_flags flags = {
  602. .drv_only = drv_only,
  603. .dont_consume = (filters.credit != NULL),
  604. .single_cmd = true,
  605. .add = false /* don't care */,
  606. };
  607. struct bnx2x_vlan_mac_ramrod_params *ramrod =
  608. &vf->op_params.vlan_mac;
  609. /* set ramrod params */
  610. bnx2x_vfop_mac_prep_ramrod(ramrod, &flags);
  611. /* set object */
  612. ramrod->vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj);
  613. /* set extra args */
  614. vfop->args.filters = filters;
  615. bnx2x_vfop_opset(BNX2X_VFOP_VLAN_MAC_CLEAR,
  616. bnx2x_vfop_vlan_mac, cmd->done);
  617. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_vlan_mac,
  618. cmd->block);
  619. }
  620. return -ENOMEM;
  621. }
  622. int bnx2x_vfop_mac_list_cmd(struct bnx2x *bp,
  623. struct bnx2x_virtf *vf,
  624. struct bnx2x_vfop_cmd *cmd,
  625. struct bnx2x_vfop_filters *macs,
  626. int qid, bool drv_only)
  627. {
  628. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  629. if (vfop) {
  630. struct bnx2x_vfop_args_filters filters = {
  631. .multi_filter = macs,
  632. .credit = NULL, /* consume credit */
  633. };
  634. struct bnx2x_vfop_vlan_mac_flags flags = {
  635. .drv_only = drv_only,
  636. .dont_consume = (filters.credit != NULL),
  637. .single_cmd = false,
  638. .add = false, /* don't care since only the items in the
  639. * filters list affect the sp operation,
  640. * not the list itself
  641. */
  642. };
  643. struct bnx2x_vlan_mac_ramrod_params *ramrod =
  644. &vf->op_params.vlan_mac;
  645. /* set ramrod params */
  646. bnx2x_vfop_mac_prep_ramrod(ramrod, &flags);
  647. /* set object */
  648. ramrod->vlan_mac_obj = &bnx2x_vfq(vf, qid, mac_obj);
  649. /* set extra args */
  650. filters.multi_filter->add_cnt = BNX2X_VFOP_FILTER_ADD_CNT_MAX;
  651. vfop->args.filters = filters;
  652. bnx2x_vfop_opset(BNX2X_VFOP_MAC_CONFIG_LIST,
  653. bnx2x_vfop_vlan_mac, cmd->done);
  654. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_vlan_mac,
  655. cmd->block);
  656. }
  657. return -ENOMEM;
  658. }
  659. int bnx2x_vfop_vlan_set_cmd(struct bnx2x *bp,
  660. struct bnx2x_virtf *vf,
  661. struct bnx2x_vfop_cmd *cmd,
  662. int qid, u16 vid, bool add)
  663. {
  664. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  665. if (vfop) {
  666. struct bnx2x_vfop_args_filters filters = {
  667. .multi_filter = NULL, /* single command */
  668. .credit = &bnx2x_vfq(vf, qid, vlan_count),
  669. };
  670. struct bnx2x_vfop_vlan_mac_flags flags = {
  671. .drv_only = false,
  672. .dont_consume = (filters.credit != NULL),
  673. .single_cmd = true,
  674. .add = add,
  675. };
  676. struct bnx2x_vlan_mac_ramrod_params *ramrod =
  677. &vf->op_params.vlan_mac;
  678. /* set ramrod params */
  679. bnx2x_vfop_vlan_mac_prep_ramrod(ramrod, &flags);
  680. ramrod->user_req.u.vlan.vlan = vid;
  681. /* set object */
  682. ramrod->vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
  683. /* set extra args */
  684. vfop->args.filters = filters;
  685. bnx2x_vfop_opset(BNX2X_VFOP_VLAN_MAC_CONFIG_SINGLE,
  686. bnx2x_vfop_vlan_mac, cmd->done);
  687. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_vlan_mac,
  688. cmd->block);
  689. }
  690. return -ENOMEM;
  691. }
  692. static int bnx2x_vfop_vlan_delall_cmd(struct bnx2x *bp,
  693. struct bnx2x_virtf *vf,
  694. struct bnx2x_vfop_cmd *cmd,
  695. int qid, bool drv_only)
  696. {
  697. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  698. if (vfop) {
  699. struct bnx2x_vfop_args_filters filters = {
  700. .multi_filter = NULL, /* single command */
  701. .credit = &bnx2x_vfq(vf, qid, vlan_count),
  702. };
  703. struct bnx2x_vfop_vlan_mac_flags flags = {
  704. .drv_only = drv_only,
  705. .dont_consume = (filters.credit != NULL),
  706. .single_cmd = true,
  707. .add = false, /* don't care */
  708. };
  709. struct bnx2x_vlan_mac_ramrod_params *ramrod =
  710. &vf->op_params.vlan_mac;
  711. /* set ramrod params */
  712. bnx2x_vfop_vlan_mac_prep_ramrod(ramrod, &flags);
  713. /* set object */
  714. ramrod->vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
  715. /* set extra args */
  716. vfop->args.filters = filters;
  717. bnx2x_vfop_opset(BNX2X_VFOP_VLAN_MAC_CLEAR,
  718. bnx2x_vfop_vlan_mac, cmd->done);
  719. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_vlan_mac,
  720. cmd->block);
  721. }
  722. return -ENOMEM;
  723. }
  724. int bnx2x_vfop_vlan_list_cmd(struct bnx2x *bp,
  725. struct bnx2x_virtf *vf,
  726. struct bnx2x_vfop_cmd *cmd,
  727. struct bnx2x_vfop_filters *vlans,
  728. int qid, bool drv_only)
  729. {
  730. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  731. if (vfop) {
  732. struct bnx2x_vfop_args_filters filters = {
  733. .multi_filter = vlans,
  734. .credit = &bnx2x_vfq(vf, qid, vlan_count),
  735. };
  736. struct bnx2x_vfop_vlan_mac_flags flags = {
  737. .drv_only = drv_only,
  738. .dont_consume = (filters.credit != NULL),
  739. .single_cmd = false,
  740. .add = false, /* don't care */
  741. };
  742. struct bnx2x_vlan_mac_ramrod_params *ramrod =
  743. &vf->op_params.vlan_mac;
  744. /* set ramrod params */
  745. bnx2x_vfop_vlan_mac_prep_ramrod(ramrod, &flags);
  746. /* set object */
  747. ramrod->vlan_mac_obj = &bnx2x_vfq(vf, qid, vlan_obj);
  748. /* set extra args */
  749. filters.multi_filter->add_cnt = vf_vlan_rules_cnt(vf) -
  750. atomic_read(filters.credit);
  751. vfop->args.filters = filters;
  752. bnx2x_vfop_opset(BNX2X_VFOP_VLAN_CONFIG_LIST,
  753. bnx2x_vfop_vlan_mac, cmd->done);
  754. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_vlan_mac,
  755. cmd->block);
  756. }
  757. return -ENOMEM;
  758. }
  759. /* VFOP queue setup (queue constructor + set vlan 0) */
  760. static void bnx2x_vfop_qsetup(struct bnx2x *bp, struct bnx2x_virtf *vf)
  761. {
  762. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  763. int qid = vfop->args.qctor.qid;
  764. enum bnx2x_vfop_qsetup_state state = vfop->state;
  765. struct bnx2x_vfop_cmd cmd = {
  766. .done = bnx2x_vfop_qsetup,
  767. .block = false,
  768. };
  769. if (vfop->rc < 0)
  770. goto op_err;
  771. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  772. switch (state) {
  773. case BNX2X_VFOP_QSETUP_CTOR:
  774. /* init the queue ctor command */
  775. vfop->state = BNX2X_VFOP_QSETUP_VLAN0;
  776. vfop->rc = bnx2x_vfop_qctor_cmd(bp, vf, &cmd, qid);
  777. if (vfop->rc)
  778. goto op_err;
  779. return;
  780. case BNX2X_VFOP_QSETUP_VLAN0:
  781. /* skip if non-leading or FPGA/EMU*/
  782. if (qid)
  783. goto op_done;
  784. /* init the queue set-vlan command (for vlan 0) */
  785. vfop->state = BNX2X_VFOP_QSETUP_DONE;
  786. vfop->rc = bnx2x_vfop_vlan_set_cmd(bp, vf, &cmd, qid, 0, true);
  787. if (vfop->rc)
  788. goto op_err;
  789. return;
  790. op_err:
  791. BNX2X_ERR("QSETUP[%d:%d] error: rc %d\n", vf->abs_vfid, qid, vfop->rc);
  792. op_done:
  793. case BNX2X_VFOP_QSETUP_DONE:
  794. bnx2x_vfop_end(bp, vf, vfop);
  795. return;
  796. default:
  797. bnx2x_vfop_default(state);
  798. }
  799. }
  800. int bnx2x_vfop_qsetup_cmd(struct bnx2x *bp,
  801. struct bnx2x_virtf *vf,
  802. struct bnx2x_vfop_cmd *cmd,
  803. int qid)
  804. {
  805. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  806. if (vfop) {
  807. vfop->args.qctor.qid = qid;
  808. bnx2x_vfop_opset(BNX2X_VFOP_QSETUP_CTOR,
  809. bnx2x_vfop_qsetup, cmd->done);
  810. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_qsetup,
  811. cmd->block);
  812. }
  813. return -ENOMEM;
  814. }
  815. /* VFOP multi-casts */
  816. static void bnx2x_vfop_mcast(struct bnx2x *bp, struct bnx2x_virtf *vf)
  817. {
  818. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  819. struct bnx2x_mcast_ramrod_params *mcast = &vfop->op_p->mcast;
  820. struct bnx2x_raw_obj *raw = &mcast->mcast_obj->raw;
  821. struct bnx2x_vfop_args_mcast *args = &vfop->args.mc_list;
  822. enum bnx2x_vfop_mcast_state state = vfop->state;
  823. int i;
  824. bnx2x_vfop_reset_wq(vf);
  825. if (vfop->rc < 0)
  826. goto op_err;
  827. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  828. switch (state) {
  829. case BNX2X_VFOP_MCAST_DEL:
  830. /* clear existing mcasts */
  831. vfop->state = BNX2X_VFOP_MCAST_ADD;
  832. vfop->rc = bnx2x_config_mcast(bp, mcast, BNX2X_MCAST_CMD_DEL);
  833. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_CONT);
  834. case BNX2X_VFOP_MCAST_ADD:
  835. if (raw->check_pending(raw))
  836. goto op_pending;
  837. if (args->mc_num) {
  838. /* update mcast list on the ramrod params */
  839. INIT_LIST_HEAD(&mcast->mcast_list);
  840. for (i = 0; i < args->mc_num; i++)
  841. list_add_tail(&(args->mc[i].link),
  842. &mcast->mcast_list);
  843. /* add new mcasts */
  844. vfop->state = BNX2X_VFOP_MCAST_CHK_DONE;
  845. vfop->rc = bnx2x_config_mcast(bp, mcast,
  846. BNX2X_MCAST_CMD_ADD);
  847. }
  848. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  849. case BNX2X_VFOP_MCAST_CHK_DONE:
  850. vfop->rc = raw->check_pending(raw) ? 1 : 0;
  851. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  852. default:
  853. bnx2x_vfop_default(state);
  854. }
  855. op_err:
  856. BNX2X_ERR("MCAST CONFIG error: rc %d\n", vfop->rc);
  857. op_done:
  858. kfree(args->mc);
  859. bnx2x_vfop_end(bp, vf, vfop);
  860. op_pending:
  861. return;
  862. }
  863. int bnx2x_vfop_mcast_cmd(struct bnx2x *bp,
  864. struct bnx2x_virtf *vf,
  865. struct bnx2x_vfop_cmd *cmd,
  866. bnx2x_mac_addr_t *mcasts,
  867. int mcast_num, bool drv_only)
  868. {
  869. struct bnx2x_vfop *vfop = NULL;
  870. size_t mc_sz = mcast_num * sizeof(struct bnx2x_mcast_list_elem);
  871. struct bnx2x_mcast_list_elem *mc = mc_sz ? kzalloc(mc_sz, GFP_KERNEL) :
  872. NULL;
  873. if (!mc_sz || mc) {
  874. vfop = bnx2x_vfop_add(bp, vf);
  875. if (vfop) {
  876. int i;
  877. struct bnx2x_mcast_ramrod_params *ramrod =
  878. &vf->op_params.mcast;
  879. /* set ramrod params */
  880. memset(ramrod, 0, sizeof(*ramrod));
  881. ramrod->mcast_obj = &vf->mcast_obj;
  882. if (drv_only)
  883. set_bit(RAMROD_DRV_CLR_ONLY,
  884. &ramrod->ramrod_flags);
  885. /* copy mcasts pointers */
  886. vfop->args.mc_list.mc_num = mcast_num;
  887. vfop->args.mc_list.mc = mc;
  888. for (i = 0; i < mcast_num; i++)
  889. mc[i].mac = mcasts[i];
  890. bnx2x_vfop_opset(BNX2X_VFOP_MCAST_DEL,
  891. bnx2x_vfop_mcast, cmd->done);
  892. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_mcast,
  893. cmd->block);
  894. } else {
  895. kfree(mc);
  896. }
  897. }
  898. return -ENOMEM;
  899. }
  900. /* VFOP rx-mode */
  901. static void bnx2x_vfop_rxmode(struct bnx2x *bp, struct bnx2x_virtf *vf)
  902. {
  903. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  904. struct bnx2x_rx_mode_ramrod_params *ramrod = &vfop->op_p->rx_mode;
  905. enum bnx2x_vfop_rxmode_state state = vfop->state;
  906. bnx2x_vfop_reset_wq(vf);
  907. if (vfop->rc < 0)
  908. goto op_err;
  909. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  910. switch (state) {
  911. case BNX2X_VFOP_RXMODE_CONFIG:
  912. /* next state */
  913. vfop->state = BNX2X_VFOP_RXMODE_DONE;
  914. vfop->rc = bnx2x_config_rx_mode(bp, ramrod);
  915. bnx2x_vfop_finalize(vf, vfop->rc, VFOP_DONE);
  916. op_err:
  917. BNX2X_ERR("RXMODE error: rc %d\n", vfop->rc);
  918. op_done:
  919. case BNX2X_VFOP_RXMODE_DONE:
  920. bnx2x_vfop_end(bp, vf, vfop);
  921. return;
  922. default:
  923. bnx2x_vfop_default(state);
  924. }
  925. op_pending:
  926. return;
  927. }
  928. int bnx2x_vfop_rxmode_cmd(struct bnx2x *bp,
  929. struct bnx2x_virtf *vf,
  930. struct bnx2x_vfop_cmd *cmd,
  931. int qid, unsigned long accept_flags)
  932. {
  933. struct bnx2x_vf_queue *vfq = vfq_get(vf, qid);
  934. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  935. if (vfop) {
  936. struct bnx2x_rx_mode_ramrod_params *ramrod =
  937. &vf->op_params.rx_mode;
  938. memset(ramrod, 0, sizeof(*ramrod));
  939. /* Prepare ramrod parameters */
  940. ramrod->cid = vfq->cid;
  941. ramrod->cl_id = vfq_cl_id(vf, vfq);
  942. ramrod->rx_mode_obj = &bp->rx_mode_obj;
  943. ramrod->func_id = FW_VF_HANDLE(vf->abs_vfid);
  944. ramrod->rx_accept_flags = accept_flags;
  945. ramrod->tx_accept_flags = accept_flags;
  946. ramrod->pstate = &vf->filter_state;
  947. ramrod->state = BNX2X_FILTER_RX_MODE_PENDING;
  948. set_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state);
  949. set_bit(RAMROD_RX, &ramrod->ramrod_flags);
  950. set_bit(RAMROD_TX, &ramrod->ramrod_flags);
  951. ramrod->rdata =
  952. bnx2x_vf_sp(bp, vf, rx_mode_rdata.e2);
  953. ramrod->rdata_mapping =
  954. bnx2x_vf_sp_map(bp, vf, rx_mode_rdata.e2);
  955. bnx2x_vfop_opset(BNX2X_VFOP_RXMODE_CONFIG,
  956. bnx2x_vfop_rxmode, cmd->done);
  957. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_rxmode,
  958. cmd->block);
  959. }
  960. return -ENOMEM;
  961. }
  962. /* VFOP queue tear-down ('drop all' rx-mode, clear vlans, clear macs,
  963. * queue destructor)
  964. */
  965. static void bnx2x_vfop_qdown(struct bnx2x *bp, struct bnx2x_virtf *vf)
  966. {
  967. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  968. int qid = vfop->args.qx.qid;
  969. enum bnx2x_vfop_qteardown_state state = vfop->state;
  970. struct bnx2x_vfop_cmd cmd;
  971. if (vfop->rc < 0)
  972. goto op_err;
  973. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  974. cmd.done = bnx2x_vfop_qdown;
  975. cmd.block = false;
  976. switch (state) {
  977. case BNX2X_VFOP_QTEARDOWN_RXMODE:
  978. /* Drop all */
  979. vfop->state = BNX2X_VFOP_QTEARDOWN_CLR_VLAN;
  980. vfop->rc = bnx2x_vfop_rxmode_cmd(bp, vf, &cmd, qid, 0);
  981. if (vfop->rc)
  982. goto op_err;
  983. return;
  984. case BNX2X_VFOP_QTEARDOWN_CLR_VLAN:
  985. /* vlan-clear-all: don't consume credit */
  986. vfop->state = BNX2X_VFOP_QTEARDOWN_CLR_MAC;
  987. vfop->rc = bnx2x_vfop_vlan_delall_cmd(bp, vf, &cmd, qid, false);
  988. if (vfop->rc)
  989. goto op_err;
  990. return;
  991. case BNX2X_VFOP_QTEARDOWN_CLR_MAC:
  992. /* mac-clear-all: consume credit */
  993. vfop->state = BNX2X_VFOP_QTEARDOWN_QDTOR;
  994. vfop->rc = bnx2x_vfop_mac_delall_cmd(bp, vf, &cmd, qid, false);
  995. if (vfop->rc)
  996. goto op_err;
  997. return;
  998. case BNX2X_VFOP_QTEARDOWN_QDTOR:
  999. /* run the queue destruction flow */
  1000. DP(BNX2X_MSG_IOV, "case: BNX2X_VFOP_QTEARDOWN_QDTOR\n");
  1001. vfop->state = BNX2X_VFOP_QTEARDOWN_DONE;
  1002. DP(BNX2X_MSG_IOV, "new state: BNX2X_VFOP_QTEARDOWN_DONE\n");
  1003. vfop->rc = bnx2x_vfop_qdtor_cmd(bp, vf, &cmd, qid);
  1004. DP(BNX2X_MSG_IOV, "returned from cmd\n");
  1005. if (vfop->rc)
  1006. goto op_err;
  1007. return;
  1008. op_err:
  1009. BNX2X_ERR("QTEARDOWN[%d:%d] error: rc %d\n",
  1010. vf->abs_vfid, qid, vfop->rc);
  1011. case BNX2X_VFOP_QTEARDOWN_DONE:
  1012. bnx2x_vfop_end(bp, vf, vfop);
  1013. return;
  1014. default:
  1015. bnx2x_vfop_default(state);
  1016. }
  1017. }
  1018. int bnx2x_vfop_qdown_cmd(struct bnx2x *bp,
  1019. struct bnx2x_virtf *vf,
  1020. struct bnx2x_vfop_cmd *cmd,
  1021. int qid)
  1022. {
  1023. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  1024. if (vfop) {
  1025. vfop->args.qx.qid = qid;
  1026. bnx2x_vfop_opset(BNX2X_VFOP_QTEARDOWN_RXMODE,
  1027. bnx2x_vfop_qdown, cmd->done);
  1028. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_qdown,
  1029. cmd->block);
  1030. }
  1031. return -ENOMEM;
  1032. }
  1033. /* VF enable primitives
  1034. * when pretend is required the caller is responsible
  1035. * for calling pretend prior to calling these routines
  1036. */
  1037. /* called only on E1H or E2.
  1038. * When pretending to be PF, the pretend value is the function number 0...7
  1039. * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
  1040. * combination
  1041. */
  1042. int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
  1043. {
  1044. u32 pretend_reg;
  1045. if (CHIP_IS_E1H(bp) && pretend_func_val > E1H_FUNC_MAX)
  1046. return -1;
  1047. /* get my own pretend register */
  1048. pretend_reg = bnx2x_get_pretend_reg(bp);
  1049. REG_WR(bp, pretend_reg, pretend_func_val);
  1050. REG_RD(bp, pretend_reg);
  1051. return 0;
  1052. }
  1053. /* internal vf enable - until vf is enabled internally all transactions
  1054. * are blocked. this routine should always be called last with pretend.
  1055. */
  1056. static void bnx2x_vf_enable_internal(struct bnx2x *bp, u8 enable)
  1057. {
  1058. REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0);
  1059. }
  1060. /* clears vf error in all semi blocks */
  1061. static void bnx2x_vf_semi_clear_err(struct bnx2x *bp, u8 abs_vfid)
  1062. {
  1063. REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid);
  1064. REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid);
  1065. REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid);
  1066. REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid);
  1067. }
  1068. static void bnx2x_vf_pglue_clear_err(struct bnx2x *bp, u8 abs_vfid)
  1069. {
  1070. u32 was_err_group = (2 * BP_PATH(bp) + abs_vfid) >> 5;
  1071. u32 was_err_reg = 0;
  1072. switch (was_err_group) {
  1073. case 0:
  1074. was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR;
  1075. break;
  1076. case 1:
  1077. was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR;
  1078. break;
  1079. case 2:
  1080. was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR;
  1081. break;
  1082. case 3:
  1083. was_err_reg = PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR;
  1084. break;
  1085. }
  1086. REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f));
  1087. }
  1088. static void bnx2x_vf_igu_reset(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1089. {
  1090. int i;
  1091. u32 val;
  1092. /* Set VF masks and configuration - pretend */
  1093. bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
  1094. REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
  1095. REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
  1096. REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
  1097. REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
  1098. REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
  1099. REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
  1100. val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
  1101. val |= (IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_MSI_MSIX_EN);
  1102. if (vf->cfg_flags & VF_CFG_INT_SIMD)
  1103. val |= IGU_VF_CONF_SINGLE_ISR_EN;
  1104. val &= ~IGU_VF_CONF_PARENT_MASK;
  1105. val |= BP_FUNC(bp) << IGU_VF_CONF_PARENT_SHIFT; /* parent PF */
  1106. REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);
  1107. DP(BNX2X_MSG_IOV,
  1108. "value in IGU_REG_VF_CONFIGURATION of vf %d after write %x\n",
  1109. vf->abs_vfid, REG_RD(bp, IGU_REG_VF_CONFIGURATION));
  1110. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  1111. /* iterate over all queues, clear sb consumer */
  1112. for (i = 0; i < vf_sb_count(vf); i++) {
  1113. u8 igu_sb_id = vf_igu_sb(vf, i);
  1114. /* zero prod memory */
  1115. REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0);
  1116. /* clear sb state machine */
  1117. bnx2x_igu_clear_sb_gen(bp, vf->abs_vfid, igu_sb_id,
  1118. false /* VF */);
  1119. /* disable + update */
  1120. bnx2x_vf_igu_ack_sb(bp, vf, igu_sb_id, USTORM_ID, 0,
  1121. IGU_INT_DISABLE, 1);
  1122. }
  1123. }
  1124. void bnx2x_vf_enable_access(struct bnx2x *bp, u8 abs_vfid)
  1125. {
  1126. /* set the VF-PF association in the FW */
  1127. storm_memset_vf_to_pf(bp, FW_VF_HANDLE(abs_vfid), BP_FUNC(bp));
  1128. storm_memset_func_en(bp, FW_VF_HANDLE(abs_vfid), 1);
  1129. /* clear vf errors*/
  1130. bnx2x_vf_semi_clear_err(bp, abs_vfid);
  1131. bnx2x_vf_pglue_clear_err(bp, abs_vfid);
  1132. /* internal vf-enable - pretend */
  1133. bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, abs_vfid));
  1134. DP(BNX2X_MSG_IOV, "enabling internal access for vf %x\n", abs_vfid);
  1135. bnx2x_vf_enable_internal(bp, true);
  1136. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  1137. }
  1138. static void bnx2x_vf_enable_traffic(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1139. {
  1140. /* Reset vf in IGU interrupts are still disabled */
  1141. bnx2x_vf_igu_reset(bp, vf);
  1142. /* pretend to enable the vf with the PBF */
  1143. bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
  1144. REG_WR(bp, PBF_REG_DISABLE_VF, 0);
  1145. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  1146. }
  1147. static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid)
  1148. {
  1149. struct pci_dev *dev;
  1150. struct bnx2x_virtf *vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
  1151. if (!vf)
  1152. goto unknown_dev;
  1153. dev = pci_get_bus_and_slot(vf->bus, vf->devfn);
  1154. if (dev)
  1155. return bnx2x_is_pcie_pending(dev);
  1156. unknown_dev:
  1157. BNX2X_ERR("Unknown device\n");
  1158. return false;
  1159. }
  1160. int bnx2x_vf_flr_clnup_epilog(struct bnx2x *bp, u8 abs_vfid)
  1161. {
  1162. /* Wait 100ms */
  1163. msleep(100);
  1164. /* Verify no pending pci transactions */
  1165. if (bnx2x_vf_is_pcie_pending(bp, abs_vfid))
  1166. BNX2X_ERR("PCIE Transactions still pending\n");
  1167. return 0;
  1168. }
  1169. /* must be called after the number of PF queues and the number of VFs are
  1170. * both known
  1171. */
  1172. static void
  1173. bnx2x_iov_static_resc(struct bnx2x *bp, struct vf_pf_resc_request *resc)
  1174. {
  1175. u16 vlan_count = 0;
  1176. /* will be set only during VF-ACQUIRE */
  1177. resc->num_rxqs = 0;
  1178. resc->num_txqs = 0;
  1179. /* no credit calculcis for macs (just yet) */
  1180. resc->num_mac_filters = 1;
  1181. /* divvy up vlan rules */
  1182. vlan_count = bp->vlans_pool.check(&bp->vlans_pool);
  1183. vlan_count = 1 << ilog2(vlan_count);
  1184. resc->num_vlan_filters = vlan_count / BNX2X_NR_VIRTFN(bp);
  1185. /* no real limitation */
  1186. resc->num_mc_filters = 0;
  1187. /* num_sbs already set */
  1188. }
  1189. /* IOV global initialization routines */
  1190. void bnx2x_iov_init_dq(struct bnx2x *bp)
  1191. {
  1192. if (!IS_SRIOV(bp))
  1193. return;
  1194. /* Set the DQ such that the CID reflect the abs_vfid */
  1195. REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0);
  1196. REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS));
  1197. /* Set VFs starting CID. If its > 0 the preceding CIDs are belong to
  1198. * the PF L2 queues
  1199. */
  1200. REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID);
  1201. /* The VF window size is the log2 of the max number of CIDs per VF */
  1202. REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND);
  1203. /* The VF doorbell size 0 - *B, 4 - 128B. We set it here to match
  1204. * the Pf doorbell size although the 2 are independent.
  1205. */
  1206. REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST,
  1207. BNX2X_DB_SHIFT - BNX2X_DB_MIN_SHIFT);
  1208. /* No security checks for now -
  1209. * configure single rule (out of 16) mask = 0x1, value = 0x0,
  1210. * CID range 0 - 0x1ffff
  1211. */
  1212. REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1);
  1213. REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0);
  1214. REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);
  1215. REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);
  1216. /* set the number of VF alllowed doorbells to the full DQ range */
  1217. REG_WR(bp, DORQ_REG_VF_NORM_MAX_CID_COUNT, 0x20000);
  1218. /* set the VF doorbell threshold */
  1219. REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 4);
  1220. }
  1221. void bnx2x_iov_init_dmae(struct bnx2x *bp)
  1222. {
  1223. DP(BNX2X_MSG_IOV, "SRIOV is %s\n", IS_SRIOV(bp) ? "ON" : "OFF");
  1224. if (!IS_SRIOV(bp))
  1225. return;
  1226. REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0);
  1227. }
  1228. static int bnx2x_vf_bus(struct bnx2x *bp, int vfid)
  1229. {
  1230. struct pci_dev *dev = bp->pdev;
  1231. struct bnx2x_sriov *iov = &bp->vfdb->sriov;
  1232. return dev->bus->number + ((dev->devfn + iov->offset +
  1233. iov->stride * vfid) >> 8);
  1234. }
  1235. static int bnx2x_vf_devfn(struct bnx2x *bp, int vfid)
  1236. {
  1237. struct pci_dev *dev = bp->pdev;
  1238. struct bnx2x_sriov *iov = &bp->vfdb->sriov;
  1239. return (dev->devfn + iov->offset + iov->stride * vfid) & 0xff;
  1240. }
  1241. static void bnx2x_vf_set_bars(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1242. {
  1243. int i, n;
  1244. struct pci_dev *dev = bp->pdev;
  1245. struct bnx2x_sriov *iov = &bp->vfdb->sriov;
  1246. for (i = 0, n = 0; i < PCI_SRIOV_NUM_BARS; i += 2, n++) {
  1247. u64 start = pci_resource_start(dev, PCI_IOV_RESOURCES + i);
  1248. u32 size = pci_resource_len(dev, PCI_IOV_RESOURCES + i);
  1249. do_div(size, iov->total);
  1250. vf->bars[n].bar = start + size * vf->abs_vfid;
  1251. vf->bars[n].size = size;
  1252. }
  1253. }
  1254. static int bnx2x_ari_enabled(struct pci_dev *dev)
  1255. {
  1256. return dev->bus->self && dev->bus->self->ari_enabled;
  1257. }
  1258. static void
  1259. bnx2x_get_vf_igu_cam_info(struct bnx2x *bp)
  1260. {
  1261. int sb_id;
  1262. u32 val;
  1263. u8 fid;
  1264. /* IGU in normal mode - read CAM */
  1265. for (sb_id = 0; sb_id < IGU_REG_MAPPING_MEMORY_SIZE; sb_id++) {
  1266. val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + sb_id * 4);
  1267. if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
  1268. continue;
  1269. fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID);
  1270. if (!(fid & IGU_FID_ENCODE_IS_PF))
  1271. bnx2x_vf_set_igu_info(bp, sb_id,
  1272. (fid & IGU_FID_VF_NUM_MASK));
  1273. DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n",
  1274. ((fid & IGU_FID_ENCODE_IS_PF) ? "PF" : "VF"),
  1275. ((fid & IGU_FID_ENCODE_IS_PF) ? (fid & IGU_FID_PF_NUM_MASK) :
  1276. (fid & IGU_FID_VF_NUM_MASK)), sb_id,
  1277. GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR));
  1278. }
  1279. }
  1280. static void __bnx2x_iov_free_vfdb(struct bnx2x *bp)
  1281. {
  1282. if (bp->vfdb) {
  1283. kfree(bp->vfdb->vfqs);
  1284. kfree(bp->vfdb->vfs);
  1285. kfree(bp->vfdb);
  1286. }
  1287. bp->vfdb = NULL;
  1288. }
  1289. static int bnx2x_sriov_pci_cfg_info(struct bnx2x *bp, struct bnx2x_sriov *iov)
  1290. {
  1291. int pos;
  1292. struct pci_dev *dev = bp->pdev;
  1293. pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
  1294. if (!pos) {
  1295. BNX2X_ERR("failed to find SRIOV capability in device\n");
  1296. return -ENODEV;
  1297. }
  1298. iov->pos = pos;
  1299. DP(BNX2X_MSG_IOV, "sriov ext pos %d\n", pos);
  1300. pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &iov->ctrl);
  1301. pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &iov->total);
  1302. pci_read_config_word(dev, pos + PCI_SRIOV_INITIAL_VF, &iov->initial);
  1303. pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &iov->offset);
  1304. pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &iov->stride);
  1305. pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &iov->pgsz);
  1306. pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
  1307. pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
  1308. return 0;
  1309. }
  1310. static int bnx2x_sriov_info(struct bnx2x *bp, struct bnx2x_sriov *iov)
  1311. {
  1312. u32 val;
  1313. /* read the SRIOV capability structure
  1314. * The fields can be read via configuration read or
  1315. * directly from the device (starting at offset PCICFG_OFFSET)
  1316. */
  1317. if (bnx2x_sriov_pci_cfg_info(bp, iov))
  1318. return -ENODEV;
  1319. /* get the number of SRIOV bars */
  1320. iov->nres = 0;
  1321. /* read the first_vfid */
  1322. val = REG_RD(bp, PCICFG_OFFSET + GRC_CONFIG_REG_PF_INIT_VF);
  1323. iov->first_vf_in_pf = ((val & GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK)
  1324. * 8) - (BNX2X_MAX_NUM_OF_VFS * BP_PATH(bp));
  1325. DP(BNX2X_MSG_IOV,
  1326. "IOV info[%d]: first vf %d, nres %d, cap 0x%x, ctrl 0x%x, total %d, initial %d, num vfs %d, offset %d, stride %d, page size 0x%x\n",
  1327. BP_FUNC(bp),
  1328. iov->first_vf_in_pf, iov->nres, iov->cap, iov->ctrl, iov->total,
  1329. iov->initial, iov->nr_virtfn, iov->offset, iov->stride, iov->pgsz);
  1330. return 0;
  1331. }
  1332. static u8 bnx2x_iov_get_max_queue_count(struct bnx2x *bp)
  1333. {
  1334. int i;
  1335. u8 queue_count = 0;
  1336. if (IS_SRIOV(bp))
  1337. for_each_vf(bp, i)
  1338. queue_count += bnx2x_vf(bp, i, alloc_resc.num_sbs);
  1339. return queue_count;
  1340. }
  1341. /* must be called after PF bars are mapped */
  1342. int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param,
  1343. int num_vfs_param)
  1344. {
  1345. int err, i, qcount;
  1346. struct bnx2x_sriov *iov;
  1347. struct pci_dev *dev = bp->pdev;
  1348. bp->vfdb = NULL;
  1349. /* verify is pf */
  1350. if (IS_VF(bp))
  1351. return 0;
  1352. /* verify sriov capability is present in configuration space */
  1353. if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV))
  1354. return 0;
  1355. /* verify chip revision */
  1356. if (CHIP_IS_E1x(bp))
  1357. return 0;
  1358. /* check if SRIOV support is turned off */
  1359. if (!num_vfs_param)
  1360. return 0;
  1361. /* SRIOV assumes that num of PF CIDs < BNX2X_FIRST_VF_CID */
  1362. if (BNX2X_L2_MAX_CID(bp) >= BNX2X_FIRST_VF_CID) {
  1363. BNX2X_ERR("PF cids %d are overspilling into vf space (starts at %d). Abort SRIOV\n",
  1364. BNX2X_L2_MAX_CID(bp), BNX2X_FIRST_VF_CID);
  1365. return 0;
  1366. }
  1367. /* SRIOV can be enabled only with MSIX */
  1368. if (int_mode_param == BNX2X_INT_MODE_MSI ||
  1369. int_mode_param == BNX2X_INT_MODE_INTX)
  1370. BNX2X_ERR("Forced MSI/INTx mode is incompatible with SRIOV\n");
  1371. err = -EIO;
  1372. /* verify ari is enabled */
  1373. if (!bnx2x_ari_enabled(bp->pdev)) {
  1374. BNX2X_ERR("ARI not supported, SRIOV can not be enabled\n");
  1375. return err;
  1376. }
  1377. /* verify igu is in normal mode */
  1378. if (CHIP_INT_MODE_IS_BC(bp)) {
  1379. BNX2X_ERR("IGU not normal mode, SRIOV can not be enabled\n");
  1380. return err;
  1381. }
  1382. /* allocate the vfs database */
  1383. bp->vfdb = kzalloc(sizeof(*(bp->vfdb)), GFP_KERNEL);
  1384. if (!bp->vfdb) {
  1385. BNX2X_ERR("failed to allocate vf database\n");
  1386. err = -ENOMEM;
  1387. goto failed;
  1388. }
  1389. /* get the sriov info - Linux already collected all the pertinent
  1390. * information, however the sriov structure is for the private use
  1391. * of the pci module. Also we want this information regardless
  1392. * of the hyper-visor.
  1393. */
  1394. iov = &(bp->vfdb->sriov);
  1395. err = bnx2x_sriov_info(bp, iov);
  1396. if (err)
  1397. goto failed;
  1398. /* SR-IOV capability was enabled but there are no VFs*/
  1399. if (iov->total == 0)
  1400. goto failed;
  1401. /* calculate the actual number of VFs */
  1402. iov->nr_virtfn = min_t(u16, iov->total, (u16)num_vfs_param);
  1403. /* allocate the vf array */
  1404. bp->vfdb->vfs = kzalloc(sizeof(struct bnx2x_virtf) *
  1405. BNX2X_NR_VIRTFN(bp), GFP_KERNEL);
  1406. if (!bp->vfdb->vfs) {
  1407. BNX2X_ERR("failed to allocate vf array\n");
  1408. err = -ENOMEM;
  1409. goto failed;
  1410. }
  1411. /* Initial VF init - index and abs_vfid - nr_virtfn must be set */
  1412. for_each_vf(bp, i) {
  1413. bnx2x_vf(bp, i, index) = i;
  1414. bnx2x_vf(bp, i, abs_vfid) = iov->first_vf_in_pf + i;
  1415. bnx2x_vf(bp, i, state) = VF_FREE;
  1416. INIT_LIST_HEAD(&bnx2x_vf(bp, i, op_list_head));
  1417. mutex_init(&bnx2x_vf(bp, i, op_mutex));
  1418. bnx2x_vf(bp, i, op_current) = CHANNEL_TLV_NONE;
  1419. }
  1420. /* re-read the IGU CAM for VFs - index and abs_vfid must be set */
  1421. bnx2x_get_vf_igu_cam_info(bp);
  1422. /* get the total queue count and allocate the global queue arrays */
  1423. qcount = bnx2x_iov_get_max_queue_count(bp);
  1424. /* allocate the queue arrays for all VFs */
  1425. bp->vfdb->vfqs = kzalloc(qcount * sizeof(struct bnx2x_vf_queue),
  1426. GFP_KERNEL);
  1427. if (!bp->vfdb->vfqs) {
  1428. BNX2X_ERR("failed to allocate vf queue array\n");
  1429. err = -ENOMEM;
  1430. goto failed;
  1431. }
  1432. return 0;
  1433. failed:
  1434. DP(BNX2X_MSG_IOV, "Failed err=%d\n", err);
  1435. __bnx2x_iov_free_vfdb(bp);
  1436. return err;
  1437. }
  1438. void bnx2x_iov_remove_one(struct bnx2x *bp)
  1439. {
  1440. /* if SRIOV is not enabled there's nothing to do */
  1441. if (!IS_SRIOV(bp))
  1442. return;
  1443. /* free vf database */
  1444. __bnx2x_iov_free_vfdb(bp);
  1445. }
  1446. void bnx2x_iov_free_mem(struct bnx2x *bp)
  1447. {
  1448. int i;
  1449. if (!IS_SRIOV(bp))
  1450. return;
  1451. /* free vfs hw contexts */
  1452. for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
  1453. struct hw_dma *cxt = &bp->vfdb->context[i];
  1454. BNX2X_PCI_FREE(cxt->addr, cxt->mapping, cxt->size);
  1455. }
  1456. BNX2X_PCI_FREE(BP_VFDB(bp)->sp_dma.addr,
  1457. BP_VFDB(bp)->sp_dma.mapping,
  1458. BP_VFDB(bp)->sp_dma.size);
  1459. BNX2X_PCI_FREE(BP_VF_MBX_DMA(bp)->addr,
  1460. BP_VF_MBX_DMA(bp)->mapping,
  1461. BP_VF_MBX_DMA(bp)->size);
  1462. }
  1463. int bnx2x_iov_alloc_mem(struct bnx2x *bp)
  1464. {
  1465. size_t tot_size;
  1466. int i, rc = 0;
  1467. if (!IS_SRIOV(bp))
  1468. return rc;
  1469. /* allocate vfs hw contexts */
  1470. tot_size = (BP_VFDB(bp)->sriov.first_vf_in_pf + BNX2X_NR_VIRTFN(bp)) *
  1471. BNX2X_CIDS_PER_VF * sizeof(union cdu_context);
  1472. for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
  1473. struct hw_dma *cxt = BP_VF_CXT_PAGE(bp, i);
  1474. cxt->size = min_t(size_t, tot_size, CDU_ILT_PAGE_SZ);
  1475. if (cxt->size) {
  1476. BNX2X_PCI_ALLOC(cxt->addr, &cxt->mapping, cxt->size);
  1477. } else {
  1478. cxt->addr = NULL;
  1479. cxt->mapping = 0;
  1480. }
  1481. tot_size -= cxt->size;
  1482. }
  1483. /* allocate vfs ramrods dma memory - client_init and set_mac */
  1484. tot_size = BNX2X_NR_VIRTFN(bp) * sizeof(struct bnx2x_vf_sp);
  1485. BNX2X_PCI_ALLOC(BP_VFDB(bp)->sp_dma.addr, &BP_VFDB(bp)->sp_dma.mapping,
  1486. tot_size);
  1487. BP_VFDB(bp)->sp_dma.size = tot_size;
  1488. /* allocate mailboxes */
  1489. tot_size = BNX2X_NR_VIRTFN(bp) * MBX_MSG_ALIGNED_SIZE;
  1490. BNX2X_PCI_ALLOC(BP_VF_MBX_DMA(bp)->addr, &BP_VF_MBX_DMA(bp)->mapping,
  1491. tot_size);
  1492. BP_VF_MBX_DMA(bp)->size = tot_size;
  1493. return 0;
  1494. alloc_mem_err:
  1495. return -ENOMEM;
  1496. }
  1497. static void bnx2x_vfq_init(struct bnx2x *bp, struct bnx2x_virtf *vf,
  1498. struct bnx2x_vf_queue *q)
  1499. {
  1500. u8 cl_id = vfq_cl_id(vf, q);
  1501. u8 func_id = FW_VF_HANDLE(vf->abs_vfid);
  1502. unsigned long q_type = 0;
  1503. set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
  1504. set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
  1505. /* Queue State object */
  1506. bnx2x_init_queue_obj(bp, &q->sp_obj,
  1507. cl_id, &q->cid, 1, func_id,
  1508. bnx2x_vf_sp(bp, vf, q_data),
  1509. bnx2x_vf_sp_map(bp, vf, q_data),
  1510. q_type);
  1511. DP(BNX2X_MSG_IOV,
  1512. "initialized vf %d's queue object. func id set to %d\n",
  1513. vf->abs_vfid, q->sp_obj.func_id);
  1514. /* mac/vlan objects are per queue, but only those
  1515. * that belong to the leading queue are initialized
  1516. */
  1517. if (vfq_is_leading(q)) {
  1518. /* mac */
  1519. bnx2x_init_mac_obj(bp, &q->mac_obj,
  1520. cl_id, q->cid, func_id,
  1521. bnx2x_vf_sp(bp, vf, mac_rdata),
  1522. bnx2x_vf_sp_map(bp, vf, mac_rdata),
  1523. BNX2X_FILTER_MAC_PENDING,
  1524. &vf->filter_state,
  1525. BNX2X_OBJ_TYPE_RX_TX,
  1526. &bp->macs_pool);
  1527. /* vlan */
  1528. bnx2x_init_vlan_obj(bp, &q->vlan_obj,
  1529. cl_id, q->cid, func_id,
  1530. bnx2x_vf_sp(bp, vf, vlan_rdata),
  1531. bnx2x_vf_sp_map(bp, vf, vlan_rdata),
  1532. BNX2X_FILTER_VLAN_PENDING,
  1533. &vf->filter_state,
  1534. BNX2X_OBJ_TYPE_RX_TX,
  1535. &bp->vlans_pool);
  1536. /* mcast */
  1537. bnx2x_init_mcast_obj(bp, &vf->mcast_obj, cl_id,
  1538. q->cid, func_id, func_id,
  1539. bnx2x_vf_sp(bp, vf, mcast_rdata),
  1540. bnx2x_vf_sp_map(bp, vf, mcast_rdata),
  1541. BNX2X_FILTER_MCAST_PENDING,
  1542. &vf->filter_state,
  1543. BNX2X_OBJ_TYPE_RX_TX);
  1544. vf->leading_rss = cl_id;
  1545. }
  1546. }
  1547. /* called by bnx2x_nic_load */
  1548. int bnx2x_iov_nic_init(struct bnx2x *bp)
  1549. {
  1550. int vfid, qcount, i;
  1551. if (!IS_SRIOV(bp)) {
  1552. DP(BNX2X_MSG_IOV, "vfdb was not allocated\n");
  1553. return 0;
  1554. }
  1555. DP(BNX2X_MSG_IOV, "num of vfs: %d\n", (bp)->vfdb->sriov.nr_virtfn);
  1556. /* initialize vf database */
  1557. for_each_vf(bp, vfid) {
  1558. struct bnx2x_virtf *vf = BP_VF(bp, vfid);
  1559. int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vfid) *
  1560. BNX2X_CIDS_PER_VF;
  1561. union cdu_context *base_cxt = (union cdu_context *)
  1562. BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr +
  1563. (base_vf_cid & (ILT_PAGE_CIDS-1));
  1564. DP(BNX2X_MSG_IOV,
  1565. "VF[%d] Max IGU SBs: %d, base vf cid 0x%x, base cid 0x%x, base cxt %p\n",
  1566. vf->abs_vfid, vf_sb_count(vf), base_vf_cid,
  1567. BNX2X_FIRST_VF_CID + base_vf_cid, base_cxt);
  1568. /* init statically provisioned resources */
  1569. bnx2x_iov_static_resc(bp, &vf->alloc_resc);
  1570. /* queues are initialized during VF-ACQUIRE */
  1571. /* reserve the vf vlan credit */
  1572. bp->vlans_pool.get(&bp->vlans_pool, vf_vlan_rules_cnt(vf));
  1573. vf->filter_state = 0;
  1574. vf->sp_cl_id = bnx2x_fp(bp, 0, cl_id);
  1575. /* init mcast object - This object will be re-initialized
  1576. * during VF-ACQUIRE with the proper cl_id and cid.
  1577. * It needs to be initialized here so that it can be safely
  1578. * handled by a subsequent FLR flow.
  1579. */
  1580. bnx2x_init_mcast_obj(bp, &vf->mcast_obj, 0xFF,
  1581. 0xFF, 0xFF, 0xFF,
  1582. bnx2x_vf_sp(bp, vf, mcast_rdata),
  1583. bnx2x_vf_sp_map(bp, vf, mcast_rdata),
  1584. BNX2X_FILTER_MCAST_PENDING,
  1585. &vf->filter_state,
  1586. BNX2X_OBJ_TYPE_RX_TX);
  1587. /* set the mailbox message addresses */
  1588. BP_VF_MBX(bp, vfid)->msg = (struct bnx2x_vf_mbx_msg *)
  1589. (((u8 *)BP_VF_MBX_DMA(bp)->addr) + vfid *
  1590. MBX_MSG_ALIGNED_SIZE);
  1591. BP_VF_MBX(bp, vfid)->msg_mapping = BP_VF_MBX_DMA(bp)->mapping +
  1592. vfid * MBX_MSG_ALIGNED_SIZE;
  1593. /* Enable vf mailbox */
  1594. bnx2x_vf_enable_mbx(bp, vf->abs_vfid);
  1595. }
  1596. /* Final VF init */
  1597. qcount = 0;
  1598. for_each_vf(bp, i) {
  1599. struct bnx2x_virtf *vf = BP_VF(bp, i);
  1600. /* fill in the BDF and bars */
  1601. vf->bus = bnx2x_vf_bus(bp, i);
  1602. vf->devfn = bnx2x_vf_devfn(bp, i);
  1603. bnx2x_vf_set_bars(bp, vf);
  1604. DP(BNX2X_MSG_IOV,
  1605. "VF info[%d]: bus 0x%x, devfn 0x%x, bar0 [0x%x, %d], bar1 [0x%x, %d], bar2 [0x%x, %d]\n",
  1606. vf->abs_vfid, vf->bus, vf->devfn,
  1607. (unsigned)vf->bars[0].bar, vf->bars[0].size,
  1608. (unsigned)vf->bars[1].bar, vf->bars[1].size,
  1609. (unsigned)vf->bars[2].bar, vf->bars[2].size);
  1610. /* set local queue arrays */
  1611. vf->vfqs = &bp->vfdb->vfqs[qcount];
  1612. qcount += bnx2x_vf(bp, i, alloc_resc.num_sbs);
  1613. }
  1614. return 0;
  1615. }
  1616. /* called by bnx2x_init_hw_func, returns the next ilt line */
  1617. int bnx2x_iov_init_ilt(struct bnx2x *bp, u16 line)
  1618. {
  1619. int i;
  1620. struct bnx2x_ilt *ilt = BP_ILT(bp);
  1621. if (!IS_SRIOV(bp))
  1622. return line;
  1623. /* set vfs ilt lines */
  1624. for (i = 0; i < BNX2X_VF_CIDS/ILT_PAGE_CIDS; i++) {
  1625. struct hw_dma *hw_cxt = BP_VF_CXT_PAGE(bp, i);
  1626. ilt->lines[line+i].page = hw_cxt->addr;
  1627. ilt->lines[line+i].page_mapping = hw_cxt->mapping;
  1628. ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */
  1629. }
  1630. return line + i;
  1631. }
  1632. static u8 bnx2x_iov_is_vf_cid(struct bnx2x *bp, u16 cid)
  1633. {
  1634. return ((cid >= BNX2X_FIRST_VF_CID) &&
  1635. ((cid - BNX2X_FIRST_VF_CID) < BNX2X_VF_CIDS));
  1636. }
  1637. static
  1638. void bnx2x_vf_handle_classification_eqe(struct bnx2x *bp,
  1639. struct bnx2x_vf_queue *vfq,
  1640. union event_ring_elem *elem)
  1641. {
  1642. unsigned long ramrod_flags = 0;
  1643. int rc = 0;
  1644. /* Always push next commands out, don't wait here */
  1645. set_bit(RAMROD_CONT, &ramrod_flags);
  1646. switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
  1647. case BNX2X_FILTER_MAC_PENDING:
  1648. rc = vfq->mac_obj.complete(bp, &vfq->mac_obj, elem,
  1649. &ramrod_flags);
  1650. break;
  1651. case BNX2X_FILTER_VLAN_PENDING:
  1652. rc = vfq->vlan_obj.complete(bp, &vfq->vlan_obj, elem,
  1653. &ramrod_flags);
  1654. break;
  1655. default:
  1656. BNX2X_ERR("Unsupported classification command: %d\n",
  1657. elem->message.data.eth_event.echo);
  1658. return;
  1659. }
  1660. if (rc < 0)
  1661. BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
  1662. else if (rc > 0)
  1663. DP(BNX2X_MSG_IOV, "Scheduled next pending commands...\n");
  1664. }
  1665. static
  1666. void bnx2x_vf_handle_mcast_eqe(struct bnx2x *bp,
  1667. struct bnx2x_virtf *vf)
  1668. {
  1669. struct bnx2x_mcast_ramrod_params rparam = {NULL};
  1670. int rc;
  1671. rparam.mcast_obj = &vf->mcast_obj;
  1672. vf->mcast_obj.raw.clear_pending(&vf->mcast_obj.raw);
  1673. /* If there are pending mcast commands - send them */
  1674. if (vf->mcast_obj.check_pending(&vf->mcast_obj)) {
  1675. rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
  1676. if (rc < 0)
  1677. BNX2X_ERR("Failed to send pending mcast commands: %d\n",
  1678. rc);
  1679. }
  1680. }
  1681. static
  1682. void bnx2x_vf_handle_filters_eqe(struct bnx2x *bp,
  1683. struct bnx2x_virtf *vf)
  1684. {
  1685. smp_mb__before_clear_bit();
  1686. clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &vf->filter_state);
  1687. smp_mb__after_clear_bit();
  1688. }
  1689. int bnx2x_iov_eq_sp_event(struct bnx2x *bp, union event_ring_elem *elem)
  1690. {
  1691. struct bnx2x_virtf *vf;
  1692. int qidx = 0, abs_vfid;
  1693. u8 opcode;
  1694. u16 cid = 0xffff;
  1695. if (!IS_SRIOV(bp))
  1696. return 1;
  1697. /* first get the cid - the only events we handle here are cfc-delete
  1698. * and set-mac completion
  1699. */
  1700. opcode = elem->message.opcode;
  1701. switch (opcode) {
  1702. case EVENT_RING_OPCODE_CFC_DEL:
  1703. cid = SW_CID((__force __le32)
  1704. elem->message.data.cfc_del_event.cid);
  1705. DP(BNX2X_MSG_IOV, "checking cfc-del comp cid=%d\n", cid);
  1706. break;
  1707. case EVENT_RING_OPCODE_CLASSIFICATION_RULES:
  1708. case EVENT_RING_OPCODE_MULTICAST_RULES:
  1709. case EVENT_RING_OPCODE_FILTERS_RULES:
  1710. cid = (elem->message.data.eth_event.echo &
  1711. BNX2X_SWCID_MASK);
  1712. DP(BNX2X_MSG_IOV, "checking filtering comp cid=%d\n", cid);
  1713. break;
  1714. case EVENT_RING_OPCODE_VF_FLR:
  1715. abs_vfid = elem->message.data.vf_flr_event.vf_id;
  1716. DP(BNX2X_MSG_IOV, "Got VF FLR notification abs_vfid=%d\n",
  1717. abs_vfid);
  1718. goto get_vf;
  1719. case EVENT_RING_OPCODE_MALICIOUS_VF:
  1720. abs_vfid = elem->message.data.malicious_vf_event.vf_id;
  1721. DP(BNX2X_MSG_IOV, "Got VF MALICIOUS notification abs_vfid=%d\n",
  1722. abs_vfid);
  1723. goto get_vf;
  1724. default:
  1725. return 1;
  1726. }
  1727. /* check if the cid is the VF range */
  1728. if (!bnx2x_iov_is_vf_cid(bp, cid)) {
  1729. DP(BNX2X_MSG_IOV, "cid is outside vf range: %d\n", cid);
  1730. return 1;
  1731. }
  1732. /* extract vf and rxq index from vf_cid - relies on the following:
  1733. * 1. vfid on cid reflects the true abs_vfid
  1734. * 2. the max number of VFs (per path) is 64
  1735. */
  1736. qidx = cid & ((1 << BNX2X_VF_CID_WND)-1);
  1737. abs_vfid = (cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1);
  1738. get_vf:
  1739. vf = bnx2x_vf_by_abs_fid(bp, abs_vfid);
  1740. if (!vf) {
  1741. BNX2X_ERR("EQ completion for unknown VF, cid %d, abs_vfid %d\n",
  1742. cid, abs_vfid);
  1743. return 0;
  1744. }
  1745. switch (opcode) {
  1746. case EVENT_RING_OPCODE_CFC_DEL:
  1747. DP(BNX2X_MSG_IOV, "got VF [%d:%d] cfc delete ramrod\n",
  1748. vf->abs_vfid, qidx);
  1749. vfq_get(vf, qidx)->sp_obj.complete_cmd(bp,
  1750. &vfq_get(vf,
  1751. qidx)->sp_obj,
  1752. BNX2X_Q_CMD_CFC_DEL);
  1753. break;
  1754. case EVENT_RING_OPCODE_CLASSIFICATION_RULES:
  1755. DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mac/vlan ramrod\n",
  1756. vf->abs_vfid, qidx);
  1757. bnx2x_vf_handle_classification_eqe(bp, vfq_get(vf, qidx), elem);
  1758. break;
  1759. case EVENT_RING_OPCODE_MULTICAST_RULES:
  1760. DP(BNX2X_MSG_IOV, "got VF [%d:%d] set mcast ramrod\n",
  1761. vf->abs_vfid, qidx);
  1762. bnx2x_vf_handle_mcast_eqe(bp, vf);
  1763. break;
  1764. case EVENT_RING_OPCODE_FILTERS_RULES:
  1765. DP(BNX2X_MSG_IOV, "got VF [%d:%d] set rx-mode ramrod\n",
  1766. vf->abs_vfid, qidx);
  1767. bnx2x_vf_handle_filters_eqe(bp, vf);
  1768. break;
  1769. case EVENT_RING_OPCODE_VF_FLR:
  1770. DP(BNX2X_MSG_IOV, "got VF [%d] FLR notification\n",
  1771. vf->abs_vfid);
  1772. /* Do nothing for now */
  1773. break;
  1774. case EVENT_RING_OPCODE_MALICIOUS_VF:
  1775. DP(BNX2X_MSG_IOV, "got VF [%d] MALICIOUS notification\n",
  1776. vf->abs_vfid);
  1777. /* Do nothing for now */
  1778. break;
  1779. }
  1780. /* SRIOV: reschedule any 'in_progress' operations */
  1781. bnx2x_iov_sp_event(bp, cid, false);
  1782. return 0;
  1783. }
  1784. static struct bnx2x_virtf *bnx2x_vf_by_cid(struct bnx2x *bp, int vf_cid)
  1785. {
  1786. /* extract the vf from vf_cid - relies on the following:
  1787. * 1. vfid on cid reflects the true abs_vfid
  1788. * 2. the max number of VFs (per path) is 64
  1789. */
  1790. int abs_vfid = (vf_cid >> BNX2X_VF_CID_WND) & (BNX2X_MAX_NUM_OF_VFS-1);
  1791. return bnx2x_vf_by_abs_fid(bp, abs_vfid);
  1792. }
  1793. void bnx2x_iov_set_queue_sp_obj(struct bnx2x *bp, int vf_cid,
  1794. struct bnx2x_queue_sp_obj **q_obj)
  1795. {
  1796. struct bnx2x_virtf *vf;
  1797. if (!IS_SRIOV(bp))
  1798. return;
  1799. vf = bnx2x_vf_by_cid(bp, vf_cid);
  1800. if (vf) {
  1801. /* extract queue index from vf_cid - relies on the following:
  1802. * 1. vfid on cid reflects the true abs_vfid
  1803. * 2. the max number of VFs (per path) is 64
  1804. */
  1805. int q_index = vf_cid & ((1 << BNX2X_VF_CID_WND)-1);
  1806. *q_obj = &bnx2x_vfq(vf, q_index, sp_obj);
  1807. } else {
  1808. BNX2X_ERR("No vf matching cid %d\n", vf_cid);
  1809. }
  1810. }
  1811. void bnx2x_iov_sp_event(struct bnx2x *bp, int vf_cid, bool queue_work)
  1812. {
  1813. struct bnx2x_virtf *vf;
  1814. /* check if the cid is the VF range */
  1815. if (!IS_SRIOV(bp) || !bnx2x_iov_is_vf_cid(bp, vf_cid))
  1816. return;
  1817. vf = bnx2x_vf_by_cid(bp, vf_cid);
  1818. if (vf) {
  1819. /* set in_progress flag */
  1820. atomic_set(&vf->op_in_progress, 1);
  1821. if (queue_work)
  1822. queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
  1823. }
  1824. }
  1825. void bnx2x_iov_adjust_stats_req(struct bnx2x *bp)
  1826. {
  1827. int i;
  1828. int first_queue_query_index, num_queues_req;
  1829. dma_addr_t cur_data_offset;
  1830. struct stats_query_entry *cur_query_entry;
  1831. u8 stats_count = 0;
  1832. bool is_fcoe = false;
  1833. if (!IS_SRIOV(bp))
  1834. return;
  1835. if (!NO_FCOE(bp))
  1836. is_fcoe = true;
  1837. /* fcoe adds one global request and one queue request */
  1838. num_queues_req = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe;
  1839. first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX -
  1840. (is_fcoe ? 0 : 1);
  1841. DP(BNX2X_MSG_IOV,
  1842. "BNX2X_NUM_ETH_QUEUES %d, is_fcoe %d, first_queue_query_index %d => determined the last non virtual statistics query index is %d. Will add queries on top of that\n",
  1843. BNX2X_NUM_ETH_QUEUES(bp), is_fcoe, first_queue_query_index,
  1844. first_queue_query_index + num_queues_req);
  1845. cur_data_offset = bp->fw_stats_data_mapping +
  1846. offsetof(struct bnx2x_fw_stats_data, queue_stats) +
  1847. num_queues_req * sizeof(struct per_queue_stats);
  1848. cur_query_entry = &bp->fw_stats_req->
  1849. query[first_queue_query_index + num_queues_req];
  1850. for_each_vf(bp, i) {
  1851. int j;
  1852. struct bnx2x_virtf *vf = BP_VF(bp, i);
  1853. if (vf->state != VF_ENABLED) {
  1854. DP(BNX2X_MSG_IOV,
  1855. "vf %d not enabled so no stats for it\n",
  1856. vf->abs_vfid);
  1857. continue;
  1858. }
  1859. DP(BNX2X_MSG_IOV, "add addresses for vf %d\n", vf->abs_vfid);
  1860. for_each_vfq(vf, j) {
  1861. struct bnx2x_vf_queue *rxq = vfq_get(vf, j);
  1862. /* collect stats fro active queues only */
  1863. if (bnx2x_get_q_logical_state(bp, &rxq->sp_obj) ==
  1864. BNX2X_Q_LOGICAL_STATE_STOPPED)
  1865. continue;
  1866. /* create stats query entry for this queue */
  1867. cur_query_entry->kind = STATS_TYPE_QUEUE;
  1868. cur_query_entry->index = vfq_cl_id(vf, rxq);
  1869. cur_query_entry->funcID =
  1870. cpu_to_le16(FW_VF_HANDLE(vf->abs_vfid));
  1871. cur_query_entry->address.hi =
  1872. cpu_to_le32(U64_HI(vf->fw_stat_map));
  1873. cur_query_entry->address.lo =
  1874. cpu_to_le32(U64_LO(vf->fw_stat_map));
  1875. DP(BNX2X_MSG_IOV,
  1876. "added address %x %x for vf %d queue %d client %d\n",
  1877. cur_query_entry->address.hi,
  1878. cur_query_entry->address.lo, cur_query_entry->funcID,
  1879. j, cur_query_entry->index);
  1880. cur_query_entry++;
  1881. cur_data_offset += sizeof(struct per_queue_stats);
  1882. stats_count++;
  1883. }
  1884. }
  1885. bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count;
  1886. }
  1887. void bnx2x_iov_sp_task(struct bnx2x *bp)
  1888. {
  1889. int i;
  1890. if (!IS_SRIOV(bp))
  1891. return;
  1892. /* Iterate over all VFs and invoke state transition for VFs with
  1893. * 'in-progress' slow-path operations
  1894. */
  1895. DP(BNX2X_MSG_IOV, "searching for pending vf operations\n");
  1896. for_each_vf(bp, i) {
  1897. struct bnx2x_virtf *vf = BP_VF(bp, i);
  1898. if (!list_empty(&vf->op_list_head) &&
  1899. atomic_read(&vf->op_in_progress)) {
  1900. DP(BNX2X_MSG_IOV, "running pending op for vf %d\n", i);
  1901. bnx2x_vfop_cur(bp, vf)->transition(bp, vf);
  1902. }
  1903. }
  1904. }
  1905. static inline
  1906. struct bnx2x_virtf *__vf_from_stat_id(struct bnx2x *bp, u8 stat_id)
  1907. {
  1908. int i;
  1909. struct bnx2x_virtf *vf = NULL;
  1910. for_each_vf(bp, i) {
  1911. vf = BP_VF(bp, i);
  1912. if (stat_id >= vf->igu_base_id &&
  1913. stat_id < vf->igu_base_id + vf_sb_count(vf))
  1914. break;
  1915. }
  1916. return vf;
  1917. }
  1918. /* VF API helpers */
  1919. static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid,
  1920. u8 enable)
  1921. {
  1922. u32 reg = PXP_REG_HST_ZONE_PERMISSION_TABLE + qid * 4;
  1923. u32 val = enable ? (abs_vfid | (1 << 6)) : 0;
  1924. REG_WR(bp, reg, val);
  1925. }
  1926. static void bnx2x_vf_clr_qtbl(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1927. {
  1928. int i;
  1929. for_each_vfq(vf, i)
  1930. bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid,
  1931. vfq_qzone_id(vf, vfq_get(vf, i)), false);
  1932. }
  1933. static void bnx2x_vf_igu_disable(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1934. {
  1935. u32 val;
  1936. /* clear the VF configuration - pretend */
  1937. bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf->abs_vfid));
  1938. val = REG_RD(bp, IGU_REG_VF_CONFIGURATION);
  1939. val &= ~(IGU_VF_CONF_MSI_MSIX_EN | IGU_VF_CONF_SINGLE_ISR_EN |
  1940. IGU_VF_CONF_FUNC_EN | IGU_VF_CONF_PARENT_MASK);
  1941. REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);
  1942. bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
  1943. }
  1944. u8 bnx2x_vf_max_queue_cnt(struct bnx2x *bp, struct bnx2x_virtf *vf)
  1945. {
  1946. return min_t(u8, min_t(u8, vf_sb_count(vf), BNX2X_CIDS_PER_VF),
  1947. BNX2X_VF_MAX_QUEUES);
  1948. }
  1949. static
  1950. int bnx2x_vf_chk_avail_resc(struct bnx2x *bp, struct bnx2x_virtf *vf,
  1951. struct vf_pf_resc_request *req_resc)
  1952. {
  1953. u8 rxq_cnt = vf_rxq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf);
  1954. u8 txq_cnt = vf_txq_count(vf) ? : bnx2x_vf_max_queue_cnt(bp, vf);
  1955. return ((req_resc->num_rxqs <= rxq_cnt) &&
  1956. (req_resc->num_txqs <= txq_cnt) &&
  1957. (req_resc->num_sbs <= vf_sb_count(vf)) &&
  1958. (req_resc->num_mac_filters <= vf_mac_rules_cnt(vf)) &&
  1959. (req_resc->num_vlan_filters <= vf_vlan_rules_cnt(vf)));
  1960. }
  1961. /* CORE VF API */
  1962. int bnx2x_vf_acquire(struct bnx2x *bp, struct bnx2x_virtf *vf,
  1963. struct vf_pf_resc_request *resc)
  1964. {
  1965. int base_vf_cid = (BP_VFDB(bp)->sriov.first_vf_in_pf + vf->index) *
  1966. BNX2X_CIDS_PER_VF;
  1967. union cdu_context *base_cxt = (union cdu_context *)
  1968. BP_VF_CXT_PAGE(bp, base_vf_cid/ILT_PAGE_CIDS)->addr +
  1969. (base_vf_cid & (ILT_PAGE_CIDS-1));
  1970. int i;
  1971. /* if state is 'acquired' the VF was not released or FLR'd, in
  1972. * this case the returned resources match the acquired already
  1973. * acquired resources. Verify that the requested numbers do
  1974. * not exceed the already acquired numbers.
  1975. */
  1976. if (vf->state == VF_ACQUIRED) {
  1977. DP(BNX2X_MSG_IOV, "VF[%d] Trying to re-acquire resources (VF was not released or FLR'd)\n",
  1978. vf->abs_vfid);
  1979. if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) {
  1980. BNX2X_ERR("VF[%d] When re-acquiring resources, requested numbers must be <= then previously acquired numbers\n",
  1981. vf->abs_vfid);
  1982. return -EINVAL;
  1983. }
  1984. return 0;
  1985. }
  1986. /* Otherwise vf state must be 'free' or 'reset' */
  1987. if (vf->state != VF_FREE && vf->state != VF_RESET) {
  1988. BNX2X_ERR("VF[%d] Can not acquire a VF with state %d\n",
  1989. vf->abs_vfid, vf->state);
  1990. return -EINVAL;
  1991. }
  1992. /* static allocation:
  1993. * the global maximum number are fixed per VF. fail the request if
  1994. * requested number exceed these globals
  1995. */
  1996. if (!bnx2x_vf_chk_avail_resc(bp, vf, resc)) {
  1997. DP(BNX2X_MSG_IOV,
  1998. "cannot fulfill vf resource request. Placing maximal available values in response\n");
  1999. /* set the max resource in the vf */
  2000. return -ENOMEM;
  2001. }
  2002. /* Set resources counters - 0 request means max available */
  2003. vf_sb_count(vf) = resc->num_sbs;
  2004. vf_rxq_count(vf) = resc->num_rxqs ? : bnx2x_vf_max_queue_cnt(bp, vf);
  2005. vf_txq_count(vf) = resc->num_txqs ? : bnx2x_vf_max_queue_cnt(bp, vf);
  2006. if (resc->num_mac_filters)
  2007. vf_mac_rules_cnt(vf) = resc->num_mac_filters;
  2008. if (resc->num_vlan_filters)
  2009. vf_vlan_rules_cnt(vf) = resc->num_vlan_filters;
  2010. DP(BNX2X_MSG_IOV,
  2011. "Fulfilling vf request: sb count %d, tx_count %d, rx_count %d, mac_rules_count %d, vlan_rules_count %d\n",
  2012. vf_sb_count(vf), vf_rxq_count(vf),
  2013. vf_txq_count(vf), vf_mac_rules_cnt(vf),
  2014. vf_vlan_rules_cnt(vf));
  2015. /* Initialize the queues */
  2016. if (!vf->vfqs) {
  2017. DP(BNX2X_MSG_IOV, "vf->vfqs was not allocated\n");
  2018. return -EINVAL;
  2019. }
  2020. for_each_vfq(vf, i) {
  2021. struct bnx2x_vf_queue *q = vfq_get(vf, i);
  2022. if (!q) {
  2023. DP(BNX2X_MSG_IOV, "q number %d was not allocated\n", i);
  2024. return -EINVAL;
  2025. }
  2026. q->index = i;
  2027. q->cxt = &((base_cxt + i)->eth);
  2028. q->cid = BNX2X_FIRST_VF_CID + base_vf_cid + i;
  2029. DP(BNX2X_MSG_IOV, "VFQ[%d:%d]: index %d, cid 0x%x, cxt %p\n",
  2030. vf->abs_vfid, i, q->index, q->cid, q->cxt);
  2031. /* init SP objects */
  2032. bnx2x_vfq_init(bp, vf, q);
  2033. }
  2034. vf->state = VF_ACQUIRED;
  2035. return 0;
  2036. }
  2037. int bnx2x_vf_init(struct bnx2x *bp, struct bnx2x_virtf *vf, dma_addr_t *sb_map)
  2038. {
  2039. struct bnx2x_func_init_params func_init = {0};
  2040. u16 flags = 0;
  2041. int i;
  2042. /* the sb resources are initialized at this point, do the
  2043. * FW/HW initializations
  2044. */
  2045. for_each_vf_sb(vf, i)
  2046. bnx2x_init_sb(bp, (dma_addr_t)sb_map[i], vf->abs_vfid, true,
  2047. vf_igu_sb(vf, i), vf_igu_sb(vf, i));
  2048. /* Sanity checks */
  2049. if (vf->state != VF_ACQUIRED) {
  2050. DP(BNX2X_MSG_IOV, "VF[%d] is not in VF_ACQUIRED, but %d\n",
  2051. vf->abs_vfid, vf->state);
  2052. return -EINVAL;
  2053. }
  2054. /* FLR cleanup epilogue */
  2055. if (bnx2x_vf_flr_clnup_epilog(bp, vf->abs_vfid))
  2056. return -EBUSY;
  2057. /* reset IGU VF statistics: MSIX */
  2058. REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0);
  2059. /* vf init */
  2060. if (vf->cfg_flags & VF_CFG_STATS)
  2061. flags |= (FUNC_FLG_STATS | FUNC_FLG_SPQ);
  2062. if (vf->cfg_flags & VF_CFG_TPA)
  2063. flags |= FUNC_FLG_TPA;
  2064. if (is_vf_multi(vf))
  2065. flags |= FUNC_FLG_RSS;
  2066. /* function setup */
  2067. func_init.func_flgs = flags;
  2068. func_init.pf_id = BP_FUNC(bp);
  2069. func_init.func_id = FW_VF_HANDLE(vf->abs_vfid);
  2070. func_init.fw_stat_map = vf->fw_stat_map;
  2071. func_init.spq_map = vf->spq_map;
  2072. func_init.spq_prod = 0;
  2073. bnx2x_func_init(bp, &func_init);
  2074. /* Enable the vf */
  2075. bnx2x_vf_enable_access(bp, vf->abs_vfid);
  2076. bnx2x_vf_enable_traffic(bp, vf);
  2077. /* queue protection table */
  2078. for_each_vfq(vf, i)
  2079. bnx2x_vf_qtbl_set_q(bp, vf->abs_vfid,
  2080. vfq_qzone_id(vf, vfq_get(vf, i)), true);
  2081. vf->state = VF_ENABLED;
  2082. return 0;
  2083. }
  2084. /* VFOP close (teardown the queues, delete mcasts and close HW) */
  2085. static void bnx2x_vfop_close(struct bnx2x *bp, struct bnx2x_virtf *vf)
  2086. {
  2087. struct bnx2x_vfop *vfop = bnx2x_vfop_cur(bp, vf);
  2088. struct bnx2x_vfop_args_qx *qx = &vfop->args.qx;
  2089. enum bnx2x_vfop_close_state state = vfop->state;
  2090. struct bnx2x_vfop_cmd cmd = {
  2091. .done = bnx2x_vfop_close,
  2092. .block = false,
  2093. };
  2094. if (vfop->rc < 0)
  2095. goto op_err;
  2096. DP(BNX2X_MSG_IOV, "vf[%d] STATE: %d\n", vf->abs_vfid, state);
  2097. switch (state) {
  2098. case BNX2X_VFOP_CLOSE_QUEUES:
  2099. if (++(qx->qid) < vf_rxq_count(vf)) {
  2100. vfop->rc = bnx2x_vfop_qdown_cmd(bp, vf, &cmd, qx->qid);
  2101. if (vfop->rc)
  2102. goto op_err;
  2103. return;
  2104. }
  2105. /* remove multicasts */
  2106. vfop->state = BNX2X_VFOP_CLOSE_HW;
  2107. vfop->rc = bnx2x_vfop_mcast_cmd(bp, vf, &cmd, NULL, 0, false);
  2108. if (vfop->rc)
  2109. goto op_err;
  2110. return;
  2111. case BNX2X_VFOP_CLOSE_HW:
  2112. /* disable the interrupts */
  2113. DP(BNX2X_MSG_IOV, "disabling igu\n");
  2114. bnx2x_vf_igu_disable(bp, vf);
  2115. /* disable the VF */
  2116. DP(BNX2X_MSG_IOV, "clearing qtbl\n");
  2117. bnx2x_vf_clr_qtbl(bp, vf);
  2118. goto op_done;
  2119. default:
  2120. bnx2x_vfop_default(state);
  2121. }
  2122. op_err:
  2123. BNX2X_ERR("VF[%d] CLOSE error: rc %d\n", vf->abs_vfid, vfop->rc);
  2124. op_done:
  2125. vf->state = VF_ACQUIRED;
  2126. DP(BNX2X_MSG_IOV, "set state to acquired\n");
  2127. bnx2x_vfop_end(bp, vf, vfop);
  2128. }
  2129. int bnx2x_vfop_close_cmd(struct bnx2x *bp,
  2130. struct bnx2x_virtf *vf,
  2131. struct bnx2x_vfop_cmd *cmd)
  2132. {
  2133. struct bnx2x_vfop *vfop = bnx2x_vfop_add(bp, vf);
  2134. if (vfop) {
  2135. vfop->args.qx.qid = -1; /* loop */
  2136. bnx2x_vfop_opset(BNX2X_VFOP_CLOSE_QUEUES,
  2137. bnx2x_vfop_close, cmd->done);
  2138. return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_close,
  2139. cmd->block);
  2140. }
  2141. return -ENOMEM;
  2142. }
  2143. void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
  2144. enum channel_tlvs tlv)
  2145. {
  2146. /* lock the channel */
  2147. mutex_lock(&vf->op_mutex);
  2148. /* record the locking op */
  2149. vf->op_current = tlv;
  2150. /* log the lock */
  2151. DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel locked by %d\n",
  2152. vf->abs_vfid, tlv);
  2153. }
  2154. void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
  2155. enum channel_tlvs expected_tlv)
  2156. {
  2157. WARN(expected_tlv != vf->op_current,
  2158. "lock mismatch: expected %d found %d", expected_tlv,
  2159. vf->op_current);
  2160. /* lock the channel */
  2161. mutex_unlock(&vf->op_mutex);
  2162. /* log the unlock */
  2163. DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n",
  2164. vf->abs_vfid, vf->op_current);
  2165. /* record the locking op */
  2166. vf->op_current = CHANNEL_TLV_NONE;
  2167. }