ql4_mbx.c 32 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2006 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. /**
  12. * qla4xxx_mailbox_command - issues mailbox commands
  13. * @ha: Pointer to host adapter structure.
  14. * @inCount: number of mailbox registers to load.
  15. * @outCount: number of mailbox registers to return.
  16. * @mbx_cmd: data pointer for mailbox in registers.
  17. * @mbx_sts: data pointer for mailbox out registers.
  18. *
  19. * This routine sssue mailbox commands and waits for completion.
  20. * If outCount is 0, this routine completes successfully WITHOUT waiting
  21. * for the mailbox command to complete.
  22. **/
  23. static int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  24. uint8_t outCount, uint32_t *mbx_cmd,
  25. uint32_t *mbx_sts)
  26. {
  27. int status = QLA_ERROR;
  28. uint8_t i;
  29. u_long wait_count;
  30. uint32_t intr_status;
  31. unsigned long flags = 0;
  32. /* Make sure that pointers are valid */
  33. if (!mbx_cmd || !mbx_sts) {
  34. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  35. "pointer\n", ha->host_no, __func__));
  36. return status;
  37. }
  38. /* Mailbox code active */
  39. wait_count = MBOX_TOV * 100;
  40. while (wait_count--) {
  41. mutex_lock(&ha->mbox_sem);
  42. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  43. set_bit(AF_MBOX_COMMAND, &ha->flags);
  44. mutex_unlock(&ha->mbox_sem);
  45. break;
  46. }
  47. mutex_unlock(&ha->mbox_sem);
  48. if (!wait_count) {
  49. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  50. ha->host_no, __func__));
  51. return status;
  52. }
  53. msleep(10);
  54. }
  55. /* To prevent overwriting mailbox registers for a command that has
  56. * not yet been serviced, check to see if a previously issued
  57. * mailbox command is interrupting.
  58. * -----------------------------------------------------------------
  59. */
  60. spin_lock_irqsave(&ha->hardware_lock, flags);
  61. intr_status = readl(&ha->reg->ctrl_status);
  62. if (intr_status & CSR_SCSI_PROCESSOR_INTR) {
  63. /* Service existing interrupt */
  64. qla4xxx_interrupt_service_routine(ha, intr_status);
  65. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  66. }
  67. /* Send the mailbox command to the firmware */
  68. ha->mbox_status_count = outCount;
  69. for (i = 0; i < outCount; i++)
  70. ha->mbox_status[i] = 0;
  71. /* Load all mailbox registers, except mailbox 0. */
  72. for (i = 1; i < inCount; i++)
  73. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  74. /* Wakeup firmware */
  75. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  76. readl(&ha->reg->mailbox[0]);
  77. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  78. readl(&ha->reg->ctrl_status);
  79. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  80. /* Wait for completion */
  81. /*
  82. * If we don't want status, don't wait for the mailbox command to
  83. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  84. * you must poll the inbound Interrupt Mask for completion.
  85. */
  86. if (outCount == 0) {
  87. status = QLA_SUCCESS;
  88. goto mbox_exit;
  89. }
  90. /* Wait for command to complete */
  91. wait_count = jiffies + MBOX_TOV * HZ;
  92. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  93. if (time_after_eq(jiffies, wait_count))
  94. break;
  95. spin_lock_irqsave(&ha->hardware_lock, flags);
  96. intr_status = readl(&ha->reg->ctrl_status);
  97. if (intr_status & INTR_PENDING) {
  98. /*
  99. * Service the interrupt.
  100. * The ISR will save the mailbox status registers
  101. * to a temporary storage location in the adapter
  102. * structure.
  103. */
  104. ha->mbox_status_count = outCount;
  105. qla4xxx_interrupt_service_routine(ha, intr_status);
  106. }
  107. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  108. msleep(10);
  109. }
  110. /* Check for mailbox timeout. */
  111. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  112. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  113. " Scheduling Adapter Reset\n", ha->host_no,
  114. mbx_cmd[0]));
  115. ha->mailbox_timeout_count++;
  116. mbx_sts[0] = (-1);
  117. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  118. goto mbox_exit;
  119. }
  120. /*
  121. * Copy the mailbox out registers to the caller's mailbox in/out
  122. * structure.
  123. */
  124. spin_lock_irqsave(&ha->hardware_lock, flags);
  125. for (i = 0; i < outCount; i++)
  126. mbx_sts[i] = ha->mbox_status[i];
  127. /* Set return status and error flags (if applicable). */
  128. switch (ha->mbox_status[0]) {
  129. case MBOX_STS_COMMAND_COMPLETE:
  130. status = QLA_SUCCESS;
  131. break;
  132. case MBOX_STS_INTERMEDIATE_COMPLETION:
  133. status = QLA_SUCCESS;
  134. break;
  135. case MBOX_STS_BUSY:
  136. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  137. ha->host_no, __func__, mbx_cmd[0]));
  138. ha->mailbox_timeout_count++;
  139. break;
  140. default:
  141. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  142. "sts = %08X ****\n", ha->host_no, __func__,
  143. mbx_cmd[0], mbx_sts[0]));
  144. break;
  145. }
  146. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  147. mbox_exit:
  148. mutex_lock(&ha->mbox_sem);
  149. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  150. mutex_unlock(&ha->mbox_sem);
  151. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  152. return status;
  153. }
  154. uint8_t
  155. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  156. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  157. {
  158. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  159. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  160. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  161. mbox_cmd[1] = 0;
  162. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  163. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  164. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  165. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  166. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  167. QLA_SUCCESS) {
  168. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  169. "MBOX_CMD_INITIALIZE_FIRMWARE"
  170. " failed w/ status %04X\n",
  171. ha->host_no, __func__, mbox_sts[0]));
  172. return QLA_ERROR;
  173. }
  174. return QLA_SUCCESS;
  175. }
  176. uint8_t
  177. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  178. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  179. {
  180. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  181. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  182. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  183. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  184. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  185. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  186. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  187. QLA_SUCCESS) {
  188. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  189. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  190. " failed w/ status %04X\n",
  191. ha->host_no, __func__, mbox_sts[0]));
  192. return QLA_ERROR;
  193. }
  194. return QLA_SUCCESS;
  195. }
  196. void
  197. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  198. struct addr_ctrl_blk *init_fw_cb)
  199. {
  200. /* Save IPv4 Address Info */
  201. memcpy(ha->ip_address, init_fw_cb->ipv4_addr,
  202. min(sizeof(ha->ip_address), sizeof(init_fw_cb->ipv4_addr)));
  203. memcpy(ha->subnet_mask, init_fw_cb->ipv4_subnet,
  204. min(sizeof(ha->subnet_mask), sizeof(init_fw_cb->ipv4_subnet)));
  205. memcpy(ha->gateway, init_fw_cb->ipv4_gw_addr,
  206. min(sizeof(ha->gateway), sizeof(init_fw_cb->ipv4_gw_addr)));
  207. if (is_ipv6_enabled(ha)) {
  208. /* Save IPv6 Address */
  209. ha->ipv6_link_local_state = init_fw_cb->ipv6_lnk_lcl_addr_state;
  210. ha->ipv6_addr0_state = init_fw_cb->ipv6_addr0_state;
  211. ha->ipv6_addr1_state = init_fw_cb->ipv6_addr1_state;
  212. ha->ipv6_default_router_state = init_fw_cb->ipv6_dflt_rtr_state;
  213. ha->ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  214. ha->ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  215. memcpy(&ha->ipv6_link_local_addr.in6_u.u6_addr8[8],
  216. init_fw_cb->ipv6_if_id,
  217. min(sizeof(ha->ipv6_link_local_addr)/2,
  218. sizeof(init_fw_cb->ipv6_if_id)));
  219. memcpy(&ha->ipv6_addr0, init_fw_cb->ipv6_addr0,
  220. min(sizeof(ha->ipv6_addr0),
  221. sizeof(init_fw_cb->ipv6_addr0)));
  222. memcpy(&ha->ipv6_addr1, init_fw_cb->ipv6_addr1,
  223. min(sizeof(ha->ipv6_addr1),
  224. sizeof(init_fw_cb->ipv6_addr1)));
  225. memcpy(&ha->ipv6_default_router_addr,
  226. init_fw_cb->ipv6_dflt_rtr_addr,
  227. min(sizeof(ha->ipv6_default_router_addr),
  228. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  229. }
  230. }
  231. uint8_t
  232. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  233. uint32_t *mbox_cmd,
  234. uint32_t *mbox_sts,
  235. struct addr_ctrl_blk *init_fw_cb,
  236. dma_addr_t init_fw_cb_dma)
  237. {
  238. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  239. != QLA_SUCCESS) {
  240. DEBUG2(printk(KERN_WARNING
  241. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  242. ha->host_no, __func__));
  243. return QLA_ERROR;
  244. }
  245. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  246. /* Save some info in adapter structure. */
  247. ha->acb_version = init_fw_cb->acb_version;
  248. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  249. ha->tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  250. ha->ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  251. ha->ipv4_addr_state = le16_to_cpu(init_fw_cb->ipv4_addr_state);
  252. ha->heartbeat_interval = init_fw_cb->hb_interval;
  253. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  254. min(sizeof(ha->name_string),
  255. sizeof(init_fw_cb->iscsi_name)));
  256. /*memcpy(ha->alias, init_fw_cb->Alias,
  257. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  258. /* Save Command Line Paramater info */
  259. ha->port_down_retry_count = le16_to_cpu(init_fw_cb->conn_ka_timeout);
  260. ha->discovery_wait = ql4xdiscoverywait;
  261. if (ha->acb_version == ACB_SUPPORTED) {
  262. ha->ipv6_options = init_fw_cb->ipv6_opts;
  263. ha->ipv6_addl_options = init_fw_cb->ipv6_addtl_opts;
  264. }
  265. qla4xxx_update_local_ip(ha, init_fw_cb);
  266. return QLA_SUCCESS;
  267. }
  268. /**
  269. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  270. * @ha: Pointer to host adapter structure.
  271. **/
  272. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  273. {
  274. struct addr_ctrl_blk *init_fw_cb;
  275. dma_addr_t init_fw_cb_dma;
  276. uint32_t mbox_cmd[MBOX_REG_COUNT];
  277. uint32_t mbox_sts[MBOX_REG_COUNT];
  278. int status = QLA_ERROR;
  279. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  280. sizeof(struct addr_ctrl_blk),
  281. &init_fw_cb_dma, GFP_KERNEL);
  282. if (init_fw_cb == NULL) {
  283. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  284. ha->host_no, __func__));
  285. return 10;
  286. }
  287. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  288. /* Get Initialize Firmware Control Block. */
  289. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  290. memset(&mbox_sts, 0, sizeof(mbox_sts));
  291. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  292. QLA_SUCCESS) {
  293. dma_free_coherent(&ha->pdev->dev,
  294. sizeof(struct addr_ctrl_blk),
  295. init_fw_cb, init_fw_cb_dma);
  296. goto exit_init_fw_cb;
  297. }
  298. /* Initialize request and response queues. */
  299. qla4xxx_init_rings(ha);
  300. /* Fill in the request and response queue information. */
  301. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  302. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  303. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  304. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  305. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  306. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  307. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  308. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  309. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  310. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  311. /* Set up required options. */
  312. init_fw_cb->fw_options |=
  313. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  314. FWOPT_INITIATOR_MODE);
  315. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  316. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  317. != QLA_SUCCESS) {
  318. DEBUG2(printk(KERN_WARNING
  319. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  320. ha->host_no, __func__));
  321. goto exit_init_fw_cb;
  322. }
  323. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  324. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  325. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  326. ha->host_no, __func__));
  327. goto exit_init_fw_cb;
  328. }
  329. status = QLA_SUCCESS;
  330. exit_init_fw_cb:
  331. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  332. init_fw_cb, init_fw_cb_dma);
  333. return status;
  334. }
  335. /**
  336. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  337. * @ha: Pointer to host adapter structure.
  338. **/
  339. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  340. {
  341. struct addr_ctrl_blk *init_fw_cb;
  342. dma_addr_t init_fw_cb_dma;
  343. uint32_t mbox_cmd[MBOX_REG_COUNT];
  344. uint32_t mbox_sts[MBOX_REG_COUNT];
  345. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  346. sizeof(struct addr_ctrl_blk),
  347. &init_fw_cb_dma, GFP_KERNEL);
  348. if (init_fw_cb == NULL) {
  349. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  350. __func__);
  351. return 10;
  352. }
  353. /* Get Initialize Firmware Control Block. */
  354. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  355. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  356. QLA_SUCCESS) {
  357. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  358. ha->host_no, __func__));
  359. dma_free_coherent(&ha->pdev->dev,
  360. sizeof(struct addr_ctrl_blk),
  361. init_fw_cb, init_fw_cb_dma);
  362. return QLA_ERROR;
  363. }
  364. /* Save IP Address. */
  365. qla4xxx_update_local_ip(ha, init_fw_cb);
  366. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  367. init_fw_cb, init_fw_cb_dma);
  368. return QLA_SUCCESS;
  369. }
  370. /**
  371. * qla4xxx_get_firmware_state - gets firmware state of HBA
  372. * @ha: Pointer to host adapter structure.
  373. **/
  374. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  375. {
  376. uint32_t mbox_cmd[MBOX_REG_COUNT];
  377. uint32_t mbox_sts[MBOX_REG_COUNT];
  378. /* Get firmware version */
  379. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  380. memset(&mbox_sts, 0, sizeof(mbox_sts));
  381. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  382. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  383. QLA_SUCCESS) {
  384. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  385. "status %04X\n", ha->host_no, __func__,
  386. mbox_sts[0]));
  387. return QLA_ERROR;
  388. }
  389. ha->firmware_state = mbox_sts[1];
  390. ha->board_id = mbox_sts[2];
  391. ha->addl_fw_state = mbox_sts[3];
  392. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  393. ha->host_no, __func__, ha->firmware_state);)
  394. return QLA_SUCCESS;
  395. }
  396. /**
  397. * qla4xxx_get_firmware_status - retrieves firmware status
  398. * @ha: Pointer to host adapter structure.
  399. **/
  400. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  401. {
  402. uint32_t mbox_cmd[MBOX_REG_COUNT];
  403. uint32_t mbox_sts[MBOX_REG_COUNT];
  404. /* Get firmware version */
  405. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  406. memset(&mbox_sts, 0, sizeof(mbox_sts));
  407. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  408. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  409. QLA_SUCCESS) {
  410. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  411. "status %04X\n", ha->host_no, __func__,
  412. mbox_sts[0]));
  413. return QLA_ERROR;
  414. }
  415. return QLA_SUCCESS;
  416. }
  417. /**
  418. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  419. * @ha: Pointer to host adapter structure.
  420. * @fw_ddb_index: Firmware's device database index
  421. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  422. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  423. * @next_ddb_index: Pointer to next valid device database index
  424. * @fw_ddb_device_state: Pointer to device state
  425. **/
  426. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  427. uint16_t fw_ddb_index,
  428. struct dev_db_entry *fw_ddb_entry,
  429. dma_addr_t fw_ddb_entry_dma,
  430. uint32_t *num_valid_ddb_entries,
  431. uint32_t *next_ddb_index,
  432. uint32_t *fw_ddb_device_state,
  433. uint32_t *conn_err_detail,
  434. uint16_t *tcp_source_port_num,
  435. uint16_t *connection_id)
  436. {
  437. int status = QLA_ERROR;
  438. uint16_t options;
  439. uint32_t mbox_cmd[MBOX_REG_COUNT];
  440. uint32_t mbox_sts[MBOX_REG_COUNT];
  441. /* Make sure the device index is valid */
  442. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  443. DEBUG2(printk("scsi%ld: %s: index [%d] out of range.\n",
  444. ha->host_no, __func__, fw_ddb_index));
  445. goto exit_get_fwddb;
  446. }
  447. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  448. memset(&mbox_sts, 0, sizeof(mbox_sts));
  449. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  450. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  451. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  452. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  453. mbox_cmd[4] = sizeof(struct dev_db_entry);
  454. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  455. QLA_ERROR) {
  456. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  457. " with status 0x%04X\n", ha->host_no, __func__,
  458. mbox_sts[0]));
  459. goto exit_get_fwddb;
  460. }
  461. if (fw_ddb_index != mbox_sts[1]) {
  462. DEBUG2(printk("scsi%ld: %s: index mismatch [%d] != [%d].\n",
  463. ha->host_no, __func__, fw_ddb_index,
  464. mbox_sts[1]));
  465. goto exit_get_fwddb;
  466. }
  467. if (fw_ddb_entry) {
  468. options = le16_to_cpu(fw_ddb_entry->options);
  469. if (options & DDB_OPT_IPV6_DEVICE) {
  470. dev_info(&ha->pdev->dev, "%s: DDB[%d] MB0 %04x Tot %d "
  471. "Next %d State %04x ConnErr %08x %pI6 "
  472. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  473. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  474. mbox_sts[4], mbox_sts[5],
  475. fw_ddb_entry->ip_addr,
  476. le16_to_cpu(fw_ddb_entry->port),
  477. fw_ddb_entry->iscsi_name);
  478. } else {
  479. dev_info(&ha->pdev->dev, "%s: DDB[%d] MB0 %04x Tot %d "
  480. "Next %d State %04x ConnErr %08x %pI4 "
  481. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  482. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  483. mbox_sts[4], mbox_sts[5],
  484. fw_ddb_entry->ip_addr,
  485. le16_to_cpu(fw_ddb_entry->port),
  486. fw_ddb_entry->iscsi_name);
  487. }
  488. }
  489. if (num_valid_ddb_entries)
  490. *num_valid_ddb_entries = mbox_sts[2];
  491. if (next_ddb_index)
  492. *next_ddb_index = mbox_sts[3];
  493. if (fw_ddb_device_state)
  494. *fw_ddb_device_state = mbox_sts[4];
  495. /*
  496. * RA: This mailbox has been changed to pass connection error and
  497. * details. Its true for ISP4010 as per Version E - Not sure when it
  498. * was changed. Get the time2wait from the fw_dd_entry field :
  499. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  500. * struct.
  501. */
  502. if (conn_err_detail)
  503. *conn_err_detail = mbox_sts[5];
  504. if (tcp_source_port_num)
  505. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  506. if (connection_id)
  507. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  508. status = QLA_SUCCESS;
  509. exit_get_fwddb:
  510. return status;
  511. }
  512. /**
  513. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  514. * @ha: Pointer to host adapter structure.
  515. * @fw_ddb_index: Firmware's device database index
  516. * @fw_ddb_entry: Pointer to firmware's ddb entry structure, or NULL.
  517. *
  518. * This routine initializes or updates the adapter's device database
  519. * entry for the specified device. It also triggers a login for the
  520. * specified device. Therefore, it may also be used as a secondary
  521. * login routine when a NULL pointer is specified for the fw_ddb_entry.
  522. **/
  523. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  524. dma_addr_t fw_ddb_entry_dma)
  525. {
  526. uint32_t mbox_cmd[MBOX_REG_COUNT];
  527. uint32_t mbox_sts[MBOX_REG_COUNT];
  528. /* Do not wait for completion. The firmware will send us an
  529. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  530. */
  531. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  532. memset(&mbox_sts, 0, sizeof(mbox_sts));
  533. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  534. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  535. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  536. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  537. mbox_cmd[4] = sizeof(struct dev_db_entry);
  538. return qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  539. }
  540. /**
  541. * qla4xxx_get_crash_record - retrieves crash record.
  542. * @ha: Pointer to host adapter structure.
  543. *
  544. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  545. **/
  546. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  547. {
  548. uint32_t mbox_cmd[MBOX_REG_COUNT];
  549. uint32_t mbox_sts[MBOX_REG_COUNT];
  550. struct crash_record *crash_record = NULL;
  551. dma_addr_t crash_record_dma = 0;
  552. uint32_t crash_record_size = 0;
  553. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  554. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  555. /* Get size of crash record. */
  556. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  557. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  558. QLA_SUCCESS) {
  559. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  560. ha->host_no, __func__));
  561. goto exit_get_crash_record;
  562. }
  563. crash_record_size = mbox_sts[4];
  564. if (crash_record_size == 0) {
  565. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  566. ha->host_no, __func__));
  567. goto exit_get_crash_record;
  568. }
  569. /* Alloc Memory for Crash Record. */
  570. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  571. &crash_record_dma, GFP_KERNEL);
  572. if (crash_record == NULL)
  573. goto exit_get_crash_record;
  574. /* Get Crash Record. */
  575. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  576. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  577. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  578. mbox_cmd[2] = LSDW(crash_record_dma);
  579. mbox_cmd[3] = MSDW(crash_record_dma);
  580. mbox_cmd[4] = crash_record_size;
  581. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  582. QLA_SUCCESS)
  583. goto exit_get_crash_record;
  584. /* Dump Crash Record. */
  585. exit_get_crash_record:
  586. if (crash_record)
  587. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  588. crash_record, crash_record_dma);
  589. }
  590. /**
  591. * qla4xxx_get_conn_event_log - retrieves connection event log
  592. * @ha: Pointer to host adapter structure.
  593. **/
  594. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  595. {
  596. uint32_t mbox_cmd[MBOX_REG_COUNT];
  597. uint32_t mbox_sts[MBOX_REG_COUNT];
  598. struct conn_event_log_entry *event_log = NULL;
  599. dma_addr_t event_log_dma = 0;
  600. uint32_t event_log_size = 0;
  601. uint32_t num_valid_entries;
  602. uint32_t oldest_entry = 0;
  603. uint32_t max_event_log_entries;
  604. uint8_t i;
  605. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  606. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  607. /* Get size of crash record. */
  608. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  609. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  610. QLA_SUCCESS)
  611. goto exit_get_event_log;
  612. event_log_size = mbox_sts[4];
  613. if (event_log_size == 0)
  614. goto exit_get_event_log;
  615. /* Alloc Memory for Crash Record. */
  616. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  617. &event_log_dma, GFP_KERNEL);
  618. if (event_log == NULL)
  619. goto exit_get_event_log;
  620. /* Get Crash Record. */
  621. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  622. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  623. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  624. mbox_cmd[2] = LSDW(event_log_dma);
  625. mbox_cmd[3] = MSDW(event_log_dma);
  626. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  627. QLA_SUCCESS) {
  628. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  629. "log!\n", ha->host_no, __func__));
  630. goto exit_get_event_log;
  631. }
  632. /* Dump Event Log. */
  633. num_valid_entries = mbox_sts[1];
  634. max_event_log_entries = event_log_size /
  635. sizeof(struct conn_event_log_entry);
  636. if (num_valid_entries > max_event_log_entries)
  637. oldest_entry = num_valid_entries % max_event_log_entries;
  638. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  639. ha->host_no, num_valid_entries));
  640. if (ql4xextended_error_logging == 3) {
  641. if (oldest_entry == 0) {
  642. /* Circular Buffer has not wrapped around */
  643. for (i=0; i < num_valid_entries; i++) {
  644. qla4xxx_dump_buffer((uint8_t *)event_log+
  645. (i*sizeof(*event_log)),
  646. sizeof(*event_log));
  647. }
  648. }
  649. else {
  650. /* Circular Buffer has wrapped around -
  651. * display accordingly*/
  652. for (i=oldest_entry; i < max_event_log_entries; i++) {
  653. qla4xxx_dump_buffer((uint8_t *)event_log+
  654. (i*sizeof(*event_log)),
  655. sizeof(*event_log));
  656. }
  657. for (i=0; i < oldest_entry; i++) {
  658. qla4xxx_dump_buffer((uint8_t *)event_log+
  659. (i*sizeof(*event_log)),
  660. sizeof(*event_log));
  661. }
  662. }
  663. }
  664. exit_get_event_log:
  665. if (event_log)
  666. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  667. event_log_dma);
  668. }
  669. /**
  670. * qla4xxx_abort_task - issues Abort Task
  671. * @ha: Pointer to host adapter structure.
  672. * @srb: Pointer to srb entry
  673. *
  674. * This routine performs a LUN RESET on the specified target/lun.
  675. * The caller must ensure that the ddb_entry and lun_entry pointers
  676. * are valid before calling this routine.
  677. **/
  678. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  679. {
  680. uint32_t mbox_cmd[MBOX_REG_COUNT];
  681. uint32_t mbox_sts[MBOX_REG_COUNT];
  682. struct scsi_cmnd *cmd = srb->cmd;
  683. int status = QLA_SUCCESS;
  684. unsigned long flags = 0;
  685. uint32_t index;
  686. /*
  687. * Send abort task command to ISP, so that the ISP will return
  688. * request with ABORT status
  689. */
  690. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  691. memset(&mbox_sts, 0, sizeof(mbox_sts));
  692. spin_lock_irqsave(&ha->hardware_lock, flags);
  693. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  694. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  695. /* Firmware already posted completion on response queue */
  696. if (index == MAX_SRBS)
  697. return status;
  698. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  699. mbox_cmd[1] = srb->fw_ddb_index;
  700. mbox_cmd[2] = index;
  701. /* Immediate Command Enable */
  702. mbox_cmd[5] = 0x01;
  703. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  704. &mbox_sts[0]);
  705. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  706. status = QLA_ERROR;
  707. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  708. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  709. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  710. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  711. }
  712. return status;
  713. }
  714. /**
  715. * qla4xxx_reset_lun - issues LUN Reset
  716. * @ha: Pointer to host adapter structure.
  717. * @db_entry: Pointer to device database entry
  718. * @un_entry: Pointer to lun entry structure
  719. *
  720. * This routine performs a LUN RESET on the specified target/lun.
  721. * The caller must ensure that the ddb_entry and lun_entry pointers
  722. * are valid before calling this routine.
  723. **/
  724. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  725. int lun)
  726. {
  727. uint32_t mbox_cmd[MBOX_REG_COUNT];
  728. uint32_t mbox_sts[MBOX_REG_COUNT];
  729. int status = QLA_SUCCESS;
  730. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  731. ddb_entry->os_target_id, lun));
  732. /*
  733. * Send lun reset command to ISP, so that the ISP will return all
  734. * outstanding requests with RESET status
  735. */
  736. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  737. memset(&mbox_sts, 0, sizeof(mbox_sts));
  738. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  739. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  740. mbox_cmd[2] = lun << 8;
  741. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  742. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  743. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  744. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  745. status = QLA_ERROR;
  746. return status;
  747. }
  748. /**
  749. * qla4xxx_reset_target - issues target Reset
  750. * @ha: Pointer to host adapter structure.
  751. * @db_entry: Pointer to device database entry
  752. * @un_entry: Pointer to lun entry structure
  753. *
  754. * This routine performs a TARGET RESET on the specified target.
  755. * The caller must ensure that the ddb_entry pointers
  756. * are valid before calling this routine.
  757. **/
  758. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  759. struct ddb_entry *ddb_entry)
  760. {
  761. uint32_t mbox_cmd[MBOX_REG_COUNT];
  762. uint32_t mbox_sts[MBOX_REG_COUNT];
  763. int status = QLA_SUCCESS;
  764. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  765. ddb_entry->os_target_id));
  766. /*
  767. * Send target reset command to ISP, so that the ISP will return all
  768. * outstanding requests with RESET status
  769. */
  770. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  771. memset(&mbox_sts, 0, sizeof(mbox_sts));
  772. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  773. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  774. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  775. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  776. &mbox_sts[0]);
  777. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  778. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  779. status = QLA_ERROR;
  780. return status;
  781. }
  782. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  783. uint32_t offset, uint32_t len)
  784. {
  785. uint32_t mbox_cmd[MBOX_REG_COUNT];
  786. uint32_t mbox_sts[MBOX_REG_COUNT];
  787. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  788. memset(&mbox_sts, 0, sizeof(mbox_sts));
  789. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  790. mbox_cmd[1] = LSDW(dma_addr);
  791. mbox_cmd[2] = MSDW(dma_addr);
  792. mbox_cmd[3] = offset;
  793. mbox_cmd[4] = len;
  794. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  795. QLA_SUCCESS) {
  796. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  797. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  798. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  799. return QLA_ERROR;
  800. }
  801. return QLA_SUCCESS;
  802. }
  803. /**
  804. * qla4xxx_get_fw_version - gets firmware version
  805. * @ha: Pointer to host adapter structure.
  806. *
  807. * Retrieves the firmware version on HBA. In QLA4010, mailboxes 2 & 3 may
  808. * hold an address for data. Make sure that we write 0 to those mailboxes,
  809. * if unused.
  810. **/
  811. int qla4xxx_get_fw_version(struct scsi_qla_host * ha)
  812. {
  813. uint32_t mbox_cmd[MBOX_REG_COUNT];
  814. uint32_t mbox_sts[MBOX_REG_COUNT];
  815. /* Get firmware version. */
  816. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  817. memset(&mbox_sts, 0, sizeof(mbox_sts));
  818. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  819. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  820. QLA_SUCCESS) {
  821. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_ABOUT_FW failed w/ "
  822. "status %04X\n", ha->host_no, __func__, mbox_sts[0]));
  823. return QLA_ERROR;
  824. }
  825. /* Save firmware version information. */
  826. ha->firmware_version[0] = mbox_sts[1];
  827. ha->firmware_version[1] = mbox_sts[2];
  828. ha->patch_number = mbox_sts[3];
  829. ha->build_number = mbox_sts[4];
  830. return QLA_SUCCESS;
  831. }
  832. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha,
  833. dma_addr_t dma_addr)
  834. {
  835. uint32_t mbox_cmd[MBOX_REG_COUNT];
  836. uint32_t mbox_sts[MBOX_REG_COUNT];
  837. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  838. memset(&mbox_sts, 0, sizeof(mbox_sts));
  839. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  840. mbox_cmd[2] = LSDW(dma_addr);
  841. mbox_cmd[3] = MSDW(dma_addr);
  842. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  843. QLA_SUCCESS) {
  844. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  845. ha->host_no, __func__, mbox_sts[0]));
  846. return QLA_ERROR;
  847. }
  848. return QLA_SUCCESS;
  849. }
  850. static int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t *ddb_index)
  851. {
  852. uint32_t mbox_cmd[MBOX_REG_COUNT];
  853. uint32_t mbox_sts[MBOX_REG_COUNT];
  854. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  855. memset(&mbox_sts, 0, sizeof(mbox_sts));
  856. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  857. mbox_cmd[1] = MAX_PRST_DEV_DB_ENTRIES;
  858. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  859. QLA_SUCCESS) {
  860. if (mbox_sts[0] == MBOX_STS_COMMAND_ERROR) {
  861. *ddb_index = mbox_sts[2];
  862. } else {
  863. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  864. ha->host_no, __func__, mbox_sts[0]));
  865. return QLA_ERROR;
  866. }
  867. } else {
  868. *ddb_index = MAX_PRST_DEV_DB_ENTRIES;
  869. }
  870. return QLA_SUCCESS;
  871. }
  872. int qla4xxx_send_tgts(struct scsi_qla_host *ha, char *ip, uint16_t port)
  873. {
  874. struct dev_db_entry *fw_ddb_entry;
  875. dma_addr_t fw_ddb_entry_dma;
  876. uint32_t ddb_index;
  877. int ret_val = QLA_SUCCESS;
  878. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev,
  879. sizeof(*fw_ddb_entry),
  880. &fw_ddb_entry_dma, GFP_KERNEL);
  881. if (!fw_ddb_entry) {
  882. DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
  883. ha->host_no, __func__));
  884. ret_val = QLA_ERROR;
  885. goto qla4xxx_send_tgts_exit;
  886. }
  887. ret_val = qla4xxx_get_default_ddb(ha, fw_ddb_entry_dma);
  888. if (ret_val != QLA_SUCCESS)
  889. goto qla4xxx_send_tgts_exit;
  890. ret_val = qla4xxx_req_ddb_entry(ha, &ddb_index);
  891. if (ret_val != QLA_SUCCESS)
  892. goto qla4xxx_send_tgts_exit;
  893. memset(fw_ddb_entry->iscsi_alias, 0,
  894. sizeof(fw_ddb_entry->iscsi_alias));
  895. memset(fw_ddb_entry->iscsi_name, 0,
  896. sizeof(fw_ddb_entry->iscsi_name));
  897. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  898. memset(fw_ddb_entry->tgt_addr, 0,
  899. sizeof(fw_ddb_entry->tgt_addr));
  900. fw_ddb_entry->options = (DDB_OPT_DISC_SESSION | DDB_OPT_TARGET);
  901. fw_ddb_entry->port = cpu_to_le16(ntohs(port));
  902. fw_ddb_entry->ip_addr[0] = *ip;
  903. fw_ddb_entry->ip_addr[1] = *(ip + 1);
  904. fw_ddb_entry->ip_addr[2] = *(ip + 2);
  905. fw_ddb_entry->ip_addr[3] = *(ip + 3);
  906. ret_val = qla4xxx_set_ddb_entry(ha, ddb_index, fw_ddb_entry_dma);
  907. qla4xxx_send_tgts_exit:
  908. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  909. fw_ddb_entry, fw_ddb_entry_dma);
  910. return ret_val;
  911. }