radeon_pm.c 22 KB

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  1. /*
  2. * Permission is hereby granted, free of charge, to any person obtaining a
  3. * copy of this software and associated documentation files (the "Software"),
  4. * to deal in the Software without restriction, including without limitation
  5. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  6. * and/or sell copies of the Software, and to permit persons to whom the
  7. * Software is furnished to do so, subject to the following conditions:
  8. *
  9. * The above copyright notice and this permission notice shall be included in
  10. * all copies or substantial portions of the Software.
  11. *
  12. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  15. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18. * OTHER DEALINGS IN THE SOFTWARE.
  19. *
  20. * Authors: Rafał Miłecki <zajec5@gmail.com>
  21. * Alex Deucher <alexdeucher@gmail.com>
  22. */
  23. #include "drmP.h"
  24. #include "radeon.h"
  25. #include "avivod.h"
  26. #ifdef CONFIG_ACPI
  27. #include <linux/acpi.h>
  28. #endif
  29. #include <linux/power_supply.h>
  30. #define RADEON_IDLE_LOOP_MS 100
  31. #define RADEON_RECLOCK_DELAY_MS 200
  32. #define RADEON_WAIT_VBLANK_TIMEOUT 200
  33. #define RADEON_WAIT_IDLE_TIMEOUT 200
  34. static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  35. static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  36. static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  37. static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  38. static void radeon_pm_update_profile(struct radeon_device *rdev);
  39. static void radeon_pm_set_clocks(struct radeon_device *rdev);
  40. #define ACPI_AC_CLASS "ac_adapter"
  41. #ifdef CONFIG_ACPI
  42. static int radeon_acpi_event(struct notifier_block *nb,
  43. unsigned long val,
  44. void *data)
  45. {
  46. struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  47. struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  48. if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  49. if (power_supply_is_system_supplied() > 0)
  50. DRM_DEBUG("pm: AC\n");
  51. else
  52. DRM_DEBUG("pm: DC\n");
  53. if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  54. if (rdev->pm.profile == PM_PROFILE_AUTO) {
  55. mutex_lock(&rdev->pm.mutex);
  56. radeon_pm_update_profile(rdev);
  57. radeon_pm_set_clocks(rdev);
  58. mutex_unlock(&rdev->pm.mutex);
  59. }
  60. }
  61. }
  62. return NOTIFY_OK;
  63. }
  64. #endif
  65. static void radeon_pm_update_profile(struct radeon_device *rdev)
  66. {
  67. switch (rdev->pm.profile) {
  68. case PM_PROFILE_DEFAULT:
  69. rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  70. break;
  71. case PM_PROFILE_AUTO:
  72. if (power_supply_is_system_supplied() > 0) {
  73. if (rdev->pm.active_crtc_count > 1)
  74. rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  75. else
  76. rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  77. } else {
  78. if (rdev->pm.active_crtc_count > 1)
  79. rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
  80. else
  81. rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
  82. }
  83. break;
  84. case PM_PROFILE_LOW:
  85. if (rdev->pm.active_crtc_count > 1)
  86. rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
  87. else
  88. rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
  89. break;
  90. case PM_PROFILE_HIGH:
  91. if (rdev->pm.active_crtc_count > 1)
  92. rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  93. else
  94. rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  95. break;
  96. }
  97. if (rdev->pm.active_crtc_count == 0) {
  98. rdev->pm.requested_power_state_index =
  99. rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
  100. rdev->pm.requested_clock_mode_index =
  101. rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
  102. } else {
  103. rdev->pm.requested_power_state_index =
  104. rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
  105. rdev->pm.requested_clock_mode_index =
  106. rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
  107. }
  108. }
  109. static void radeon_unmap_vram_bos(struct radeon_device *rdev)
  110. {
  111. struct radeon_bo *bo, *n;
  112. if (list_empty(&rdev->gem.objects))
  113. return;
  114. list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
  115. if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
  116. ttm_bo_unmap_virtual(&bo->tbo);
  117. }
  118. if (rdev->gart.table.vram.robj)
  119. ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
  120. if (rdev->stollen_vga_memory)
  121. ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
  122. if (rdev->r600_blit.shader_obj)
  123. ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
  124. }
  125. static void radeon_sync_with_vblank(struct radeon_device *rdev)
  126. {
  127. if (rdev->pm.active_crtcs) {
  128. rdev->pm.vblank_sync = false;
  129. wait_event_timeout(
  130. rdev->irq.vblank_queue, rdev->pm.vblank_sync,
  131. msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
  132. }
  133. }
  134. static void radeon_set_power_state(struct radeon_device *rdev)
  135. {
  136. u32 sclk, mclk;
  137. if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
  138. (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
  139. return;
  140. if (radeon_gui_idle(rdev)) {
  141. sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
  142. clock_info[rdev->pm.requested_clock_mode_index].sclk;
  143. if (sclk > rdev->clock.default_sclk)
  144. sclk = rdev->clock.default_sclk;
  145. mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
  146. clock_info[rdev->pm.requested_clock_mode_index].mclk;
  147. if (mclk > rdev->clock.default_mclk)
  148. mclk = rdev->clock.default_mclk;
  149. /* voltage, pcie lanes, etc.*/
  150. radeon_pm_misc(rdev);
  151. if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
  152. radeon_sync_with_vblank(rdev);
  153. if (!radeon_pm_in_vbl(rdev))
  154. return;
  155. radeon_pm_prepare(rdev);
  156. /* set engine clock */
  157. if (sclk != rdev->pm.current_sclk) {
  158. radeon_pm_debug_check_in_vbl(rdev, false);
  159. radeon_set_engine_clock(rdev, sclk);
  160. radeon_pm_debug_check_in_vbl(rdev, true);
  161. rdev->pm.current_sclk = sclk;
  162. DRM_DEBUG("Setting: e: %d\n", sclk);
  163. }
  164. /* set memory clock */
  165. if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
  166. radeon_pm_debug_check_in_vbl(rdev, false);
  167. radeon_set_memory_clock(rdev, mclk);
  168. radeon_pm_debug_check_in_vbl(rdev, true);
  169. rdev->pm.current_mclk = mclk;
  170. DRM_DEBUG("Setting: m: %d\n", mclk);
  171. }
  172. radeon_pm_finish(rdev);
  173. } else {
  174. /* set engine clock */
  175. if (sclk != rdev->pm.current_sclk) {
  176. radeon_sync_with_vblank(rdev);
  177. radeon_pm_prepare(rdev);
  178. radeon_set_engine_clock(rdev, sclk);
  179. radeon_pm_finish(rdev);
  180. rdev->pm.current_sclk = sclk;
  181. DRM_DEBUG("Setting: e: %d\n", sclk);
  182. }
  183. /* set memory clock */
  184. if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
  185. radeon_sync_with_vblank(rdev);
  186. radeon_pm_prepare(rdev);
  187. radeon_set_memory_clock(rdev, mclk);
  188. radeon_pm_finish(rdev);
  189. rdev->pm.current_mclk = mclk;
  190. DRM_DEBUG("Setting: m: %d\n", mclk);
  191. }
  192. }
  193. rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
  194. rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
  195. } else
  196. DRM_DEBUG("pm: GUI not idle!!!\n");
  197. }
  198. static void radeon_pm_set_clocks(struct radeon_device *rdev)
  199. {
  200. int i;
  201. mutex_lock(&rdev->ddev->struct_mutex);
  202. mutex_lock(&rdev->vram_mutex);
  203. mutex_lock(&rdev->cp.mutex);
  204. /* gui idle int has issues on older chips it seems */
  205. if (rdev->family >= CHIP_R600) {
  206. if (rdev->irq.installed) {
  207. /* wait for GPU idle */
  208. rdev->pm.gui_idle = false;
  209. rdev->irq.gui_idle = true;
  210. radeon_irq_set(rdev);
  211. wait_event_interruptible_timeout(
  212. rdev->irq.idle_queue, rdev->pm.gui_idle,
  213. msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
  214. rdev->irq.gui_idle = false;
  215. radeon_irq_set(rdev);
  216. }
  217. } else {
  218. if (rdev->cp.ready) {
  219. struct radeon_fence *fence;
  220. radeon_ring_alloc(rdev, 64);
  221. radeon_fence_create(rdev, &fence);
  222. radeon_fence_emit(rdev, fence);
  223. radeon_ring_commit(rdev);
  224. radeon_fence_wait(fence, false);
  225. radeon_fence_unref(&fence);
  226. }
  227. }
  228. radeon_unmap_vram_bos(rdev);
  229. if (rdev->irq.installed) {
  230. for (i = 0; i < rdev->num_crtc; i++) {
  231. if (rdev->pm.active_crtcs & (1 << i)) {
  232. rdev->pm.req_vblank |= (1 << i);
  233. drm_vblank_get(rdev->ddev, i);
  234. }
  235. }
  236. }
  237. radeon_set_power_state(rdev);
  238. if (rdev->irq.installed) {
  239. for (i = 0; i < rdev->num_crtc; i++) {
  240. if (rdev->pm.req_vblank & (1 << i)) {
  241. rdev->pm.req_vblank &= ~(1 << i);
  242. drm_vblank_put(rdev->ddev, i);
  243. }
  244. }
  245. }
  246. /* update display watermarks based on new power state */
  247. radeon_update_bandwidth_info(rdev);
  248. if (rdev->pm.active_crtc_count)
  249. radeon_bandwidth_update(rdev);
  250. rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
  251. mutex_unlock(&rdev->cp.mutex);
  252. mutex_unlock(&rdev->vram_mutex);
  253. mutex_unlock(&rdev->ddev->struct_mutex);
  254. }
  255. static ssize_t radeon_get_pm_profile(struct device *dev,
  256. struct device_attribute *attr,
  257. char *buf)
  258. {
  259. struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
  260. struct radeon_device *rdev = ddev->dev_private;
  261. int cp = rdev->pm.profile;
  262. return snprintf(buf, PAGE_SIZE, "%s\n",
  263. (cp == PM_PROFILE_AUTO) ? "auto" :
  264. (cp == PM_PROFILE_LOW) ? "low" :
  265. (cp == PM_PROFILE_HIGH) ? "high" : "default");
  266. }
  267. static ssize_t radeon_set_pm_profile(struct device *dev,
  268. struct device_attribute *attr,
  269. const char *buf,
  270. size_t count)
  271. {
  272. struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
  273. struct radeon_device *rdev = ddev->dev_private;
  274. mutex_lock(&rdev->pm.mutex);
  275. if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  276. if (strncmp("default", buf, strlen("default")) == 0)
  277. rdev->pm.profile = PM_PROFILE_DEFAULT;
  278. else if (strncmp("auto", buf, strlen("auto")) == 0)
  279. rdev->pm.profile = PM_PROFILE_AUTO;
  280. else if (strncmp("low", buf, strlen("low")) == 0)
  281. rdev->pm.profile = PM_PROFILE_LOW;
  282. else if (strncmp("high", buf, strlen("high")) == 0)
  283. rdev->pm.profile = PM_PROFILE_HIGH;
  284. else {
  285. DRM_ERROR("invalid power profile!\n");
  286. goto fail;
  287. }
  288. radeon_pm_update_profile(rdev);
  289. radeon_pm_set_clocks(rdev);
  290. }
  291. fail:
  292. mutex_unlock(&rdev->pm.mutex);
  293. return count;
  294. }
  295. static ssize_t radeon_get_pm_method(struct device *dev,
  296. struct device_attribute *attr,
  297. char *buf)
  298. {
  299. struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
  300. struct radeon_device *rdev = ddev->dev_private;
  301. int pm = rdev->pm.pm_method;
  302. return snprintf(buf, PAGE_SIZE, "%s\n",
  303. (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
  304. }
  305. static ssize_t radeon_set_pm_method(struct device *dev,
  306. struct device_attribute *attr,
  307. const char *buf,
  308. size_t count)
  309. {
  310. struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
  311. struct radeon_device *rdev = ddev->dev_private;
  312. if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
  313. mutex_lock(&rdev->pm.mutex);
  314. rdev->pm.pm_method = PM_METHOD_DYNPM;
  315. rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
  316. rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
  317. mutex_unlock(&rdev->pm.mutex);
  318. } else if (strncmp("profile", buf, strlen("profile")) == 0) {
  319. mutex_lock(&rdev->pm.mutex);
  320. rdev->pm.pm_method = PM_METHOD_PROFILE;
  321. /* disable dynpm */
  322. rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
  323. rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
  324. cancel_delayed_work(&rdev->pm.dynpm_idle_work);
  325. mutex_unlock(&rdev->pm.mutex);
  326. } else {
  327. DRM_ERROR("invalid power method!\n");
  328. goto fail;
  329. }
  330. radeon_pm_compute_clocks(rdev);
  331. fail:
  332. return count;
  333. }
  334. static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
  335. static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
  336. void radeon_pm_suspend(struct radeon_device *rdev)
  337. {
  338. mutex_lock(&rdev->pm.mutex);
  339. cancel_delayed_work(&rdev->pm.dynpm_idle_work);
  340. rdev->pm.current_power_state_index = -1;
  341. rdev->pm.current_clock_mode_index = -1;
  342. rdev->pm.current_sclk = 0;
  343. rdev->pm.current_mclk = 0;
  344. mutex_unlock(&rdev->pm.mutex);
  345. }
  346. void radeon_pm_resume(struct radeon_device *rdev)
  347. {
  348. radeon_pm_compute_clocks(rdev);
  349. }
  350. int radeon_pm_init(struct radeon_device *rdev)
  351. {
  352. int ret;
  353. /* default to profile method */
  354. rdev->pm.pm_method = PM_METHOD_PROFILE;
  355. rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
  356. rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
  357. rdev->pm.dynpm_can_upclock = true;
  358. rdev->pm.dynpm_can_downclock = true;
  359. rdev->pm.current_sclk = 0;
  360. rdev->pm.current_mclk = 0;
  361. if (rdev->bios) {
  362. if (rdev->is_atom_bios)
  363. radeon_atombios_get_power_modes(rdev);
  364. else
  365. radeon_combios_get_power_modes(rdev);
  366. radeon_pm_init_profile(rdev);
  367. rdev->pm.current_power_state_index = -1;
  368. rdev->pm.current_clock_mode_index = -1;
  369. }
  370. if (rdev->pm.num_power_states > 1) {
  371. if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  372. mutex_lock(&rdev->pm.mutex);
  373. rdev->pm.profile = PM_PROFILE_DEFAULT;
  374. radeon_pm_update_profile(rdev);
  375. radeon_pm_set_clocks(rdev);
  376. mutex_unlock(&rdev->pm.mutex);
  377. }
  378. /* where's the best place to put these? */
  379. ret = device_create_file(rdev->dev, &dev_attr_power_profile);
  380. if (ret)
  381. DRM_ERROR("failed to create device file for power profile\n");
  382. ret = device_create_file(rdev->dev, &dev_attr_power_method);
  383. if (ret)
  384. DRM_ERROR("failed to create device file for power method\n");
  385. #ifdef CONFIG_ACPI
  386. rdev->acpi_nb.notifier_call = radeon_acpi_event;
  387. register_acpi_notifier(&rdev->acpi_nb);
  388. #endif
  389. INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
  390. if (radeon_debugfs_pm_init(rdev)) {
  391. DRM_ERROR("Failed to register debugfs file for PM!\n");
  392. }
  393. DRM_INFO("radeon: power management initialized\n");
  394. }
  395. return 0;
  396. }
  397. void radeon_pm_fini(struct radeon_device *rdev)
  398. {
  399. if (rdev->pm.num_power_states > 1) {
  400. mutex_lock(&rdev->pm.mutex);
  401. if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  402. rdev->pm.profile = PM_PROFILE_DEFAULT;
  403. radeon_pm_update_profile(rdev);
  404. radeon_pm_set_clocks(rdev);
  405. } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
  406. /* cancel work */
  407. cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
  408. /* reset default clocks */
  409. rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
  410. rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
  411. radeon_pm_set_clocks(rdev);
  412. }
  413. mutex_unlock(&rdev->pm.mutex);
  414. device_remove_file(rdev->dev, &dev_attr_power_profile);
  415. device_remove_file(rdev->dev, &dev_attr_power_method);
  416. #ifdef CONFIG_ACPI
  417. unregister_acpi_notifier(&rdev->acpi_nb);
  418. #endif
  419. }
  420. if (rdev->pm.i2c_bus)
  421. radeon_i2c_destroy(rdev->pm.i2c_bus);
  422. }
  423. void radeon_pm_compute_clocks(struct radeon_device *rdev)
  424. {
  425. struct drm_device *ddev = rdev->ddev;
  426. struct drm_crtc *crtc;
  427. struct radeon_crtc *radeon_crtc;
  428. if (rdev->pm.num_power_states < 2)
  429. return;
  430. mutex_lock(&rdev->pm.mutex);
  431. rdev->pm.active_crtcs = 0;
  432. rdev->pm.active_crtc_count = 0;
  433. list_for_each_entry(crtc,
  434. &ddev->mode_config.crtc_list, head) {
  435. radeon_crtc = to_radeon_crtc(crtc);
  436. if (radeon_crtc->enabled) {
  437. rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
  438. rdev->pm.active_crtc_count++;
  439. }
  440. }
  441. if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  442. radeon_pm_update_profile(rdev);
  443. radeon_pm_set_clocks(rdev);
  444. } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
  445. if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
  446. if (rdev->pm.active_crtc_count > 1) {
  447. if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
  448. cancel_delayed_work(&rdev->pm.dynpm_idle_work);
  449. rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
  450. rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
  451. radeon_pm_get_dynpm_state(rdev);
  452. radeon_pm_set_clocks(rdev);
  453. DRM_DEBUG("radeon: dynamic power management deactivated\n");
  454. }
  455. } else if (rdev->pm.active_crtc_count == 1) {
  456. /* TODO: Increase clocks if needed for current mode */
  457. if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
  458. rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
  459. rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
  460. radeon_pm_get_dynpm_state(rdev);
  461. radeon_pm_set_clocks(rdev);
  462. queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
  463. msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
  464. } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
  465. rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
  466. queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
  467. msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
  468. DRM_DEBUG("radeon: dynamic power management activated\n");
  469. }
  470. } else { /* count == 0 */
  471. if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
  472. cancel_delayed_work(&rdev->pm.dynpm_idle_work);
  473. rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
  474. rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
  475. radeon_pm_get_dynpm_state(rdev);
  476. radeon_pm_set_clocks(rdev);
  477. }
  478. }
  479. }
  480. }
  481. mutex_unlock(&rdev->pm.mutex);
  482. }
  483. static bool radeon_pm_in_vbl(struct radeon_device *rdev)
  484. {
  485. u32 stat_crtc = 0, vbl = 0, position = 0;
  486. bool in_vbl = true;
  487. if (ASIC_IS_DCE4(rdev)) {
  488. if (rdev->pm.active_crtcs & (1 << 0)) {
  489. vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
  490. EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
  491. position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
  492. EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
  493. }
  494. if (rdev->pm.active_crtcs & (1 << 1)) {
  495. vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
  496. EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
  497. position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
  498. EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
  499. }
  500. if (rdev->pm.active_crtcs & (1 << 2)) {
  501. vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
  502. EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
  503. position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
  504. EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
  505. }
  506. if (rdev->pm.active_crtcs & (1 << 3)) {
  507. vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
  508. EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
  509. position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
  510. EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
  511. }
  512. if (rdev->pm.active_crtcs & (1 << 4)) {
  513. vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
  514. EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
  515. position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
  516. EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
  517. }
  518. if (rdev->pm.active_crtcs & (1 << 5)) {
  519. vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
  520. EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
  521. position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
  522. EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
  523. }
  524. } else if (ASIC_IS_AVIVO(rdev)) {
  525. if (rdev->pm.active_crtcs & (1 << 0)) {
  526. vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
  527. position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
  528. }
  529. if (rdev->pm.active_crtcs & (1 << 1)) {
  530. vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
  531. position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
  532. }
  533. if (position < vbl && position > 1)
  534. in_vbl = false;
  535. } else {
  536. if (rdev->pm.active_crtcs & (1 << 0)) {
  537. stat_crtc = RREG32(RADEON_CRTC_STATUS);
  538. if (!(stat_crtc & 1))
  539. in_vbl = false;
  540. }
  541. if (rdev->pm.active_crtcs & (1 << 1)) {
  542. stat_crtc = RREG32(RADEON_CRTC2_STATUS);
  543. if (!(stat_crtc & 1))
  544. in_vbl = false;
  545. }
  546. }
  547. if (position < vbl && position > 1)
  548. in_vbl = false;
  549. return in_vbl;
  550. }
  551. static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
  552. {
  553. u32 stat_crtc = 0;
  554. bool in_vbl = radeon_pm_in_vbl(rdev);
  555. if (in_vbl == false)
  556. DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
  557. finish ? "exit" : "entry");
  558. return in_vbl;
  559. }
  560. static void radeon_dynpm_idle_work_handler(struct work_struct *work)
  561. {
  562. struct radeon_device *rdev;
  563. int resched;
  564. rdev = container_of(work, struct radeon_device,
  565. pm.dynpm_idle_work.work);
  566. resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
  567. mutex_lock(&rdev->pm.mutex);
  568. if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
  569. unsigned long irq_flags;
  570. int not_processed = 0;
  571. read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
  572. if (!list_empty(&rdev->fence_drv.emited)) {
  573. struct list_head *ptr;
  574. list_for_each(ptr, &rdev->fence_drv.emited) {
  575. /* count up to 3, that's enought info */
  576. if (++not_processed >= 3)
  577. break;
  578. }
  579. }
  580. read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
  581. if (not_processed >= 3) { /* should upclock */
  582. if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
  583. rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
  584. } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
  585. rdev->pm.dynpm_can_upclock) {
  586. rdev->pm.dynpm_planned_action =
  587. DYNPM_ACTION_UPCLOCK;
  588. rdev->pm.dynpm_action_timeout = jiffies +
  589. msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
  590. }
  591. } else if (not_processed == 0) { /* should downclock */
  592. if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
  593. rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
  594. } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
  595. rdev->pm.dynpm_can_downclock) {
  596. rdev->pm.dynpm_planned_action =
  597. DYNPM_ACTION_DOWNCLOCK;
  598. rdev->pm.dynpm_action_timeout = jiffies +
  599. msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
  600. }
  601. }
  602. /* Note, radeon_pm_set_clocks is called with static_switch set
  603. * to false since we want to wait for vbl to avoid flicker.
  604. */
  605. if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
  606. jiffies > rdev->pm.dynpm_action_timeout) {
  607. radeon_pm_get_dynpm_state(rdev);
  608. radeon_pm_set_clocks(rdev);
  609. }
  610. }
  611. mutex_unlock(&rdev->pm.mutex);
  612. ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
  613. queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
  614. msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
  615. }
  616. /*
  617. * Debugfs info
  618. */
  619. #if defined(CONFIG_DEBUG_FS)
  620. static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
  621. {
  622. struct drm_info_node *node = (struct drm_info_node *) m->private;
  623. struct drm_device *dev = node->minor->dev;
  624. struct radeon_device *rdev = dev->dev_private;
  625. seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
  626. seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
  627. seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
  628. if (rdev->asic->get_memory_clock)
  629. seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
  630. if (rdev->asic->get_pcie_lanes)
  631. seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
  632. return 0;
  633. }
  634. static struct drm_info_list radeon_pm_info_list[] = {
  635. {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
  636. };
  637. #endif
  638. static int radeon_debugfs_pm_init(struct radeon_device *rdev)
  639. {
  640. #if defined(CONFIG_DEBUG_FS)
  641. return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
  642. #else
  643. return 0;
  644. #endif
  645. }