nouveau_drv.c 12 KB

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  1. /*
  2. * Copyright 2005 Stephane Marchesin.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #include <linux/console.h>
  25. #include "drmP.h"
  26. #include "drm.h"
  27. #include "drm_crtc_helper.h"
  28. #include "nouveau_drv.h"
  29. #include "nouveau_hw.h"
  30. #include "nouveau_fb.h"
  31. #include "nouveau_fbcon.h"
  32. #include "nv50_display.h"
  33. #include "drm_pciids.h"
  34. MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
  35. int nouveau_ctxfw = 0;
  36. module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
  37. MODULE_PARM_DESC(noagp, "Disable AGP");
  38. int nouveau_noagp;
  39. module_param_named(noagp, nouveau_noagp, int, 0400);
  40. MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
  41. static int nouveau_modeset = -1; /* kms */
  42. module_param_named(modeset, nouveau_modeset, int, 0400);
  43. MODULE_PARM_DESC(vbios, "Override default VBIOS location");
  44. char *nouveau_vbios;
  45. module_param_named(vbios, nouveau_vbios, charp, 0400);
  46. MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
  47. int nouveau_vram_pushbuf;
  48. module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  49. MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
  50. int nouveau_vram_notify = 1;
  51. module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
  52. MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
  53. int nouveau_duallink = 1;
  54. module_param_named(duallink, nouveau_duallink, int, 0400);
  55. MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
  56. int nouveau_uscript_lvds = -1;
  57. module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
  58. MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
  59. int nouveau_uscript_tmds = -1;
  60. module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
  61. MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
  62. int nouveau_ignorelid = 0;
  63. module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
  64. MODULE_PARM_DESC(noaccel, "Disable all acceleration");
  65. int nouveau_noaccel = 0;
  66. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  67. MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
  68. int nouveau_nofbaccel = 0;
  69. module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
  70. MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
  71. int nouveau_override_conntype = 0;
  72. module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
  73. MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n");
  74. int nouveau_tv_disable = 0;
  75. module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
  76. MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
  77. "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
  78. "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
  79. "\t\tDefault: PAL\n"
  80. "\t\t*NOTE* Ignored for cards with external TV encoders.");
  81. char *nouveau_tv_norm;
  82. module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
  83. MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
  84. "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
  85. "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
  86. "\t\t0x100 vgaattr, 0x200 EVO (G80+). ");
  87. int nouveau_reg_debug;
  88. module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
  89. int nouveau_fbpercrtc;
  90. #if 0
  91. module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
  92. #endif
  93. static struct pci_device_id pciidlist[] = {
  94. {
  95. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  96. .class = PCI_BASE_CLASS_DISPLAY << 16,
  97. .class_mask = 0xff << 16,
  98. },
  99. {
  100. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
  101. .class = PCI_BASE_CLASS_DISPLAY << 16,
  102. .class_mask = 0xff << 16,
  103. },
  104. {}
  105. };
  106. MODULE_DEVICE_TABLE(pci, pciidlist);
  107. static struct drm_driver driver;
  108. static int __devinit
  109. nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  110. {
  111. return drm_get_dev(pdev, ent, &driver);
  112. }
  113. static void
  114. nouveau_pci_remove(struct pci_dev *pdev)
  115. {
  116. struct drm_device *dev = pci_get_drvdata(pdev);
  117. drm_put_dev(dev);
  118. }
  119. int
  120. nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
  121. {
  122. struct drm_device *dev = pci_get_drvdata(pdev);
  123. struct drm_nouveau_private *dev_priv = dev->dev_private;
  124. struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
  125. struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
  126. struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  127. struct nouveau_channel *chan;
  128. struct drm_crtc *crtc;
  129. int ret, i;
  130. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  131. return -ENODEV;
  132. if (pm_state.event == PM_EVENT_PRETHAW)
  133. return 0;
  134. NV_INFO(dev, "Disabling fbcon acceleration...\n");
  135. nouveau_fbcon_save_disable_accel(dev);
  136. NV_INFO(dev, "Unpinning framebuffer(s)...\n");
  137. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  138. struct nouveau_framebuffer *nouveau_fb;
  139. nouveau_fb = nouveau_framebuffer(crtc->fb);
  140. if (!nouveau_fb || !nouveau_fb->nvbo)
  141. continue;
  142. nouveau_bo_unpin(nouveau_fb->nvbo);
  143. }
  144. NV_INFO(dev, "Evicting buffers...\n");
  145. ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
  146. NV_INFO(dev, "Idling channels...\n");
  147. for (i = 0; i < pfifo->channels; i++) {
  148. struct nouveau_fence *fence = NULL;
  149. chan = dev_priv->fifos[i];
  150. if (!chan || (dev_priv->card_type >= NV_50 &&
  151. chan == dev_priv->fifos[0]))
  152. continue;
  153. ret = nouveau_fence_new(chan, &fence, true);
  154. if (ret == 0) {
  155. ret = nouveau_fence_wait(fence, NULL, false, false);
  156. nouveau_fence_unref((void *)&fence);
  157. }
  158. if (ret) {
  159. NV_ERROR(dev, "Failed to idle channel %d for suspend\n",
  160. chan->id);
  161. }
  162. }
  163. pgraph->fifo_access(dev, false);
  164. nouveau_wait_for_idle(dev);
  165. pfifo->reassign(dev, false);
  166. pfifo->disable(dev);
  167. pfifo->unload_context(dev);
  168. pgraph->unload_context(dev);
  169. NV_INFO(dev, "Suspending GPU objects...\n");
  170. ret = nouveau_gpuobj_suspend(dev);
  171. if (ret) {
  172. NV_ERROR(dev, "... failed: %d\n", ret);
  173. goto out_abort;
  174. }
  175. ret = pinstmem->suspend(dev);
  176. if (ret) {
  177. NV_ERROR(dev, "... failed: %d\n", ret);
  178. nouveau_gpuobj_suspend_cleanup(dev);
  179. goto out_abort;
  180. }
  181. NV_INFO(dev, "And we're gone!\n");
  182. pci_save_state(pdev);
  183. if (pm_state.event == PM_EVENT_SUSPEND) {
  184. pci_disable_device(pdev);
  185. pci_set_power_state(pdev, PCI_D3hot);
  186. }
  187. acquire_console_sem();
  188. nouveau_fbcon_set_suspend(dev, 1);
  189. release_console_sem();
  190. nouveau_fbcon_restore_accel(dev);
  191. return 0;
  192. out_abort:
  193. NV_INFO(dev, "Re-enabling acceleration..\n");
  194. pfifo->enable(dev);
  195. pfifo->reassign(dev, true);
  196. pgraph->fifo_access(dev, true);
  197. return ret;
  198. }
  199. int
  200. nouveau_pci_resume(struct pci_dev *pdev)
  201. {
  202. struct drm_device *dev = pci_get_drvdata(pdev);
  203. struct drm_nouveau_private *dev_priv = dev->dev_private;
  204. struct nouveau_engine *engine = &dev_priv->engine;
  205. struct drm_crtc *crtc;
  206. int ret, i;
  207. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  208. return -ENODEV;
  209. nouveau_fbcon_save_disable_accel(dev);
  210. NV_INFO(dev, "We're back, enabling device...\n");
  211. pci_set_power_state(pdev, PCI_D0);
  212. pci_restore_state(pdev);
  213. if (pci_enable_device(pdev))
  214. return -1;
  215. pci_set_master(dev->pdev);
  216. NV_INFO(dev, "POSTing device...\n");
  217. ret = nouveau_run_vbios_init(dev);
  218. if (ret)
  219. return ret;
  220. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
  221. ret = nouveau_mem_init_agp(dev);
  222. if (ret) {
  223. NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
  224. return ret;
  225. }
  226. }
  227. NV_INFO(dev, "Reinitialising engines...\n");
  228. engine->instmem.resume(dev);
  229. engine->mc.init(dev);
  230. engine->timer.init(dev);
  231. engine->fb.init(dev);
  232. engine->graph.init(dev);
  233. engine->fifo.init(dev);
  234. NV_INFO(dev, "Restoring GPU objects...\n");
  235. nouveau_gpuobj_resume(dev);
  236. nouveau_irq_postinstall(dev);
  237. /* Re-write SKIPS, they'll have been lost over the suspend */
  238. if (nouveau_vram_pushbuf) {
  239. struct nouveau_channel *chan;
  240. int j;
  241. for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
  242. chan = dev_priv->fifos[i];
  243. if (!chan || !chan->pushbuf_bo)
  244. continue;
  245. for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
  246. nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
  247. }
  248. }
  249. NV_INFO(dev, "Restoring mode...\n");
  250. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  251. struct nouveau_framebuffer *nouveau_fb;
  252. nouveau_fb = nouveau_framebuffer(crtc->fb);
  253. if (!nouveau_fb || !nouveau_fb->nvbo)
  254. continue;
  255. nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
  256. }
  257. if (dev_priv->card_type < NV_50) {
  258. nv04_display_restore(dev);
  259. NVLockVgaCrtcs(dev, false);
  260. } else
  261. nv50_display_init(dev);
  262. /* Force CLUT to get re-loaded during modeset */
  263. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  264. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  265. nv_crtc->lut.depth = 0;
  266. }
  267. acquire_console_sem();
  268. nouveau_fbcon_set_suspend(dev, 0);
  269. release_console_sem();
  270. nouveau_fbcon_zfill_all(dev);
  271. drm_helper_resume_force_mode(dev);
  272. nouveau_fbcon_restore_accel(dev);
  273. return 0;
  274. }
  275. static struct drm_driver driver = {
  276. .driver_features =
  277. DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
  278. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
  279. .load = nouveau_load,
  280. .firstopen = nouveau_firstopen,
  281. .lastclose = nouveau_lastclose,
  282. .unload = nouveau_unload,
  283. .preclose = nouveau_preclose,
  284. #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
  285. .debugfs_init = nouveau_debugfs_init,
  286. .debugfs_cleanup = nouveau_debugfs_takedown,
  287. #endif
  288. .irq_preinstall = nouveau_irq_preinstall,
  289. .irq_postinstall = nouveau_irq_postinstall,
  290. .irq_uninstall = nouveau_irq_uninstall,
  291. .irq_handler = nouveau_irq_handler,
  292. .reclaim_buffers = drm_core_reclaim_buffers,
  293. .get_map_ofs = drm_core_get_map_ofs,
  294. .get_reg_ofs = drm_core_get_reg_ofs,
  295. .ioctls = nouveau_ioctls,
  296. .fops = {
  297. .owner = THIS_MODULE,
  298. .open = drm_open,
  299. .release = drm_release,
  300. .unlocked_ioctl = drm_ioctl,
  301. .mmap = nouveau_ttm_mmap,
  302. .poll = drm_poll,
  303. .fasync = drm_fasync,
  304. #if defined(CONFIG_COMPAT)
  305. .compat_ioctl = nouveau_compat_ioctl,
  306. #endif
  307. },
  308. .pci_driver = {
  309. .name = DRIVER_NAME,
  310. .id_table = pciidlist,
  311. .probe = nouveau_pci_probe,
  312. .remove = nouveau_pci_remove,
  313. .suspend = nouveau_pci_suspend,
  314. .resume = nouveau_pci_resume
  315. },
  316. .gem_init_object = nouveau_gem_object_new,
  317. .gem_free_object = nouveau_gem_object_del,
  318. .name = DRIVER_NAME,
  319. .desc = DRIVER_DESC,
  320. #ifdef GIT_REVISION
  321. .date = GIT_REVISION,
  322. #else
  323. .date = DRIVER_DATE,
  324. #endif
  325. .major = DRIVER_MAJOR,
  326. .minor = DRIVER_MINOR,
  327. .patchlevel = DRIVER_PATCHLEVEL,
  328. };
  329. static int __init nouveau_init(void)
  330. {
  331. driver.num_ioctls = nouveau_max_ioctl;
  332. if (nouveau_modeset == -1) {
  333. #ifdef CONFIG_VGA_CONSOLE
  334. if (vgacon_text_force())
  335. nouveau_modeset = 0;
  336. else
  337. #endif
  338. nouveau_modeset = 1;
  339. }
  340. if (nouveau_modeset == 1) {
  341. driver.driver_features |= DRIVER_MODESET;
  342. nouveau_register_dsm_handler();
  343. }
  344. return drm_init(&driver);
  345. }
  346. static void __exit nouveau_exit(void)
  347. {
  348. drm_exit(&driver);
  349. nouveau_unregister_dsm_handler();
  350. }
  351. module_init(nouveau_init);
  352. module_exit(nouveau_exit);
  353. MODULE_AUTHOR(DRIVER_AUTHOR);
  354. MODULE_DESCRIPTION(DRIVER_DESC);
  355. MODULE_LICENSE("GPL and additional rights");